MANUFACTURING METHOD OF AN INCREASED SOURCE AND DRAIN TRANSISTOR

Description

TECHNICAL FIELD

[0001] The present invention relates to a method for producing spacers for a transistor. It relates more particularly to the production of “L” shaped spacers. The present invention will find advantageous application in the production of a transistor comprising raised source and drain surfaces and having inclined lateral facets. STATE OF THE ART

[0002] The switching performance of a transistor can be improved by reducing the access resistance to the source and drain regions of the transistor.

[0003] One solution to reduce this access resistance is to raise the source and drain regions on either side of the transistor gate, usually by epitaxial growth from the substrate. Such a transistor configuration with a gate and raised source and drain regions is called RSD, an acronym for "Raised Source / Drain".

[0004] The transistor gate is isolated from the source and drain regions by spacers. The source and drain regions are undifferentiated here and referred to by the same acronym "S / D".

[0005] The spacers cover the lateral sides of the grid and rest on the substrate at the base of the grid. Document EP3246948A1 discloses examples of spacer embodiments.

[0006] In an RSD configuration, the resumption of epitaxy at the edge of the spacers can be influenced by the shape of these spacers. Spacers with substantially vertical sides over the entire height of the gate promote the formation of raised S / Ds in a layer, resting against the spacers. This configuration, however, generates an increase in the overlap capacitance between the S / Ds and the gate, which is detrimental to the switching performance of the transistor.

[0007] L-shaped spacers against the gate flanks promote the formation of faceted raised S / Ds, with free flanks separated from the spacers. This latter configuration increases the separation distance between the faceted S / Ds and the gate. The overlap capacitance is thus reduced. The performance of the RSD transistors is thus improved.

[0008] THE Figures 1A to 1E illustrate a known method for forming L-shaped spacers and, in fine, faceted S / Ds.

[0009] This known method comprises the following process steps: A first layer 30 made of a first dielectric material is deposited conformally on the grid 20 and on the active semiconductor layer 11.

[0010] A second layer 40 made of a second material differing from the first material is deposited conformally on the first layer 30 ( Fig. 1B ).

[0011] An anisotropic etching of the first and second materials, selective with respect to the material of the semiconductor layer 11, is carried out so as to remove a sacrificial part of the first and second layers 30, 40 opposite the active layer 11, while retaining parts 31, 32, 41 of the first and second layers 30, 40 located on the sides 24 of the gate 20 ( Fig. 1C ).

[0012] An isotropic etching of the second material, selective with respect to the first material, is carried out so as to remove the part 41 of the second layer 40 while retaining the parts 31, 32 of the first layer 30.

[0013] The parts 31, 32 of the first layer 30 thus form an L-shaped spacer on each of the sides 24 of the grid 20 ( Fig. 1D ).

[0014] The S / D 60 formed by epitaxial recovery then have faceted sides 61 ( Fig. 1E ).

[0015] A disadvantage of this solution is that the anisotropic etching of the first and second materials induces consumption of the active layer 11 by over-etching. This consumption of the active layer 11 has the disadvantage of promoting the appearance of crystalline defects in the S / D during the resumption of epitaxy.

[0016] Another disadvantage of this solution is that the different etching speeds of the first and second materials induce, at the scale of the plate (usually designated by the English term wafer) carrying the transistors, an inhomogeneity in the consumption of the active layer, in particular in the case of a high integration density of the transistors.

[0017] The present invention aims to at least partially overcome the drawbacks mentioned above.

[0018] An object of the present invention is to provide a method of forming L-shaped spacers limiting the consumption of the active layer.

[0019] Another object of the invention is to provide a method of producing a transistor comprising faceted raised S / Ds having improved crystal quality. SUMMARY

[0020] To achieve this objective, the present invention provides a method for producing on an active semiconductor layer at least one transistor comprising a gate, a source and a drain, said source and drain being raised relative to the active layer and having lateral facets inclined relative to a direction normal to the active layer, referenced direction Z, the method comprising at least the following steps: Providing a stack comprising the active layer extending mainly along a main plane and a grid pattern, the grid pattern having lateral flanks extending perpendicular to the active layer; Depositing on the grid pattern and the active layer a layer of a dielectric material having a thickness e 30 and comprising portions, called lateral portions, covering the lateral flanks, and portions, called basal portions, extending mainly parallel to said main plane, the lateral portions being substantially normal to the basal portions;Carrying out an isotropic modification of said layer over a thickness e 301 , so as to obtain a first portion of modified layer comprising a modified dielectric material, with e 301 < e 30 , Before or after the step of carrying out an isotropic modification: Carrying out an anisotropic modification of said layer over a thickness e 30 , in the direction normal to the active layer, so as to obtain second portions of modified layer comprising the modified dielectric material while retaining portions of unmodified layer on the lateral flanks of the gate pattern and on the active layer at the foot of the gate pattern, directly above the lateral portions covering the flanks of the gate pattern, Removing the first and second modified portions while retaining the portions of unmodified layer, by selective etching of the modified dielectric material with respect to the unmodified dielectric material, so as to form spacers having an L shape. ; The first modified layer portion is retained after isotropic modification and the second modified layer portions are retained after anisotropic modification. Isotropic modification is not an etching of the layer material into a dielectric material. It is a separate step prior to removing the first modified portion. Anisotropic modification is also not an etching of the layer material into a dielectric material. It is a separate step prior to removing the second modified portions.

[0021] The removal of the first and second modified portions is performed after the isotropic and anisotropic modifications.

[0022] Optionally, a step is then carried out consisting of epitaxying the source and drain so as to obtain source and drain raised relative to the active layer and having lateral facets inclined relative to the Z direction. This epitaxy is carried out from the active layer and at the edge of said L-shaped spacers, preferably in contact with the latter.

[0023] Thus, the method according to the invention makes it possible to produce L-shaped spacers on the sides of the grid pattern from a single layer deposit of a dielectric material.

[0024] The etching of the modified material also allows in a single step to: form the L-shaped spacers and expose the active layer for epitaxial growth of the source and drain.

[0025] The method according to the invention therefore requires fewer deposition and etching steps than a conventional method for forming L-shaped spacers as presented above.

[0026] Furthermore, the etching of the modified material is advantageously isotropic.

[0027] This isotropic etching of the modified material alone is easier to control than an anisotropic etching of a stack of two materials, as implemented in the conventional process illustrated in Figures 1A to 1E .

[0028] In particular, such isotropic etching can be precisely stopped at the surface of the active layer, limiting or even eliminating the consumption of the latter.

[0029] The next step of growth of faceted S / D by epitaxial resumption therefore benefits from improved germination on the surface of the non-degraded or slightly degraded active semiconductor layer.

[0030] The crystal quality of faceted S / D is improved.

[0031] The isotropic and anisotropic modifications of the method according to the present invention can advantageously be carried out in no particular order.

[0032] These isotropic and anisotropic modifications can also be advantageously carried out within the same frame, for example in a plasma reactor or in a conventional implanter.

[0033] Other objects, features, and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. BRIEF DESCRIPTION OF THE FIGURES

[0034] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which: THE Figures 1A to 1E illustrate steps of a method for producing faceted S / Ds according to the prior art. The Figures 2A to 2E illustrate steps of an embodiment of the method for producing faceted S / Ds according to the invention. The figure 3 illustrates, in a simplified manner in the form of a flowchart, the steps of two embodiments of the method for producing faceted S / Ds according to the invention.

[0035] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily to the scale of practical applications. In particular, the relative thicknesses of the different layers and modified portions are not representative of reality. DETAILED DESCRIPTION

[0036] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below: According to one embodiment, the deposition of the layer of a dielectric material is a conformal deposition, so that the lateral and basal portions have substantially the same thickness e 30 . According to one embodiment, the isotropic modification is carried out before the anisotropic modification. Alternatively, the isotropic modification is carried out after the anisotropic modification. According to one embodiment, the layer of a dielectric material is homogeneous and comprises only said dielectric material. In particular, this layer does not comprise a plurality of layers having different chemical natures, before the isotropic and anisotropic modifications. According to one embodiment, the dielectric material is chosen from SiN, SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, and SiO2. According to one embodiment, the thickness e 30 is between 5 nm and 30 nm, preferably between 7 nm and 12 nm, and the thickness e 301 is between 3 nm and 6 nm.According to one embodiment, the e 300 is the thickness of the dielectric layer that remains unmodified after the isotropic implantation step, with e 300 such that e 300 = e 30 - e 301 and e 300 ≥ 2nm, preferably e 300 ≥ 3 nm and preferably e 300 ≥ 5nm. According to one embodiment, the thickness e 300 is such that e 300 ≤ e 30 - 3 nm. According to one embodiment, the isotropic and anisotropic modifications are carried out by implantation of ions from an ion beam of at least one species among argon (Ar), fluorine (F), oxygen (O) and hydrogen (H). According to one embodiment, the isotropic modification is carried out by varying an inclination angle of the ion beam during implantation, said inclination angle being between -30° and +30° relative to the Z direction. According to one embodiment, the anisotropic modification is carried out for an ion beam mainly directed in the Z direction during implantation.In one embodiment, the isotropic and anisotropic modifications are performed by implantation of ions from a plasma, from at least one of H2, He, HBr, and NH3 species. In one embodiment, the isotropic modification is performed by maintaining a pressure greater than 100 milli Torr during the plasma implantation. In one embodiment, the anisotropic modification is performed by maintaining a pressure less than 100 milli Torr during the plasma implantation. In one embodiment, the selective etching of the modified dielectric material with respect to the dielectric material is a wet etching using a hydrofluoric acid (HF)-based solution or using a phosphoric acid (H3PO4)-based solution.According to one embodiment, the selective etching of the modified dielectric material with respect to the dielectric material is a dry etching, preferably carried out in a plasma formed from nitrogen trifluoride (NF3) and ammonia (NH3) and in which the dry etching comprises an etching step consisting of the formation of solid salts followed by a step of sublimation of said solid species.According to one embodiment, the selective etching of the modified dielectric material with respect to the dielectric material comprises: a dry etching carried out by placing the first and second modified portions in the presence of a gaseous mixture, preferably only gaseous, comprising at least a first component based on hydrofluoric acid (HF), the hydrofluoric acid transforming said first and second modified portions into non-volatile residues at room temperature, after the dry etching, a removal of the non-volatile residues at room temperature by wet cleaning or by sublimation thermal annealing.According to one embodiment, the isotropic modification is achieved by isotropically implanting ions into the dielectric material layer using an implanter and changing a bombardment direction during the implantation or by isotropically implanting ions from a plasma preferably comprising helium ions or hydrogen-based ions, at a pressure preferably greater than 100 milli Torr. According to one embodiment, the anisotropic modification is achieved by anisotropically implanting ions into the dielectric material layer using an implanter and maintaining a substantially constant bombardment direction during the implantation, this direction being substantially parallel to the lateral flanks of the gate pattern.According to one embodiment, the anisotropic modification is carried out by anisotropic implantation of ions from a plasma preferably comprising helium ions or hydrogen-based ions, at a pressure preferably less than 100 milli Torr. According to one embodiment, the gate pattern is intended to form a gate for the transistor. The gate pattern is then functional. This is then a process that can be described as "gate first", i.e. in which the gate is produced beforehand. According to another embodiment, the gate pattern is intended to be removed, after forming the spacers, to then be replaced by a functional gate pattern. The gate pattern is then sacrificial. This is then a process that can be described as "gate last", i.e. in which the gate is produced in a second step.

[0037] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0038] A layer can also be composed of several sub-layers of the same material or of different materials.

[0039] A substrate, film or layer "based" on a material A means a substrate, film or layer comprising this material A only or this material A and possibly other materials, for example doping elements or alloying elements. Thus, a silicon-based layer means, for example, a Si, n-doped Si, p-doped Si, SiGe layer. A germanium-based layer means, for example, a Ge, n-doped Ge, p-doped Ge, SiGe layer.

[0040] The word "dielectric" describes a material whose electrical conductivity is sufficiently low in the given application to serve as an insulator. In the present invention, a dielectric material preferably has a dielectric constant of less than 7.

[0041] The dielectric materials envisaged within the framework of the present invention are, in a non-limiting manner, SiN, SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH, SiO2.

[0042] The modified dielectric material is said to be different from the unmodified dielectric material.

[0043] The terms "dielectric material", "initial dielectric material", "unmodified dielectric material" are synonymous.

[0044] It is specified that, in the context of the present invention, the thickness of a layer or of the substrate is measured in a direction perpendicular to the surface along which this layer or this substrate has its maximum extension.

[0045] In the present invention, the substrate and the active layer extend along a principal plane. A direction normal to the substrate or to the active layer is a direction perpendicular to this principal plane.

[0046] In the figures, this plane corresponds to the XY plane of the orthogonal reference frame XYZ illustrated in Figure 2A The normal direction is parallel to the Z axis of this coordinate system.

[0047] In the figures, the thickness is taken along the vertical in areas that extend mainly horizontally, such as the basal portions.

[0048] On the other hand, the thickness is taken along the horizontal in areas that extend mainly vertically, such as the lateral portions. Thus, the thickness of spacers that cover vertical flanks of a grid or grid pattern will be measured along the horizontal direction in the figures.

[0049] Similarly, when we indicate that an element is located directly above or directly above another element, this means that these two elements are both located on the same line perpendicular to the main plane, or on the same line oriented vertically in the figures.

[0050] In the present invention, “L”-shaped spacers are formed. The “L” shape corresponds to a shape having a longitudinal portion oriented vertically in the figures, and a foot substantially transverse to this longitudinal portion, located at one end of this longitudinal portion. The “L” shape also includes its symmetrical shape along the Z axis.

[0051] The foot of the “L” shape may have a bevel, depending on the embodiment of the invention implemented.

[0052] This “L” shape is specifically sought here, for the advantages that it confers and which are recalled in the introduction to the present invention.

[0053] The intentionally created “L” shape in the present invention must be distinguished from an unintentional “L” shape resulting from poorly controlled engraving, for example. Such an unintentional “L” shape could only be a fortuitous disclosure.

[0054] THE Figures 2A to 2E illustrate an embodiment of the method according to the invention.

[0055] According to this embodiment, an initial structure illustrated in Figure 2A is provided.

[0056] This structure may typically comprise a substrate 10 topped with an active semiconductor layer 11 based on silicon or germanium.

[0057] The substrate 10 may comprise a support topped by an electrically insulating layer, typically an oxide layer.

[0058] The support, the insulating layer and the active layer 11 can form an elaborate substrate of the semiconductor on insulator type, for example a silicon on insulator SOI substrate (acronym for “silicon on insulator”) or a germanium on insulator GeOI substrate (acronym for “germanium on insulator”).

[0059] In the remainder of the description, the active layer 11, the substrate 10 and the produced substrate may be referred to interchangeably as “substrate”.

[0060] The active layer 11 is topped with a grid stack 20 or grid pattern 20.

[0061] Conventionally, the gate stack 20 may successively have the following layers arranged from the active layer 11: an interface oxide layer 21 with a high dielectric constant, called a “high k” layer (for example based on hafnium oxide), a polysilicon gate 22 and a hard mask 23.

[0062] The grid stack 20 typically has a height along Z of several tens of nanometers to several hundreds of nanometers.

[0063] In the remainder of the description, and for the sake of brevity, the grid stack or grid pattern will hereinafter be referred to as grid 20.

[0064] The invention also covers an alternative embodiment for which the grid pattern 20 is a sacrificial pattern intended to be removed after the spacers have been produced, then to be replaced by another grid stack forming a grid 20. Such a method is commonly referred to as “gate last” according to English terminology. The grid 20 in the following therefore indifferently designates a grid stack of the “gate first” type (the grid is retained after the spacers have been produced) or of the “gate last” type (the grid is replaced after the spacers have been produced).

[0065] To form a transistor isolated from an adjacent transistor or component, isolation trenches 50 commonly referred to as STI (from the English acronym "Shallow Trench Isolation") can be formed.

[0066] The steps of forming the L-shaped spacers on this initial structure, and consequently, the production of the raised source and drain making it possible to obtain an RSD transistor from this initial structure, are described below with reference to a first embodiment.

[0067] As illustrated in the Figure 2B , a layer 30 of a dielectric material is deposited on the gate 20 and on the active semiconductor layer 11, preferably in a conformal manner.

[0068] This layer 30 comprises a lateral portion 30L on each of the lateral flanks 24 of the grid 20, basal portions 30B on the surface of the substrate on either side of the grid 20, in contact with the active layer 11, and a basal portion 30B at the top 25 of the grid 20. The lateral portions 30L extend along planes perpendicular to the XY plane and the basal portions 30B extend along planes parallel to the XY plane.

[0069] The layer 30 has a thickness e 30 of between 5 nm and 30 nm, preferably between 7 nm and 12 nm.

[0070] As illustrated in the Figure 2C , a first step of isotropic modification is carried out.

[0071] The isotropic modification notably comprises an implantation 100 of species, in particular ions, in a first portion 301 of the superficial layer 30, so as to modify the initial dielectric material.

[0072] This isotropic modification forms a continuous portion 301 within the layer 30 and which extends from the surface of this layer 30. This portion 301 has a constant thickness e 301 along the layer 30, from the surface of the layer 30.

[0073] Portion 301 extends both along the main plane of the substrate and along the lateral flanks of gate 20. Portion 301 comprises the modified dielectric material.

[0074] The isotropic modification is configured to obtain a thickness e 301 of modified dielectric material such that e 301 is strictly less than e 30 .

[0075] The thickness e 301 ≥ 2nm and preferably e 301 ≥ 5nm. The thickness e 301 is such that e 301 ≤ e 30 - 3 nm. Preferably e 301 is between 2 nm and 6 nm.

[0076] Different embodiments of the isotropic modification will be described in detail below.

[0077] At the end of the isotropic modification step, a portion 300 of the initial layer 30 remains unmodified. This portion 300 has a thickness e 300 = e 30 - e 301 .

[0078] As illustrated in the 2D figure , a second modification step, this time anisotropic, is carried out.

[0079] The anisotropic modification notably comprises an implantation 200 of species, in particular ions, in second portions 302 of the layer 30, so as to modify the initial dielectric material. This anisotropic implantation is carried out according to a main direction of bombardment of the ions. This main direction is parallel to the plane in which the flanks 24 of the gate 20 mainly extend. In this example, this main direction is perpendicular to the XY plane of the substrate. This direction therefore corresponds to the Z axis.

[0080] This anisotropic modification forms within the layer 30 discontinuous portions 302 over the entire substrate. These portions 302 have a thickness e 30 at the level of the basal portions 30B of the layer 30.

[0081] The portions 302 extend only along the principal plane of the substrate. The portions 302 comprise the modified dielectric material. The anisotropic modification is configured to modify the dielectric material over an entire thickness of the layer 30.

[0082] Portions 302 are partly superimposed on portion 301.

[0083] Different embodiments of the anisotropic modification will be described in detail below.

[0084] At the end of these isotropic modification and anisotropic modification steps, portions 31, 32 of the initial layer 30 are preserved. These portions 31, 32 comprise the initial dielectric material, i.e. unmodified.

[0085] The portions 31 extend along the lateral flanks 24 of the grid 20. These portions 31 are arranged directly in contact with the grid. They extend over the entire height of the grid 20. They have the thickness e 300.

[0086] They advantageously form the longitudinal part of the L.

[0087] The portions 32 extend along the active layer 11. They are preferably directly in contact with the active layer 11. They have a thickness e 32 along z, such that e 32 = e 30 - e 301. They have a dimension l 32 along y, substantially equal to e30.

[0088] They advantageously form the foot of the L.

[0089] It will be noted that the distal end of the foot of the L is formed by a portion located directly above the modified portions 301 located on the sides 24 of the grid 20. The dimension of this distal end of the foot of the L along the Y axis is equal to the thickness e 301 . This dimension is directly conditioned by the thickness e 301 .

[0090] Indeed, according to this embodiment comprising an isotropic modification carried out before the anisotropic modification, it is these modified portions 301 located on the sides 24 of the grid 20 which mask the distal end of the foot of the L during the isotropic modification and prevent their modification.

[0091] According to another embodiment comprising an anisotropic modification carried out before the isotropic modification, the distal end of the foot is masked by the lateral portion 30L during the anisotropic modification. It is then formed during the anisotropic modification on the thickness e 301.

[0092] It will be noted that during this anisotropic implantation, it is possible that ions are implanted laterally in the dielectric layer 30 covering the sides 24 of the gate pattern 20. This lateral implantation, which is therefore not carried out in the preferred direction of the anisotropic implantation, is for example due to a certain defection of the ions. This lateral implantation is carried out over a depth less than or equal to 2 nm, this depth being measured in the horizontal direction on the 2D figure .

[0093] Advantageously, this involuntary lateral implantation does not negatively impact the dimensional control of the spacers 31 which will be formed. Indeed, this lateral implantation depth remains less than the depth e 301 modified during the isotropic implantation step. This technical effect is provided regardless of the order in which the isotropic and anisotropic modification steps are carried out.

[0094] An etching of the portions 301, 302 is then carried out, so as to expose the portions 31, 32.

[0095] This etching is a selective etching of the modified dielectric material with respect to the unmodified dielectric material, and with respect to the substrate.

[0096] It is preferably isotropic.

[0097] Different engraving solutions adapted to this engraving step will be detailed below.

[0098] At the end of this etching step, the L-shaped spacers are advantageously formed on each of the lateral flanks 24 of the grid 20 ( Fig. 2E ).

[0099] The S / D 60 are then formed by epitaxial growth at the edge of the L-shaped spacers. The S / D 60 thus formed advantageously have faceted sides 61 ( Fig. 2E ).

[0100] In the embodiment described above with reference to the Figures 2A to 2E, the isotropic modification is performed before the anisotropic modification.

[0101] However, according to another embodiment covered by the claims, the isotropic modification is carried out after the anisotropic modification. It follows that the steps illustrated in Figures 2C and 2D are reversed.

[0102] There figure 3 illustrates in a simplified manner in the form of a flowchart the main steps of two embodiments of the method for producing faceted S / Ds according to the invention.

[0103] Step E1 concerns the conformal deposition of the layer 30 of thickness e 30 on the grid 20.

[0104] Step E2 concerns the isotropic modification of the layer 30 by isotropic implantation 100 to form the modified portion 301 on the surface of the layer 30.

[0105] Step E3 concerns the anisotropic modification by anisotropic implantation 200 of the entire thickness e 30 of the layer 30.

[0106] This figure 3 also shows the embodiment in which the anisotropic modification is carried out before the isotropic modification. This embodiment corresponds to steps E2' and E3'.

[0107] At the end of these steps E2 then E3 or E2' then E3', the structure therefore has unmodified portions 31, 32 of the layer 30 which form Ls on the sides 24 of the grid 20.

[0108] Step E4 corresponds to the removal of the modified portions 301, 302 selectively from the unmodified portions 31, 32 of the layer 30. At the end of this step E4, the L-shaped spacers are produced.

[0109] Step E5 corresponds to the growth of the source 60 and drain 60 by epitaxy, which, thanks to the foot of the L-shaped spacers, makes it possible to grow the facets 61 of the source 60 and drain 60 in an inclined manner.

[0110] Different embodiments of the above-mentioned steps will now be described in detail. Isotropic modification 100

[0111] As mentioned above with reference to the Figure 2C , the isotropic modification of a portion 301 of the dielectric layer 30 is carried out by an isotropic implantation 100 of ions.

[0112] This continuous portion 301 is obtained and can be compared to a layer.

[0113] The implantation 100 thus makes it possible to define in the dielectric layer 30: a modified layer 301 whose thickness e 301 corresponds to the implantation depth of the dielectric layer 30, an unmodified layer 300, topped by the modified layer 301. The thickness e 300 of this unmodified layer corresponds to the initial thickness e 30 of the dielectric layer 30 minus the thickness e 301 of the modified layer 301. Typically, e 301 ≥ 2 nm, and preferably e 301 ≥ 5 nm. More generally, 2 nm ≤ e 301 ≤ 10 nm. For example, if 5 nm < e 30 < 30 nm, then 2 nm < e 301 < 10 nm.

[0114] According to a first example, isotropic implantation 100 can be carried out in a conventional implanter (usually referred to as "beamline"), i.e. with ion beam implantation.

[0115] An advantage provided by the use of an implanter is the possibility of modifying the lateral portions 30L of the dielectric layer 30 on the lateral flanks 24 of the grid 20 by bombarding according to several inclinations (tilt) of implantation direction.

[0116] For this type of implantation, the following species will be used, for example, to modify the dielectric layer 30: argon (Ar), fluorine (F), oxygen (O) or hydrogen (H). The angle of inclination of the implantation as well as the energy of the ions will be adapted according to the density and the shape of the patterns formed by the grid stacks 20, as well as according to the thickness of the dielectric layer 30.

[0117] Typically, the dose implanted by ion beam is greater than 1 E< 13 atoms per square centimeter (at / cm 2< ). It will more generally be between 1 E< 14 and 1 E< 17 at / cm 2< .

[0118] These implantation conditions are for example determined by simulation using simulation tools such as SRIM (stopping and range of ions matter) or TRIM (transport simulation of ions in matter). These simulation tools can also be used to determine the implantation conditions for plasma implantations which will be detailed below.

[0119] In a second, preferred example, isotropic implantation 100 can be performed in plasma etching equipment. In this case, a capacitively coupled plasma (CCP) reactor or an inductively coupled plasma (ICP) reactor, or an immersion plasma, can be used.

[0120] Plasma ion implantation is an advantageous solution, particularly since it allows precise control of the implanted depth in order to: to implant and therefore modify only part of the thickness of the dielectric layer 30; not to implant the underlying layers, in particular the active layer 11 and the different layers of the gate stack 20.

[0121] Furthermore, the advantage of plasma is that we have a chemical modification, particularly by H implantation, which makes the removal of the modified layer easier.

[0122] According to an exemplary embodiment, this modification comprises the implantation of hydrogen-based ions (H, H +< , H 2 +< , H 3 +< , etc.).

[0123] According to another embodiment, the implanted ions are helium ions (He) or a mixture of helium and hydrogen ions (H / He).

[0124] These ions can come for example from the following gases introduced into the reactor: H 2 , HBr; NH 3 .

[0125] In order to obtain a 100 isotropic modification by plasma implantation, several parameters can be used: the pressure. Preferably it is greater than 100 milli Torr. This allows for a deflection of the ions to reach the lateral flanks 24 of the gate stacks 20. The temperature. It is preferably less than 100°C, which allows for more effective modification of the dielectric layer 30. It has been observed that above 100°C the implanted H ions desorb, which reduces the expected modification effect. The implanted species. The H and He-based ions allow implantation of the dielectric layer 30 without sputtering of the latter and without deposition on the surface of the latter. The bias voltage and / or the source can also be pulsed so as to accentuate the isotropic effect.

[0126] In addition to the advantages mentioned above, plasma implantation has the advantage of allowing continuous implantation in a volume extending from the surface of the implanted layer.

[0127] Furthermore, the use of plasma allows implantation at shallower depths than the minimum depths that can be obtained with implanters. Thus, plasma implantation allows very thin thicknesses, typically a few nanometers, to be implanted efficiently and relatively homogeneously, or at least continuously. This continuity of implantation from the implanted face improves the homogeneity of the modification according to the depth, which leads to a constant etching speed over time of the implanted layer. Furthermore, the increase in selectivity conferred by implantation with respect to other layers is effective from the start of etching of the implanted layer. Plasma implantation thus allows significantly improved control of etching precision.

[0128] At the end of this isotropic implantation step 100, only a portion 301 of the dielectric layer 30 is modified.

[0129] The modified layer 301 has a constant thickness e 301 over its entire surface, the thickness of this layer 301 being measured, at each point of this layer 301, in a direction perpendicular to the tangent at this point. Anisotropic modification 200

[0130] As mentioned above with reference to the 2D figure , the step following or preceding the isotropic modification step 100, consists of anisotropically modifying the layer 30, over the entire thickness e 30 and in a direction parallel to the lateral flanks 24 of the gate stack 20.

[0131] This anisotropic modification 200 thus makes it possible to modify the basal portions 30B of the layer 30 over the entire thickness e 30 .

[0132] On the other hand, this modification does not modify the portions 31, 32 located on the sides 24 and at the foot of the grid stack 20, these portions being masked by the basal portion 30B located at the top 25 of the grid stack 20.

[0133] This anisotropic modification 200 is carried out by anisotropic implantation of ions over the entire thickness e 30 with a stop at the interface between the dielectric layer 30 and the layers 11, 50 which are underlying it.

[0134] As for the isotropic modification 100, this anisotropic modification 200 can be carried out in an implanter or from a plasma. These two embodiments and their variants are detailed below: According to a first example, the anisotropic implantation can be carried out in a conventional implanter.

[0135] Unlike isotropic implantation, the implantation angle remains constant throughout the implantation. This inclination is parallel to the sides 24 of the gate 20 covered with the dielectric layer 30.

[0136] The implanted species may be argon (Ar), fluorine (F), oxygen (O) or hydrogen (H). These species allow precise implantation in order to stop the implantation at the interfaces between the dielectric layer 30 and the layers 11, 50 underlying it on the one hand, and between the dielectric layer 30 and the gate stack 20 (interface 25) on the other hand.

[0137] In the next step, the modified portions 301, 302 of the dielectric layer 30 can thus be removed by dry etching and selectively with respect to the active layer 11 and the gate stack 20.

[0138] In a second, preferred example, the anisotropic implantation 200 can be carried out in plasma etching equipment. In this case, a capacitively coupled plasma reactor (CCP) or an inductively coupled plasma reactor (ICP), or an immersion plasma, can be used.

[0139] Plasma ion implantation is an advantageous solution, particularly since it allows precise control of the implanted depth in order to: to implant and therefore to modify the entire thickness of the dielectric layer 30; not to implant the underlying layers, in particular the active layer 11 and the different layers of the gate stack 20.

[0140] The other advantages mentioned in the case of isotropic 100 plasma implantation are also valid for anisotropic 200 plasma implantation.

[0141] The following parameters will be adjusted in order to obtain an anisotropic implantation 200 by plasma implantation, over a precise depth corresponding to the entire thickness of the dielectric layer 30.

[0142] These parameters are in particular: the pressure prevailing inside the plasma reactor chamber. Preferably, this pressure is less than 100 milli Tor, in order to avoid isotropic implantation; the temperature will preferably be less than 100°C, in order to effectively modify the dielectric layer 30.

[0143] For all these embodiments, the implantation conditions can be determined by simulation using an SRIM or TRIM tool.

[0144] In addition to the advantages mentioned above, plasma implantation allows the same plasma reactor to be used for both isotropic modification 100 and anisotropic modification 200.

[0145] Preferably, the isotropic modification will be carried out with the same equipment as the anisotropic modification in order to simplify the process and reduce costs.

[0146] According to yet another embodiment, during the isotropic modification step or during the anisotropic modification step, and preferably during each of these modification steps, the plasma used is formed from a gas comprising at least a first non-carbon gaseous component whose dissociation generates said light ions and a second gaseous component comprising at least one species promoting the dissociation of the first component to form said light ions, in which the gas ratio between the first component and the second component is between 1:19 and 19:1.

[0147] Preferably said ratio is between 1:9 and 9:1 and preferably between 1:5 and 5:1.

[0148] Preferably: the first component is selected from hydrogen (H2), silicon nitride (SiH4), hydrogen nitride (NH3) or hydrogen bromide (HBr). the second component is selected from helium (He), nitrogen (N2), argon (Ar) or xenon (Xe). Preferably the flow rate of the first component is between 10 and 1000 sccm (cubic centimeter per minute) and the flow rate of the second component is preferably between 10 and 1000 sccm.

[0149] Advantageously, the role of the first component is to modify, by ion bombardment, the crystalline structure of the dielectric layer in order to be able, subsequently, to differentiate the initial dielectric layer from the modified dielectric layer. The problem is that if we use a plasma based only on a single component, hydrogen (H 2 ), for example, the risk is not to modify the dielectric layer uniformly in its thickness. This leads to poor control of the actual depth up to which the modified layer has significantly improved selectivity. In this case, the depth of the ion implantation in the dielectric layer is not equivalent to the thickness of the modified dielectric layer whose selectivity is significantly improved and which will be etched following the bombardment.

[0150] The addition of a second component acting advantageously as a dissociation gas (such as argon, helium, xenon, nitrogen), makes it possible to facilitate the dissociation of the first component and thereby promote the implantation of said dissociated first component in the dielectric layer, in the form of light ions. The implanted dose is therefore higher without needing to increase the maximum implantation depth.

[0151] It is therefore important to find a correct ratio between the content of the first component and the second component in the plasma intended to modify the dielectric layer. Advantageously, the gas ratio between the first component and the second component is greater than 1:19 and less than 19:1.

[0152] These ion implantations 100, 200 are preferably carried out on a full plate. They make it possible to modify the dielectric layer 30 without sputtering it. Thus, it is essentially a chemical modification, the addition of ions in this layer 30 changing the etching selectivity of this layer 30. Thus, the modified portions 301, 302 of this layer 30 will be etched much more easily than the unmodified portions 31, 32, the underlying layers 11, 50 as well as the gate stack 20. Selective removal of amended portions 301, 302

[0153] For each of the embodiments mentioned above and based on ion implantation, several variant embodiments for the selective removal of the modified portions 301, 302 of the dielectric layer 30 are possible.

[0154] Either dry or wet etching chemistries mentioned can be used.

[0155] According to one embodiment, the step of removing the modified portions 301, 302 is carried out by selective wet etching of the semiconductor material of the active layer 11. If the semiconductor material is silicon, then the step of removing the modified portions 301, 302 is carried out by selective wet etching of the isolation trenches 50 with silicon (Si) and / or silicon oxide (SiO 2 ).

[0156] Preferably, selective silicon etching is achieved using a hydrofluoric acid (HF) based solution or a phosphoric acid (H 3 PO 4 ) based solution.

[0157] As an example for a dielectric layer 30 in SiN, with a solution based on hydrofluoric acid (HF), the etching rate ratio between modified SiN and SiN is of the order of 30; as an example, the etching rate ratio between modified SiN and SiO 2 is of the order of 38.

[0158] This makes it possible to completely remove the modified portions 301, 302 without consuming the unmodified portions 31, 32 on the sides 24 and at the foot of the grid 20; the active layer 11; the trenches 50.

[0159] The performance of the transistors is thus preserved.

[0160] The semiconductor material can also be germanium (Ge) or silicon germanium (SiGe).

[0161] According to one embodiment, particularly advantageous when the dielectric layer 30 is made of a material taken from: a silicon nitride, SiC, SiCN, SiCBN, the selective etching of the modified portions 301, 302 with respect to the unmodified portions comprises a wet etching based on a solution comprising hydrofluoric acid (HF) diluted to x% by mass, with x≤0.2 and having a pH less than or equal to 1.5.

[0162] Preferably, the pH is less than or equal to 1.3, preferably less than or equal to 1 and preferably strictly less than 1.

[0163] Preferably, x≤0.15 and preferably x≤0.1. According to one example, x is substantially equal to 0.1.

[0164] Preferably, the solution is obtained by adding at least one of: hydrochloric acid (HCl), sulfuric acid H 2 SO 4 , nitric acid HNO 3 .

[0165] Particularly surprisingly, this etching makes it possible to very significantly increase the selectivity of the etching of the modified dielectric layer with respect to materials based on silicon oxide, generally designated SiOy in the present patent application, with y being an integer greater than or equal to 1.

[0166] This improved selectivity is very advantageous since very often a hard mask on the top 25 of the grid 20 or an isolation trench 50, based on SiOy, are present during the etching step.

[0167] It follows that the hard mask 25 or the isolation trenches 50 are not altered by the etching of the spacers. They can therefore fully play their roles.

[0168] Usually such acidic pHs are not used because they are of no interest in the context of classic etching of SiOy such as SiO2.

[0169] For example, with the method according to the invention, a selectivity of the etching with respect to silicon dioxide is obtained such that for a thickness e1 of etched modified nitride, only a thickness e1 / 33.7 of silicon dioxide is etched at the same time.

[0170] According to another embodiment, the removal step is carried out by selective dry etching of the semiconductor material. Preferably, the step of removing the modified portions 301, 302, typically made of silicon nitride, is carried out by selective dry etching of silicon (Si) and / or silicon oxide (SiO 2 ). According to one embodiment, the dry etching is carried out in a plasma formed in a confined enclosure from nitrogen trifluoride (NF 3 ) and ammonia (NH 3 ).

[0171] Advantageously, the dry etching comprises: an etching step consisting of the formation of solid salts; a step of sublimation of the solid species. This embodiment makes it possible to obtain very good selectivity of the etching of the modified nitride compared to the unmodified nitride and to the semiconductor material. In particular, this etching selectivity is much higher (typically at least a factor of 10) than that obtained with an HF solution.

[0172] According to another embodiment, the step of removing the modified portions 301, 302 from the unmodified portions 31, 32 comprises a dry etching carried out by placing in the presence of a gaseous mixture, preferably only gaseous, comprising at least a first component based on hydrofluoric acid (HF). The hydrofluoric acid transforms the modified portions 301, 302 of the dielectric layer 30 into non-volatile residues, preferably non-volatile at room temperature.

[0173] Advantageously, the step of removing the portions 301, 302 comprises, only after dry etching, removal of the non-volatile residues at room temperature by wet cleaning or sublimation thermal annealing.

[0174] Advantageously, the dry etching consumes the modified portions 301, 302 of the dielectric layer 30 preferentially to the unmodified portions 31, 32 and to the active layer 11. Thus, the risk of excessive consumption of semiconductor material on the surface of the active layer 11 is reduced, or even eliminated.

[0175] The epitaxial resumption intended to form the S / D 60 thus benefits from an undegraded germination surface.

[0176] Epitaxy recovery is optimized. The 60 faceted S / Ds have improved crystal quality.

[0177] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the claims.

Claims

1. Method for producing, on a semiconductive active layer (11) of at least one transistor comprising a gate, a source and a drain (60), said source and drain (60) being raised with respect to the active layer (11) and having lateral faces (61) tilted with respect to a direction (Z) normal to the active layer (11), referenced direction Z, the method comprising at least the following steps: - Providing a stack comprising the active layer (11) extending mainly along a main plane (XY) and a gate pattern (20), the gate pattern (20) having lateral flanks (24) extending perpendicularly to the active layer (11); - Depositing, on the gate pattern (20) and the active layer (11), a layer (30) made of a dielectric material having a thickness e30 and comprising portions, called lateral portions (30L), covering the lateral flanks (24), and portions, called basal portions (30B), extending mainly parallel to said main plane (XY), the lateral portions (30L) being substantially normal to the basal portions (30B); - Carrying out an isotropic modification of said layer (30) over a thickness e301, so as to obtain a first portion (301) of modified layer comprising a modified dielectric material, with e301 < e30, the first portion (301) of modified layer being conserved from the isotropic modification, said isotropic modification being carried out by implantation of ions; - Before or after the step of carrying out an isotropic modification: - Carrying out an anisotropic modification of said layer (30) over a thickness e30, along the direction normal to the active layer (11), so as to obtain second portions (302) of modified layer comprising the modified dielectric material by conserving portions (31, 32) of non-modified layer on the lateral flanks (24) of the gate pattern (20) and on the active layer (11) at the foot of the gate pattern, just under the lateral portions (30L) covering the flanks (24) of the gate pattern (20), the second portions (302) of modified layer being conserved from the anisotropic modification, said anisotropic modification being carried out by implantation of ions; - Removing the first (301) and second (302) modified portions after the isotropic and anisotropic modifications by conserving the portions (31, 32) of non-modified layer by selective etching of the modified dielectric material opposite the non-modified dielectric material, so as to form spacers having an L-shape; - Epitaxially growing the source and drain (60) in contact with the L-shaped spacers, so as to obtain the raised source and drain with respect to the active layer (11) and having lateral faces (61) tilted with respect to the direction Z.

2. Method according to the preceding claim, wherein the layer (30) made of a dielectric material is homogenous and only comprises said dielectric material.

3. Method according to any one of the preceding claims, wherein the deposition of the layer (30) made of a dielectric material is a conformal deposition, such that the lateral (30L) and the basal (30B) portions have substantially the same thickness e30.

4. Method according to any one of the preceding claims, wherein the thickness e300 is the thickness of said layer (30) which remains non-modified by said isotropic modification, with e300 = e30 - e301, and wherein e300 is such that e300 ≥ 2nm, and preferably e300 ≥ 5nm.

5. Method according to the preceding claim, wherein the thickness e300 is such that e300 ≤ e30 - 3nm.

6. Method according to any one of the preceding claims, wherein the thickness e30 is between 5nm and 30nm, preferably between 7nm and 12nm, and the thickness e301 is between 3nm and 6nm.

7. Method according to any one of the preceding claims, wherein the dielectric material is selected from among SiN, SiCO, SiC, SiCN, SiOCN, SiCBN, SiOCH and SiO2.

8. Method according to any one of the preceding claims, wherein the isotropic and anisotropic modifications are carried out by implantation of ions from an ion beam of at least one type from among argon (Ar), fluorine (F), oxygen (O) and hydrogen (H).

9. Method according to the preceding claim, wherein the anisotropic modification is carried out for an ion beam mainly directed along the direction normal to the substrate during the implantation.

10. Method according to any one of claims 1 to 7, wherein the isotropic and anisotropic modifications are carried out by implantation of ions (100, 200) coming from a plasma, from at least one type from among H2, He, HBr, and NH3.

11. Method according to the preceding claim, wherein the isotropic modification is carried out by maintaining a pressure greater than 100 milli Torr during the implantation (100).

12. Method according to any one of the two preceding claims, wherein the anisotropic modification is carried out by maintaining a pressure less than 100 milli Torr during the implantation (200).

13. Method according to any one of the preceding claims, wherein the selective etching of the modified dielectric material opposite the dielectric material is a wet etching using a hydrofluoric (HF) acid-based solution or using a phosphoric (H3PO4) acid-based solution.