PROCESSOR MEMORY ACCESS

Description

[0001] The invention relates to the field of processors and their interactions with memory devices.

[0002] Typically, a computing device comprises a set of one or more processors. Each processor comprises one or more processing units, or PUs for " Processing Units ". Each PU includes one or more computing units called arithmetic and logic units, or ALUs for " Arithmetic-Logic Unit ". To have a high-performance computing device, i.e. one that is fast enough to perform computing operations, it is common to provide a large number of ALUs. Thus, the ALUs can process operations in parallel, i.e. at the same time. The unit of time is then a calculation cycle. It is therefore common to quantify the computing power of the computing device in terms of the number of operations it is capable of performing per calculation cycle. US 5,513,366 and GB 2,407,179 deal with these subjects.

[0003] However, having a large number of ALUs is insufficient, or even useless, if the elements of the device interacting with the ALUs are not arranged (sized) in line with the number of ALUs that are to be operated simultaneously. In other words, if the number of ALUs is large, the limiting criterion for the power of the device may be the configuration of the ALU environment. In particular, the device comprises a memory assembly, itself comprising one or more memory units, each having a fixed number of memory locations on which computer data can be stored permanently. During computer processing, the ALUs receive data from the memory units as input and provide data as output which are, in turn, stored on the memory units. It is then understood that, in addition to the number of ALUs, the number of memory units is another determining criterion for the computing power of the device.

[0004] Data routing between the ALUs and the memory units, in both directions, is provided by a device bus. The term "bus" is used here in its general sense of a data transfer system (or interface) including hardware (interface circuit) and the protocols governing the exchanges. The bus transmits the data itself, addresses and control signals. Each bus also has hardware and software limitations so that data routing is limited. In particular, the bus has a limited number of ports on the memory unit side and a limited number of ports on the ALUs side. In the present context, it is considered that the memory units are single-port, that is to say that the read and write operations are implemented during different cycles, as opposed to so-called "dual-port" memories (more expensive in terms of surface area and requiring larger duplicated control buses for writing and reading).Thus, during a calculation cycle, a memory location is accessible via the bus in a single direction (“read” or “write”). Furthermore, during a calculation cycle, a memory location is accessible for a single ALU. Alternatively, the proposed technical solutions can be implemented with so-called “dual-port” memories. In such embodiments, reads and writes can be implemented during the same calculation cycle.

[0005] Between the bus and the ALUs, a computer device generally includes a set of registers and local memory units, which can be seen as memories distinct from the aforementioned memory units. To facilitate understanding, a distinction is made here between "registers", intended to store data as such, and "local memory units", intended to store memory addresses. Each register is assigned the ALUs of a PU. A PU is assigned several registers. The storage capacity of the registers is very limited compared to the memory units, but their content is directly accessible to the ALUs.

[0006] To perform the calculations, each ALU must generally, first, obtain the input data of the calculation, typically the two operands of an elementary calculation. A "read" operation from the corresponding memory location via the bus to import each of the two operands into a register is therefore implemented. Then, the ALU performs the calculation operation itself from the data in a register and exporting the result in the form of data into a register. Finally, a "write" operation is implemented to save, in a memory location, the result of the calculation. During such a write operation, the result stored in the register is saved into a memory location via the bus. Each of the operations consumes a priori one or more calculation cycles.

[0007] In known computing devices, it is common to try to execute several operations (or several instructions) during the same computation cycle, in order to reduce the total number of computation cycles and thus increase efficiency. This is called parallel "processing chains" or "pipelines". However, there are often many dependencies of the operations on each other. For example, it is impossible to perform an elementary computation until the operands have been read and are accessible on a register for the ALU. Implementing processing chains therefore involves checking the dependency of the operations (instructions) on each other, which is complex and therefore expensive.

[0008] Usually, several independent operations are implemented during the same calculation cycle. Generally, for a given ALU and during the same calculation cycle, it is possible to perform a calculation operation and a read or write operation. On the other hand, for a given ALU and during the same calculation cycle, it is impossible to perform both a read operation and a write operation (in the case of single-port memory devices). On the other hand, memory accesses (the bus) do not allow reading or writing operations to be performed for two ALUs distinct from each other during the same calculation cycle and for a given memory location.

[0009] To ensure that each ALU is as active as possible (without wasted computation cycles), it is therefore instinctive to try to achieve a situation in which, at each computation cycle, three memory locations are accessible for each of the ALUs: two intended to supply operands to two inputs of the ALU (read) and one to receive an elementary computation result from the ALU (write). Thus, the two read operations are selected to obtain (stored in a register) the operands necessary for the elementary computation to be implemented during the following computation cycle. To improve computational power, it is therefore instinctive to provide both a high number of ALUs and a proportional number of memory locations (e.g. at least three times more memory locations than ALUs).

[0010] However, increasing the number of ALUs and the number of memory devices increases the complexity of the interactions between these two types of elements. Increasing the number of ALUs in the device and the number of memory devices that can be connected to them leads to a non-linear increase in the complexity of the bus. Increasing the number of ALUs and the number of memory devices is therefore complex and expensive.

[0011] This disclosure improves the situation.

[0012] A computer device is proposed comprising: a plurality of arithmetic and logic units; a set of registers capable of supplying operand-type data to the inputs of said arithmetic and logic units and capable of being supplied with data from the outputs of said arithmetic and logic units; a memory; a memory interface via which data is transmitted and routed between the registers and the memory; a control unit configured to control the arithmetic and logic units according to a processing chain microarchitecture so that the arithmetic and logic units perform calculations in parallel with each other, the control unit being further arranged to control memory accesses via the memory interface.The controls generate: at least one cycle i including both the implementation of at least one first calculation by an arithmetic and logic unit and the downloading, from the memory to at least one register, of a first data set; at least one cycle ii, subsequent to the at least one cycle i, including the implementation of a second calculation by an arithmetic and logic unit, second calculation for which at least part of the first data set forms at least one operand.

[0013] Such a device makes it possible to read, in a single operation, a set of data from a memory device and to store them temporarily in a register. All of the data read during a calculation cycle t may not all be used during the immediately subsequent calculation cycle t+1. In some cases at least, data among those read are useless during the cycle of said subsequent calculation t+1 but are used during a still later calculation cycle t+1+n without it being necessary to carry out an additional reading operation and therefore without consuming an additional calculation cycle.

[0014] In the field of parallel data processing by a computing device, the usual approach is to schedule a dedicated memory access to read each of the data necessary for the next elementary calculation to be implemented and only those necessary for the next elementary calculation. This usual approach could be called "just-in-time memory access". In such a usual approach, it is considered unnecessary to read (and store in a register) a data that is not immediately necessary. Thus, each memory access operation is chronologically prior to the elementary calculation itself (imperative) but scheduled directly and only as a function of the next elementary calculation. The applicant has gone against the a priori of the field by implementing a different approach.

[0015] The applicant thus proposes an approach in which, at each reading operation, the number of data read is greater than the number of data strictly necessary for the implementation of the next calculation. Such an approach could, by contrast, be called "predictive memory access". It is then possible that a piece of data among the data read is used for a future calculation, other than the calculation implemented immediately after reading. In such cases, the necessary data were obtained during a single memory access operation (with an increase in the memory bandwidth) whereas the usual approach would have required at least two separate memory accesses. The approach proposed by the applicant therefore has the effect, at least in certain cases, of reducing the consumption of calculation cycles for memory accesses and therefore makes it possible to improve the efficiency of the device.In the long term (several consecutive calculation cycles) the number of memory accesses (reading and / or writing) is reduced.

[0016] This approach does not exclude losses: some of the data read and stored in a register may be lost (overwritten by other data subsequently stored in the same register) before even being used in a calculation. Nevertheless, over a large number of calculations and calculation cycles, the applicant observed an improvement in performance, including in the absence of selection of the sets of data read. In other words, even in the absence of selection of the data read (or random selection) this approach statistically improves the efficiency of the computing device compared to the usual approach.

[0017] According to another aspect, there is provided a data processing method implemented by a control unit of a computing device, said device comprising: a plurality of arithmetic and logic units; a set of registers capable of supplying operand-type data to the inputs of said arithmetic and logic units and capable of being supplied with data from the outputs of said arithmetic and logic units; a memory; a memory interface via which data is transmitted and routed between the registers and the memory; the control unit configured to control the arithmetic and logic units according to a processing chain microarchitecture so that the arithmetic and logic units perform calculations in parallel with each other, the control unit being further arranged to control memory accesses via the memory interface; The method comprises at least: generating a cycle i including both the implementation of at least a first calculation by an arithmetic and logic unit and the downloading, from the memory to at least one register, of a first data set; generating a cycle ii, subsequent to cycle i, including the implementation of a second calculation by an arithmetic and logic unit, second calculation for which at least part of the first data set forms at least one operand.

[0018] According to another aspect, there is provided a computer program, in particular a compilation program, comprising instructions for implementing all or part of a method as defined herein when this program is executed by a processor. According to another aspect, there is provided a non-transitory recording medium, readable by a computer, on which such a program is recorded.

[0019] The following features may optionally be implemented. They may be implemented independently of each other or in combination with each other: The control unit is further configured to, prior to controlling the arithmetic units and the memory accesses, implement an algorithm for identifying the first data set to be downloaded during the at least one cycle i as a function of the second calculation to be implemented during the at least one cycle ii. This makes it possible to adapt the data read as a function of the calculations to be performed and therefore to improve the relevance of the data of the first downloaded data set. The control unit is configured to implement two cycles i distinct from each other so that two first data sets distinct from each other are downloaded to at least one register, at least a portion of each of the two first data sets forming an operand of the second calculation of the at least one cycle ii. This makes it possible, during said at least two cycles, to accumulate the calculations and the memory accesses.Thus, at the end of the two cycles i, all the operands necessary for the following calculations may have been downloaded. The control unit is configured to implement a plurality of cycles ii distinct from one another, and such that the part of the first data set forming at least one operand of the second calculation of a cycle ii is different from one cycle ii to another cycle ii of the plurality. This makes it possible to implement several elementary calculations for a single downloaded data set. The control unit is configured to carry out at least two iterations of a series of at least one cycle i, and one cycle ii, said two iterations being at least partly superimposed such that at least one cycle ii of the first iteration constitutes a cycle i of the following iteration. This makes it possible to carry out calculations and memory accesses over a particularly limited number of calculation cycles, and thus to further increase efficiency.The control unit is configured to precede a first cycle i with an initialization phase including the downloading, from the memory to at least one register, of at least one data set forming operands for the first calculation of said first cycle i. This makes it possible to initialize the method and then repeat cycles i and ii as many times as necessary for each of the data sets to be processed. The control unit is further arranged to control the memory accesses via the memory interface so that said controls generate: during a cycle i, the implementation of a plurality of first calculations by a plurality of arithmetic and logic units; during a cycle ii, the implementation of a plurality of second calculations by a plurality of arithmetic and logic units, . the grouping of the data by data set to be downloaded being selected in correspondence with a distribution of the allocations of the calculation operations to each of the arithmetic and logic units of the plurality so that said arithmetic and logic units have a synchronous, asynchronous or mixed operation. This makes it possible to further improve efficiency by adapting the coordinated operation of the ALUs according to the processing to be carried out and the available resources.

[0020] The invention is defined in the appended independent claims, to which reference should be made. Advantageous features are set out in the appended dependent claims.

[0021] Other characteristics, details and advantages of the invention will appear on reading the detailed description below, and on analyzing the attached drawings, in which: there figure 1 shows an architecture of a computing device according to the invention; the figure 2 is a partial representation of an architecture of a computing device according to the invention; and the figure 3 represents an example of memory access according to the invention; and the figure 4 is a variation of the example of the figure 3 .

[0022] The drawings and the description below contain, for the most part, elements of a certain character. They may therefore not only serve to better understand the present invention, but also contribute to its definition, if necessary.

[0023] There figure 1 shows an example of a computer device 1. The device 1 comprises a set of one or more processors 3, sometimes called central processing units or CPUs. The set of processor(s) 3 comprises at least one control unit 5 and at least one processing unit 7, or PU 7 for “Processing Unit”. Each PU 7 comprises one or more computing units called arithmetic and logic units 9, or ALU 9 for “Arithmetic-Logic Unit”. In the example described here, each PU 7 further comprises a set of registers 11. The device 1 comprises at least one memory 13 capable of interacting with the set of processor(s) 3. For this purpose, the device 1 further comprises a memory interface 15, or “Bus”.

[0024] In the present context, it is considered that the memory organs are single-port, that is to say that the reading and writing operations are implemented during different cycles, as opposed to so-called “dual-port” memories (more expensive in terms of surface area and requiring wider split control buses for writing and reading). Alternatively, the proposed technical solutions can be implemented with so-called “dual-port” memories. In such embodiments, readings and writings can be implemented during the same calculation cycle.

[0025] In figure 1 , three PU 7 are represented: PU 1, PU X and PU N. Only the structure of PU X is represented in detail in order to simplify the figure 1 . However, the structures of the PUs are similar to each other. In variants, the number of PUs is different. The device 1 may comprise a single PU, two PUs or more than three PUs.

[0026] In the example described here, the PU X comprises four ALUs: ALU X.0, ALU X.1, ALU X.2 and ALU X.3. In variants, the PUs may comprise a number of ALUs different from each other and / or different from four, including a single ALU. Each PU comprises a set of registers 11, here at least one register 11 allocated to each ALU. In the example described here, the PU X comprises a single register 11 per ALU, i.e. four registers referenced REG X.0, REG X.1, REG X.2 and REG X.3 and allocated respectively to ALU X.0, ALU X.1, ALU X.2 and ALU X.3. In variants, each ALU is allocated a plurality of registers 11.

[0027] Each register 11 is capable of supplying operand-type data to the inputs of said ALUs 9 and is capable of being supplied with data from the outputs of said ALUs 9. Each register 11 is, in addition, capable of storing data from the memory 13 obtained via the bus 15 by a so-called “read” operation. Each register 11 is, in addition, capable of transmitting stored data, to the memory 13 and via the bus 15, by a so-called “write” operation. The read and write operations are managed by controlling the memory accesses from the control unit 5.

[0028] The control unit 5 imposes on each ALU 9 the manner of carrying out elementary calculations, in particular their order, and assigns to each ALU 9 the operations to be executed. In the example described here, the control unit 5 is configured to control the ALUs 9 according to a processing chain microarchitecture so that the ALUs 9 carry out calculations in parallel with each other. For example, the device 1 has a Single instruction stream and multiple data stream architecture, called SIMD for “Single Instructions Multiple Data”, and / or a Multiple instruction stream and multiple data stream architecture, called MIMD for “Multiple Instructions Multiple Data”. Furthermore, the control unit 5 is further arranged to control memory accesses via the memory interface 15 and in particular, here, the read and write operations. The two types of control (calculation and memory access) are represented, in figure 1 , by broken arrows.

[0029] Reference is now made to the figure 2 , on which a single ALU Y is represented. Data transmissions are represented by solid arrows. Since data transmission is carried out step by step, we understand that the figure 2 does not necessarily represent an instant t with simultaneous data transmissions. On the contrary, for data to be transmitted from a register 11 to an ALU 9, it is for example necessary that said data be previously transmitted to said register 11 from memory 13, here via memory interface 15 (or Bus).

[0030] In the example of the figure 2 , three registers 11, referenced respectively REG Y.0, REG Y.1 and REG Y.2, are assigned an ALU referenced ALU Y. Each ALU 9 has at least three ports, namely two inputs and one output. For each operation, at least two operands are received, respectively by the first and second input. The result of the calculation is emitted via the output. In the example shown in figure 2 , the operands received as input come respectively from the register REG Y.0 and the register REG Y.2. The result of the calculation is written to the register REG Y.1. Once written to the register REG Y.1, the result (in the form of data) is written to memory 13, via the memory interface 15. In variants, at least one ALU can have more than two inputs and receive more than two operands for a calculation.

[0031] Each ALU 9 can perform: arithmetic operations on integer data (addition, subtraction, multiplication, division, etc.); arithmetic operations on floating-point data (addition, subtraction, multiplication, division, inversion, square root, logarithms, trigonometry, etc.); logical operations (two's complement, "AND", "OR", "exclusive OR", etc.).

[0032] The ALUs 9 do not exchange data directly with each other. For example, if the result of a first calculation performed by a first ALU constitutes an operand for a second calculation to be performed by a second ALU, then the result of the first calculation must at least be written to a register 11 before it can be used by an ALU 9.

[0033] In embodiments, the data written to a register 11 are further systematically written to memory 13 (via the memory interface 15), even if said data is obtained only to serve as an operand and not as a result of a processing process as a whole.

[0034] In embodiments, the data obtained to serve as an operand and having a short relevance (intermediate result without interest at the end of the processing as a whole) are not systematically written in memory 13 and can be stored only temporarily in a register 11. For example, if the result of a first calculation carried out by a first ALU constitutes an operand for a second calculation to be carried out by a second ALU, then the result of the first calculation must be written in a register 11. Then, said data is transmitted to the second ALU as an operand directly from the register 11. It is then understood that the allocation of a register 11 to an ALU 9 can change over time and in particular from one calculation cycle to another.This allocation may in particular take the form of addressing data which makes it possible to locate, at any time, the location of a piece of data, whether in a register 11 or in a location in the memory 15.

[0035] In the following, the operation of the device 1 is described for processing applied to computer data, the processing being composed of a set of operations, including calculations performed in parallel by a plurality of ALUs 9 during a period of time consisting of a sequence of calculation cycles. It is then said that the ALUs 9 operate according to a processing chain microarchitecture. Nevertheless, the processing implemented by the device 1 and which is in question here may, itself, constitute a part (or a subset) of a more global computer process. Such a more global process may comprise, in other parts or subsets, calculations performed in a non-parallel manner by a plurality of ALUs, for example according to a serial operation, or in cascade.

[0036] The operating architectures (parallel or serial) may be constant or dynamic, for example imposed (driven) by the control unit 5. The architectural variations may for example be a function of the data to be processed and the current instructions received as input from the device 1. Such dynamic adaptation of the architectures may be implemented from the compilation stage, by adapting the machine instructions generated by the compiler according to the type of data to be processed and the instructions when the type of data to be processed and the instructions can be deduced from the source code. Such adaptation may also be implemented only at the level of the device 1, or of a processor, when it executes a conventional machine code and is programmed to implement a set of configuration instructions depending on the data to be processed and the current instructions received.

[0037] The memory interface 15, or "bus", transmits and routes data between the ALUs 9 and the memory 15, in both directions. The memory interface 15 is controlled by the control unit 5. Thus, the control unit 5 controls access to the memory 13 of the device 1 via the memory interface 15.

[0038] The control unit 5 controls in a coordinated manner the operations (calculations) implemented by the ALUs 9 and the memory accesses. The control of the control unit 5 comprises the implementation of a succession of operations broken down into calculation cycles. The control comprises the generation of a first cycle i and a second cycle ii. Chronologically, the first cycle i is prior to the second cycle ii. As will be described in more detail in the examples below, the second cycle ii may be immediately subsequent to the first cycle i, or the first cycle i and the second cycle ii may be chronologically spaced from each other, for example with intermediate cycles.

[0039] The first cycle i includes: the implementation of a first calculation by at least one ALU 9; and the downloading, from the memory 13 to at least one register 11, of a first data set.

[0040] The second cycle ii comprises the implementation of a second calculation by at least one ALU 9. The second calculation may be implemented by the same ALU 9 as the first calculation or by a separate ALU 9. At least a portion of the first data set downloaded during the first cycle i forms an operand for the second calculation.

[0041] Reference is now made to the figure 3 . Data, or blocks of data, are referenced respectively A0 to A15 and are stored in memory 13. In the example, it is considered that data A0 to A15 are grouped by four in the following manner: a dataset referenced AA0_3 consisting of data A0, A1, A2 and A3; a dataset referenced AA4_7 consisting of data A4, A5, A6 and A7; a dataset referenced AA8_11 consisting of data A8, A9, A10 and A11; and a dataset referenced AA12_15 consisting of data A12, A13, A14 and A15.

[0042] Alternatively, the data may be grouped differently, in particular by group (or “block”, or “slot”) of two, three or more than four. A data set may be seen as a group of data accessible on the memory 13 via a single port of the memory interface 15 during a single read operation. Similarly, the data of a data set may be written to memory 13 via a single port of the memory interface 15 during a single write operation.

[0043] Thus, during a first cycle i, at least one data set AA0_3, AA4_7, AA8_11 and / or AA12_15 is downloaded to at least one register 11. In the example of the figure, each of the data sets AA0_3, AA4_7, AA8_11 and / or AA12_15 is downloaded to a respective register 11, i.e. four registers 11 distinct from each other. Each of the registers 11 is allocated at least temporarily to a respective ALU 9, here referenced respectively ALU 0, ALU 1, ALU 2 and ALU 3. During this same cycle i, the ALUs 9 may have implemented a calculation.

[0044] During a second cycle ii, each ALU 9 implements a calculation for which at least one of the data stored on the corresponding register 11 forms an operand. For example, ALU 0 implements a calculation for which one of the operands is A0. A1, A2 and A3 may be unused during the second cycle ii.

[0045] Generally speaking, downloading data from memory 13 to a register 11 consumes less computation time than implementing computations by ALUs 9. Thus, it can generally be considered that a memory access operation (here a reading) consumes a single computation cycle, while the implementation of a computation by an ALU 9 consumes one computation cycle or a succession of several computation cycles, for example four.

[0046] In the example of the figure 3 , there are a plurality of registers 11 allocated to each ALU 9, represented by groups of registers 11 referenced REG A, REG B and REG C. The data downloaded from the memory 13 to the registers 11 correspond to the groups REG A and REG B. The group REG C is here intended to store data obtained by calculations implemented by the ALUs 9 (during a write operation).

[0047] Registers 11 of groups REG B and REG C can thus contain data sets referenced in a manner similar to those of REG A: the group REG B comprises four registers 11 on which are respectively stored a data set BB0_3 consisting of data B0 to B3, a data set BB4_7 consisting of data B4 to B7, a data set BB8_11 consisting of data B8 to B11 and a data set BB12_15 consisting of data B12 to B15; the group REG C comprises four registers 11 on which are respectively stored a data set CC0_3 consisting of data C0 to C3, a data set CC4_7 consisting of data C4 to C7, a data set CC8_11 consisting of data C8 to C11 and a data set CC12_15 consisting of data C12 to C15.

[0048] In the example of the figure 3 , the data AN and BN constitute the operands of a calculation implemented by an ALU 9 while the data CN constitutes the result, with "N" an integer between 0 and 15. For example, in the case of an addition, CN = AN + BN. In such an example, the data processing implemented by the device 1 corresponds to 16 operations. The 16 operations are independent of each other in the sense that none of the results of the 16 operations is necessary to implement one of the other 15 operations.

[0049] The implementation of the treatment (the 16 operations) can therefore, for example, be broken down as follows, into 18 cycles. Exemple 1 :

[0050] cycle #0: reading AA0_3; cycle #1: reading BB0_3; cycle #2: calculating C0 (from set CC0_3) and reading AA4_7 (forming for example a cycle i); cycle #3: calculating C1 (from set CC0_3) and reading BB4_7 (forming for example a cycle i); cycle #4: calculating C2 (from set CC0_3); cycle #5: calculating C3 (from set CC0_3) and writing CC0_3; cycle #6: calculating C4 (from set CC4_7) and reading AA8_11 (forming for example a cycle ii); cycle #7: calculating C5 (from set CC4_7) and reading BB8_11 (forming for example a cycle ii); cycle #8: calculating C6 (from set CC4_7) (forming for example a cycle ii); cycle #9: calculation of C7 (from the set CC4_7) and writing of CC4_7 (forming for example a cycle ii); cycle #10: calculation of C8 (from the set CC8_11) and reading of AA12_15; cycle #11: calculation of C9 (from the set CC8_11) and reading of BB12_15; cycle #12: calculation of C10 (from the set CC8_11); cycle #13: calculation of C11 (from the set CC8_11) and writing of CC8_11; cycle #14: calculation of C12 (from the set CC12_15);cycle #15: calculation of C13 (from the set CC12_15); cycle #16: calculation of C14 (from the set CC12_15); cycle #17: calculation of C15 (from the set CC12_15) and writing of CC12_15. ;

[0051] We then understand that, with the exception of the initial cycles #0 and #1, memory accesses (reads and writes) are implemented in parallel with the calculations, without consuming an additional calculation cycle. Reading sets of (several) data, or blocks of data, rather than reading a single data item, makes it possible to complete the import of data from memory 13 onto the registers even before said data becomes necessary, as an operand, for a calculation.

[0052] In the example of cycle #2 above, if only the immediately needed data (A0) had been read rather than reading the set AA0_3 = {A0; A1; A2; A3}, then it would have been necessary to implement, later, three additional read operations to obtain A1, A2 and A3.

[0053] To better understand, and for comparison, we reproduce below the implementation of a processing in which a single data item is read each time rather than a set of (several) data. We note that 48 cycles are necessary. Exemple 0 :

[0054] cycle #0: reading A0; cycle #1: reading B0; cycle #2: calculating C0 and writing C0; cycle #3: reading A1; cycle #4: reading B1; cycle #5: calculating C1, writing C1; ... cycle #45: reading A15; cycle #46: reading B15; cycle #47: calculating C15 and writing C15.

[0055] In example 1 (18 cycles), we notice that the first two cycles #0 and #1 constitute initialization cycles. The number I of initialization cycles corresponds to the number of operands per calculation. Then a pattern of four successive cycles is repeated four times. For example, cycles #2 to #5 together form a pattern. The number of cycles per pattern corresponds to the number D of data per data set while the number of patterns corresponds to the number E of data sets to be processed. The total number of cycles can therefore be expressed as follows: I + D*E.

[0056] Achieving good performance is equivalent to minimizing the total number of cycles. Under the conditions considered, i.e. 16 elementary and independent operations each of which can be implemented in one cycle, the optimum number of cycles therefore seems to be equal to the number of elementary operations (16) to which is added the initialization phase (2 cycles), i.e. a total of 18 cycles.

[0057] In a variant, we consider that the number of data accessible (read or write) in a single cycle (the number D of data per data set) is equal to three (and no longer four), for example because of hardware limitations. Then, the succession of cycles can, for example, be broken down as follows: an initialization phase of 2 cycles; then 5 patterns of 3 cycles for a total of 15 elementary calculations out of the 16 to be carried out; then a final cycle to calculate and save the result of the last elementary calculation. Exemple 2 :

[0058] cycle #0: reading AA0_2={A0; A1; A2}; cycle #1: reading BB0_2={B0; B1; B2}; cycle #2: calculating C0 (from the set CC0_2={C0; C1; C2}) and reading AA3_5 (forming for example a cycle i); cycle #3: calculating C1 (from the set CC0_2) and reading BB3_5 (forming for example a cycle i); cycle #4: calculating C2 (from the set CC0_2) and writing CC0_2; cycle #5: calculating C3 (from the set CC3_5) and reading AA6_8 (forming for example a cycle ii); cycle #6: calculating C4 (from the set CC3_5) and reading BB6_8 (forming for example a cycle ii); cycle #7: calculation of C5 (from the set CC3_5) and writing of CC3_5 (forming for example a cycle ii); cycle #8: calculation of C6 (from the set CC6_8) and reading of AA9_11; cycle #9: calculation of C7 (from the set CC6_8) and reading of BB9_11; cycle #10: calculation of C8 (from the set CC6_8) and writing of CC6_8; cycle #11: calculation of C9 (from the set CC9_11) and reading of AA12_14; cycle #12: calculation of C10 (from the set CC9_11) and reading of BB12_14;cycle #13: calculation of C11 (from set CC9_11) and writing of CC9_11; cycle #14: calculation of C12 (from set CC12_14) and reading of A15 (forming for example a cycle i); cycle #15: calculation of C13 (from set CC12_14) and reading of B15 (forming for example a cycle i); cycle #16: calculation of C14 (from set CC12_14) and writing of CC12_14; cycle #17: calculation of C15 (isolated data) and writing of C15 (forming for example a cycle ii). ;

[0059] In example 2, we see that each cycle includes a memory access operation (read or write). We therefore understand that, if the number D of data accessible in a single cycle is strictly less than three, then additional cycles will be necessary to perform memory accesses. The optimum of 18 cycles for 16 elementary operations will therefore no longer be reached. However, even if the optimum is not reached, the number of cycles remains significantly lower than the number of cycles necessary in example 0. An embodiment in which the data sets include two data presents an improvement compared to the existing one.

[0060] In example 1, if cycles #2 and / or #3 correspond for example to a cycle i as defined above, then each of cycles #6, #7, #8 and #9 corresponds to a cycle ii. Of course, this is transposable from motif to motif. In example 2, if cycles #2 and / or #3 correspond for example to a cycle i as defined above, then each of cycles #5, #6 and #7 corresponds to a cycle ii. Of course, this is transposable from motif to motif.

[0061] In the examples described so far, in particular examples 1 and 2, the low total number of cycles is achieved in particular because a maximum number of memory access operations is implemented per set of (several) data rather than individually and in parallel with calculation operations. Thus, for certain parts of the process (for all parts in the optimized examples), the reading of all the necessary operands can be completed even before the preceding elementary calculation operation is completed. Preferably, computing power is preserved to perform a calculation and save (write operation) the result of said calculation in a common calculation cycle (cycle #5 of example 1 for example).

[0062] In the examples, reading operand data in advance is implemented throughout the process (repeated from one pattern to another). The operands necessary for the calculations performed during a pattern are systematically obtained (read) during the chronologically previous pattern. It will be noted that, in degraded embodiments, reading in advance is implemented only partially (for two successive patterns only). Such a degraded mode compared to the examples above presents better results than existing methods.

[0063] In the examples described so far, it has been assumed that the data were read before being used as operands. In embodiments, the data read in advance are read randomly, or at least independently of the calculations to be performed in the future. Thus, at least some of the data read in advance from among the data sets actually correspond to operands for later calculations while other data read are not operands for later calculations. For example, at least some of the data read may subsequently be erased from the registers 11 without having been used by the ALUs 9, typically overwritten by other data subsequently recorded on the registers 11. Some data is therefore read unnecessarily (and recorded unnecessarily on the registers 11).However, it is sufficient that at least some of the data among the data sets read are actually operands for a saving in calculation cycle to occur, and therefore for the situation to be improved compared to the existing situation. Also, depending on the number of data to be processed and the number of cycles, it is probable (in the mathematical sense of the term), that at least some of the pre-read data can actually be used as operands in a calculation carried out by an ALU 9 in a following cycle.

[0064] In embodiments, the data read in advance are preselected, and depend on the calculations to be performed. This improves the relevance of the pre-read data. Indeed, in the examples with 16 elementary calculations above, each of the 16 elementary calculations requires as input a pair of operands, respectively A0 and B0; A1 and B1; ...; A15 and B15. If the data are read randomly, then the first two cycles could correspond to the reading of AA0_3 and BB4_7. In such a case, no complete pair of operands is available on the registers 11 at the end of the first two cycles. Consequently, the ALUs 9 cannot implement any elementary calculation in the following cycle. One or more additional cycles would therefore necessarily be consumed for memory access before the elementary calculations can begin, which increases the total number of cycles and is therefore detrimental to efficiency.

[0065] Relying on chance and probability to ensure that the data obtained from reading are as relevant as possible is sufficient to improve the existing situation, but it is not entirely satisfactory. The situation can still be improved.

[0066] Implementing a prefetch algorithm allows you to obtain, as soon as possible, all the operands for the next calculation to be performed. In the example above, reading AA0_3 and BB0_3 during the first two cycles allows, for example, to make available, on registers 11, all the operands necessary for the implementation of the first 4 elementary calculations.

[0067] Such an algorithm receives as input parameters information data relating to the calculations to be carried out subsequently by the ALUs 9, and in particular relating to the necessary operands. Such an algorithm makes it possible, at output, to select the data read (by set) in anticipation of the future calculations to be carried out. Such an algorithm is, for example, implemented by the control unit 5 when controlling memory accesses.

[0068] According to a first approach, the algorithm imposes an organization of the data as soon as they are recorded in the memory 13. For example, the data that one wishes to see together form a data set are juxtaposed and / or ordered so that the entire data set can be called by a single request. For example, if the addresses of the data A0, A1, A2 and A3 are referenced respectively @A0 @A1, @A2, @A3, then the memory interface 15 can be configured to, in response to a read request on @A0, also automatically read the data at the following three addresses @A1, @A2 and @A3.

[0069] According to a second approach, the prefetching algorithm provides memory access requests as output adapted according to the calculations to be carried out subsequently by the ALUs 9, and in particular relating to the necessary operands. In the previous examples, the algorithm identifies for example that the data to be read as a priority are those of AA0_3 and BB0_3 to make possible, from the following cycle, the elementary calculations resulting in CC0_3, i.e. the calculation of C0 with the operands A0 and B0, the calculation of C1 with the operands A1 and B1, the calculation of C2 with the operands A2 and B2 and the calculation of C3 with the operands A3 and B3. The algorithm therefore provides, as output, memory access requests constructed to generate the reading of AA0_3 and BB0_3.

[0070] The two approaches can, optionally, be combined with each other: the algorithm identifies the data to be read and the control unit 5 deduces memory access requests to the memory interface 15 to obtain said data, the requests being adapted according to the characteristics (structure and protocol) of the memory interface 15.

[0071] In the preceding examples, in particular examples 1 and 2 above, the number of ALUs assigned to the elementary calculations is not defined. A single ALU 9 can perform all the elementary calculations, cycle by cycle. The elementary calculations to be performed can also be distributed over a plurality of ALUs 9 of a PU, for example four. In such cases, coordinating the distribution of the calculations on the ALUs with the manner of grouping the data to be read at each read operation can make it possible to further improve efficiency. Two approaches can be distinguished.

[0072] In a first approach, the data read in one operation form operands in calculations implemented by a single ALU 9. For example, the groups AA0_3 and BB0_3 of data A0, A1, A2, A3, B0, B1, B2 and B3 are read first and a first ALU is responsible for calculating CC0_3 (C0, C1, C2 and C3). The groups AA4_7 (A4, A5, A6, A7) and BB4_7 (B4, B5, B6 and B7) are read next and a second ALU is responsible for calculating CC4_7 (C4, C5, C6 and C7). We then understand that the first ALU will be able to start implementing the calculations before the second ALU can do the same because the operands necessary for the calculations of the first ALU will be available on registers 11 before the operands necessary for the calculations of the second ALU are available. The ALUs 9 of a PU then operate in parallel and asynchronously.

[0073] In a second approach, the data read in one operation form operands in calculations each implemented by different ALUs 9, for example four. For example, two groups of data including respectively A0, A4, A8 and A12; B0, B4, B8 and B12 are read first. A first ALU is responsible for calculating C0, a second ALU is responsible for calculating C4, a third ALU is responsible for calculating C8 and a fourth ALU is responsible for calculating C12. It is then understood that the four ALUs will be able to start implementing their respective calculations in a substantially simultaneous manner, because the necessary operands will be available on the registers 11 at the same time because downloaded in a common operation. The ALUs 9 of a PU operate in parallel and synchronized manner. Depending on the types of calculations to be performed, the accessibility of the data in memory and the available resources, one or the other of the two approaches may be preferred.The two approaches can also be combined: ALUs can be organized into subgroups, with the ALUs in a subgroup operating synchronously and the subgroups operating asynchronously with respect to each other.

[0074] To enforce synchronized, asynchronous, or mixed operation of ALUs, the grouping of data to be read per read operation must be selected in correspondence with the distribution of the allocations of computation operations to various ALUs.

[0075] In the previous examples, the elementary calculations are independent of each other. The order in which they are performed therefore has no a priori no matter. In applications where at least some of the computations are dependent on each other, the scheduling of the computations may be specific. Such a situation typically arises in the context of recursive computations. In such cases, the algorithm can be configured to identify the data to be acquired (read) first. For example, if: the result C1 is obtained by a calculation one of whose operands is C0, C0 itself being obtained from the operands A0 and B0, the result C5 is obtained by a calculation one of whose operands is C4, C4 itself being obtained from the operands A4 and B4, the result C9 is obtained by a calculation one of whose operands is C8, C8 itself being obtained from the operands A8 and B8, and the result C13 is obtained by a calculation one of whose operands is C12, C12 itself being obtained from the operands A12 and B12, then the algorithm can be configured to read, during the first two initialization cycles #0 and #1, the data sets defined as follows: {A0; A4; A8; A12}, and {B0; B4; B8; B12}.

[0076] The dataset thus defined is represented in figure 4 . Figuratively, we can say that the data are grouped "online" in the embodiment shown in figure 3 and grouped “in a column” in the embodiment shown in figure 4 . Thus, the implementation of the algorithm makes it possible to read and make available on registers 11, the operands useful for the elementary priority calculations. In other words, the implementation of the algorithm makes it possible to increase the short-term relevance of the data read compared to a random reading.

[0077] The invention is not limited to the examples of processing units and methods described above, solely by way of example, but it encompasses all the variants that may be envisaged by those skilled in the art within the framework of the protection sought defined in the attached claims, to which reference should be made.

Claims

1. A computing device (1) comprising: - a plurality of arithmetic logic units (9); - a set of registers (11) able to supply data of operand type to the inputs of said arithmetic logic units (9) and able to be supplied with data from the outputs of said arithmetic logic units (9); - a memory (13); - a memory interface (15) by way of which data (A0, A15) are transmitted and routed between the registers (11) and the memory (13); - a control unit (5) configured so as to control the arithmetic logic units (9) in accordance with a processing chain microarchitecture such that the arithmetic logic units (9) perform computing operations in parallel with one another, characterized in that the control unit (5) furthermore is designed to control the memory access operations by way of the memory interface (15), said control operations generating: - at least one cycle i including both implementing in parallel at least one first computing operation by way of an arithmetic logic unit (9) and downloading a first dataset (AA4_7; BB4_7) from the memory (13) to at least one register (11), at least part of this first dataset (AA4_7; BB4_7) not being used by any computing operation by way of the arithmetic logic units (9) during this cycle i; - at least one cycle ii, following the at least one cycle i, including implementing a second computing operation by way of an arithmetic logic unit (9), for which second computing operation at least this part (A4; B4) of the first dataset (AA4_7; BB4_7) forms at least one operand.

2. The device as claimed in claim 1, wherein the control unit (5) is furthermore configured, prior to controlling the arithmetic units and the memory access operations, so as to implement an identification algorithm for identifying the first dataset (AA4_7; BB4_7) to be downloaded during the at least one cycle i on the basis of the second computing operation to be implemented during the at least one cycle ii.

3. The device as claimed in either of the preceding claims, wherein the control unit (5) is configured so as to implement two cycles i separate from one another, such that two first datasets (AA4_7, BB4_7) separate from one another are downloaded to at least one register (11), at least part (A4, B4) of each of the two first datasets (AA4_7, BB4_7) forming an operand for the second computing operation of the at least one cycle ii.

4. The device as claimed in one of the preceding claims, wherein the control unit (5) is configured so as to implement a plurality of cycles ii separate from one another, and such that the part (A4; A5; A6; A7) of the first dataset (AA4_7) forming at least one operand for the second computing operation of a cycle ii is different from one cycle ii to another cycle ii of the plurality.

5. The device as claimed in one of the preceding claims, wherein the control unit (5) is configured so as to perform at least two iterations of a series of at least one cycle i, and one cycle ii, said two iterations being at least partly superimposed such that at least one cycle ii of the first iteration forms a cycle i of the following iteration.

6. The device as claimed in one of the preceding claims, wherein the control unit (5) is configured so as to precede a first cycle i with an initialization phase including downloading, from the memory (13) to at least one register (11), at least one dataset (AA0_3; BB0_3) forming operands for the first computing operation of said first cycle i.

7. The device as claimed in one of the preceding claims, wherein the control unit (5) is furthermore designed to control the memory access operations by way of the memory interface (15), such that said control operations generate: - during a cycle i, the implementation of a plurality of first computing operations by a plurality of arithmetic logic units (9); - during a cycle ii, the implementation of a plurality of second computing operations by a plurality of arithmetic logic units (9), the grouping of the data per dataset to be downloaded being selected so as to match a distribution of the assignments of the computing operations to each of the arithmetic logic units (9) of the plurality, such that said arithmetic logic units (9) have synchronized, asynchronous or mixed operation.

8. A data processing method implemented by a control unit (5) of a computing device (1), said device (1) comprising: - a plurality of arithmetic logic units (9); - a set of registers (11) able to supply data of operand type to the inputs of said arithmetic logic units (9) and able to be supplied with data from the outputs of said arithmetic logic units (9); - a memory (13); - a memory interface (15) by way of which data (A0, A15) are transmitted and routed between the registers (11) and the memory (13); - the control unit (5) configured so as to control the arithmetic logic units (9) in accordance with a processing chain microarchitecture such that the arithmetic logic units (9) perform computing operations in parallel with one another, characterized in that the control unit (5) furthermore is designed to control the memory access operations by way of the memory interface (15); said method comprising at least: - generating a cycle i including both implementing at least one first computing operation by way of an arithmetic logic unit (9) and downloading a first dataset (AA4_7; BB4_7) from the memory (13) to at least one register (11); - generating a cycle ii, following the cycle i, including implementing a second computing operation by way of an arithmetic logic unit (9), for which second computing operation at least part (A4; B4) of the first dataset (AA4_7; BB4_7) forms at least one operand.

9. A computer program comprising instructions for implementing the method as claimed in claim 8 when this program is executed by a computer device according to claim 1.

10. A non-transient computer-readable recording medium on which there is recorded a program for implementing the method as claimed in claim 8 when this program is executed by a computer device according to claim 1.