METHOD FOR PREPARING AN EXTENDED SUBSTRATE AND EXTENDED SUBSTRATE

Description

FIELD OF INVENTION

[0001] The present invention relates to the field of realization of SOI type semiconductor components (abbreviation for Silicon on Insulator, or Silicon on Insulator), and in particular the field of realization of advanced substrates for hybrid integration of components configured for different applications or functionalities. STATE OF THE ART

[0002] A silicon-on-insulated (SOI) structure typically comprises an active silicon layer containing the actual components, beneath which lies a buried silicon oxide layer. This layer provides insulation against parasitic currents and charges from ionized particles. It also ensures good isolation of neighboring components within the same silicon layer, and in particular, significantly reduces parasitic capacitance between such neighboring components. The SOI itself rests on a silicon substrate, which acts as a mechanical support.

[0003] This type of substrate is generally produced using the Smart Cut™ process, which includes the following steps: provision of a support substrate, provision of a single-crystal silicon donor substrate, formation of a weakening zone in the donor substrate, to delimit the future active layer (the weakening zone can be formed by implanting atomic species at a determined depth of the donor substrate), bonding of the first donor substrate to the support substrate, after forming an oxide layer on the support substrate or on the donor substrate or both, the oxide layer being intended to form the buried oxide layer, detachment of the first donor substrate along the weakening zone, leading to the transfer of the active layer onto the support substrate.performing a finishing treatment on the transferred layer, to repair or remove defects related to the detachment step and to give said layer the optimal roughness and thickness characteristics to obtain the final SOI type substrate on which the intended components will be integrated.

[0004] The finishing process typically involves either heat treatments to correct defects from the implantation and detachment process, followed by chemical-mechanical polishing to improve the surface roughness of the transferred layer while helping to achieve its thickness at the target value; or heat treatments to achieve the target thickness of the transferred layer, followed by additional heat treatments at high temperatures, typically above 1100 °C, to smooth the surface of the active layer through thermo-activated diffusion of silicon atoms.

[0005] In general, the transferred active silicon layer typically has a thickness ranging from a few nanometers to several hundred nanometers, while the buried oxide layer has a thickness ranging from a few tens of nanometers to several hundred nanometers (typically 1000 nm) or more.

[0006] The thicknesses of the active layer and the buried oxide layer generally vary depending on the intended application. For example, the thickness of the silicon active layer is typically between approximately 3 and 40 nm, and that of the buried oxide layer is typically between approximately 10 and 40 nm, for substrates intended for fully depleted silicon-on-ion (SOI) components. Conversely, for substrates configured for radio frequency (RF) SOI components, the thicknesses of both the silicon active layer and the buried oxide layer are typically greater than approximately 50 nm.

[0007] Indeed, varying thicknesses of the buried silicon oxide layer allow for different degrees of insulation, leakage currents, voltage ratings, and equivalent capacitances—all parameters that can be chosen by the developer. Furthermore, one or more functional layers can be interposed between the buried oxide layer and the silicon substrate. This type of layer arrangement aims to limit self-polarization and distortions between components, transmitted through the substrate, particularly those induced by the strong electromagnetic radiation from radio-frequency components.

[0008] Therefore, for certain applications or functions, it will be preferable to select SOI type substrates with a thin buried silicon oxide layer, for example to make FDSOI type transistors, for other applications it will be preferable to select SOI type substrates with a thick buried silicon oxide layer and / or with an additional functional layer to make, for example, power components or radio frequency components.

[0009] Moreover, due to the industrial manufacturing processes known to those skilled in the art, the vast majority of SOI type substrates are "homogeneous," in other words, the thicknesses of the buried oxide layer and the active layer are constant over the entire substrate.

[0010] However, attempts are known to have been made to produce components by alternating "bulk" type areas and SOI type areas on the same substrate.

[0011] The article "Transistors on hybrid UTBB / Bulk substrates fabricated by local internal BOX dissolution" by P. Nguyen et al., published in "Solid State Electronics, Vol. 90, pp. 39-43, 2013", describes the fabrication of CMOS components on a hybrid SOI / bulk substrate obtained using the technique of internal and local dissolution of the buried oxide layer. However, this technique suffers from two major problems for industrial use.

[0012] Indeed, the dissolution process generates a poorly controlled transition between portions of the buried oxide layer that have different thicknesses. The transition zones between these portions are long (on the order of a few micrometers at best, due to the dissolution process used) and therefore incompatible with large-scale cointegration.

[0013] Furthermore, for a dissolved oxide layer thickness on the order of ten nm, the dissolution process generates significant non-uniformity in the buried oxide layer and, consequently, in the active layer on the insulator. This non-uniformity leads to discontinuities in electrical behavior between areas with different buried oxide layer thicknesses, which is detrimental to the proper functioning of the various components fabricated on this type of hybrid substrate. US2007 / 200144 proposes a fabrication process for a SOI with a patterned buried oxide layer. DESCRIPTION OF THE INVENTION

[0014] There is currently a need to provide a "monolithic" SOI-type substrate with a buried electrically insulating layer (or active layer) comprising at least two zones of different thicknesses, while ensuring: uniformity of thickness across different portion of the layers, optimal roughness, and an abrupt transition between different portion of the layers having varying thicknesses. compatible with the specifications for large-scale integration of different types of components on said monolithic substrate, including for example FDSOI type components.

[0015] There is also a need to provide a substrate fabrication process with the specifications mentioned above, which is easy to implement and compatible with specific donor and / or recipient substrates, for example, those containing trap-rich or doped layers. Indeed, this type of substrate requires limited thermal finishing budgets, particularly for smoothing the surface of the active layer on the insulation (processes such as rapid thermal annealing, as opposed to batch annealing or thermal batch annealing).

[0016] These needs are becoming increasingly important, particularly in the field of systems on chip or SoC (acronym for the Anglo-Saxon term "System on Chip") which integrate several functions on the same chip, or in the field of co-integration of digital components and radio frequency components, or even in the field of microsystems integrating, for example, sensors or accelerometers along with reading circuits.

[0017] We aim to satisfy these needs while avoiding the aforementioned drawbacks by developing a process for creating an advanced substrate that includes the following steps: a) Provide a receiving substrate and a donor substrate, said donor substrate comprising: A support substrate; An active layer of a single-crystal semiconductor material; and A sacrificial layer of a material that can be selectively etched with respect to the active layer, the sacrificial layer being interposed between the support substrate and the active layer; A silicon oxide layer having a free surface and arranged so that the active layer is interposed between the sacrificial layer and the oxide layer; b) Form a cavity in the oxide layer, the cavity having an opening flush with the free surface such that the oxide layer comprises a first portion having a first thickness e1 and arranged between the cavity and the active layer, and a second portion having a second thickness e2 greater than the first thickness e1, the second portion being arranged between the free surface and the active layer;c) Form a polycrystalline silicon filling layer so as to completely fill the cavity and form a second continuous and substantially flat free surface, comprising at least a first polycrystalline silicon surface; d) Assemble the receiving substrate and the donor substrate at the level of the second free surface; e) Remove the support substrate after step d) retaining the active layer and the sacrificial layer.

[0018] According to one embodiment, the process may include a step of selective etching of the sacrificial layer while preserving the active layer, after step e). Furthermore, the assembly step d) may include a step of bonding by molecular adhesion.

[0019] According to one embodiment, the process may further include the following steps: b0) Form, before step b) and after step a), a zone of embrittlement in the supporting substrate, the zone of embrittlement being substantially flat and located in the vicinity of the interface between the sacrificial layer and the supporting substrate; e0) Fracture the supporting substrate along the zone of embrittlement, after step d).

[0020] Furthermore, the sacrificial layer can be made of a material that can be selectively etched relative to the substrate material. Therefore, the remaining substrate, deposited on the sacrificial layer, can be selectively etched after the fracture step (e0). The filler layer can also be formed by chemical vapor deposition at a temperature between 150 °C and 250 °C.

[0021] According to one embodiment, the single-crystal silicon active layer can be produced by epitaxy. Furthermore, the active layer retained after step e) can be locally thinned so as to locally reduce the thickness of the active layer.

[0022] According to one embodiment, the filling layer can cover the silicon oxide layer. In addition, an additional layer of polycrystalline silicon can be formed above the second portion of the silicon oxide layer, said additional layer preferably having a thickness e' of between 1 and 1000 nm, the second free surface formed as a result of step c) being in this case entirely of polycrystalline silicon.

[0023] Furthermore, step c) may involve thinning the filler layer and / or the oxide layer so that the second free surface also has a second silicon oxide surface.

[0024] An advanced substrate is also planned, comprising: A receiving substrate; An active layer of single-crystal semiconductor material; and An electrically insulating layer of silicon oxide interposed between the active layer and the receiving substrate; the advanced substrate further comprising a layer of polycrystalline silicon disposed on the receiving substrate, the polycrystalline silicon layer being coated by the electrically insulating layer so as to define a first portion of the electrically insulating layer having a first thickness e1 and interposed between the polycrystalline silicon layer and the active layer, and a second portion of the electrically insulating layer having a second thickness e2 greater than the first thickness e1, the second portion being disposed between the receiving substrate and the active layer.

[0025] In one embodiment, the substrate comprises an additional polycrystalline silicon layer interposed between the receiving substrate and the assembly formed by the electrically insulating layer and the polycrystalline silicon layer. The substrate may further comprise an additional electrically insulating layer interposed between the additional layer and the receiving substrate. Preferably, the receiving substrate comprises an epitaxially doped layer configured to form microelectronic components within said epitaxially layer. Furthermore, the receiving substrate may include integrated circuits. BRIEF DESCRIPTION OF THE FIGURES

[0026] Other features and advantages of the invention will become apparent from the detailed description that follows, with reference to the accompanying drawings in which: THE Figures 1A to 1F, including 1D' and 1F', represent schematic cross-sectional views illustrating steps in a process for manufacturing an advanced substrate according to different implementation methods; and the figures 2 to 4 represent schematic cross-sectional views of advanced substrates according to different embodiments.

[0027] For the sake of clarity, the different layers are not necessarily shown to scale. Reference symbols used identically in each figure designate identical elements or elements performing the same function. DETAILED DESCRIPTION OF METHODS OF IMPLEMENTING THE INVENTION

[0028] For the different implementation methods, the same references will be used for identical elements or elements performing the same function, for the sake of simplifying the description.

[0029] THE Figures 1A to 1Fschematically represent embodiments of a process according to the invention. To facilitate illustration, the respective thicknesses of the different layers are not shown to scale.

[0030] According to one embodiment, the process for producing an advanced substrate 1 comprises a step a) of supplying a receiving substrate 20 (see the figures 1E , 1F and 1F'The receiving substrate 20 can be made of a semiconductor material or another material, depending on whether it is intended to provide only mechanical support or an electrical function within the final advanced substrate 1. Preferably, the receiving substrate 20 is silicon-based. Furthermore, the receiving substrate 20 may include one or more additional functional layers such as a trapping layer known as "Trap Rich," for example, based on polycrystalline silicon (possibly with a silicon oxide layer interposed between the substrate 20 and the trapping layer), or such as an epitaxial layer of doped semiconductor material, etc.

[0031] As illustrated in the Figure 1A This step also includes a step of supplying a donor substrate 10 comprising: A support substrate 11; An active layer 13 of a single-crystal semiconductor material; and A sacrificial layer 12 of a material that can be selectively etched with respect to the active layer, the sacrificial layer 12 being interposed between the support substrate 11 and the active layer 13; A silicon oxide layer 14 having a free surface 15 and arranged so that the active layer 13 is interposed between the sacrificial layer 12 and the oxide layer 14.

[0032] The support substrate 11 can be made of a semiconductor material or another material, taking into account the expected crystalline quality of the layers 12 and 13. Preferably, the support substrate 11 is silicon-based.

[0033] Active layer 13 is a layer configured to receive microelectronic components. In other words, these components will be formed in active layer 13. Preferably, active layer 13 is made of monocrystalline silicon, or monocrystalline silicon germanium, which can be strained or relaxed.

[0034] According to one embodiment, the active layer 13 is advantageously formed by epitaxy. Indeed, a layer formed by epitaxy makes it possible to obtain optimal roughness, thickness uniformity and surface finish of the layer, in particular compatible with the specifications of the most demanding microelectronic component fabrication processes, such as the FDSOI component fabrication process.

[0035] Advantageously, the sacrificial layer 12 is also produced by epitaxy, to facilitate the eventual epitaxy of the active layer 13. The sacrificial layer can be silicon- and germanium-based, when the active layer is silicon- or silicon- and germanium-based. Furthermore, layer 12 can also be made of any material that allows for selective etching of the sacrificial layer 12 relative to the active layer 13, provided that its crystalline quality remains compatible with that required for the active layer 13.

[0036] Even more advantageously, the materials of the support substrate 11 and the sacrificial layer 12 are configured such that the support material 11 is selectively etched with respect to the sacrificial layer 12, and such that the sacrificial layer 12 is selectively etched with respect to the active layer 13.

[0037] The oxide layer 14 can be produced by any technique known to those skilled in the art and compatible with conventional processes in the field of microelectronics. Preferably, the oxide layer 14 is a common thermal oxide.

[0038] The thickness of the substrate 11 can be on the order of a few hundred µm, typically 775 µm for substrates with a diameter of approximately 300 mm. The thickness of the sacrificial layer 12 depends on the etching technique and / or solution used. Those skilled in the art will know how to adjust its thickness so that it can be etched selectively and efficiently with respect to the active layer 13. Advantageously, its thickness is also adjusted so that the substrate material 11 can be etched selectively with respect to the sacrificial layer 12 while preserving the crystalline properties of the active layer 13.

[0039] The thickness of the active layer 13 is preferably between 5 and 500 nm, and the thickness of the oxide layer 14 is preferably between 10 and 500 nm.

[0040] As illustrated in the figure 1B The process includes a step b) of forming at least one cavity 30 in the silicon oxide layer 14. The cavity 30 is through-hole and includes an opening flush with the free surface 15 of the oxide layer 14. The cavity 30 has walls. The walls of the cavity 30 and the opening of the cavity 30 define the volume of the cavity 30. Advantageously, the cavity 30 is not through-hole and does not have an opening flush with the interface between the oxide layer 14 and the active layer 13, so that the oxide layer 14 has a first portion 14a having a first non-zero thickness e1. The first portion 14a is located between the cavity 30 and the active layer 13.

[0041] The oxide layer 14 thus comprises a second portion 14b having a second thickness e2 greater than the first thickness e1 of the first portion 14a. The second portion 14b is situated between the free surface 15 and the active layer 13.

[0042] For the sake of simplicity in the figures, two cavities 30 have been shown, but it is understood that a donor substrate 10 can in principle comprise a large number of cavities extending parallel to one another. Preferably, a network of cavities 30 is distributed in the oxide layer 14 so as to delimit several motifs defining the second portions 14b. In other words, each motif forming the second portion 14b of the oxide layer 14 is delimited by the cavities 30.

[0043] The cavity, or cavity array 30, can be fabricated using any conventional technique. Advantageously, the cavity 30 can be fabricated through a series of photolithography and etching steps, well-known and widely used in microelectronics. This allows for an abrupt transition between the different portions of the oxide layers, which have varying thicknesses. This also ensures uniformity of the layer thicknesses, particularly of the oxide layers.

[0044] After the formation of cavity 30, the process includes a step c) intended to form a filling layer for cavity 30. As illustrated in figures 1C, 1D And 1D' , the filling layer 40 is formed so as to completely fill the cavity 30 and form a second continuous and substantially flat free surface 41 comprising at least a first surface 43 based on the filling material.

[0045] According to one embodiment, the filling layer 40 covers the silicon oxide layer 14.

[0046] Advantageously, the filler layer 40 is made of polycrystalline silicon. Polycrystalline silicon is a material that is easy to deposit onto a silicon oxide layer. Furthermore, this material allows for low-temperature deposition, making it compatible with a structure incorporating an epitaxially grown and / or implanted donor substrate. Finally, polycrystalline silicon can advantageously serve both as a conductive layer beneath a future thin buried oxide layer, defined, for example, in zone 14a, and as a trapping layer (commonly called a "Trap Rich" layer) in zone 14b, while also being compatible with molecular adhesion to the recipient substrate 20.

[0047] Furthermore, it is known that polycrystalline silicon has better thermal conductivity than silicon oxide. Therefore, using a buried silicon oxide layer incorporating polycrystalline silicon layers in combination with a silicon receiving substrate advantageously allows for better heat dissipation from the active zone to and within the receiving substrate.

[0048] Preferably, step c) includes a planarization or thinning step, configured to make the second free surface 41 substantially flat. The planarization step may involve combined actions of mechanical and chemical forces, such as a chemical-mechanical polishing process, commonly known as the CMP process.

[0049] According to an embodiment illustrated in the figure 1D, step c), in particular the planarization step, is implemented so as to completely eliminate the polycrystalline silicon covering the second portion 14b of the oxide layer 14. In other words, step c) includes the planarization or thinning step of the layer 40 and / or the oxide layer 14 so that the second free surface 41 also includes a second surface 44 in silicon oxide.

[0050] According to another embodiment illustrated in the figure 1D'A polycrystalline silicon layer 42 is formed above the second portion 14b of the silicon oxide layer 14 and the filled cavity 30. Preferably, the layer 42 has a thickness e' between 1 and 1000 nm. According to this embodiment, the second free surface 41 formed as a result of step c) is entirely made of polycrystalline silicon. The layer 42 can be formed, for example, by successively adjusting the thickness of the formed layer 40 and then the thickness removed from the layer 40 after the planarization or thinning step of the polycrystalline silicon layer 40.

[0051] Therefore, the advanced substrate 1 obtained (see an example of the final substrate obtained, illustrated in the figure 3The substrate will advantageously comprise a buried insulating layer including a thick layer 14b with a functional layer (a trapping layer commonly called a "Trap Rich" layer) interposed between the receiving substrate 20 and the buried insulating layer 14b, and a thin oxide layer 14a. This type of substrate will offer the possibility of efficient co-integration of FDSOI-type components arranged on a thin buried insulator (portion 14a) and radio frequency components arranged on a thick buried insulator (portion 14b and a polycrystalline silicon layer), while limiting self-polarization and distortions between the components carried by the advanced substrate 1, particularly those induced by the strong electromagnetic radiation of radio frequency components. This is possible thanks to the functional layer (layer 42) arranged "below" the thick silicon oxide portion 14b.

[0052] Furthermore, the process also includes a step d) of assembling the receiving substrate 20 and the donor substrate 10 at the level of the second free surface 41 (Cf. figure 1E Advantageously, step d) of assembly is carried out by molecular adhesion. The assembly is advantageously carried out by direct contact of the second free surface 41 of the donor substrate 10 with the recipient substrate 20.

[0053] In one embodiment, an additional electrically insulating layer, preferably made of silicon oxide, can be formed on the donor substrate 10 and / or on the recipient substrate 20 before the assembly step. Advantageously, this additional layer is formed on the recipient substrate 20, so as not to disrupt the quality of the layers already formed on the donor substrate 10. This additional layer is thus interposed between the recipient substrate 20 and the donor substrate 10 (see, for example, the final substrate obtained and illustrated in Figure 10). figure 4This layer improves the quality of the assembly through molecular adhesion, particularly if one of the contacting surfaces contains polycrystalline silicon. The substrate thus formed will resemble and have the advantages of a double SOI. It will also electrically isolate the receiving substrate 20 from the influence of the potentials applied in the active layer 13 and in the filling layer 40. It therefore allows the receiving substrate 20 to itself carry integrated circuits or a functional layer (layer 61 of the figure 4 ). For example, a doped semiconductor layer, preferably epitaxial, allowing the co-integration of additional components on a bulk substrate (substrate 20), such as embedded memories (Embedded DRAM according to Anglo-Saxon terminology).

[0054] The process further includes a step e) of removing the support substrate 11 after step d), retaining the active layer 13 and the sacrificial layer 120 to obtain the advanced substrate 1 (cf. figures 1F and 1F' This removal can be achieved by any conventional technique known to those skilled in the art and compatible with the processes used in the field of microelectronics. For example, this removal can be achieved by abrasion or chemical etching, or preferably by introducing a weakened area followed by a fracture.

[0055] The process according to the invention is easy to implement and advantageously allows the formation of a "monolithic" substrate with an electrically insulating buried layer comprising at least two zones of different thicknesses, while ensuring continuity of electrical behavior between the zones of different thicknesses of the buried oxide layer. Indeed, thanks to the formation of a cavity in the oxide layer, which is filled with polycrystalline silicon before the assembly of the donor and recipient substrates, the resulting advanced substrate benefits from uniform thicknesses of the different portions of the layers, optimal roughness, and an abrupt transition between the different portions of the layers having different thicknesses.These characteristics thus make possible large-scale integration, optimized for the realization of different types of components on the same substrate, including FDSOI type devices and radio frequency devices.

[0056] According to one embodiment, the process includes a step of selectively etching the sacrificial layer 12 with respect to the active layer 13, the latter being retained on the final advanced substrate 1.

[0057] Selective etching is preferentially performed using wet chemical etching. For example, the selective etching of a silicon layer relative to a sacrificial germanium silicon layer can be carried out using a TMAH solution. The selective etching of a germanium silicon layer relative to a silicon layer can be carried out using an acetic acid solution.

[0058] Selective etching advantageously allows us to obtain in the end a desired active layer whose thickness and roughness is equivalent to the performance of an epitaxial substrate, which would not be the case if a single mechanical or mechano-chemical polishing were implemented.

[0059] Advantageously, the step of selectively etching the sacrificial layer 12 with respect to the active layer 13 is carried out just before the process of making the components on the active layer 13. Indeed, the sacrificial layer 12 can also play the role of a passivation layer, thus avoiding the formation of a native oxide layer on the active layer 13, and also protecting the latter during the substrate storage phase.

[0060] According to one embodiment, the process further comprises the following steps (see the figures 1A to 1E ) : b0) Form, before step b) and after step a), a weakening zone 50 in the support substrate 11, the weakening zone 50 being substantially flat and located in the vicinity of the interface between the sacrificial layer 12 and the support substrate 11; e0) Fracture the support substrate 11 according to the weakening zone 50, after step d), and preferably, before the selective etching of the sacrificial layer 12, if it is carried out.

[0061] In other words, the removal of the support substrate 11 can be achieved by detaching and fracturing it. Thus, the support substrate is not entirely lost and can advantageously be reused, particularly in a new cycle for producing another advanced substrate according to the invention.

[0062] The weakening zone 50 and the interface between the sacrificial layer 12 and the supporting substrate 11 delimit a residual layer 51 intended to be transferred onto the sacrificial layer 12 after the fracture of the supporting substrate 11.

[0063] Preferably, the materials of the sacrificial layer 12 and the substrate support are chosen so that the residual layer can be selectively etched with respect to the sacrificial layer 12. As illustrated in figures 1F and 1F' The process advantageously involves selective etching of the residual layer 51 relative to the sacrificial layer 12 after the fracture step e0).

[0064] Advantageously, the filling layer 40 is formed by a chemical vapor deposition at a temperature low enough to be carried out without impacting the embrittlement zone 50. Preferably, the filling layer 40 is formed by a chemical vapor deposition at a temperature between 150 °C and 250 °C.

[0065] According to one embodiment, the embrittlement zone 50 can be obtained by implanting at least one type of species selected from the following group: Hydrogen and Helium. The embrittlement implantation can also be carried out with several species implanted sequentially. Preferably, the support substrate 11 is silicon-based.

[0066] The conditions for creating the embrittlement layer 50 (implanted species, energy and implantation dose) and for fracture depend on the thicknesses of layers 12 and 13. Furthermore, a person skilled in the art will be able to adjust these conditions so as to form an embrittlement zone 50 in the supporting substrate 11. Moreover, the fracture step e0) is preferably carried out by a heat treatment at a temperature that can be between 350 and 500 °C.

[0067] The sequence of steps in the process according to the invention advantageously allows for the formation of a weakened zone prior to the structuring of the buried oxide layer by creating a cavity and then filling it with a semiconductor material. Thus, a substantially flat weakened zone can be obtained easily and conventionally, thereby facilitating fracture and detachment. Furthermore, the deposition of the filling material can advantageously be carried out at low temperatures to avoid premature fracture and / or alteration of the support substrate before the assembly of the donor and recipient substrates.

[0068] Although all steps of the process according to the invention can be carried out at temperatures not exceeding 500 °C, it is advantageous to obtain uniform layers with optimal surface roughness and surface characteristics, particularly compatible with a process for manufacturing FDSOI-type components. The process according to the invention also eliminates the need for high-temperature finishing steps and advantageously avoids the recrystallization of the polycrystalline silicon layer. Consequently, the polycrystalline silicon layer can act as a functional layer, such as a trap-rich layer, within the final advanced substrate.Finally, the use of such a narrow temperature range would allow, according to a particular embodiment of the invention, the transfer of the donor substrate formed onto a "structured" receiving substrate, comprising functional devices, within the framework of a transfer of three-dimensional layers.

[0069] According to one embodiment, the active layer 13 retained after step e) is locally thinned so as to locally reduce the thickness of the active layer 13. This advantageously yields an advanced substrate with an active layer having portions of varying thicknesses and a buried oxide layer also having portions of varying thicknesses. The advanced substrate can thus be configured to efficiently fabricate components with different functionalities.

[0070] Furthermore, the aim is to satisfy the previously outlined needs while avoiding the aforementioned drawbacks, by also providing an advanced substrate 1 comprising (see the figures 2 and 3 ): A receiving substrate 20; An active layer 13 of single-crystal semiconductor material; and An electrically insulating layer 14 of silicon oxide interposed between the active layer 13 and the receiving substrate 20.

[0071] The substrate further comprises a polycrystalline silicon layer 40 disposed on the receiving substrate 20. The polycrystalline silicon layer 40 is coated by the electrically insulating layer 14 so as to define a first portion 14a and a second portion 14b of the electrically insulating layer 14. The first portion 14a has a first thickness e1 and is interposed between the polycrystalline silicon layer 40 and the active layer 13. The second portion 14b of the electrically insulating layer 14 has a second thickness e2 greater than the first thickness e1. Portion 14b is disposed between the receiving substrate 20 and the active layer 13. Preferably, the active layer 13 is surmounted by a sacrificial layer 12, which can be selectively etched with respect to the active layer 13, just before the components are formed in the active layer.In other words, the sacrificial layer also plays the role of a protective layer for the advanced substrate 1.

[0072] According to an embodiment illustrated in the figure 3 , the advanced substrate includes an additional layer 42 of polycrystalline silicon interposed between, the receiving substrate 20 and the assembly formed by the electrically insulating layer 14 and the polycrystalline silicon layer 40.

[0073] According to another embodiment illustrated in the figure 4 , the advanced substrate 1 includes, under layer 42, a second electrically insulating layer 60, for example a silicon oxide layer disposed on the receiving substrate 20. The receiving substrate 20 may itself include a functional layer 61 such as a doped epitaxial layer, or even include microelectronic devices such as integrated circuits, within the framework of a 3D approach.

Claims

1. Method for making an advanced substrate (1) comprising the following steps: a) Providing a receiver substrate (20) and a donor substrate (10), said donor substrate (10) comprising: - A support substrate (11) - An active layer (13) made of a monocrystalline semiconductor material; and - A sacrificial layer (12) made of a material which can be selectively etched in relation to the active layer (12), the sacrificial layer (12) being interposed between the support substrate (11) and the active layer (13); - A silicon oxide layer (14), provided with a free surface (15) and disposed such that the active layer (13) is interposed between the sacrificial layer (12) and the oxide layer (14); b) Forming a cavity (30) in the oxide layer (14), the cavity (30) having an opening flush with the free surface (15) such that the oxide layer (14) comprises a first portion (14a) having a first thickness (e1) and disposed between the cavity (30) and the active layer (13), and a second portion (14b) having a second thickness (e2) greater than the first thickness (e1), the second portion (14b) being disposed between the free surface (15) and the active layer (13) c) Forming a filling layer (40) made of polycrystalline silicon so as to fill the cavity (30) completely and form a second continuous and substantially planar free surface (41), comprising at least a first surface (43) made of polycrystalline silicon; d) Assembling the receiver substrate (20) and the donor substrate (10) at the second free surface (41); e) Eliminating the support substrate (11) after step d) while preserving the active layer (13) and the sacrificial layer (12).

2. Method according to claim 1, comprising a step of selective etching of the sacrificial layer (12) while preserving the active layer (13), after step e).

3. Method according to one of the preceding claims, wherein the assembly step d) comprises a step of bonding by molecular adhesion.

4. Method according to one of the preceding claims, comprising the following steps: b0) Forming, before step b) and after step a), an embrittlement zone (50) in the support substrate (11), the embrittlement zone being substantially planar and located in the vicinity of the interface between the sacrificial layer (12) and the support substrate (11); e0) Fracturing the support substrate (11) along the embrittlement zone (50), after step d).

5. Method according to claim 4, wherein the support substrate (11) is made of a material which can be selectively etched in relation to the material of the sacrificial layer (12), the method further comprising selective etching of the remainder of the support substrate (11) disposed on the sacrificial layer (12) after the fracture step e0).

6. Method according to one of claims 4 or 5, wherein the filling layer (40) is formed by chemical vapour phase deposition at a temperature between 150°C and 250°C.

7. Method according to one of the preceding claims, wherein the active layer (13) made of monocrystalline silicon is made by epitaxy.

8. Method according to one of the preceding claims, wherein the filling layer (40) covers the silicon oxide layer (14).

9. Method according to claim 8, wherein a layer (42) made of polycrystalline silicon is formed above the second portion (14b) of the silicon oxide layer (14), the layer (42) having a thickness (e') between 1 and 1000 nm, the second free surface (41) formed following step c) being entirely made of polycrystalline silicon.

10. Method according to one of claims 1 to 8, wherein step c) comprises thinning the filling layer (40) and / or the oxide layer (14) such that the second free surface (41) further comprises a second surface (44) made of silicon oxide.

11. Method according to one of the preceding claims, wherein the active layer (13) preserved after step e), is locally thinned so as to reduce the thickness of the active layer (13) locally.

12. Advanced substrate (1) comprising: - A receiver substrate (20) - An active layer (13) made of monocrystalline semiconductor material; and - An electrically-insulating layer (14) made of silicon oxide interposed between the active layer (13) and the receiver substrate (20); the advanced substrate (1) further comprising a polycrystalline silicon layer (40) disposed on the receiver substrate (20), the polycrystalline silicon layer (40) being coated by the electrically-insulating layer (14) so as to define a first portion (14a) of the electrically-insulating layer (14) having a first thickness (e1) and interposed between the polycrystalline silicon layer (40) and the active layer (13), and a second portion (14b) of the electrically-insulating layer (14) having a second thickness (e2) greater than the first thickness (e1), the second portion (14b) being disposed between the receiver substrate (20) and the active layer (13).

13. Advanced substrate (1) according to the preceding claim, comprising an additional layer (42) made of polycrystalline silicon interposed between, the receiver substrate (20) and the assembly formed by the electrically-insulating layer (14) and the polycrystalline silicon layer (40).

14. Advanced substrate (1) according to the preceding claim, comprising an additional electrically-insulating layer (60) interposed between the additional layer (42) and the receiver substrate (20).

15. Advanced substrate (1) according to the preceding claim, where the receiver substrate (20) comprises an epitaxial and doped layer (61), configured to form microelectronic components in said epitaxial layer (61).

16. Advanced substrate according to one of claims 14 and 15, where the receiver substrate (20) comprises integrated circuits.