METHOD FOR HOMOGENIZING THE NANOWIRE SECTION FOR LIGHT-EMITTING DIODES

Description

[0001] This patent application claims priority from French patent application FR19 / 06898. Technical field

[0002] The present invention relates generally to light-emitting diode optoelectronic devices comprising three-dimensional semiconductor elements, for example, microwires, nanowires, micrometer- or nanometer-sized tapered elements, or micrometer- or nanometer-sized frustoconical elements and methods of fabricating such devices. Prior art

[0003] The improvement of optoelectronic devices with axial-type light-emitting diodes, comprising an active zone formed at the top of each three-dimensional element, is considered here in particular. The active zone of the light-emitting diode is the region from which the majority of the electromagnetic radiation provided by the light-emitting diode is emitted.

[0004] The three-dimensional elements considered here comprise a semiconductor material comprising predominantly a group III element and a group V element (e.g. gallium nitride GaN), hereinafter referred to as a III-V compound. Such devices are, for example, described in patent US9728680.

[0005] Each active region is sandwiched between the associated three-dimensional semiconductor element, which is usually doped with a first conductivity type, and a semiconductor layer of the same III-V compound as the semiconductor element and doped with the opposite conductivity type.

[0006] An example of a manufacturing process for the optoelectronic device involves the formation of three-dimensional semiconductor elements by metal-organic chemical vapor deposition (MOCVD). However, it can be difficult to precisely control the average diameter of the semiconductor elements with such a growth process. Therefore, the same optoelectronic device may include semiconductor elements having different average diameters. The wavelength of the radiation emitted by the active region of the light-emitting diode may depend on the average diameter of the active region and therefore on the average diameter of the semiconductor element on which the active region is formed. Uncontrolled wavelength dispersion of the radiation emitted by the light-emitting diodes may then be achieved.

[0007] WO 2019 / 002786 A1, US 2014 / 110664 A1 and US 2016 / 365480 A1 each describe methods of manufacturing optoelectronic devices comprising light-emitting diodes (LEDs). Summary of the invention

[0008] Thus, an object of an embodiment is to at least partially overcome the drawbacks of the optoelectronic devices described previously and their manufacturing methods.

[0009] Another object of an embodiment is to reduce the wavelength dispersion of the radiation emitted by the light-emitting diodes of the optoelectronic device.

[0010] Thus, one embodiment provides a method for manufacturing an optoelectronic device comprising light-emitting diodes comprising forming three-dimensional semiconductor elements of a III-V compound each comprising a lower portion and an upper portion, and, for each semiconductor element, forming an active area covering the top of the upper portion and forming at least one semiconductor layer of the III-V compound covering the active area. The upper portions are formed by vapor deposition at a pressure of less than 1.33 mPa.

[0011] According to one embodiment, the lower portions are formed by selective etching or by epitaxial growth, preferably by an organometallic chemical vapor deposition technique, or by molecular beam epitaxy.

[0012] According to the invention, the upper portions are formed by molecular beam epitaxy.

[0013] According to the invention, for each semiconductor element, the upper portion is flared relative to the lower portion.

[0014] According to the invention, for each semiconductor element, the top of the upper portion has an area greater than at least 20% compared to the cross section of the lower portion.

[0015] According to the invention, for the formation of the upper portions, the III / V ratio is between 1.3 and 2.

[0016] According to the invention, for the formation of the upper portions, the temperature of the upper portions is between 700°C and 850°C.

[0017] According to one embodiment, for the formation of the lower portions, the III / V ratio is between 0.01 and 1.

[0018] According to one embodiment, for the formation of the lower portions, the temperature of the lower portions is between 700°C and 850°C.

[0019] According to one embodiment, the active zones are formed by molecular beam epitaxy.

[0020] According to one embodiment, the lower portions of the three-dimensional semiconductor elements are microwires, nanowires, conical elements of micrometric or nanometric size, or frustoconical elements of micrometric or nanometric size.

[0021] According to one embodiment, the active zones are the regions from which the majority of the electromagnetic radiation provided by the light-emitting diodes is emitted. Brief description of the drawings

[0022] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there Figure 1 is a partial, schematic sectional view of an example of an axial-type light-emitting diode optoelectronic device; Figure 2 is a partial and schematic sectional view of an embodiment of an optoelectronic device with light-emitting diodes of the axial type; Figure 3 illustrates a step of an embodiment of a method of manufacturing the optoelectronic device represented in Figure 2 ; there Figure 4 illustrates another step in the process; the Figure 5 illustrates another step in the process; the Figure 6 represents images obtained by scanning electron microscopy of nanowires for different growth conditions; the Figure 7is a curve showing the evolution of the ratio between the average diameter of a nanowire after widening and the average diameter of the nanowire before widening as a function of the average diameter of the nanowire before widening; figure 8 represents an image obtained by scanning electron microscopy of an example of certain axial-type light-emitting diode elements each having the structure illustrated in Figure 1 ; there figure 9 represents, as a function of the wavelength, the spectra of the radiation emitted by the active zones represented in figure 8 ; there Figure 10 represents an image obtained by scanning electron microscopy of an embodiment of certain axial-type light-emitting diode elements each having the structure illustrated in Figure 2 ; and the Figure 11 represents, as a function of the wavelength, the spectra of the radiation emitted by the active zones represented in the Figure 10 . Description of the embodiments

[0023] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties. For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the means for controlling the optoelectronic devices are well known and are not described.

[0024] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to an optoelectronic device in a normal position of use.

[0025] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%. In addition, the terms "insulator" and "conductor" are considered here to mean "electrically insulating" and "electrically conducting", respectively.

[0026] The present invention relates to optoelectronic devices comprising three-dimensional semiconductor elements, for example microwires, nanowires, conical elements of micrometric or nanometric size, or frustoconical elements of micrometric or nanometric size. The term "microwire", "nanowire", "conical element" or "truncated element" designates a three-dimensional structure of elongated shape, for example cylindrical, conical or frustoconical, in a preferred direction, called axis hereinafter, of which at least two dimensions, called minor dimensions, are between 5 nm and 2.5 µm, preferably between 50 nm and 1 µm, the third dimension, called major dimension, being greater than or equal to 1 time, preferably greater than or equal to 5 times and even more preferably greater than or equal to 10 times, the largest of the minor dimensions, for example between 1 µm and 50 µm.In particular, a conical or frustoconical element may be a circular or circular frustoconical conical element or a pyramidal or pyramidal frustoconical conical element. In the remainder of the description, embodiments are described for optoelectronic devices comprising microwires or nanowires, generally called wires. However, these embodiments may be implemented for semiconductor elements other than microwires or nanowires, for example conical or frustoconical elements. In the remainder of the description, the average diameter of a wire is called the diameter of the disk with the same surface area as the cross-section of the wire. In addition, the central wavelength of radiation is called the wavelength of the radiation that carries the most energy.

[0027] There Figure 1is a partial and schematic sectional view of an example of an optoelectronic device 10 with axial-type light-emitting diodes. The optoelectronic device 10 comprises, from bottom to top, Figure 1 : a substrate 14, for example a semiconductor substrate, comprising parallel faces 16 and 18, preferably planar, the face 18 being treated to promote the growth of wires. This treatment is shown schematically in Figure 1 by a germination layer 20 made of a material promoting the growth of the wires, on the face 18 of the substrate 14; an insulating layer 22 covering the germination layer 20 and comprising through openings 24; wires 26 with parallel C axes, two wires 26 being shown on the Figure 1at least partly doped with a first type of conductivity, for example doped with n-type; for each wire 26, a head 28 covering the upper face 30, also called the top, of the wire 26; an insulating layer 32 covering the lateral faces of the wires 26 and partially the lateral faces of the heads 28; and an electrode layer 34 covering the insulating layer 32 and in contact with the heads 28.

[0028] The optoelectronic device 10 comprises another electrode, not shown, for polarizing the base of the wires 26.

[0029] Each head 28 includes from bottom to top in Figure 1 : an active zone 40 covering the upper face 30 of the wire 26; and a semiconductor stack 42 covering the active zone 40 and comprising a semiconductor layer 44 doped with a second conductivity type opposite to that of the wire 26, for example doped with p-type, and covering the active zone 40.

[0030] The assembly formed by each wire 26 and the associated head 28 corresponds to a light-emitting diode DEL in axial configuration.

[0031] The semiconductor stack 42 may further comprise an electron blocking layer 46 between the active area 40 and the semiconductor layer 44 and a semiconductor bonding layer 48 covering the semiconductor layer 44 on the side opposite the active area 40, the bonding layer 48 being covered by the electrode layer 34 and in contact with the electrode layer 34. The electron blocking layer 46 is in contact with the active area 40 and the semiconductor layer 44, and makes it possible to optimize the presence of electrical carriers in the active area 40. The bonding layer 48 may be of the same material as the semiconductor layer 44 and doped with the same conductivity type as the semiconductor layer 44 but with a higher concentration of dopants to allow the formation of an ohmic contact between the semiconductor layer 44 and the electrode layer 34.

[0032] The active area 40 is the area of ​​the light-emitting diode LED from which the majority of the electromagnetic radiation provided by the light-emitting diode LED is emitted. According to one example, the active area 40 may comprise confinement means. The active area 40 may comprise at least one quantum well, comprising a layer of a semiconductor material having a bandgap energy lower than that of the wire 26 and the semiconductor layer 44, preferably interposed between two barrier layers, thereby improving the confinement of the charge carriers, the barrier layers being able to be of the same material as the wire 26 and not intentionally doped. The active area 40 may be formed of a single quantum well or a plurality of quantum wells. For example, in Figure 1 , an alternation along the C axis of two quantum wells 50 and three barrier layers 52 has been represented.

[0033] An example of a method for manufacturing the optoelectronic device 10 comprises growing the wires 26, the active zones 40 and the semiconductor stacks 42 by implementing a growth method which promotes crystal growth along the C axis of the wires 26. The method for growing the wires may be a method of the metal-organic chemical vapor deposition (MOCVD) type, also known as metal-organic vapor phase epitaxy (or MOVPE). The MOCVD method has the particular advantage of high growth rates. The growth of each wire 26 begins in one of the openings 24 and continues outside the opening 24. The average diameter of the wire 26 outside the opening 24 may be different from the average diameter of the opening 24, and is generally greater than the average diameter of the opening 24.

[0034] A disadvantage is that the MOCVD method may not allow the average diameter of the wires 26 to be precisely controlled. As a result, a significant dispersion of the average diameters of the wires 26 of the optoelectronic device 10 may be obtained. For each light-emitting diode (LED), the average diameter of the active area 40 depends on the average diameter of the wire 26 and may be substantially equal to the average diameter of the wire 26. When the active area 40 comprises a quantum well or quantum wells, the central wavelength of the radiation emitted by the active area 40 of the light-emitting diode (LED) depends in particular on the average diameter of the active area 40 and therefore on the average diameter of the wire 26 on which the active area 40 is formed. A significant dispersion of the central wavelengths of the radiation emitted by the light-emitting diodes may then be obtained.

[0035] The inventors have demonstrated that, after a first step of growing the wires 26 by MOCVD in which a lower portion of each wire is formed, and before the step of forming the active zones 40, by carrying out a second step of growing the wires 26 by a particular growth method, an upper portion is formed for each wire 26 delimiting the upper face 30, on which the active zone 40 will be formed such that the dispersion of the average diameters of the upper surfaces is less than the dispersion of the average diameters of the lower portions of the wires. The particular growth methods are growth methods by vacuum vapor deposition at a pressure of less than 1.33 mPa (10 -5 < Torr), preferably less than 0.0133 mPa (10 -7 < Torr), for which molecular jets are projected onto the surfaces on which crystal growth is desired.This is molecular beam epitaxy (MBE), particularly plasma-assisted molecular beam epitaxy (PA-MBE) or ammonia-assisted MBE.

[0036] There Figure 2 is a sectional view of an embodiment of an optoelectronic device 60. The optoelectronic device 60 comprises all of the elements of the optoelectronic device 10 shown in Figure 1with the difference that each wire 26 comprises a lower portion 62 of substantially constant cross-section extending into an upper portion 64 which, in the present embodiment, has a shape that flares outwards for which the cross-section increases along the axis C moving away from the substrate 14. According to another embodiment, the wires 26 can be divided into first wires each comprising the upper portion 64 that flares outwards and into second wires for each of which the upper portion 64 has the shape of a truncated pyramid whose large base rests on the lower portion 62.

[0037] Preferably, for each wire 26, the upper face 30 of the upper portion 64 of the wire 26 corresponds to a substantially planar face orthogonal to the axis C of the wire 26. The area of ​​the upper face 30 is at least 20% greater than the cross-section of the lower portion 62 of the wire 26. The height of the upper portion 64 of each wire 26 measured along the axis C may be between 5 nm and 2 µm, preferably between 20 nm and 500 nm. The height of the lower portion 62 of each wire 26 measured along the axis C may be between 200 nm and 5 µm. For each wire 26, the average diameter of the lower portion 62 of the wire 26 may be between 50 nm and 10 µm, preferably between 100 nm and 2 µm, more preferably between 100 nm and 1 µm. The cross-section of the lower portion 62 of the wire 26 may have different shapes, for example oval, circular or polygonal, in particular rectangular, square or hexagonal.

[0038] The wires 26, the barrier layers 52, the semiconductor layers 44 and the bonding layers 48 may be, at least in part, formed from semiconductor materials comprising predominantly a III-V compound, for example a III-N compound. Examples of group III elements include gallium (Ga), indium (In) or aluminum (Al). Examples of III-N compounds are GaN, AlN, InN, InGaN, AlGaN or AlInGaN. Other group V elements may also be used, for example phosphorus or arsenic. Generally, the elements in the III-V compound may be combined with different mole fractions. The III-V compounds of the wires 26 and the layers 44, 48 may comprise a dopant, for example silicon (Si) which is an n-type dopant for the III-V compounds or magnesium (Mg) which is a p-type dopant for the III-V compounds.

[0039] The semiconductor material of the quantum well 50 or quantum wells 50 of the active area 40 may comprise the III-V compound of the wire 26 and the semiconductor layer 44 in which at least one additional element is incorporated. For example, in the case of wires 26 made of GaN, the additional element is for example indium (In). The atomic percentage of the additional element is a function of the desired optical properties and the emission spectrum of the light-emitting diode LED. When the upper portion 64 of the wire 26 is not intentionally doped, it may replace one of the barrier layers 52 of the active area 40.

[0040] The electron blocking layer 46 may be formed from a ternary alloy, for example aluminum gallium nitride (AlGaN) or aluminum indium nitride (AlInN).

[0041] The substrate 14 may correspond to a single-piece structure or correspond to a layer covering a support made of another material. The substrate 14 is preferably a semiconductor substrate, for example a substrate made of silicon, germanium, silicon carbide, a III-V compound, such as GaN or GaAs, or a conductive substrate, for example a metal substrate, in particular copper, titanium, molybdenum, a nickel-based alloy or steel, or a sapphire substrate. Preferably, the substrate 14 is a monocrystalline silicon substrate. Preferably, it is a semiconductor substrate compatible with the manufacturing methods implemented in microelectronics. The substrate 14 may correspond to a multilayer structure of the silicon-on-insulator type, also called SOI (Silicon On Insulator).

[0042] The seed layer 20 is made of a material that promotes the growth of the wires 26. For example, the material making up the seed layer 20 may be a nitride, a carbide or a boride of a transition metal from column IV, V or VI of the periodic table of elements or a combination of these compounds. For example, the seed layer 20 may be made of aluminum nitride (AlN). The seed layer 20 may have a single-layer structure or correspond to a stack of two layers or more than two layers. Examples of material for the seed layer 20 are described in patent FR2997557.

[0043] The insulating layer 22 may be made of a dielectric material, for example silicon oxide (SiO 2 ) or silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4 ). For example, the thickness of the insulating layer 22 is between 5 nm and 100 nm, for example equal to approximately 30 nm. The insulating layer 22 may have a single-layer structure or correspond to a stack of two layers or more than two layers.

[0044] The insulating layer 32 may be made of a dielectric material, for example silicon oxide (SiO 2 ) or silicon nitride (Si x N y , where x is approximately equal to 3 and y is approximately equal to 4, for example Si 3 N 4 ). The insulating layer 32 may have a single-layer structure or correspond to a stack of two layers or more than two layers. For example, the insulating layer 32 may be made of a polymeric material, an inorganic material or a combination of a polymeric material and an inorganic material. For example, the inorganic material may be titanium oxide (TiO 2 ) or aluminum oxide (Al x O y , where x is approximately equal to 2 and y is approximately equal to 3, for example Al 2 O 3 ).

[0045] The electrode layer 34 is adapted to polarize the active zone 40 covering each wire 26 and to allow the electromagnetic radiation emitted by the light-emitting diodes LED to pass through. The material forming the electrode layer 34 may be a transparent and conductive material such as indium-tin oxide (or ITO, English acronym for Indium Tin Oxide), zinc oxide doped or not with aluminum or gallium, or graphene. For example, the electrode layer 34 has a thickness of between 5 nm and 200 nm, preferably between 20 nm and 50 nm.

[0046] THE figures 3 to 5 are partial and schematic sectional views of the structure obtained at successive stages of an embodiment of a method of manufacturing the optoelectronic device 60 shown in Figure 2 .

[0047] There Figure 3 represents the structure obtained after the following steps: forming on the substrate 14 the seed layer 20; forming the insulating layer 22 on the seed layer 20; forming the openings 24 in the insulating layer 22 to expose portions of the seed layer 20 at the desired locations of the wires 26, the diameter of the openings 24 corresponding substantially to the average diameter of the wires 26; and growing the lower portions 62 of the wires 26 from the seed layer 20 into the openings 24.

[0048] The seed layer 20 and the insulating layer 22 may be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or ALD.

[0049] According to one embodiment, the growth of the lower portions 62 of the wires 26 is carried out by MOCVD. For example, the method may comprise injecting into a reactor a precursor of a group III element and a precursor of a group V element. Examples of precursors of group III elements are trimethylgallium (TMGa), triethylgallium (TEGa), trimethylindium (TMIn) or trimethylaluminum (TMAl). Examples of precursors of group V elements are ammonia (NH 3 ), tertiarybutylphoshine (TBT), arsine (AsH 3 ), or asymmetric dimethylhydrazine (UDMH). The III / V ratio is the ratio of the gas flow of the precursor of the group III element to the gas flow of the precursor of the group V element. The pressure in the reactor is between 50 torr (about 7 kPa) and 500 torr (70 kPa).The growth conditions in the reactor are adapted to promote preferential growth of the lower portion 62 of each wire 26 along its axis C. This means that the growth rate of the wire 26 along the axis C is significantly higher, preferably by at least one order of magnitude, than the growth rate of the wire 26 along a direction perpendicular to the axis C. According to one embodiment, the III / V ratio is between 0.01 and 1, preferably between 0.01 and 0.1. The temperature in the reactor is, for example, between 900°C and 1150°C, preferably between 1000°C and 1100°C.

[0050] According to another embodiment, the lower portions 62 of the wires 26 can be formed by etching in a layer of the III-V compound, in particular according to a so-called top-down technology.

[0051] There Figure 4represents the structure obtained after the growth of the upper portions 64 of the wires 26. According to the invention, the growth of the upper portions 64 of the wires 26 is carried out by MBE, preferably PA-MBE. The pressure in the reactor is less than 1.33 mPa (10 -5< Torr), preferably between 10 -4< (approximately 13.3 mPa) and 10 -7< Torr (approximately 0.0133 mPa). The III / V ratio, which is then the ratio between the atomic flux of the group III element and the atomic flux of the group V element, is between 0.8 and 2. To obtain a widening of the upper portion 64 of each wire 26, the III / V ratio is greater than 1.3, in particular between 1.3 and 2. To obtain a widening of the upper portion 64 of each wire 26, the temperature in the reactor is preferably between 750°C and 875°C, according to the invention, the temperature is between 700°C and 850°C.The growth phase of the upper portions 64 by PA-MBE can result in the formation of a GaN shell on the sidewalls of the lower portions 62 of the wires 26.

[0052] If we call ϕ Ga the atomic flux of the group III element, ϕ N the atomic flux of the group V element, D the diameter of the lower portion 62 of the wire (which we consider to be approximately cylindrical with a circular base), θ the angle of incidence of the atomic flux of the group III element and the atomic flux of the group V element on the upper face 30 of the wire 26, n Ga the effective number of atoms of the group III element on the upper face 30 and n N the effective number of atoms of the group V element on the upper face 30, and if we consider that the diffusion length λ of the group III element on the side walls of the wires depends only on the temperature, we can determine the following Math 1 relation: n Ga n N ∼ k T ϕ Ga ϕ N 1 + 4 λ D tanθ where k(T) is a factor accounting for the temperature dependence of desorption of the group III element from the side walls and top face of wire 26.

[0053] In stabilized mode, the dimensions of the upper face 30 are fixed by the ratio n Ga / n N . It therefore appears, advantageously, that when the upper portions 64 of the wires 26 are formed by PA-MBE, the dimensions of the upper face 30 of each upper portion 64, where the active zone 40 is formed, evolve towards dimensions which are substantially independent of the average diameter of the lower portion 62 of the wire 26 from which the upper portion 64 extends and which depend on the III / V ratio used for the formation of the upper portion 64. This therefore makes it possible to precisely control the dimensions of the upper face 30 of the upper portion 64 and therefore the lateral dimensions of the active zone 40. This makes it possible to at least partially compensate for the dispersion of the average diameters of the lower portions 62 of the wires 26 which may result from the manufacturing process of these lower portions 62.If the growth of the upper portions 64 is interrupted before reaching the stability regime, the upper faces 30 of the wires 26 may not have exactly the same dimensions.

[0054] Furthermore, the wavelength of the radiation emitted by a quantum well depends in particular on the proportion of the additional element of group III, for example indium, incorporated in the ternary compound of the quantum well. This proportion itself depends on the lateral dimensions of the active zone 40. Therefore, precise control of the lateral dimensions of the active zone 40 makes it possible to precisely control the wavelength of the radiation emitted by the active zone 40. The wavelength dispersion of the radiation emitted by the light-emitting diodes can therefore be reduced.

[0055] There Figure 5represents the structure obtained after the growth of the layers of the active zones 40 and the semiconductor stacks 42. According to one embodiment, the growth of the layers of the active zones 40 and the semiconductor stacks 42 is carried out by PA-MBE. The pressure in the reactor is between 10 -4< and 10 -7< torr. For the formation of the quantum well or each quantum well, an additional element of group III is added to the reactor. The ratio between the atomic fluxes of the elements of group III and the atomic flux of the element of group V for the formation of the active zones 40 can be between 0.3 and 2. The temperature in the reactor is, for example, between 600°C and 850°C, preferably between 700°C and 800°C.

[0056] For the formation of the electron blocking layer 46, an additional element from group III is added to the reactor, the III / V ratio is preferably close to 1 and the ratio between the atomic flux of the additional element and the atomic flux of the element from group V is between 0.1 and 0.3. The electron blocking layer 46 may be p-doped, for example with magnesium. For the formation of the electron blocking layer 46, the temperature in the reactor is, for example, between 600°C and 1000°C, preferably between 700°C and 950°C, more preferably between 750°C and 900°C. For the formation of the semiconductor layer 44 or 48, the III / V ratio is preferably less than 1.3, in particular between 1.1 and 1.3. For the formation of the semiconductor layer 44 or 48, the temperature in the reactor is, for example, between 700°C and 900°C, preferably between 750°C and 850°C.

[0057] On the Figure 5, each active zone 40 has been represented with a substantially constant cross section along the C axis. As a variant, the growth conditions of the active zone 40 can be selected so that the active zone 40 has a truncated pyramid shape with axis C with a cross section which decreases along axis C moving away from the substrate 14. Such a shape can be obtained without significant loss of the volume of the quantum well or quantum wells compared to the case where the cross section is constant. An active zone 40 in the shape of a truncated pyramid advantageously makes it possible to increase the thickness of the semiconductor layer 44 which covers it and to improve the passivation of the surface of the active zone 40.

[0058] According to another embodiment, the growth of the active zones 40 and / or the semiconductor stacks 42 is carried out by MOCVD.

[0059] Tests were carried out. For these tests, four GaN wires NW1, NW2, NW3 and NW4 having lower portions 62 of different average diameters were made by MOCVD using openings 24 of different diameters. The upper portions 64 of GaN wires NW1, NW2, NW3 and NW4 were formed by PA-MBE. D0, or initial diameter, is the average diameter of the lower portion 62 of wire 26 measured at the top of the lower portion 62 before the MBE growth phase of the upper portion 64. The initial diameter of wire NW1 was 120 nm. The initial diameter of wire NW2 was 180 nm. The initial diameter of wire NW3 was 260 nm. The initial diameter of wire NW4 was 480 nm. For the MBE growth phase, different temperatures and different Ga / N ratios were used.

[0060] There Figure 6represents images obtained by scanning electron microscopy of the NW1, NW2, NW3 and NW4 wires for different growth temperatures and Ga / N ratios used for the MBE. In each image, the NW1 wire is located at the bottom left of the image, the NW2 wire is located at the top right of the image, the NW3 wire is located at the top left of the image and the NW4 wire is located at the bottom right of the image. In the case of the invention where a flared upper portion 64 is sought for the majority of the NW1, NW2, NW3 and NW4 wires, the Ga / N ratio is between 1.3 and 2 and the temperature is between 700°C and 850°C.

[0061] The measurement results in the case where the Ga / N ratio was approximately 1.6 and the temperature was approximately 850°C are shown in Table I below. [Table 1] Thread D0 (nm) D (nm) D / D0 NW1 120 434,55 3,62 NW2 180 520,70 2,89 NW3 260 551,65 2,12 NW4 480 626,48 1,46

[0062] There Figure 7is a curve showing the evolution of the D / D0 ratio between the average diameter D of a wire after widening and the initial average diameter D0 of the nanowire before widening as a function of the initial average diameter D0 of the nanowire before widening.

[0063] There figure 8represents an image obtained by scanning electron microscopy of the wires and active areas 40 of axial-type light-emitting diodes formed with the wires NW1, NW2, NW3 and NW4 for which only the lower portion 62 was present. The lower portions 62 of the wires 26 were made of n-type doped GaN. Each active area 40 comprised a single InGaN quantum well between barrier layers of intentionally undoped GaN. Each semiconductor stack 42 comprised an AlGaN blocking layer and a p-type doped GaN semiconductor layer. The lower portions 62 of the wires were formed by PA-MBE with a Ga / N ratio of 1.3 and a temperature of 900°C. The InGaN quantum wells were formed by PA-MBE with a Ga+In / N ratio of 1.6 and a temperature of 750°C. The AlGaN blocking layers 46 were formed by PA-MBE with a Ga+Al / N ratio of 1, an Al / N ratio of 0.2, and a Ga / N ratio of 0.8.The 44 p-type doped GaN semiconductor layers were grown by PA-MBE with a Ga / N ratio of 0.8 and a temperature of 850°C.

[0064] There figure 9 represents evolution curves C1, C2, C3 and C4, as a function of the wavelength, of the spectrum of the radiation emitted by photoluminescence by the active zones 40 of the figure 8 corresponding to wires NW1, NW2, NW3 and NW4 respectively. The difference between the center wavelength of the light-emitting diode corresponding to wire NW1 and the center wavelength of the light-emitting diode corresponding to wire NW4 was about 80 nm.

[0065] THE Figures 10 and 11 are figures analogous respectively to the figures 8 and 9in the case where the wires NW1, NW2, NW3 and NW4 were formed as previously described with an upper portion 64 formed by PA-MBE. The upper portions 64 of the wires 26 were made of unintentionally doped GaN. The upper portions 64 of the wires 26 were formed by PA-MBE with a Ga / N ratio of 1.6 and a temperature of 850°C for 10 minutes. The difference between the central wavelength of the light-emitting diode corresponding to the wire NW1 and the central wavelength of the light-emitting diode corresponding to the wire NW4 was about 50 nm. The wavelength dispersion of the active areas shown in Figure 10 is lower than the dispersion obtained with the active zones represented in figure 8 .

[0066] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. The embodiments according to the invention are defined in the following claims.

Claims

1. Method of manufacturing an optoelectronic device (60) comprising light-emitting diodes (DEL) comprising the forming of three-dimensional semiconductor elements (26) made of a III-V compound, each comprising a lower portion (62) and an upper portion (64), and, for each semiconductor element, the forming of an active area (40) covering the top (30) of the upper portion and the forming of at least one semiconductor layer (44) of the III-V compound covering the active area, the upper portions are formed by molecular beam epitaxy at a pressure smaller than 1.33 mPa, for each semiconductor element (26), the upper portion (64) is flared with respect to the lower portion (62), the top (30) of the upper portion (64) having an area greater by at least 20% than the cross-section area of the lower portion (62), for the forming of the upper portions (64), the III / V ratio is in the range from 1.3 to 2 and the temperature of the upper portions is in the range from 700°C to 850°C.

2. Method according to claim 1, wherein the lower portions (62) are formed by selective etching or by epitaxial growth, preferably by a metal-organic chemical vapor deposition, or by molecular beam epitaxy.

3. Method according to claim 1 or 2, wherein, for the forming of the lower portions (62), the III / V ratio is in the range from 0.01 to 1.

4. Method according to claim 3, wherein, for the forming of the lower portions (62), the temperature of the lower portions is in the range from 700°C to 850°C.

5. Method according to any of claims 1 to 4, wherein the active areas (40) are formed by molecular beam epitaxy.

6. Method according to any of claims 1 to 5, wherein the lower portions (62) of the three-dimensional semiconductor elements (26) are microwires, nanowires, micrometer- or nanometer-range conical elements, or micrometer- or nanometer-range frustoconical elements.

7. Method according to any of claims 1 to 6, wherein the active areas (40) are the regions from which most of the electromagnetic radiation supplied by the light-emitting diodes (DEL) is emitted.