Reduced Parasitic Capacitive Semiconductor Components and Their Manufacturing Method

Description

BACKGROUND

[0001] The present Application for Patent claims priority to Non-provisional Application No. 16 / 408,207 entitled "SEMICONDUCTOR DEVICES WITH LOW PARASITIC CAPACITANCE" filed May 9, 2019, assigned to the assignee hereof.Field

[0002] Certain aspects of the present disclosure generally relate to semiconductor devices, and more particularly, to semiconductor devices with low parasitic capacitance.Background

[0003] Transistors are fundamental building blocks for semiconductor devices. As semiconductor fabrication technology advances, dimension of transistors becomes smaller and smaller, which results in more transistors integrated into a single semiconductor device. Figure 1 illustrates an exemplary semiconductor device comprising a plurality of transistors. A semiconductor device 100 is shown in Figure 1. The semiconductor device 100 comprises a substrate 102. As an example, the substrate 102 may comprise Silicon (Si) or other semiconductor materials. The semiconductor device 100 also comprises a source region 104 and a drain region 106 in the substrate 102. As an example, the source region 104 and the drain region 106 may comprise doped Si. The semiconductor device 100 also comprises a gate oxide layer 108, gate spacers 110(1) and 110(2), a metal gate 112, a cap layer 114, and a top dielectric layer 116 on the substrate 102. The gate oxide layer 108, the gate spacers 110(1) and 110(2), the metal gate 112, the cap layer 114, and the top dielectric layer 116 form a gate region of the semiconductor device 100. As an example, the gate oxide layer 108 may comprise Silicon Dioxide (SiO 2 ) or Hafnium Oxide (HfO x ). The gate spacers 110(1) and 110(2) may comprise Silicon Nitride (SiN). The metal gate 112 may comprise Aluminum (Al) or Tungsten (W). The cap layer 114 may comprise SiN. The top dielectric layer 116 may comprise SiO 2 . The semiconductor device 100 further comprises a source contact region 118 and a drain contact region 120 on the substrate 102. Top surfaces of the source contact region 118 and the drain contact region 120 are coplanar with a top surface of the gate region. As an example, the source contact region 118 and the drain contact region 120 may comprise W.

[0004] In the semiconductor device 100, parasitic capacitance may exist between the source contact region 118 and the metal gate 112 and between the drain contact region 120 and the metal gate 112. A magnitude of such parasitic capacitance depends on widths of the gate spacers 110(1) and 110(2). As semiconductor fabrication technology advances to smaller nodes, the widths of the gate spacers 110(1) and 110(2) become smaller and smaller, which results in an increase of the parasitic capacitance. For example, for semiconductor fabrication technology nodes such as 7 nanometer (nm) and 5 nm, the parasitic capacitance between the source / drain contact regions and the metal gate may equal one half of the capacitance of the whole semiconductor device. The parasitic capacitance can slow down device speed and increase power consumption. Thus, the parasitic capacitance may prevent further scaling of the semiconductor fabrication technology. There is a need to develop semiconductor devices with low parasitic capacitance. Attention is drawn to US 2016 / 141379 A1 relating to devices and methods for forming semiconductor devices with middle of line capacitance reduction in self-aligned contact process flow and fabrication. One method includes: obtaining a wafer with at least one source, drain, and gate; forming a first contact region over the at least one source and a second contact region over the at least one drain; and forming at least one first and second small contact over the first and second contact regions. One intermediate semiconductor device includes: a wafer with a gate, source region, and drain region; at least one first contact region positioned over a portion of the source region; at least one second contact region positioned over a portion of the drain region; at least one first small contact positioned above the first contact region; and at least one second small contact positioned above the second contact region. Further attention is drawn to US 2019 / 088742 A1 describing a method including forming a device above an active region defined in a semiconducting substrate. The device includes a first gate structure, a first spacer formed adjacent to the first gate structure, and first conductive source / drain contact structures positioned adjacent to the first gate structure and separated from the first gate structure by the first spacer. A first portion of the first conductive source / drain contact structures is recessed at a first axial position along the first gate structure to define a first cavity. A second portion of the first conductive source / drain contact structures is recessed at a second axial position along the first gate structure to define a second cavity. A dielectric cap layer is formed in the first and second cavities. A first conductive contact contacting the first gate structure at the first axial position is formed. Attention is also drawn to US 2018 / 114846 A1 relating to a method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.SUMMARY

[0005] The invention is defined by the appended independent claims. Further embodiments are defined by the appended dependent claims. Certain aspects of the present disclosure provide a semiconductor device. The semiconductor device includes a substrate. The semiconductor device also includes a gate region on the substrate. The semiconductor device further includes a contact region on the substrate, wherein the contact region comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.

[0006] Certain aspects of the present disclosure provide a method for fabricating a semiconductor device. The method includes forming a plurality of gate regions on a substrate. The method further includes forming a plurality of contact regions on the substrate, wherein each contact region of the plurality of contact regions comprises a first portion and a second portion, wherein the first portion is in contact with the substrate and has a first surface above the substrate, and wherein the second portion is in contact with the substrate and has a second surface above the substrate different from the first surface.

[0007] This summary has outlined the features and embodiments of the present disclosure so that the following detailed description may be better understood. Additional features and embodiments of the present disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other equivalent structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the present disclosure as set forth in the appended claims. The features, which are believed to be characteristic of the present disclosure, both as to its organization and method of operation, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 illustrates an exemplary semiconductor device comprising a plurality of transistors; Figure 2 illustrates an exemplary semiconductor device comprising a plurality of transistors with low parasitic capacitance in accordance with certain aspects of the present disclosure; Figures 3A-3D illustrate an exemplary fabrication process for the exemplary semiconductor device of Figure 2 in accordance with certain aspects of the present disclosure; and Figure 4 is a block diagram showing an exemplary wireless communication system in which an aspect of the present disclosure may be employed. DETAILED DESCRIPTION

[0009] With reference to the drawing figures, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0010] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various aspects and is not intended to represent the only aspect in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. It will be apparent to those skilled in the art, however, that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0011] Figure 2 illustrates an exemplary semiconductor device comprising a plurality of transistors with low parasitic capacitance in accordance with certain aspects of the present disclosure. A semiconductor device 200 is shown in Figure 2 with a top view and three different cross-section views (A-A, B-B, and C-C). The semiconductor device 200 comprises a substrate 202. As an example, the substrate 202 may comprise Silicon (Si) or other semiconductor materials. The semiconductor device 200 also comprises a source region 204 and a drain region 206 in the substrate 202. As an example, the source region 204 and the drain region 206 may comprise doped Si. The semiconductor device 200 also comprises a gate oxide layer 208, gate spacers 210(1) and 210(2), a metal gate 212, a cap layer 214, and a top dielectric layer 216 on the substrate 202. The gate oxide layer 208, the gate spacers 210(1) and 210(2), the metal gate 212, the cap layer 214, and the top dielectric layer 216 form a gate region of the semiconductor device 200. As an example, the gate oxide layer 208 may comprise Silicon Dioxide (SiO 2 ) or Hafnium Oxide (HfO x ). The gate spacers 210(1) and 210(2) may comprise Silicon Nitride (SiN). The metal gate 212 may comprise Aluminum (Al) or Tungsten (W). The cap layer 214 may comprise SiN. The top dielectric layer 216 may comprise SiO 2 . The semiconductor device 200 further comprises a source contact region comprising a first portion 218(1) and a second portion 218(2) and a drain contact region comprising a third portion 220(1) and a fourth portion 220(2) on the substrate 202. As an example, the source contact region and the drain contact region may comprise W. In the source contact region, the first portion 218(1) is in contact with the substrate 202 and has a first surface 222 above the substrate 202. The second portion 218(2) is in contact with the substrate 202 and has a second surface 224 above the substrate 202. The first surface 222 has a first height above the substrate 202. The second surface 224 has a second height above the substrate 202. The first height is smaller than the second height. As an example, the first height may be around 30% to 50% of the second height. The second surface 224 is coplanar with a top surface of the gate region. The second surface 224 may be a via landing surface for the source contact region. In the drain contact region, the third portion 220(1) is in contact with the substrate 202 and has a third surface 226 above the substrate 202. The fourth portion 220(2) is in contact with the substrate 202 and has a fourth surface 228 above the substrate 202. The third surface 226 has a third height above the substrate 202. The fourth surface 228 has a fourth height above the substrate 202. The third height is smaller than the fourth height. As an example, the third height may be around 30% to 50% of the fourth height. The fourth surface 228 is coplanar with the top surface of the gate region. The fourth surface 228 may be a via landing surface for the drain contact region.

[0012] In the semiconductor device 200, parasitic capacitance may exist between the source contact region and the metal gate 212 and between the drain contact region and the metal gate 212. In the source contact region, the first height of the first surface 222 of the first portion 218(1) is smaller than the second height of the second surface 224 of the second portion 218(2), where the second surface 224 of the second portion 218(2) is coplanar with the top surface of the gate region. The parasitic capacitance between the source contact region and the metal gate is lower in the semiconductor device 200 than in the semiconductor device 100, because in the semiconductor device 200, the source contact region has smaller areas to form the parasitic capacitance with the metal gate. In the drain contact region, the third height of the third surface 226 of the third portion 220(1) is smaller than the fourth height of the fourth surface 228 of the fourth portion 220(2), where the fourth surface 228 of the fourth portion 220(2) is coplanar with the top surface of the gate region. The parasitic capacitance between the drain contact region and the metal gate is lower in the semiconductor device 200 than in the semiconductor device 100, because in the semiconductor device 200, the drain contact region has smaller areas to form the parasitic capacitance with the metal gate. Since the parasitic capacitance between both the source contact region and the drain contact region and the metal gate is lower in the semiconductor device 200, the semiconductor device 200 would have a lower overall parasitic capacitance compared to the semiconductor device 100 and would be suitable for smaller nodes as semiconductor fabrication technology advances.

[0013] Figures 3A-3D illustrate an exemplary fabrication process for the semiconductor device 200 in Figure 2 in accordance with certain aspects of the present disclosure. In Figure 3A, stage 300(1) includes forming a plurality of gate regions on a substrate 302. As an example, the substrate 302 may comprise Si or other semiconductor materials. The substrate 302 comprises a source region 304 and a drain region 306. As an example, the source region 304 and the drain region 306 may comprise doped Si. A gate region in the plurality of gate regions comprises a gate oxide layer 308, gate spacers 310(1) and 310(2), a metal gate 312, a cap layer 314, and a top dielectric layer 316. As an example, the gate oxide layer 308 may comprise SiO 2 or HfO x . The gate spacers 310(1) and 310(2) may comprise SiN. The metal gate 312 may comprise Al or W. The cap layer 314 may comprise SiN. The top dielectric layer 316 may comprise SiO 2 . Stage 300(1) further includes forming a plurality of contact regions on the substrate 302. The plurality of contact regions comprises a source contact region 318 and a drain contact region 320. Top surfaces of the source contact region 318 and the drain contact region 320 are coplanar with a top surface of the gate region. As an example, the source contact region 318 and the drain contact region 320 may comprise W.

[0014] In Figure 3B, stage 300(2) includes recessing the plurality of contact regions. As an example, recessing the plurality of contact regions may comprise recessing the plurality of contact regions using dry etching. After recessing, the source contact region 318 comprises a first portion 318(1) in contact with the substrate 302 and the first portion 318(1) has a first surface 322 above the substrate 302. The first surface 322 has a first height above the substrate 302. The source contact region 318 further comprises a second portion 318(2) in contact with the substrate 302 and the second portion 318(2) has a second surface 324 above the substrate 302. The second surface 324 has a second height above the substrate 302. The first height is smaller than the second height. As an example, the first height may be around 30% to 50% of the second height. The second surface 324 is coplanar with the top surface of the gate region. The second surface 324 may be a via landing surface for the source contact region 318. After recessing, the drain contact region 320 comprises a third portion 320(1) in contact with the substrate 302 and the third portion 320(1) has a third surface 326 above the substrate 302. The third surface 326 has a third height above the substrate 302. The drain contact region 320 further comprises a fourth portion 320(2) in contact with the substrate 302 and the fourth portion 320(2) has a fourth surface 328 above the substrate 302. The fourth surface 328 has a fourth height above the substrate 302. The third height is smaller than the fourth height. As an example, the third height may be around 30% to 50% of the fourth height. The fourth surface 328 is coplanar with the top surface of the gate region. The fourth surface 328 may be a via landing surface for the drain contact region 320.

[0015] Parasitic capacitance may exist between the source contact region 318 and the metal gate 312 and between the drain contact region 320 and the metal gate 312. After recessing, in the source contact region 318, the first height of the first surface 322 of the first portion 318(1) is smaller than the second height of the second surface 324 of the second potion 318(2), where the second surface 324 of the second portion 318(2) is coplanar with the top surface of the gate region. The parasitic capacitance between the source contact region 318 and the metal gate 312 would decrease because after recessing the source contact region 318 would have smaller areas to form the parasitic capacitance with the metal gate 312. After recessing, in the drain contact region 320, the third height of the third surface 326 of the third portion 320(1) is smaller than the fourth height of the fourth surface 328 of the fourth portion 320(2), where the fourth surface 328 of the fourth portion 320(2) is coplanar with the top surface of the gate region. The parasitic capacitance between the drain contact region 320 and the metal gate 312 would decrease because after recessing the drain contact region 320 would have smaller areas to form the parasitic capacitance with the metal gate 312. Since the parasitic capacitance between both the source contact region 318 and the drain contact region 320 and the metal gate 312 decreases, overall parasitic capacitance decreases, which improves device speed and power consumption.

[0016] In Figure 3C, stage 300(3) includes forming a dielectric layer 330 on the plurality of gate regions and the plurality of contact regions. As an example, the dielectric layer 330 may comprise SiO 2 .

[0017] In Figure 3D, stage 300(4) includes patterning the dielectric layer 330 and forming a plurality of vias 332. As an example, the plurality of vias may comprise Copper (Cu), W, Ruthenium (Ru), or Cobalt (Co). After patterning the dielectric layer 330, the second surface 324 of the second portion 318(2) of the source contact region 318 and the fourth surface 328 of the fourth portion 320(2) of the drain contact region 320 are exposed and used as via landing surfaces. One via of the plurality of vias 332 is formed on the second surface 324 of the second portion 318(2) of the source contact region 318 and another via of the plurality of vias 332 is formed on the fourth surface 328 of the fourth portion 320(2) of the drain contact region 320. The plurality of vias 332 connects the plurality of contact regions to other elements in a semiconductor device.

[0018] The elements described herein are sometimes referred to as means for performing particular functions. In this regard, the plurality of contact regions is sometimes referred to herein as "means for contacting." The plurality of vias is sometimes referred to herein as "means for connecting." According to a further aspect of the present disclosure, the aforementioned means may be any layer, module, or any apparatus configured to perform the functions recited by the aforementioned means.

[0019] The semiconductor device comprising the plurality of transistors with low parasitic capacitance according to certain aspects disclosed herein may be provided in or integrated into any electronic device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, and a drone.

[0020] In this regard, Figure 4 is a block diagram showing an exemplary wireless communication system 400 in which an aspect of the present disclosure may be employed. For purposes of illustration, Figure 4 shows three remote units 420, 430, and 450 and two base stations 440. It will be recognized that wireless communication systems may have many more remote units and base stations. Remote units 420, 430, and 450 include integrated circuit (IC) devices 425A, 425C, and 425B that may include the disclosed semiconductor device. It will be recognized that other devices may also include the disclosed semiconductor device, such as the base stations, switching devices, and network equipment. Figure 4 shows forward link signals 480 from the base stations 440 to the remote units 420, 430, and 450 and reverse link signals 490 from the remote units 420, 430, and 450 to the base stations 440.

[0021] In Figure 4, remote unit 420 is shown as a mobile telephone, remote unit 430 is shown as a portable computer, and remote unit 450 is shown as a fixed location remote unit in a wireless local loop system. For example, a remote unit may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a PDA, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other communication device that stores or retrieves data or computer instructions, or combinations thereof. Although Figure 4 illustrates remote units according to certain aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Certain aspects of the present disclosure may be suitably employed in many devices, which include the disclosed semiconductor device.

[0022] The devices described herein may be employed in any circuit, hardware component, IC, or IC chip, as examples. Memory disclosed herein may be any type and size of memory and may be configured to store any type of information desired.

[0023] It is also noted that the operational steps described in any of the exemplary aspects herein are described to provide examples and discussion.

[0024] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate (202, 302); a gate region (208, 210, 212, 214, 216, 308, 310, 312, 314, 316) on the substrate; a source contact region on the substrate positioned adjacent to the gate region, the source contact region comprising a first portion (218(1), 318(1)) and a second portion (218(2), 318(2)) on the substrate; and a drain contact region on the substrate positioned adjacent to the gate region, the drain contact region comprising a third portion (220(1), 320(1)) and a fourth portion (220(2), 320(2)) on the substrate, wherein the first portion is in contact with the substrate and has a first surface (222, 322) above the substrate at a first axial position along the gate region, wherein the second portion is in contact with the substrate and has a second surface (224, 324) above the substrate different from the first surface at a second axial position along the gate region, wherein the third portion is in contact with the substrate and has a third surface (226, 326) above the substrate at a third axial position along the gate region, wherein the fourth portion is in contact with the substrate and has a fourth surface (228, 328) above the substrate different from the third surface at a fourth axial position along the gate region different from the second axial position, wherein the first surface has a first height above the substrate, the second surface has a second height above the substrate, the third surface has a third height above the substrate, and the fourth surface has a fourth height above the substrate, and wherein the first height is smaller than the second height and the third height is smaller than the fourth height.

2. The semiconductor device of claim 1, wherein the first height is around 30% to 50% of the second height.

3. The semiconductor device of claim 1, further comprising a dielectric layer (330) on the gate region and the source / drain contact regions, wherein the dielectric layer comprises Silicon Dioxide, SiO2.

4. The semiconductor device of claim 1, further comprising a via (332) on the second surface of the second portion of the source contact region, wherein the via comprises at least one of Copper, Cu, Tungsten, W, Ruthenium, Ru, and Cobalt, Co.

5. The semiconductor device of claim 1, wherein the gate region comprises a gate oxide layer (208, 308), gate spacers (210, 310), a metal gate (212, 312), a cap layer (214, 314), and a top dielectric layer (216, 316).

6. The semiconductor device of claim 1, wherein the source / drain contact regions comprise W.

7. The semiconductor device of claim 1, wherein the second surface is coplanar with a top surface of the gate region.

8. A method for fabricating a semiconductor device, comprising: forming a plurality of gate regions (208, 210, 212, 214, 216, 308, 310, 312, 314, 316) on a substrate (202, 302); and forming a plurality of contact regions on the substrate comprising at least one source contact region and at least one drain contact region adjacent to a respective gate region of the plurality of gate regions, wherein each source contact region of the plurality of contact regions comprises a first portion (218(1), 318(1)) and a second portion (218(2), 318(2)) on the substrate and each drain contact region of the plurality of contact regions comprises a third portion (220(1), 320(1)) and a fourth portion (220(2), 320(2)) on the substrate, wherein the first portion is in contact with the substrate and has a first surface (222, 322) above the substrate at a first axial position along the respective gate region, wherein the second portion is in contact with the substrate and has a second surface (224, 324) above the substrate different from the first surface at a second axial position along the respective gate region, wherein the third portion is in contact with the substrate and has a third surface (226, 326) above the substrate at a third axial position along the respective gate region, wherein the fourth portion is in contact with the substrate and has a fourth surface (228, 328) above the substrate different from the third surface at a fourth axial position along the respective gate region different from the second axial position, wherein the first surface has a first height above the substrate, the second surface has a second height above the substrate, the third surface has a third height above the substrate, and the fourth surface has a fourth height above the substrate, and wherein the first height is smaller than the second height and the third height is smaller than the fourth height.

9. The method of claim 8, wherein the first height is around 30% to 50% of the second height.

10. The method of claim 8, wherein the second surface is coplanar with a top surface of the respective gate region of the plurality of gate regions.

11. The method of claim 8, wherein the forming the plurality of contact regions on the substrate comprises recessing the plurality of contact regions using dry etching.

12. The method of claim 8, further comprising forming a dielectric layer (330) on the plurality of gate regions and the plurality of contact regions.

13. The method of claim 12, wherein the dielectric layer comprises Silicon Dioxide, SiO2.

14. The method of claim 12, further comprising forming a via (332) on the second surface of the second portion of each source contact region, wherein the via comprises at least one of Copper, Cu, Tungsten, W, Ruthenium, Ru, and Cobalt, Co.

15. The method of claim 8, wherein the plurality of contact regions comprises W.