CONTROL SWITCH OF A DRIVER CIRCUIT, ARRAY SUBSTRATE AND DISPLAY PANEL

Description

TECHNICAL FIELD

[0001] This invention relates to the field of display technology, and more particularly relates to a control switch of a driving circuit, an array substrate, and a display panel.BACKGROUND

[0002] The statements herein are intended for the mere purpose of providing background information related to the present invention and do not necessarily constitute prior art.

[0003] Document US 2019 / 0296152 A1 discloses a thin film transistor including a gate, an active layer, a source, and a drain. The source includes a connecting portion, a first sub-portion, a second sub-portion, and a third sub-portion that are arranged sequentially and in parallel. At first ends of the sub-portions, the connecting portion is connected to the portions to form two adjacent recesses. At second ends of the sub-portions, the distance from an end of the second sub-portion to the connecting portion is smaller than a distance from an end of the first sub-portion to the connecting portion and a distance from an end of the third sub-portion to the connecting portion. The drain includes a connecting block, a first drain and a second drain disposed in the two recesses respectively, and at least a portion of the connecting block is disposed between the first and the second drains to connect the first and the second drains.

[0004] Document US 2013 / 0270567 A discloses a method of fabricating a thin film transistor including providing a substrate where a gate, an insulating layer, and a channel layer are formed. A conductive layer is formed on the substrate to cover the channel layer and the insulating layer. A photoresist layer is formed on the conductive layer. A photo mask is placed above the photoresist layer and has a data line pattern, a source pattern, and a drain pattern.

[0005] Document CN 105 140 293 A discloses a thin-film transistor comprising a source electrode and a drain electrode, which are arranged at the same layer and are in a comb form respectively; the source electrode is connected with a source electrode lead; the source electrode comprises a plurality of first source electrode comb tooth parts, a source electrode comb handle part and a second source electrode comb tooth part; the source electrode comb handle part is connected with the plurality of first source electrode comb tooth parts; the drain electrode comprises at least one first drain electrode comb tooth part, a drain electrode comb handle part and a second drain electrode comb tooth part; the drain electrode comb handle part is connected with the first drain electrode comb tooth part; the second source electrode comb tooth part is connected with the source electrode comb handle part and is connected with the source electrode lead; the second drain electrode comb tooth part is located between the second source electrode comb tooth part and the first source electrode comb tooth part close to the second source electrode comb tooth part; and the second drain electrode comb tooth part is not connected with the drain electrode comb handle part.

[0006] Document CN 106 200 160 A discloses an array substrate comprising a display region and a driving circuit region, the driving circuit region comprises multiple driving circuit pads and multiple thin-film transistors, each thin-film transistor comprising a source electrode and a drain electrode, each drain electrode comprises multiple first comb tooth electrodes which are spaced and parallelly arranged and a first comb handle electrode connecting the first comb tooth electrodes, and each source electrode comprises second comb tooth electrodes which are spaced and parallelly arranged and a second comb handle electrode connecting the second comb tooth electrodes. Each drain electrode and the corresponding source electrode are in interpolation structure distribution, each drain electrode further comprises a drain electrode connecting lead, and the first end of each drain electrode connecting lead is connected with the corresponding first comb handle electrode while the second end of the same is connected with the corresponding driving circuit pad.

[0007] Nowadays, display technology is widely used in the display of televisions, mobile phones and the display of public information. There are a variety of display panels for displaying pictures, and they can display colorful pictures. More and more display panels, such as Thin Film Transistor-Liquid Crystal Displays (TFT-LCD), Organic Light Emitting Diode (OLED) displays, etc., need to use Gate Driver on Array (GOA) technology, in which the GOA circuits are integrated onto the array substrate in the display panel to realize the scanning and driving of the display panel, so that the product costs can be reduced in terms of materials cost and manufacturing process.

[0008] Typically, when manufacturing a GOA circuit, the source, drain and source leads in a thin film transistor are disposed in the same layer and formed by etching at the same time, but the problem of uneven etching is prone to occur during the etching process. Furthermore, as the degree of integration of GOA circuits is getting increasingly higher, the channel distance between the source and the drain is getting smaller and smaller, so when the etching is not uniform, the source lead will be easily connected to both the source and the drain, resulting in a short circuit between the source and the drain.SUMMARY

[0009] The present invention provides a control switch of a driving circuit, an array substrate, and a display panel, which can prevent the occurrence of a short circuit between a source electrode and a drain electrode caused by uneven etching of the driving circuit.

[0010] Specifically, the invention provides a control switch of a driving circuit as claimed in claim 1 attached, an array substrate as claimed in claim 6 attached, and a display panel as claimed in claim 7 attached. Preferred embodiments of the invention are claimed in dependent claims attached.

[0011] The present invention improves the thin film transistor and the source lead in the driving circuit, so that the extension line of the source lead is located between the first drain branch and the source trunk, and does not overlap with the drain branch. When etching the film layer where the source electrode, the drain electrode and the source electrode lead are located, even if there is a problem of uneven etching, which causes the top of the source electrode lead to protrude from the first source branch, its protruding position will at most extend to between the first drain branch and the source truck, and does not intersect the first drain branch, so it will not cause a short circuit between the source electrode and the drain electrode.BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the embodiments of the present invention, constitute a part of the specification, are used to illustrate the embodiments of the present invention, and together with the written description, serve to explain the principles of the present invention. Obviously, the drawings used in the following description merely depict some embodiments of the present invention, and for those having ordinary skill in the art, other drawings can also be obtained from these drawings without investing creative effort. In the drawings: FIG. 1 is a schematic plan view of an array substrate. FIG. 2 is a partial enlarged view of portion M shown in FIG. 1. FIG. 3 is a partial schematic diagram of a gate driving unit not in accordance with the present invention. FIG. 4 is a partial schematic diagram of another gate driving unit not in accordance with the present invention. FIG. 5 is a schematic diagram based on FIG. 3 in an ideal state not in accordance with the present invention. FIG. 6 is a schematic diagram based on FIG. 4 in an ideal state not in accordance with the present invention. FIG. 7 is a partial schematic diagram of a driving circuit including a first type of thin film transistor not in accordance with of the present invention. FIG. 8 is a partial schematic diagram of a driving circuit including a second type of thin film transistor not in accordance with the present invention. FIG. 9 is a partial schematic diagram of a driving circuit including a third type of thin film transistors provided by an embodiment of the present invention. FIG. 10 is a partial schematic diagram of a driving circuit including the first type of thin film transistor not in accordance with the present invention. FIG. 11 is a partial schematic diagram of a driving circuit including the second type of thin film transistor not in accordance with the present invention. FIG. 12 is a schematic diagram of a display panel according to an embodiment of the present invention. DETAILED DESCRIPTION OF EMBODIMENTS

[0013] It should be understood that the terminology used herein, the specific structural and functional details disclosed are intended for the mere purpose of describing specific embodiments and are representative, but the present invention may be embodied in many alternative forms and should not be construed as limited only the embodiments set forth herein.

[0014] In the description of this invention, the terms "first" and "second" are merely used for description purposes, and cannot be understood as indicating relative importance, or implicitly indicating the number of indicated technical features. Thus, unless otherwise specified, features defined as "first" and "second" may expressly or implicitly include one or more of the features; "plurality" means two or more. The terms "including", "comprising", and any variations thereof are intended to mean a non-exclusive inclusion, namely one or more other features, integers, steps, operations, units, components and / or combinations thereof may be present or added.

[0015] In addition, terms such as "center", "transverse", "lateral", "above", "on", "under", "below", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicative of orientations or positional relationships are described based on the orientations or relative positional relationships illustrated in the drawings, and are intended for the mere purpose of convenience of simplified description of the present invention, rather than indicating that the device or element referred to must have a specific orientation or be constructed, and operate in a particular orientation. Thus, these terms should not be construed as limiting the present invention.

[0016] In addition, unless otherwise expressly specified and defined, terms "installed on", "connected to", and "coupled to" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection, or may also be an electrical connection; it may be a direct connection, an indirect connection through an intermediate medium, or an internal connection between two components. For those having ordinary skill in the art, the specific meanings of the above terms in this invention can be understood depending on specific contexts.

[0017] The present invention will be described in detail below with reference to the accompanying drawings and optional embodiments. It should be noted that, should no conflict be present, the embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0018] FIGS. 1 and 2 show schematic plan views of an array substrate. A scan line 300 is disposed in a display area of the array substrate 100, and a driving circuit 200 is disposed in a non-display area of the array substrate 100, which may specifically be an array substrate gate driving circuit. The driving circuit 200 includes a frame start signal line 205 (STV), a gate voltage control line 206 (VGL), a clock signal line 207 (CKV) and a plurality of gate driving units 270. The input ends of the gate driving unit 270 are respectively connected to STV, VGL and CKV, and the output end of the gate driving circuit 270 is connected to the scan line 300 to drive the scan line 300.

[0019] In particular, the gate driving unit 270 includes a first thin film transistor 201, a second thin film transistor 202, a third thin film transistor 203 and a fourth thin film transistor 204. The source electrode 230 of the first thin film transistor 201 is connected to the gate voltage control line 206 and to the source electrode 230 of the second thin film transistor 202 through two source leads 210, respectively. The drain electrode 240 of the first thin film transistor 201 is connected to the source electrode 230 of the third thin film transistor 203 and to the gate electrode 260 of the fourth thin film transistor 204, and the gate electrode 260 of the first thin film transistor 201 is connected to the gate 260 of the second thin film transistor 202. The drain electrode 240 of the second thin film transistor 202 is connected to the source electrode 230 of the fourth thin film transistor 204, and the gate electrode 260 of the second thin film transistor 202 is connected to the gate electrode 260 of the fourth thin film transistor 204. The drain 240 of the third thin film transistor 203 is connected to the frame start signal line 205. The drain 240 of the fourth thin film transistor 204 is connected to the clock signal line 207.

[0020] In the gate driving unit 270 shown in FIG. 2, there are four thin film transistors connected to each other and other wirings. It can be seen in FIG. that there are three blank areas, namely area A, area B and area C; between area B and area C, two thin film transistors 220 are connected through a source lead 210. Before the metal layer is etched into the source electrode 230, the drain electrode 240 and other metal line patterns, an etching stop layer needs to be formed on the source electrode 230, the drain electrode 240 and other metal line patterns, and then a developer is used to form the stop layer pattern. Since the area B and the area C are relatively large, more developer needs to be consumed, so that the developing energy consumed by the area D and the area E is reduced, and so the stop layers corresponding to the area D and the area E cannot be easily completely etched, hence the problem of uneven etching occurs when etching the metal layer pattern, resulting in the short circuit of the source electrode 230 and the drain electrode 240 at the region D and the region E.

[0021] FIGS. 3 and 4 show partial schematic diagrams of two exemplary GOAs not in accordance with the present invention. When the metal patterns corresponding to the regions D and E are not uniformly etched, the source leads 210 in FIGS. 3 and 4 will extend into the channel of the source 230 of the thin film transistor 220, or even connect with the drain electrode 240, resulting in a short circuit between the source electrode 230 and the drain electrode 240.

[0022] FIGS. 5 and 6 are schematic diagrams respectively based on FIGS. 3 and 4 under ideal conditions, but they need to consume a lot of developer to ensure that the stop layers corresponding to the regions D and E are completely etched, so that when the metal pattern is subsequently etched, the source lead 210 does not protrude from the source electrode 230 and extend into the channel of the source electrode 230.

[0023] In view of this, the present invention provides a control switch of a driving circuit 200 that does not cause a short circuit between the source electrode 230 and the drain electrode 240 even when the etching is uneven. As illustrated in FIGS. 1, 2, 7 to 11, whereby FIGS. 7, 8, 10 and 11 are not according to the claimed invention, the control switch includes a thin film transistor 220, and the driving circuit 200 further includes a source lead 210 connected to the thin film transistor 220. The thin film transistor 220 includes a source electrode 230, a drain electrode 240 and a gate electrode 260.The source electrode 230 includes at least four source branches 231 arranged in parallel, and a source trunk 234 connecting the at least four source branches 231. The drain electrode 240 is disposed in the same layer as the source electrode 230, and includes at least three drain branches 241, and a drain trunk 244 connecting the at least three drain branches 241 together, where the source branch 231 directly connected to the source lead 210 is a first source branch 232, and the first source branch 232 is connected to an end of the source trunk 234. The at least three drain branches 241 and the at least four source branches 231 are arranged in parallel and alternately to form channels. In particular, the drain branch 241 disposed adjacent to the first source branch 232 is the first drain branch 242, the gate 260 is disposed corresponding to the source 230 and the drain 240, and where the extension line of the source lead 210 is located between the first drain branch 242 and the source trunk 234.

[0024] Moreover, the gate electrode 260 may be located under the source electrode 230 and the drain electrode 240 to form a bottom gate structure in the thin film transistor 220, and the gate electrode 260 may also alternatively be located above the source electrode 230 and the drain electrode 240 to form a top gate structure in the thin film transistor 220.

[0025] Currently, the source lead 210 is generally connected vertically to the first source branch 232. Due to higher and higher requirements for the integration of the driving circuit 200, the channel spacing between the source electrode 230 and the drain electrode 240 becomes smaller and smaller. When the metal film layer where the source electrode 230, the drain electrode 240 and the source electrode branch 231 are located is not etched uniformly due to various reasons, for example, in FIG. 2, due to the large blank areas of regions B and C, more etching solution needs to be consumed, so that the etching solution in regions D and E is insufficient, resulting in the problem of uneven etching of the metal patterns in the regions D and E. At this time, the end of the source lead 210 is not etched cleanly, resulting in the end of the source lead 210 protruding from the first source branch 232. Since the channel distance between the source 230 and the drain 240 is small, it is easy to connect the source electrode lead 210 to the drain electrode 240, so that the source electrode 230 and the drain electrode 240 are short-circuited. Moreover, in the current design, since the width dimension of the source lead 210 is generally large to increase the charging effect on the thin film transistor 220, the source lead 210 is more susceptible to the influence of uneven etching, and the protruding area from the first source branch 232 is large, increasing the risk of a short circuit between the source 230 and the drain 240.

[0026] The present invention improves the thin film transistor 220 and the source lead 210 in the driving circuit 200, so that the extension line of the source lead 210 is located between the first drain branch 242 and the source trunk 234, and does not overlap the drain branch 241. When the film layer where the source electrode 230, the drain electrode 240 and the source electrode lead 210 are located is etched, even if there is a problem of uneven etching so that the top of the source electrode lead 210 protrudes from the first source branch 232, the protruding position will at most extend between the first drain branch 242 and the source trunk 234, and will not intersect the first drain branch 242, so it will not cause a short circuit between the source 230 and the drain 240. In this solution, the channel width between the source electrode 230 and the drain electrode 240 and the width of the source lead 210 are not limited. Therefore, the driving circuit 200 can be made to meet the advantages of high integration, high charging effect, and resistance to short circuit at the same time, thereby improving the competitiveness among products of the same type.

[0027] In FIGS. 7 to 9, one thin film transistor 220 is connected to two source leads 210 at the same time. In this case, there are two first source branches 232 and at least one first drain branch 242. In FIGS. 10-11, one thin film transistor 220 is only connected to one source lead 210. At this time, there is only one first source branch 232, at least one second source branch 233, and only one first drain branch 242. These two connection situations can be applied to one driving circuit 200 or to different driving circuits 200, which can be specifically designed depending on usage conditions.

[0028] As shown in FIG. 7 and not in accordance with the present invention, the source electrode 230 has only two first source branches 232 connected to the source leads 210 in one-to-one correspondence, and a source trunk 234 connecting the two first source branches 232 together. The drain electrode 240 has only one first drain branch 242, and the first drain branch 242 is located between the two first source branches 232. The two first source branches 232 are each between the first drain branch 242 and the source truck 234 while not overlapping the first drain branch 242. The thin film transistor 220 adopts the simplest dual-channel structure, the shape of the source electrode 230 is similar to a U-shape, and two channels are formed between the first drain branch 242 and the two first source branches 232. Since the two source leads 210 are compared and distinguished with the same first drain branch 242 as long as they are not in contact with the first drain branch 242, the design of the etching pattern is simple.

[0029] As shown in FIG. 8 and not in accordance with the present invention, the source electrode 230 includes two first source electrode branches 232, one second source electrode branch 233 and one source electrode trunk 234 at this time. The two first source branches 232 are respectively connected to both ends of the source trunk 234, and are respectively connected to the two source leads 210 in one-to-one correspondence. The second source branch 233 is arranged in parallel between the two first source branches 232, and is connected to the middle of the source trunk 234. The drain 240 includes two first drain branches 242 and a drain trunk 244. The two first drain branches 242 are respectively connected to two ends of the drain trunk 244. Each drain branch 241 is located between two adjacent first source branch 232 and second source branch 233. In this embodiment, the shape of the source electrode 230 is similar to the W-shape, and the shape of the drain electrode 240 is similar to the U-shape. Each source lead 210 may extend in the region formed between the first source branch 232 and the adjacent second source branch 233 without contacting other structures. Therefore, when the problem of uneven etching is serious, there is enough fault tolerance space to prevent the source lead 210 from being extended too long to cause the source 230 and the drain 240 to be short-circuited.

[0030] As shown in FIG. 9, at this time, the source electrode 230 includes two first source electrode branches 232, two second source electrode branches 233 and a source electrode trunk 234. The two first source branches 232 are respectively connected to both ends of the source trunk 234, and are respectively connected to the two source leads 210 in a one-to-one correspondence. The two second source branches 233 are arranged in parallel between the two first source branches 232, and are connected to the source trunk 234. The drain 240 includes two first drain branches 242, a second drain branch 243 and a drain trunk 244. The two first drain branches 242 are respectively connected to two ends of the drain trunk 244. The second drain branch 243 is arranged in parallel between the two first drain branches 242, and is connected to the middle of the drain trunk 244. Each of the first drain branches 242 is located between two adjacent first source branch 232 and second source branch 233. The second drain branch 243 is located between two adjacent second source branches 233. In this embodiment, the shape of the source electrode 230 is similar to three parallel U-shaped structures, and the shape of the drain electrode 240 is similar to the W-shaped structure. Compared with FIGS. 7 and 8, the electrical performance of the thin film transistor 220 in FIG. 9 is better. Of course, the present invention can also continue to increase the number of the second source branches 233 and the second drain branches 243 on the basis of FIG. 9, so that the electrical performance of the thin film transistor 220 can be further improved.

[0031] As shown in FIG. 10 and not in accordance with the present invention, the source electrode 230 has only one first source branch 232 connected to the source lead 210, one second source branch 233 not connected to the source lead 210, and one source truck 234 connecting the first source branch 232 and the second source branch 233 together. The drain 240 has only one first drain branch 242, and the first drain branch 242 is arranged in parallel between the first source branch 232 and the second source branch 233, and the first drain branch 242 forms two channels with the first source branch 232 and the second source branch 233 respectively. In this embodiment, the thin film transistor 220 is also the simplest dual-channel type, but the difference from FIG. 7 is that since the thin film transistor in FIG. 10 is only connected to one source lead 210, the source lead has a larger extension space, and it is not easy to short-circuit with other structures.

[0032] As shown in FIG. 11 and not in accordance with the present invention, the drain electrode 240 includes one first source branch 232 connected to the source lead 210, two second source branches 233 not connected to a source lead 210, and a source trunk 234 connecting the first source branch 232 and the second source branch 233 together. One of the second source branches 233 and the first source branch 232 are connected to both ends of the source trunk 234, and the other second source branch 233 is connected to the middle of the source trunk 234. The drain 240 includes a first drain branch 242, a second drain branch 243 and a drain trunk 244. The first drain branch 242 and the second drain branch 243 are respectively connected to both ends of the drain trunk 244. The first drain branches 242 are arranged in parallel between the adjacent first source branch 232 and second source branch 233. The second drain branch 243 is arranged in parallel between two adjacent second source branches 233. In order to further increase the electrical performance of the thin film transistor 220, the number of the second source branches 233 and the second drain branches 243 may be further increased on the basis of FIG. 11.

[0033] In the present invention, the distance between the first drain branch 242 and the source trunk 234 can be increased by shortening the length of the first drain branch 242, so that the extension line of the source lead 210 can be made between the first drain branch 242 and the source trunk 234, and does not overlap the first drain branch 242. It is also possible to reduce the width of the source lead 210, so that when the extension line of the source lead 210 is between the first drain branch 242 and the source trunk 234, the extension line of the source lead 210 does not overlap the first drain branch 242. It is also possible to reduce the width of the source trunk 234, so that when the extension line of the source lead 210 is between the first drain branch 242 and the source trunk 234, the extension line of the source lead 210 does not overlap the first drain branch 242. The same technical effect can also be achieved by a combination of two or more of the above methods.

[0034] In FIGS. 7 to 11, the distance between the first drain branch 242 and the source stem 234 is increased by shortening the length of the first drain branch 242. This method will not affect the charging effect of the source lead 210, nor will it affect the electrical uniformity effects of the source electrode 230 and the drain electrode 240. Moreover, compared with other methods, this method can arbitrarily control the length of the drain 240. Since the length of the drain electrode 240 is relatively large, the distance between the first drain branch 242 and the source electrode stem 234 can be made relatively large. In FIG. 9 and FIG. 11, the length of the second drain branch 243 does not need to be changed, and the distance between the second drain branch 243 and the source truck 234 is smaller than the distance between the first drain branch 242 and the source trunk 234. Such a design makes the channel distance between the source electrode 230 and the drain electrode 240 not greatly affected although the length of the first drain branch 242 is reduced, and the influence on the thin film transistor 220 is small.

[0035] Specifically, the distance by which the first drain branch 242 is shortened can be equal to the width of the source lead 240, that is, the difference between the lengths of the second drain branch 243 and the first drain branch 242 is equal to the width of the source lead 210. The length direction of the first drain branch 242 and the second drain branch 243 is the extension direction of the first drain branch 242 and the second drain branch 243. Such a close arrangement makes full use of the blank area between the first drain branch 242 and the source truck 234, which is beneficial to reduce the volume of the thin film transistor 220. Furthermore, the second drain branch 243 is flush with the top of the source lead 210 (the side close to the source trunk), which facilitates the alignment design when making the pattern, thereby reducing the etching difficulty of etching the barrier pattern and improving the uniform effect of etching the metal layer where the source electrode 230, the drain electrode 240 and the source electrode lead 210 are located.

[0036] Moreover, when the thin film transistor 220 is connected with the two source leads 210, the two source leads 210 can be arranged on the same straight line, so that the shortened distances of the two first drain branches 242 can be the same, which not only facilitates improving the uniformity of the source 230 and the drain 240 at both ends of the thin film transistor 220, but also maximize the lengths of the two first drain branches 242 to avoid that one first drain branch 242 is long and the other first drain branch 242 is short, which would otherwise reduce the electrical performance of the thin film transistor 220. Of course, the two source leads 210 may not be arranged on the same straight line, so as to prevent the two source leads 210 from being short-circuited, resulting in the risk of a short circuit.

[0037] In this invention, all source branches 231 and drain branches 241 are strip-shaped structures, which can be rectangular, oval or other shapes. The extension direction of the source branch 231 and the extension direction of the source trunk 234 are perpendicular to each other, and the extension direction of the drain branch 241 and the extension direction of the drain trunk 244 are also perpendicular to each other. However, the extension direction of the source branch 231 and the extension direction of the source trunk 234 may form an acute angle, and the extension direction of the drain branch 241 and the extension direction of the drain trunk 244 may also form an acute angle. The source lead 210 and the first source branch 232 may be arranged vertically or obliquely with respect to each other.

[0038] Moreover, the widths of the source branches 231, the source trunk 234, the drain branches 241 and the drain trunk 244 are all equal, and the channel widths between the second source branches 233 and the adjacent drain branches 241 are also equal, thereby increasing the conductivity of the thin film transistor 220. Since the present invention only needs to reduce the length of the first drain branch 242 to overcome the short circuit between the source electrode 230 and the drain electrode 240 caused by uneven etching, the channel width between the source branch 231 and the drain branch 241 can be further reduced, the distance between the second drain branch 243 and the source trunk 234 can be further reduced, and the distance between the source trunk 234 and the drain trunk 244 can be further reduced, so as to further improve the integration degree in the driving circuit 200, reduce the occupied area of the driving circuit 200 in the display panel, and further reduce the narrow bezel of the display panel. FIG. 12 shows a schematic diagram of a display panel. As another embodiment of the present invention, a display panel 400 is further disclosed. The display panel 400 includes the array substrate 100 illustrated in FIG. 1, a color filter substrate 500 disposed opposite to the array substrate 100, and a liquid crystal layer 600 disposed between the array substrate 100 and the color filter substrate 500. The non-display area of the array substrate 100 includes the above-mentioned driving circuit 200. In addition, the thin film transistor 220 in the present invention is not only applicable to the row driving circuit of the array substrate in the non-display area, but also applicable to the active switches in the display area of the array substrate 100.

[0039] The technical solutions of the present invention may be widely used in various display panels, such as TN (Twisted Nematic) display panels, IPS (In-Plane Switching) display panels, VA (Vertical Alignment) display panels, and MVA (Multi-Domain Vertical Alignment) display panels. Of course, the above solutions are also applicable to other types of display panels.

[0040] It should be noted that the inventive concept of the present invention can form a large number of embodiments, but they cannot be enumerated because the length of the invention document is limited.

[0041] The foregoing is a further detailed description of the present invention in conjunction with specific optional embodiments, but it should not be construed as that the specific implementation of the present invention will be limited to these descriptions.

Claims

1. A control switch of a driving circuit (200), the control switch comprising a thin film transistor (220), the driving circuit (200) further comprising at least one source lead (210) connected to the thin film transistor (220), the thin film transistor (220) comprising: a source electrode (230), comprising at least four source branches (231) arranged in parallel, and a source trunk (234) connecting the at least four source branches (231) together, wherein each source branch (231) directly connected to the at least one source lead (210) is a first source branch (232), and wherein the first source branch (232) is connected to an end of the source trunk (234); a drain electrode (240), disposed in a same layer as the source electrode (230), comprising at least three drain branches (241) and a drain trunk (244) connecting the at least three drain branches (241) together, wherein the at least three drain branches (241) and the at least four source branches (231) are arranged in parallel and alternately to form channels, and wherein each drain branch (241) disposed adjacent to each first source branch (232) is a first drain branch (242); and a gate electrode (260), disposed corresponding to the source electrode (230) and the drain electrode (240); wherein an extension line of each of the source leads (210) is located between the respective first drain branch (242) and the source trunk (234); the thin film transistor (220) is connected to two said source leads (210), wherein a number of the first source branches (232) is two, and wherein the two first source branches (232) are respectively connected to both ends of the source trunk (234) and are connected to the two source leads (210) in one-to-one correspondence; each first drain branch (242) is disposed between the two first source branches (232), and wherein an extension line of each of the two source leads (210) is located between the respective first drain branch (242) and the source trunk (234) and does not overlap the respective first drain branch (242); each source branch (231) not directly connected to the at least one source lead (210) is a second source branch (233), wherein the number of the second source branches is at least two, and wherein the second source branch (233) is arranged in parallel between the two first source branches (232), and is connected to the source trunk (234); each drain branch (241 ) not disposed adjacent to the first source branch (232) is a second drain branch (243), wherein a number of the first drain branches (242) is two and a number of the second drain branches is at least one, and the two first drain branches (242) are respectively connected to two ends of the drain trunk (244), wherein the second drain branch (243) is arranged in parallel between the two first drain branches (242), and is connected to the drain trunk (244); each first drain branch (242) is arranged between the respective first source branch (232) and the respective second source branch (233) that are adjacent to each other, and the second drain branch (243) is arranged between two adjacent second source branches (233); and a distance between the at least one second drain branch (243) and the source trunk (234) is less than a distance between each first drain branch (242) and the source trunk (234).

2. The control switch of claim 1, wherein the source electrode (230) comprises two first source branches (232), two second source branches (233), and one source trunk (234); wherein the drain electrode (240) comprises two first drain branches (242), one second drain branch (243), and one drain trunk (244); wherein each first drain branch (242) is located between the respective first source branch (232) and the respective second source branch (233) that are adjacent to each other; and wherein the second drain branch (243) is located between the two adjacent second source branches (233).

3. The control switch of claim 1, wherein the two source leads (210) are located on a same straight line.

4. The control switch of claim 1, wherein the two source leads (210) are not located on a same straight line.

5. The control switch of claim 1, wherein the at least four source branches (231) and the at least three drain branches (241) each have a strip, a rectangular or an ellipse shape.

6. An array substrate (100), comprising a driving circuit (200), a source lead (210), and a scan line (300) driven by the driving circuit (200), the driving circuit comprising a control switch according to claim 1.

7. A display panel comprising an array substrate (100) according to claim 6, a color filter substrate (500) disposed opposite to the array substrate (100), and a liquid crystal layer (600) disposed between the array substrate (100) and the color filter substrate (500).