Non-volatile memory cell array formed in a P-well in a deep N-well in a P-substrate

Description

PRIORITY CLAIM

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 190,200, filed on May 18, 2021, and titled, "Non-Volatile Memory Cell Array with Substrate Capable of Receiving Negative Voltage During Erase Operations," and U.S. Patent Application No. 17 / 461,981 filed on August 30, 2021, and titled "Non-volatile Memory Cell Array Formed in a P-Well in a Deep N-Well in a P-Substrate".FIELD OF THE INVENTION

[0002] Numerous embodiments are disclosed for a non-volatile memory cell array formed in a p-well in a deep n-well in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which reduces the peak positive voltage required to erase the cells in the array.

[0003] US 6768671 B1 discribes that in an array of nonvolatile memory cells, as many memory cells as desired and indeed even the entire array of memory cells may be placed in a single region of the bulk, illustratively a p-well. Peripheral circuitry is used to in effect section the memory array into blocks and groups of blocks, and to establish suitable biasing and counter-biasing within those blocks and groups during page or block erase operations to limit erase disturb. Each group is provided with its own set of voltage switches, which furnishes the bias voltages for the various modes of operation, including erase. Each of the voltage switches furnish either a large positive voltage when its group is selected, or a large negative voltage when its group is unselected. The size of the group is established as a compromise between degree of erase disturb and substrate area required for the voltage switches.

[0004] US 20060044872 A1 describes NAND architecture Flash memory strings, memory arrays, and memory devices that utilize depletion mode floating gate memory cells. Depletion mode floating gate memory cells allegedly allow for increased cell current through lower channel rdS resistance and decreased "narrow width" effect, allegedly allowing for increased scaling of NAND memory cell strings.

[0005] US 20070028001 A1 describes a method for programming and erasing an array of NMOS electrically erasable programmable read only memory (EEPROM) cells. In addition, the array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

[0006] US 20110096609 A1 describes that a nonvolatile memory array has nonvolatile memory cells arranged in rows and columns where each column has a bit line and source line associated with and in parallel with the nonvolatile memory cells. In programming the nonvolatile memory cell, approximately equal program voltage levels are applied to a drain and a source of a selected charge retaining transistor such that the difference in the voltage between the drain and the source of the selected charge retaining transistor is less than a drain to source breakdown voltage of the selected charge retaining transistor to prevent drain-to-source punch through. In programming or erasing the nonvolatile memory cell a control gate and a bulk program voltage level is applied to a control gate and bulk such that the magnitude of the control gate and bulk program voltage levels is less than a breakdown voltage level of peripheral circuitry.

[0007] US 20190115088 A1 describes that during a program, read, or erase operation of one or more non-volatile flash memory cells in an array of non-volatile flash memory cells, a negative voltage can be applied to the word lines and / or coupling gates of the selected or unselected non-volatile flash memory cells. The negative voltage is generated by a negative high voltage level shifter using one of several embodiments disclosed herein.

[0008] EP 1002320 A1 describes that the negative supply voltage (317) and isolation well bias (320) used by the wordline drivers (306) during erase are decoded separately from the decoding of the inputs of the individual wordline drivers. The wordline drivers selectively drive wordlines with a wordline voltage from either a first supply voltage source or a second supply voltage source in response to address signals which identify the respective drivers. The second supply voltage source includes a set of supply voltage selectors (302, 319). Each supply voltage selector in the set is coupled with a subset of the set of drivers.BACKGROUND OF THE INVENTION

[0009] Different types of non-volatile memories are well known. For example, U.S. Patent 5,029,130 ("the "130 patent"), discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 110 is shown in Figure 1. Each memory cell 110 includes source region 14 and drain region 16 formed in semiconductor substrate 12, with channel region 18 there between. Floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of channel region 18, and over a portion of source region 14. Word line terminal 22 (which is typically coupled to a word line) has a first portion that is disposed over and insulated from (and controls the conductivity of) a second portion of channel region 18, and a second portion that extends up and over the floating gate 20. Floating gate 20 and word line terminal 22 are insulated from substrate 12 by a gate oxide. Bitline 24 is coupled to drain region 16.

[0010] Memory cell 110 is erased (where electrons are removed from the floating gate) by placing a high positive voltage (with respect to substrate 12) on word line terminal 22, which causes electrons on floating gate 20 to tunnel through the intermediate insulation from floating gate 20 to word line terminal 22 via Fowler-Nordheim (FN) tunneling.

[0011] Memory cell 110 is programmed by source side injection (SSI) with hot electrons (where electrons are placed on the floating gate) by placing a positive voltage (with respect to substrate 12) on word line terminal 22, and a positive voltage on source region 14. Electron current will flow from drain region 16 towards source region 14. The electrons will accelerate and become heated when they reach the gap between word line terminal 22 and floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from floating gate 20.

[0012] Memory cell 110 is read by placing positive read voltages (with respect to substrate 12) on drain region 16 and word line terminal 22 (which turns on the portion of the channel region 18 under the word line terminal). If floating gate 20 is positively charged (i.e. erased of electrons), then the portion of channel region 18 under floating gate 20 is turned on as well, and current will flow across channel region 18, which is sensed as the erased or "1" state. If floating gate 20 is negatively charged (i.e., programmed with electrons), then the portion of the channel region 18 under floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across channel region 18, which is sensed as the programmed or "0" state.

[0013] Table No. 1 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 110 for performing read, erase, and program operations: Table No. 1: Operation of Flash Memory Cell 110 of Figure 1 WLBLSLRead2-3V0.6-2V0VErase~11-13V0V0VProgram1-2V10.5-3µA9-10V

[0014] The voltages of Table No. 1 are with reference to substrate 12, to which 0V is applied during a read, erase, or program operation.

[0015] Other split gate memory cell configurations, which are other types of flash memory cells, are known.

[0016] For example, Figure 2 depicts a four-gate memory cell 210 comprising source region 14, drain region 16, floating gate 20 over a first portion of channel region 18, select gate 22 (typically coupled to a word line, WL) over a second portion of the channel region 18, control gate 28 over the floating gate 20, and erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310. Here, all gates are non-floating gates except floating gate 20, meaning that they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injected through the gate oxide onto floating gate 20 due to the attractive electrostatic force from the floating gate 20. Erasing is performed by electrons tunneling from floating gate 20 to erase gate 30.

[0017] Table No. 2 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 210 for performing read, erase, and program operations: Table No. 2: Operation of Flash Memory Cell 210 of Figure 2 WL / SGBLCGEGSLRead1.0-2V0.6-2V0-2.6V0-2.6V0VErase-0.5V / 0V0V0V / -8V8-12V0VProgram1V0.1-1µA8-11V4.5-9V4.5-5V

[0018] A voltage of 0V is be applied to substrate 12 during a read, erase, or program operation.

[0019] Figure 3 depicts a three-gate memory cell 310, which is another type of flash memory cell. Memory cell 310 is identical to memory cell 210 of Figure 2 except that memory cell 310 does not have a separate control gate. The erase operation (whereby erasing occurs through use of the erase gate) and read operation are similar to that of memory cell 210 of Figure 2 except that no control gate bias applied. The programming operation also is done without the control gate bias, and as a result, a higher voltage must be applied on the source line during a program operation to compensate for a lack of control gate bias.

[0020] Table No. 3 depicts typical voltage and current ranges that can be applied to the terminals of memory cell 310 for performing read, erase, and program operations: Table No. 3: Operation of Flash Memory Cell 310 of Figure 3 WL / SGBLEGSLRead0.7-2.2V0.6-2V0-2.6V0VErase-0.5V / 0V0V11.5V0VProgram1V0.2-3µA4.5V7-9V

[0021] A voltage of 0V is applied to substrate 12 during a read, erase, or program operation.

[0022] Space within a semiconductor die is precious. In the prior art systems described above, substantial space is required for circuits external to the array that are necessary for read, program, and / or erase operations. For example, the high voltages required for erase operations require special high voltage generation and regulation circuitry, which in turns requires high voltage transistors that require large areas on the semiconductor die due to thicker gate oxide, longer channel length, and wider physical spacing.

[0023] What is needed is a new architecture for an array of non-volatile memory cells that reduces the voltage required for erase operations, which would then reduce the space required for high voltage generation and regulation circuitry.SUMMARY OF THE INVENTION

[0024] The invention relates to a non-volatile memory system according to independent claim 1. Further preferred embodiments are defined in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 depicts a prior art split gate flash memory cell. Figure 2 depicts another prior art split gate flash memory cell. Figure 3 depicts another prior art split gate flash memory cell. Figure 4 depicts a non-volatile memory system. Figure 5 depicts a non-volatile memory system comprising a p-well surrounding the array. Figure 6 depicts a non-volatile memory system comprising p-wells surrounding an array, low voltage decoder circuitry, and high voltage decoder circuitry. Figure 7 depicts a non-volatile memory system comprising p-wells surrounding a first array, a second array, low voltage decoder circuitry, and high voltage decoder circuitry in accordance with the invention. Figure 8 depicts a non-volatile memory system comprising p-wells surrounding a first array, a second array, first low voltage decoder circuitry, second low voltage decoder circuitry, first high voltage decoder circuitry, and second high voltage decoder circuitry in accordance with the invention. Figure 9 depicts a cross-section of a non-volatile memory system comprising a p-well surrounding an array. DETAILED DESCRIPTION OF THE INVENTION

[0026] The embodiments described herein enable a negative-voltage to be applied to a p-well surrounding certain components to enable a lower voltage to be used during erase operations of non-volatile memory cells.

[0027] Figure 4 depicts a block diagram of non-volatile memory system 400. Non-volatile memory system 400 comprises array 401, row decoder 402, high voltage decoder 403, column decoders 404, bit line drivers (also known as column drivers) 405 (for controlling program (current) on bitline terminals), output circuit 407, control logic 408, and bias generator 409. Non-volatile memory system 400 further comprises high voltage generation block 410, which comprises charge pump 411, charge pump regulator 412, and high voltage level generator 413. Non-volatile memory system 400 further comprises (program / erase, or weight tuning) algorithm controller 414, analog circuitry 415, control engine 416 (that may include special functions such as arithmetic functions, activation functions, or embedded microcontroller logic, without limitation), and test control logic 417.

[0028] Output circuit 407 may include circuits such as digital sensing circuitry to convert cell current into a logic '1' or '0', or analog sensing circuitry such as a ADC (analog to digital converter) to convert neuron analog output to digital bits), AAC (analog to analog converter) such as a current to voltage converter, logarithmic converter, APC (analog to pulse(s) converter), analog to time modulated pulse converter, or any other type of converters. The output circuit 407 may implement an activation function such as a rectified linear activation function (ReLU) or sigmoids. Output circuit 407 may implement statistic normalization, regularization, up / down scaling / gain functions, statistical rounding, or arithmetic functions (e.g., add, subtract, divide, multiply, shift, log) for neuron outputs. Output circuit 407 may implement a temperature compensation function for bitline outputs.

[0029] In the embodiments described below with reference to Figures 5-9, the array, and optionally other components, are placed within a p-well surrounded by, and on top of, a deep n-well. A negative voltage, in relation to p-substrate, is then be applied to the p-well, by bias generator 409 or another voltage source, during certain operations such as erase operations of non-volatile memory cells. This reduces the maximum voltage required for the erase operation, thereby reducing the overall size and power of the high voltage generation block 410

[0030] Figure 5 depicts a top view of non-volatile memory system 500. Non-volatile memory system 500 comprises array 501, row decoder 502 (an example of row decoder 402 in Figure 4), and high voltage decoder 503 (an example of high voltage decoder 403 in Figure 4). Array 501 is formed within p-well 504, which is formed within deep n-well 505, and deep n-well 505 is formed within p-substrate 580. P-well 504 hence can receive a different voltage (including but not limited to a negative voltage) due to its isolation from p-substrate 580 by deep n-well 505. For example, p-substrate 580 can be biased at 0V, deep n-well 505 can be biased at 0-2V, and p-well 504 can be biased at -0.1V to - 10V. These bias voltages can be generated by bias generator 409 or another voltage source.

[0031] Figure 6 depicts non-volatile memory system 600. Non-volatile memory system 600 comprises array 601, row decoder 602 (an example of row decoder 402 in Figure 4), and high voltage decoder 603 (an example of high voltage decoder 403 in Figure 4).

[0032] Array 601 is formed within p-well 604, and p-well 604 is formed within deep n-well 605.

[0033] Row decoder 602 is formed within p-well 608, which p-well 608 is formed within deep n-well 609.

[0034] High voltage decoder 603 is formed within p-well 606, and p-well 606 is formed within deep n-well 607.

[0035] Deep n-wells 605, 607, and 609 are respectively formed within (and on top of) p-substrate 680. Optionally, deep n-wells 605, 607, and 609 can be separate deep n-wells or part of a common deep n-well.

[0036] P-well 604 containing array 601 hence can be driven with a negative voltage, in relation to p-substrate 680, by bias generator 409 or another voltage source due to its isolation from p-substrate 680 by deep n-well 605.

[0037] P-well 606 containing high voltage decoder 603 hence can be driven with a negative voltage, in relation to p-substrate 680, by bias generator 409 or another voltage source due to its isolation from p-substrate 680 by deep n-well 607.

[0038] For example, p-substrate 680 can be biased at 0V, deep n-wells 605, 707, and 609 can be biased at 0-3V, and p-wells 604, 606, and 608 can be biased at -0.1V to -10V. These bias voltages can be generated by bias generator 409 or another voltage source.

[0039] Figure 7 depicts non-volatile memory system 700 according to the invention. Non-volatile memory system 700 comprises array 701, array 702, low voltage decoder 703, and high voltage decoder 704. Array 701 is formed within p-well 705, and p-well 705 is formed within deep n-well 706. Array 702 is formed within p-well 707, and p-well 707 is formed within deep n-well 708. Low voltage decoder 703 is formed within p-well 709, and p-well 709 is formed within deep n-well 710. High voltage decoder 704 is formed within p-well 711, and p-well 711 is formed within deep n-well 712. Optionally, deep n-wells 706, 708, 710, and 712 can be separate deep n-wells or part of a common deep n-well. The p substrate PSUB 780 is the substrate that all circuits, i.e., array 701, array 702, low voltage decoder 703, and high voltage decoder 704, are formed upon.

[0040] Figure 8 depicts non-volatile memory system 800 according to the invention. Non-volatile memory system 800 comprises array 801, array 802, low voltage decoder 803, low voltage decoder 804, high voltage decoder 805, and high voltage decoder 806. Array 801 is formed within p-well 807, and p-well 807is formed within deep n-well 808. Array 802 is formed within p-well 809, and p-well 809 is also formed within deep n-well 808. Low voltage decoder 803 is formed within p-well 810, and p-well 810 is formed within deep n-well 811. Low voltage decoder 804 is formed within p-well 812, and p-well 812is formed within deep n-well 813. High voltage decoder 805 is formed within p-well 814, and p-well 814is formed within deep n-well 815. High voltage decoder 806 is formed within p-well 816, and p-well 816 is formed within deep n-well 817. Optionally, deep n-wells 808, 811, 815, 813, and 817 can be separate deep n-wells or part of a common deep n-well. P-substrate 880 is the substrate that all circuits, i.e., array 801, array 802, low voltage decoder 803, low voltage decoder 804, high voltage decoder 805, and high voltage decoder 806, are formed upon.

[0041] P-well 807 or 809 hence can go be driven to a negative voltage, in respect to p-substrate 880, independently, by bias generator 409 or another voltage source, due to its isolation from p-substrate 880 by deep n-well 808. Similarly, p-wells 810, 812, 814, 816 hence can be driven to a negative voltage independently, in respect to p-substrate 880, by bias generator 409 or another voltage source, due to their isolation from p-substrate 880 by respective deep n-wells 811, 813, 815, and 817.

[0042] Figure 9 depicts cross-section 900. Array 901 or low voltage decoder, row decoder 902, or high voltage decoder 903 (which are representative of the arrays, row decoders, and high voltage decoders, respectively, depicted in Figures 5-8) is formed within p-well 904, p-well 904 is formed within deep n-well 905, and deep n-well 905 is formed within p-substrate 980. P-well terminal 906 provides access to p-well 904 and can be used, for example, to apply a negative voltage (in relation to p-substrate 980) to p-well 904 by bias generator 409 or another voltage source during an erase operation. N-well terminal 907 is used to apply a bias voltage to deep n-well 905, and p-substrate terminal 908 is used to apply a bias voltage (which can include 0V) to p-substrate 980. P- substrate 980 is the substrate that all circuits, i.e., array 901 or low voltage decoder, row decoder 902, or high voltage decoder 903, are formed upon.

[0043] Optionally, p-substrate 980 in Figures 5-9 can be biased by bias generator 409 or another voltage source at a negative voltage such as - 0.1V to -3V instead of 0V.

[0044] Using the architectures of Figures 5-9, the following operating voltages can be used to perform read, program, and erase operations on non-volatile memory cells 110, 210, and 310 of Figures 1-3, with the understanding that substrate 12 (which is a p-substrate) in Figures 1-3 is modified to include a p-well within a deep n-well, such as shown in cross-section 900 of Figure 9, where substrate 12 then becomes p-substrate 980, deep n-well 905 is formed within substrate 12, and p-well 904 is formed within deep n-well 905, where arrays of memory cells 110, 210, and 310 are formed within p-well 904. In addition, p-well 904 is accessed using p-well-terminal 906, deep n-well 905 is accessed using n-well terminal 907, and p-substrate 980 is accessed using p-substrate 980 as in Figure 9. In this configuration, p-well 904 acts as a (virtual) p-substrate for the memory cells of the array and for the other components.

[0045] Table Nos. 4-10 that follow contain exemplary operating voltages to be applied to memory cells 110, 210, and 310 when configured as in Figure 9. In these examples, a voltage of 0V is applied to p-substrate 980 (substrate 12) through p-substrate terminal 908, a voltage of 0-2V is applied to deep n-well 905 through n-well terminal 907, and a voltage of -0.1V to -12V is applied to p-well 904 through p-well terminal 906 by bias generator 409 or another voltage source.

[0046] Table No. 4 depicts a first set of operating voltages (defined with respect to substrate 12) for memory cell 110 of Figure 1 when the substrate 12 is modified to include p-well 904 within deep n-well 905 within substrate 12: Table No. 4: Operation of Memory Cell 110 of Figure 1 WL BL SL P-Well 904 Selected Cell: Program1.5 V1-3 µA8-9 V0 VRead2.5 V0.6-1.0 V0 V0 VErase (Using Positive Voltages)12.5 VFLTFLT0 VErase (Using a combination of Positive and Negative Voltages)10.5 VFLT / -2.5 VFLT / -2.5 V-2.5 VUn-Selected Cell: Program0 VVdp / VINH8-9 V / 0.5 V0 VRead0 V0.6-1.0 V0 V0 VErase (Using Positive Voltages)0 VFLT0 V0 VErase (Using a Combination of Positive and Negative Voltages)0 VFLTY / -2.5 VFLT / -2.5 V-2.5 V

[0047] Table No. 5 depicts a second set of operating voltages for memory cell 110 of Figure 1 when the substrate includes a p-well within a deep n-well: Table No. 5: Operation of Memory Cell 110 of Figure 1 WL BL SL P-Well 904 Selected Cell: Program1.5 V1-3 µA8-9 V0 VRead2.5 V0.6-1.0 V0 V0 VErase (Using Positive Voltages)12.5 VFLTFLT0 VErase (Using a Combination of Positive and Negative Voltages)8 VFLT / -4.5 VFLT / -4.5 V-4.5 VUn-Selected Cell: Program0 VVdp / VINH8-9 V / 0.5 V0 VRead0 V0.6-1.0 V0 V0 VErase (Using Positive Voltages)0 VFLT0 V0 VErase (Using a Combination of Positive and Negative Voltages)-2.5 VFLTY / -4.5 VFLT / -4.5 V-4.5 V

[0048] P-well 904 is particularly advantageous in a situation where a negative voltage is applied to one or more terminals of the cell during an erase operation, because in that situation, applying a negative voltage to p-well 904 using bias generator 409 or another voltage source will reduce stress on the gate oxide regions when the negative voltage is applied to the terminal, as p-well 904 will serve as a virtual substrate for the cell that is biased to a negative voltage.

[0049] Table No. 4 is appropriate if stress on gate oxide regions is not a concern, while Table No. 5 is appropriate if stress on gate oxide regions is a concern. In Table No. 4, a word line voltage of 0V is applied to un-selected cells during an erase operation, while in Table No. 5, a word line voltage of -2.5V is applied to unselected cells during an erase operation, due to the fact that it is desired to reduce stress on the gate oxide regions of memory cell 110 as well as the peripheral (decoding) transistor for the 2.5V gate oxide. In the operation of Table No. 4, stress on the gate oxide regions of the decoding circuits is not a concern because the absolute voltage required will not cause the voltage across a gate oxide region to exceed the gate oxide break down voltage for both the decoding circuitry and the cells, and as a result, an isolated p-sub well 04 is not needed for the decoding circuitry. By contrast, in the implementation of Table 5, bias generator 409 or another voltage source applies negative voltages to certain terminals to reduce stress on the gate oxide regions, and as a result, an isolated p-sub well 904 is advantageous for the decoding circuitry.

[0050] Table No. 6 depicts a first set of operating voltages for memory cell 210 of Figure 2 when the substrate includes a p-well within a deep n-well: Table No. 6: Operation of Memory Cell 210 of Figure 2 WL BL SL CG EG P-Well 904 Selected Cell: Program0.7 V1 µA4.5 V10 V4.5 V0 VRead1.8 V0.6-1.0 V0 V1.8 V0-1.8 V0 VErase0 VFLT / -2 VFLT / -2 V0 V10.5 V-2 VUn-Selected Cell: Program0 VVdp / VINH4.5 / 0.5 V0 / 2.5 V4.5 / 0 V0 VRead0 V0.6-1.0 V0 V1.8 V0-2.5 V0 VErase0 VFLT / -2 VFLT / -2 V0 V0 V-2 V

[0051] Table No. 7 depicts a second set of operating voltages for memory cell 210 of Figure 2 when the substrate includes a p-well within a deep n-well: Table No. 7: Operation of Memory Cell 210 of Figure 2 WL BL SL CG EG P-Well 904 Selected Cell: Program0.7 V1 µA4.5 V8-10 V4.5-8 V0 VRead1.8 V0.6-1.0 V0 V1.8 V0-1.8 V0 VErase0 VFLT / -4 VFLT / -4 V-6 V6 V-4 VUn-Selected Cell :Program0 VVdp / VINH4.5 / 0.5 V0 / 2.5 V4.5-8 / 0 V0 VRead0 V0.6-1.0 V0 V2.5 V0-2.5 V0 VErase-2 VFLT / -4 VFLT / -4 V0 V0 V-4 V

[0052] Table No. 8 depicts a first set of operating voltages for memory cell 310 of Figure 3 when the substrate includes a p-well within a deep n-well: Table No. 8: Operation of Memory Cell 310 of Figure 3 WL BL SL EG P-Well 904 Selected Cell: Program1.5 V1-3 µA8-9 V4-9 V0 VRead2.5 V0.6-1.0 V0 V0-2.5 V0 VErase-2.5 VFLT / -4.5 VFLT / -4.5V8.5 V-4.5 VUn-Selected Cell: Program0 VVdp / VINH8-9 V / 0.5 V4-9 V / 0 V0 VRead0 V0.6-1.0 V0 V0-2.5 V0 VErase-2.5 VFLT / -4.5 VFLT / -4.5 V-2.5V-4.5 V

[0053] For the same reasons discussed above with respect to Table Nos. 5 and 6, the use of p-well 904 would be particularly advantageous for Table No. 8 and to a greater extent than for Table No. 7.

[0054] Table No. 9 depicts a second set of operating voltages for memory cell 310 of Figure 3 when the substrate includes a p-well within a deep n-well: Table No. 9: Operation of Memory Cell 310 of Figure 3 WL BL SL EG P-Well 904 Selected Cell: Program1.5 V1-3 µA8-9 V4-9 V0 VRead2.5 V0.6-1.0 V0 V0-2.5 V0 VErase0 VFLT / -2.5 VFLT / -2.5V10.5 V-2.5 VUn-Selected Cell: Program0 VVdp / VINH8-9 V / 0.5 V4-9 V / 0 V0 VRead0 V0.6-1.0 V0 V0-2.5 V0 VErase0 VFLT / -2.5 VFLT / -2.5 V0V-2.5 V Table No. 10: Operation of Memory Cell 310 of Figure 3 WL BL SL EG P-Well 904 Selected Cell: Program1.5 V1-3 µA8-9 V4-9 V0 VRead2.5 V0.6-1.0 V0 V0-2.5 V0 VErase-2.5 VFLT / -2.5 VFLT / -2.5V8.5 V-4.5 V Un-Selected Cell: Program0 VVdp / VINH8-9 V / 0.5 V4-9 V / 0 V0 VRead0 V0.6-1.0 V0 V0-2.5 V0 VErase-2.5 VFLT / -2.5 VFLT / -2.5 V-2.5V-4.5 V

[0055] For the same reasons discussed above with respect to Table Nos. 5 and 6, the use of p-well 904 would be particularly advantageous for Table No. 10 and to a greater extent than for Table No. 9.

[0056] It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween). Likewise, the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed there between), "mounted to" includes "directly mounted to" (no intermediate materials, elements or space disposed there between) and "indirectly mounted to" (intermediate materials, elements or spaced disposed there between), and "electrically coupled" includes "directly electrically coupled to" (no intermediate materials or elements there between that electrically connect the elements together) and "indirectly electrically coupled to" (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials / elements there between.

Claims

1. A non-volatile memory system (800), comprising: a deep n-well (808) formed in a p-substrate (880) in a semiconductor die; a first p-well (807) formed within the deep n-well; a second p-well (809) formed within the deep n-well; a first array (801) of non-volatile split-gate flash memory cells formed within the first p-well, each non-volatile split-gate flash memory cell in the first array comprising a floating gate and a plurality of terminals; a second array (802) of non-volatile split gate flash memory cells formed within the second p-well, each non-volatile split-gate flash memory cell in the second array comprising a floating gate and a plurality of terminals; a bias generator (409) to apply a negative voltage to the first p-well during an erase operation of one or more of the non-volatile split-gate flash memory cells in the first array and to apply independently a negative voltage to the second p-well during an erase operation of one or more of the non-volatile split-gate flash memory cells in the second array; a low voltage decoder (803, 804) formed within a third p-well (810, 812) formed within a second deep n-well (811, 813); and a high voltage decoder circuit (805, 806) formed within a fourth p-well (814, 816) formed within a third deep n-well (815, 817).

2. The non-volatile memory system of claim 1, wherein the plurality of terminals for each non-volatile split-gate flash memory cell in the first array and the second array comprises a bit line terminal, a source line terminal, and a word line terminal.

3. The non-volatile memory system of claim 2, wherein the plurality of terminals for each non-volatile split-gate flash memory cell in the first array and the second array further comprises an erase gate terminal.

4. The non-volatile memory system of claim 3, wherein the plurality of terminals for each non-volatile split-gate flash memory cell in the first array and the second array further comprises a control gate terminal.

5. The non-volatile memory system of claim 1, wherein the bias generator is to apply a voltage of 0 V to word lines of un-selected non-volatile split-gate flash memory cells (210, 310) during read, erase, and programming operations.

6. The non-volatile memory system of claim 1, wherein the bias generator is to apply a negative voltage to a control gate terminal of a selected split-gate flash memory cell during an erase operation.