EFFICIENT ARCHITECTURE FOR HIGH-PERFORMANCE SERDES BASED ON DSP
Patent Information
- Application Number
- DE602022025548
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-10-12
- Filing Date
- 2022-10-11
- Publication Date
- 2025-11-26
- Estimated Expiration
- 2042-10-11
AI Technical Summary
Conventional DSP-based serializer deserializers face challenges in maintaining high efficiency and reducing power and chip area while handling densely-populated channels with reflections, leading to increased latency and complexity, which affects jitter tolerance and bit-error-rate performance.
Implementing a low-power, low-area architecture with a cascaded combination of three filters and an optional interpolator, including a short RX-FFE, reflection canceller FIR filter, and noise-shaping PR FIR filter, to achieve fast-timing recovery and reflection-cancellation.
The proposed architecture reduces power consumption and chip area while maintaining low bit-error-rates by using a cascaded filter structure that enables efficient noise shaping and reflection cancellation, resulting in faster timing recovery and reduced latency.