METHOD FOR FABRICING A SEMI-CONDUCTOR ARRANGEMENT WITH STORAGE CELLS, HIGH-VOLTAGE ARRANGEMENTS AND LOGICAL ARRANGEMENTS ON A SUBSTRATE USING A DUMMY AREA
DE602022027433T2Active Publication Date: 2025-12-24SILICON STORAGE TECHNOLOGY INC
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Patent Information
- Application Number
- DE602022027433
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2022-05-16
- Filing Date
- 2022-05-18
- Publication Date
- 2025-12-24
- Estimated Expiration
- 2042-05-18
AI Technical Summary
Technical Problem
Existing methods for forming non-volatile memory cells and logic devices on a semiconductor substrate often adversely affect each other during processing, leading to performance issues.
Method used
A method involving substrate recessing, insulation layer formation, and selective etching to create separate trenches and conductive layers for memory cells, high voltage devices, and low voltage logic devices, with a dummy area to isolate and protect the logic devices from processing impacts.
Benefits of technology
This method allows for simultaneous formation of memory cells, high voltage devices, and low voltage logic devices on a substrate without adverse effects, ensuring precise control over layer thickness and structure, enhancing device performance and reducing complexity.
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