DIGITAL TIME CONVERTER AND PHASE LOOP

Description

Domaine technique

[0001] This description relates generally to electronic circuits, and more particularly to converters of a duration into a digital signal representative of said duration, or time-digital converters, and to phase-locked loops comprising such time-digital converters. Technique antérieure

[0002] Digital-to-time converters are known. These converters are configured to convert a duration into a digital signal representing the value of that duration.

[0003] For example, a known time-digital converter comprises a series of stages forming a delay line. The state of each stage of the delay line is sampled at each active edge of a clock signal from the converter. Furthermore, the delay line receives as input an edge of a first signal, which propagates along the delay line. At the next active edge of the clock signal, the sampled state of the delay line then represents the time interval between the input of the first signal's edge to the delay line and the next active edge of the clock signal. A drawback of such a time-digital converter, called a flash time-digital converter, is that the accuracy of measuring the time interval between the first signal's edge and the next active edge of the clock signal is limited by the propagation time of a stage of the converter.Such a converter also requires propagation delay calibration at each stage so that each stage introduces the same delay. Furthermore, when such a converter is implemented in an all-digital phase-locked loop (ADPLL), normalization of the converter output is generally necessary, which involves undesirable additional processing.

[0004] US 2017 / 194972 A1 discloses a digital time converter based on a Wilkinson-type converter.

[0005] DAYANIK MEHMET BATUHAN ET AL: "A 28.5-33.5GHz fractional-N PLL using a 3rd order noise shaping time-to-digital converter with 176fs resolution", 2013 PROCEEDINGS OF THE ESSCIRC (ESSCIRC), IEEE, September 14, 2015 (2015-09-14), pages 376-379, concerns a fractional-N digital phase-locked loop, based on a continuous-time delta-sigma type time-to-digital converter. Summary of the invention

[0006] There is a need to overcome all or part of the drawbacks of known digital time converters.

[0007] For example, there is a need to overcome all or part of the disadvantages of known digital-time converters intended for implementation in a phase-locked loop in all-digital operation.

[0008] For example, there is a need for a digital-time converter which, when implemented in an all-digital phase loop, provides an output in the form of a normalized phase gap.

[0009] For example, there is a need for a digital time converter which, when implemented in an all-digital phase-locked loop, does not require any clock signal other than the clock signals respectively received and supplied by the phase-locked loop.

[0010] For example, there is a need for a digital time converter that is simple and compact to implement.

[0011] For example, there is a need for a digital-time converter which, when implemented in an all-digital phase-locked loop, takes advantage of the low-pass filtering implemented in the loop.

[0012] For example, there is a need for a time-to-digital converter that is particularly suited for implementation in an all-digital phase-locked loop, and is also usable in any other electronic application or system where time-to-digital conversion is required.

[0013] One embodiment overcomes all or part of the disadvantages of known time-to-digital converters, for example when implemented in a phase-locked loop in all-digital operation.

[0014] One embodiment provides a digital-to-time converter comprising: a first circuit configured to provide, at each active edge of a first signal, a first pulse of duration determined by a difference between said active edge of the first signal and an immediately successive active edge of a second signal; an integrator circuit configured, at each first pulse, to integrate: the first pulse, a second pulse starting after the first pulse and in synchronism with a clock signal, and a third pulse starting after the second pulse and in synchronism with the clock signal, a second circuit configured to generate, for each first pulse, the corresponding second pulse; a third circuit configured to quantize on one bit an output signal of the integrator circuit and, at the beginning of each third pulse, to store on a first bit said binary quantization;and a fourth circuit configured to generate, for each first pulse, the corresponding third pulse from the first bit.

[0015] According to one embodiment, the second circuit is configured to receive the clock signal, and to generate, at least in part from the clock signal, at least a third signal configured to control the memorizations by the third circuit and the generation of the third pulses by the fourth circuit.

[0016] According to one embodiment, the first circuit is configured to provide a fourth signal indicating a start and end of each first pulse, the second circuit being configured to receive the fourth signal and to generate the third signal from the clock signal and the fourth signal.

[0017] According to one embodiment, the first and second circuits are configured so that the second pulses place a converter conversion zero in the middle of the converter dynamics.

[0018] According to one embodiment, the fourth circuit is configured so that the integration of each third pulse implements a subtraction of the binary quantization stored at the beginning of said third pulse.

[0019] According to one embodiment, the first and second circuits are configured so that each second pulse causes, on the output signal of the integrator circuit, a variation of amplitude identical and of opposite sign to a variation of amplitude that would be caused by a first pulse of duration determined by half of the dynamics of the converter.

[0020] The converter is of the sigma-delta type and the fourth circuit is configured so that every third pulse implements a negative sigma-delta feedback.

[0021] According to one embodiment: the first, second and third pulses are signed; the first and second circuits are configured so that a sign of the second pulses is opposite to a sign of the first pulses and that a maximum duration of the first pulses that the converter can convert multiplied by an amplitude of the first pulses is equal to twice a duration of the second pulses multiplied by an amplitude of the second pulses; and the fourth circuit is configured so that a sign of each third pulse is determined by a state of the first bit and that an amplitude of the third pulses multiplied by a duration of the third pulses is equal to the duration of the second pulses multiplied by the amplitude of the second pulses.

[0022] According to one embodiment, the second and third pulses each have a duration that is a multiple of one period of the clock signal, preferably equal to one period of the clock signal.

[0023] According to one embodiment, an output of said converter is at least partly determined by the first bit.

[0024] According to one embodiment, the converter is of the multi-stage noise-shaping sigma-delta type, the converter comprising a first stage including the integrator circuit and the first, second, third and fourth circuits, and a second stage configured to receive an output signal from the integrator circuit of the first stage and to provide a digital output signal from the second stage from the output signal of the integrator circuit of the first stage, an output of said converter being determined at least in part by the first bit and the digital output signal of the second stage.

[0025] According to one embodiment, the second floor is configured to: generate, after every third pulse, a fourth pulse starting in synchronism with the clock signal; integrate, during each fourth pulse, a sum of the output signal of the integrator circuit of the first stage and a feedback signal, quantize on one bit a result of said integration and store on a second bit said binary quantization at the end of the fourth pulse; generate, during each third pulse, a fifth pulse from the second bit, and the feedback signal by integrating said fifth pulse; and store the second bit on a third bit at each active edge of the first signal, the digital output signal of the second stage being generated from the second and third bits or corresponding to the second and third bits.

[0026] According to one embodiment, the second floor comprises: a fifth circuit configured to generate, after every third pulse, a fourth pulse starting in synchronism with the clock signal; an integrator circuit configured to integrate, during each fourth pulse, a sum of the output signal of the integrator circuit of the first stage and a feedback signal; a sixth circuit configured to quantize on one bit an output of the integrator circuit of the second stage and to store said binary quantization on a second bit, at the end of each fourth pulse; a seventh circuit configured, at each third pulse, to provide said feedback signal by integrating, during said third pulse, a fifth pulse determined from the second bit;and a circuit configured to store the second bit on a third bit at each active edge of the first signal, the digital output signal of the second stage being generated from the second and third bits or corresponding to the second and third bits.

[0027] According to one embodiment, the converter includes a first input configured to receive the first signal and a second input configured to receive the clock signal, and: the second signal and the clock signal are either confused, or the converter includes a frequency divider circuit, preferably by two, configured to receive the clock signal and to provide the second signal.

[0028] Another embodiment provides an all-digital phase-locked loop configured to receive a signal at a first frequency and to provide a signal at a second frequency equal to N / D times the first frequency, with N and D being two positive values, the phase-locked loop comprising a converter as described above, the first input of the converter being configured to receive the signal at the first frequency and the second input of the converter being configured to receive the signal at the second frequency.

[0029] According to one embodiment, the phase-locked loop comprises a circuit configured to provide a first digital signal incremented by the value N at the first frequency; a circuit configured to provide a second digital signal incremented by the value D at the second frequency and a third digital signal corresponding to a memorization of the second digital signal clocked at the first frequency; a digital filter configured to receive a subtraction of an output of the converter and of the third digital signal from the first digital signal and to control an oscillator configured to provide the signal at the second frequency, in which the second signal from the converter is coincident with the signal at the second frequency.

[0030] According to one embodiment, the phase-locked loop comprises: either a circuit configured to provide a first digital signal incremented by the value N at the first frequency, and a circuit configured to provide a second digital signal incremented by the value D / 2 at the second frequency, with D even, or a circuit configured to provide a first digital signal incremented by the value 2N at the first frequency and a circuit configured to provide a second digital signal incremented by the value D at the second frequency; a circuit configured to provide a third digital signal corresponding to a memorization of the second digital signal clocked by the second signal of the converter;a digital filter configured to receive a subtraction of a converter output and the third digital signal from the first digital signal and to control an oscillator configured to provide the signal at the second frequency, the second signal from the converter being obtained by dividing the frequency of the signal at the second frequency by two. Brève description des dessins

[0031] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the attached figures, among which: there figure 1 represents, in a very schematic way and in the form of functional blocks, one implementation of a digital-to-time converter; the figure 2 represents, schematically, details of an example embodiment of the digital-to-time converter of the figure 1 ; there figure 3 illustrates, through timing diagrams, the operation of the converter of the figure 2 ; there figure 4 represents, schematically and in block form, a fully digital implementation of a phase-locked loop; figure 5 represents, schematically, details of an example embodiment of the digital-to-time converter of the figure 1 , in a case where the converter is implemented in a phase-locked loop of the type of that of the figure 4 ; there figure 6 illustrates, through timing diagrams, the operation of the converter of the figure 5 ; there figure 7 represents, schematically, details of another example of an embodiment of the digital-to-time converter of the figure 1 , in a case where the converter is implemented in a phase-locked loop of the type of that of the figure 4 ; there figure 8 illustrates, through timing diagrams, the operation of the converter of the figure 7 ; there figure 9 illustrates a variant implementation of the converter of the figure 1 ; there figure 10 illustrates an example of the implementation of part of the converter from the previous figures; the figure 11 illustrates an example of the implementation of another part of the converter from the previous figures; the figure 12 illustrates an example of the implementation of yet another part of the converter from the previous figures; the figure 13 illustrates an example of the implementation of yet another part of the converter from the previous figures; and the figure 14 illustrates a detailed embodiment of the variant embodiment of the figure 9 . Description des modes de réalisation

[0032] The same elements have been designated by the same reference numerals in the different figures. In particular, structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0033] For the sake of clarity, only the steps and elements useful for understanding the implementation methods described have been represented and are detailed.

[0034] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0035] In the description that follows, when referring to absolute positional qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative positional qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientational qualifiers, such as the terms "horizontal", "vertical", etc., unless otherwise specified, it refers to the orientation of the figures.

[0036] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0037] In this application, unless otherwise specified, a "pulse" is defined as, for example, a square wave variation in the level of a signal relative to an initial or resting state, also called the zero level, of the signal. Unless otherwise specified, the "amplitude of a pulse" is defined as, for example, the absolute value of the signal level during the pulse relative to its zero level, i.e., the absolute value of the pulse level, it being understood that a pulse may have a negative or positive level relative to the zero level of the signal. A pulse with a negative level will be called a "negative pulse" and a pulse with a positive level will be called a "positive pulse". For example, a negative pulse of amplitude A corresponds to a pulse with a level equal to -A and a positive pulse of amplitude A corresponds to a pulse with a level equal to +A.

[0038] Unless otherwise specified, the "dynamics" of a time-to-digital converter is, for example, the difference between the largest and smallest values ​​that the converter can measure.

[0039] A sigma-delta type digital time converter is proposed here to measure the duration between each active edge of a first signal and an active edge of a second signal following the active edge of the first signal.

[0040] According to one embodiment, at each active edge of the first signal, the converter is configured to successively integrate, with an integrator circuit, a first pulse representing the time to be measured, a second pulse configured to center an output dynamic of the integrator circuit, and a third pulse configured to implement the negative feedback of the sigma-delta loop, the converter being further configured to quantize and store on one bit an output of the integrator circuit, for example, at the beginning of each third pulse.

[0041] In other words, each second pulse is configured to cause a change in the integrator's output signal of the same amplitude and opposite sign to a change in the integrator's output signal caused by a first pulse with a measurement duration equal to half the converter's dynamic range. Put another way, the second pulses are configured to place the converter's conversion zero point at the midpoint of the converter's dynamic range.

[0042] For example, the converter is configured so that the sign of the first pulses is opposite to that of the second pulses and so that a maximum duration of the first pulses that the converter can convert multiplied by an amplitude of the first pulses is equal to twice a duration of the second pulses multiplied by an amplitude of the second pulses.

[0043] In other words, each third pulse is configured, for example, to subtract from the input of the integrator circuit the stored result of the quantization of the output of the integrator circuit performed at the beginning of the third pulse, so that after the integration of the third pulse, the output of the integrator circuit includes only the residual quantization error.

[0044] For example, the converter is configured so that the sign of each third pulse is determined by the state of the bit corresponding to the quantization memory of the integrator circuit's output, and so that an amplitude of the third pulses multiplied by a duration of the third pulses is equal to the amplitude of the second pulses multiplied by the duration of the second pulses.

[0045] Put another way, a sigma-delta type digital time converter is proposed here which operates, at each conversion cycle, according to at least three phases comprising successively a first phase during which the time to be converted is integrated, a second phase during which a conversion zero is centered in the middle of the converter dynamics, and a third phase during which the negative sigma-delta feedback is implemented.

[0046] There figure 1 represents, in a very schematic way and in the form of functional blocks, an embodiment of a sigma-delta type digital time converter 1.

[0047] Converter 1 includes a first circuit C1. Circuit C1 is configured to provide, at each active edge, for example, each rising edge, of a signal S1, a pulse P1. The duration of the pulse P1 is determined by the difference between the active edge of signal S1 and an immediately following active edge, for example, a rising edge, of a signal S2. In other words, circuit C1 is configured to provide, at each active edge of signal S1, a pulse P1 having a duration representative of the time separating that edge of signal S1 from the next active edge of signal S2. Each pulse P1 is, for example, a pulse starting at an active edge of signal S1 and ending at the immediately following active edge of signal S2.

[0048] In the following description, Dmax is defined as the maximum duration of the P1 pulses that the converter can convert. For example, a P1 pulse with a duration Dmax corresponds to a measurable duration equal to the maximum duration that the converter can measure, that is, the maximum difference between an active edge of signal S1 and a subsequent active edge of signal S2 that the converter can measure.

[0049] In the following description, we consider as an example that the pulses P1 all have a duration less than or equal to Dmax, or, in other words, that the durations to be measured with converter 1 are all included in the dynamics of the converter.

[0050] According to one embodiment, the converter 1 is configured to convert the time between each active edge of the signal S1 and an immediately successive active edge of the signal S2 into a digital output signal of the converter 1.

[0051] As an example, circuit C1 is configured to receive signals S1 and S2 and to provide pulses P1.

[0052] In one embodiment, at each active edge of signal S1, circuit C1 is configured to generate a signal or pulse CMD1. The duration of pulse CMD1 is determined by the time between the edge of signal S1 and the immediately following edge of signal S2. The duration of pulse CMD1 determines the duration of pulse P1, or, in other words, pulse P1 is determined from pulse CMD1. Put another way, each pulse CMD1 indicates the beginning and end of a corresponding pulse P1. Each pulse CMD1 is, for example, a pulse that begins at an active edge of signal S1 and ends at the immediately following active edge of signal S2. Each pulse P1 is, for example, a pulse that begins and ends simultaneously with a corresponding pulse CMD1.

[0053] As an example, circuit C1 includes a flip-flop, not shown in figure 1 receiving signals S1 and S2 on two of its inputs and providing CMD1 pulses. Preferably, the flip-flop is an RS flip-flop with an initialization input, i.e., the S input of the flip-flop, configured to receive signal S1, a reset input, i.e., the R input of the flip-flop, configured to receive signal S2, and an output, for example, the Q output of the flip-flop, configured to provide signal CMD1. Preferably, the S input, or R input, of the flip-flop is sensitive to the rising edges of signals S1 and S2, respectively. Of course, a person skilled in the art can replace this flip-flop with any other circuit capable of generating CMD1 pulses from signals S1 and S2. For example, a person skilled in the art can replace the RS flip-flop in circuit C1 with a D flip-flop, or with a circuit other than a flip-flop.

[0054] Converter 1 further includes an integrator circuit INT. The INT circuit is configured to integrate the pulses it receives and to provide an output signal RES1 corresponding to the result of this integration. More specifically, at each first pulse P1, the INT circuit is configured to integrate the pulse P1, then a pulse P2 corresponding to, or associated with, this pulse P1, and then a pulse P3 corresponding to, or associated with, this pulse P1.

[0055] For each pulse P1, the associated pulse P2 begins after pulse P1, in synchronism with a clock signal clk, and the associated pulse P3 begins after pulse P2, also in synchronism with the clk signal. For example, pulses P2 and P3 begin in synchronism with the rising edges of the clk signal. In another example, pulses P2 and P3 begin in synchronism with the falling edges of the clk signal. In one embodiment, pulses P2 and P3 each have durations that are multiples, preferably integers, of one period of the clk signal; for example, durations equal to one period of the clk signal.

[0056] In one embodiment, the frequency of the clk signal is sufficiently high so that the conversion by the converter, triggered by an active edge of the S1 signal, is completed before the start of the next conversion triggered by the following edge of the S1 signal. For example, a multiplicative factor between the frequency of the clk signal and that of the S1 signal is determined such that, following each active edge of the S1 signal, the converter 1 updates its output before a new active edge of the S1 signal occurs. Determining this multiplicative factor is within the scope of a person skilled in the art.

[0057] A circuit C2 of converter 1 is configured to generate, for each pulse P1, the corresponding pulse P2. For example, circuit C2 is configured to receive the signals clk and CMD1, and to provide the corresponding pulses P2. Alternatively, circuit C2 is configured to generate the pulses P2 from the signals clk and CMD1.

[0058] Circuit C2 is configured so that the P2 pulses center the output dynamics of the integrator INT. In other words, circuits C2 and C1 are configured so that each P2 pulse causes a change in the RES1 signal of the same amplitude and opposite sign to a change in the RES1 signal caused by a P1 pulse corresponding to a measurement duration equal to half the converter's dynamic range. Put another way, circuits C2 and C1 are configured so that the second pulses place the converter's conversion zero at the midpoint of the converter's dynamic range; that is, so that the second P2 pulses, when integrated by circuit INT, produce a shift or bias that places the conversion dynamic zero at the midpoint of the maximum duration that converter 1 can measure.

[0059] We call A1 the amplitude of the pulses P1, A2 the amplitude of the pulses P2 and K2*Tclk the duration of the pulses P2, with A1 and A2 strictly positive real values, K2 a positive and non-zero integer, and Tclk the duration of one period of the signal clk.

[0060] In one embodiment, the pulses P1 and P2 are signed. The circuits C1 and C2 are then configured so that the pulses P1 and P2 have opposite signs and the product of the maximum duration Dmax of the pulses P1 and the amplitude A1 of the pulses P1 is equal to twice the product of the duration K2*Tclk of the pulses P2 and the amplitude A2 of the pulses P2. In other words, the circuits C1 and C2 are configured so that the pulses P1 and P2 have opposite signs and Dmax*A1 = 2*K2*Tclk*A2. For example, the pulses P1 are positive and therefore each have a level equal to A1, and the pulses P2 are negative and therefore each have a level equal to -A2. For example, when A1 = 2*A2 and K2 = 1, then the duration Dmax of the pulses P1 is equal to Tclk.In such an example, if each pulse P1 starts at an active edge of signal S1 and ends at the next active edge of signal S2, then the maximum time that the converter can measure between each active edge of signal S1 and the next active edge of signal S2 is equal to Dmax.

[0061] This description is not limited to the above example, and a person skilled in the art is able to foresee other values ​​of K2, A1 and A2 that allow the operation described above.

[0062] A circuit C3 of converter 1 is configured to quantize the output signal RES1 of the integrator circuit INT onto one bit, and to store, at the beginning of each pulse P3, this binary quantization of the signal RES1 onto one bit OUT1.

[0063] In one embodiment, circuit C3 is configured to provide a comp1 bit corresponding to the binary quantization of the RES1 signal, and to update the OUT1 bit from the comp1 bit at the beginning of each P3 pulse. More specifically, circuit C3 is configured to compare the RES1 signal to a ref level, preferably equal to half the output dynamic range of the INT circuit, and to provide the comp1 bit in a first binary state when the RES1 signal is above the ref reference level, and in a second binary state when the RES1 signal is below the ref reference level. For example, the first binary state of the comp1 signal corresponds to a high level of the comp1 signal, and the second binary state of the comp1 signal corresponds to a low level of the comp1 signal.As an example, the reference level or potential is equal to half the difference between a high supply potential Vdd and a low supply potential, for example ground or Vss=-Vdd, of converter 1.

[0064] In one embodiment, the storage operations performed by circuit C3, that is, the updates to the state of the output bit OUT1 of circuit C3, are controlled by a signal, or pulses, CMD3. The CMD3 signal has active edges that are synchronized, or coincide, with the beginnings of the P3 pulses. For example, each P3 pulse begins at the same time as an active edge of the CMD3 signal, or, in other words, at the same time as a CMD3 pulse. Preferably, the durations of the CMD3 pulses and the P3 pulses are equal. As an example, the P3 pulses are determined from the CMD3 signal, or, in other words, the CMD3 signal controls the generation or provision of the P3 pulses.As an example, the C3 circuit includes a flip-flop, for example of type D, which samples the result of the binary quantization comp1 of the RES1 signal with respect to the ref level at each start of a P3 pulse, for example at each start of a CMD3 pulse, and which provides the OUT1 bit as output.

[0065] In one embodiment, circuit C2 is configured to provide the CMD3 signal. In another embodiment, circuit C2 is configured to provide the CMD3 signal at least partially from the clk signal. In another embodiment, circuit C2 is configured to provide the CMD3 signal from both the clk and CMD1 signals.

[0066] A circuit C4 of converter 1 is configured to generate, for each pulse P1, the corresponding pulse P3 from bit OUT1.

[0067] In one embodiment, circuit C4 is configured so that the integration of each pulse P3 implements a subtraction of the binary quantization stored at the beginning of that third pulse P3. More specifically, circuit C4 is configured so that, for each pulse P1, the integration of the associated pulse P3 by circuit INT corresponds to a subtraction, from signal RES1, of the binary quantization stored at the beginning of pulse P3 by circuit C3. Put another way, circuit C4 is configured so that each pulse P3 implements the negative sigma-delta feedback, that is, the negative sigma-delta feedback implemented in converter 1.

[0068] In one embodiment, the C4 circuit is configured to generate the P3 pulses from the OUT1 bit and the CMD3 signal. In other words, the supply of the P3 pulses is controlled by the CMD3 signal.

[0069] In one embodiment, the P3 pulses are signed like the P1 and P2 pulses. The sign of each P3 pulse is then determined by the value (or state) of the OUT2 bit. For example, when the OUT2 bit is in a first binary state, the P3 pulse has a negative level equal to -A3, and when the OUT2 bit is in a second binary state, the P3 pulse has a positive level equal to +A3. A3 is a strictly positive real value corresponding to the amplitude of each P3 pulse and is identical for all P3 pulses. Because each P3 pulse has an amplitude equal to A3, the P3 signal has a peak-to-peak amplitude equal to 2*A3.

[0070] Let K3*Tclk be the duration of the pulses P3, where K3 is a positive, non-zero integer. In one embodiment, the circuit C4 is configured such that the product of the duration K3*Tclk of the pulses P3 and the amplitude A3 of the pulses P3 is equal to the product of the duration K2*Tclk of the pulses P2 and the amplitude A2 of the pulses P2. In other words, the circuit C4 is configured such that K3*A3 = K2*A2.

[0071] Converter 1 described above is particularly simple and compact to implement.

[0072] In addition, converter 1 does not require a calibration phase, unlike many known digital-time converters.

[0073] In the sigma-delta converter 1, quantization is implemented on a single bit. This results in better conversion linearity than if quantization had been implemented on multiple bits. Although single-bit quantization generates a large quantization error in the form of high quantization noise, converter 1 is of the sigma-delta type and therefore has the property of shifting this quantization noise to higher frequencies, such that the noise density at low frequencies is decreased while the noise density at high frequencies is increased. Thus, by applying digital low-pass filtering to the output of converter 1, a large portion of the quantization noise, for example, more than 99% of the quantization noise, is removed, and the signal-to-noise ratio of the useful signal is improved, for example, by 40 dB. In the example illustrated in figure 1 The OUT1 signal corresponds to the converter's output signal. Implementing a digital low-pass filter, for example clocked at the frequency of the S1 signal, on this OUT1 output signal then provides a binary word indicating the measured time value with less quantization noise than the OUT1 bit.

[0074] In an embodiment where converter 1 is implemented in an all-digital phase-locked loop, the digital low-pass filtering of the OUT1 signal is performed by the digital filter of the phase-locked loop, it being understood that the output signal of converter 1 can be combined with other digital signals before being supplied to the filter. In such an embodiment, converter 1 takes advantage of the digital low-pass filter already present in the all-digital phase-locked loop.

[0075] According to an embodiment in which converter 1 is implemented in an all-digital phase-locked loop, the clk signal corresponds to the periodic output signal of the phase-locked loop, the S1 signal corresponds to the periodic input signal of the phase-locked loop, and the S2 signal is obtained from the clk signal. Thus, the converter does not require any clock or timing signals other than those available at the input and output of the phase-locked loop.

[0076] According to an embodiment in which converter 1 is implemented in an all-digital phase-locked loop, converter 1 directly provides a normalized phase gap, without requiring additional calculation.

[0077] There figure 2 represents, schematically, details of an example embodiment of converter 1 of the figure 1 .

[0078] In this example, the active fronts of signals S1 and S2 are the rising fronts of these signals, it being understood that the person skilled in the art is able to adapt the description given below in the case where the active fronts of one and / or the other of signals S1 and S2 are falling fronts.

[0079] Furthermore, in this example, the level of pulses P1 is equal to +A1, the level of pulses P2 is equal to - A2, and K2 and K3 are each equal to 1. Thus, the amplitude A3 of pulses P3 is equal to the amplitude A2 of pulses P2, and, furthermore, Dmax = 2*A2 / A1*Tclk.

[0080] In the example of the figure 2 Circuit C1 includes a 200 flip-flop. The 200 flip-flop is configured so that a rising edge of signal S1 sets signal CMD1 high, and the next rising edge of signal S2 sets signal CMD1 low. In other words, the 200 flip-flop is configured so that a rising edge of signal S1 starts a corresponding CMD1 pulse, and the next rising edge of signal S2 ends that CMD1 pulse. For example, the 200 flip-flop is an RS flip-flop with an input S (initialization input) receiving signal S1, an input R (reset input) receiving signal S2, and an output Q providing the CMD1 pulses.

[0081] In the example of the figure 2 , circuit C1 also includes a circuit 202 (block "A1" in figure 2 Circuit 202 is configured to receive CMD1 pulses and provide the corresponding P1 pulses. In other words, circuit C1 is configured to provide P1 pulses of amplitude A1 from the CMD1 signal. As an example, circuit 202 includes one or more resistive elements and / or a switch controlled by the CMD1 signal.

[0082] In the example of the figure 2 Circuit C2 is configured to generate, after each CMD1 pulse, a P2 pulse starting simultaneously with an active edge, for example, a rising edge, of the clk signal, and to generate, after each P2 pulse, a CMD3 pulse starting simultaneously with an active edge, for example, a rising edge, of the clk signal. Circuit C2 is configured so that the duration of each P2 pulse is equal to K2*Tclk and the duration of each CMD3 pulse is equal to K3*Tclk, with K2 and K3 each equal to 1 in this example.

[0083] For example, as illustrated in figure 2 Circuit C2 comprises three flip-flops: 206, 208, and 210. Flip-flop 206 is configured to provide, from the CMD1 signal, a run signal indicating for each CMD1 pulse whether the pulse is complete or not. Flip-flop 208 is configured to provide a CMD2 signal determining the start and end of each P2 pulse from the run signal and the clk signal. Flip-flop 210 is configured to provide the CMD3 signal from the CMD2 signal and the clk signal. Circuit C2 further includes a circuit 212 (block "-A2") configured to provide the P2 pulses from the CMD2 signal, each P2 pulse having an amplitude of A2.

[0084] As an example, the 206 flip-flop is a type D flip-flop (D flip-flop in English) with a data input D receiving a high level ('1' in figure 2 ), for example the supply potential Vdd of converter 1, a clock (or synchronization) input C active on falling edge and receiving the CMD1 signal, a reset input R active on high level and receiving the CMD2 signal and an output Q providing the run signal.

[0085] As an example, the 208 flip-flop is a D-type flip-flop ("D flip-flop" in English) having a data input D receiving the run signal, a clock input C receiving the clk signal and being sensitive, or active, on the active edges of the clk signal, and an output Q providing the CMD2 signal.

[0086] As an example, the 210 flip-flop is a D-type flip-flop having a data input D receiving the CMD2 signal, a clock input C receiving the clk signal and being sensitive, or active, on the active edges of the clk signal, and an output Q providing the CMD3 signal.

[0087] Circuit 212 is configured to receive CMD2 pulses and provide the corresponding P2 pulses. In this example, the P1 pulses are positive and each have a level equal to A1, while the P2 pulses are negative and each have a level equal to -A2. For example, circuit 212 includes one or more resistive elements and / or a switch controlled by the CMD2 signal.

[0088] In the example of the figure 2 The INT circuit includes an operational amplifier 214 configured as an integrator; the integrator configuration of operational amplifier 214 is not detailed in figure 2 The amplifier 214 includes a first coupled input, preferably connected, to a node 216 configured to receive pulses P1, P2 and P3. An output of the amplifier 214 provides the signal RES1.

[0089] For example, as illustrated in figure 2 The C3 circuit may include a comparator 218, for example, implemented from an operational amplifier. The comparator 218 has one input receiving the RES1 signal, another input receiving the ref level against which the RES1 signal is compared, and an output providing a binary comp1 signal in a first state, for example, high, when the RES1 signal is above the ref level, and in a second state, for example, low, when the RES1 signal is below the ref level. The comp1 signal corresponds to the one-bit quantization, or binary quantization, of the RES1 signal. The C3 circuit may then also include, as illustrated in figure 2 A memory element 220 is clocked by the CMD3 signal. Element 220 is configured to provide the OUT1 bit from the comp1 bit, for example, to update the state of the OUT1 bit from the state of the comp1 bit at the beginning of each CMD3 pulse. In other words, element 220 is configured to sample the comp1 bit, for example, on each rising or falling edge of the CMD3 signal, and store the sampled level of the comp1 bit in the OUT1 bit. As an example, element 220 is a D-type flip-flop with a data input D receiving the comp1 signal, a clock input C receiving the CMD3 signal and active on the rising edge of the CMD3 signal, and an output Q providing the OUT1 bit.

[0090] In the example of the figure 2 , circuit C4 corresponds to a 222 circuit (block "-A3 / +A3" in figure 2 The 222 circuit receives the OUT1 signal and the CMD3 signal and provides the corresponding P3 pulses. As an example, the 222 circuit includes one or more resistive elements and / or a switch controlled by the CMD3 signal.

[0091] Consider, for example, the case where a positive, or negative, pulse P1, P2, or P3 input to integrator 214 causes an increase, or a decrease, in the signal RES1, respectively. In this example, after each update of bit OUT1, circuit 222 provides a negative pulse P3 of amplitude A3 when bit OUT1 is in a binary state indicating that signal RES1 is above the ref level, and a positive pulse P3 of amplitude A3 when bit OUT1 is in a binary state indicating that signal RES1 is below the ref level. In other words, after each update of bit OUT1, circuit 222 provides a pulse P3 of level -A3 when bit OUT1 indicates that signal RES1 is above the ref level, and of level +A3 when bit OUT1 indicates that signal RES1 is below the ref level.

[0092] A person skilled in the art will be able to deduce from the above example the polarity of the P3 pulses as a function of the state of the OUT1 bit in the case where a positive, or negative, P1, P2 or P3 pulse at the input of the integrator 214 causes a decrease, or an increase, of the RES1 signal.

[0093] There figure 3 illustrates, through timing diagrams, an example of the operation of converter 1 of the figure 1 when implemented in the manner described in relation to the figure 2 In the example of the figure 3 K2 and K3 are each equal to 1, and the amplitudes A2 and A3 are equal to 0.5 times the amplitude A1, although a person skilled in the art may adapt the description given below in the case where K2, K2, A1, A2 and A3 have other values. In this example, a positive, or negative, pulse P1, P2 or P3 at the input of integrator 214 causes an increase, or decrease, of the signal RES1, and, furthermore, that the bit OUT1 is updated to high, or low, when at the time of this update the signal RES1 is above, or below, the ref level.

[0094] As an example, at time t0, the output RES1 of the INT circuit and the signals P1, P2 and P3 are at their zero level, the signals S1 and S2, run and OUT being in the low state.

[0095] There figure 3 illustrates a single operating cycle of converter 1, that is, the succession of steps repeated after each active edge of signal S1.

[0096] At a time t1 later than time t0, signal S1 switches to the high state. The rising edge of signal S1 causes signal CMD1 (not shown in figure 3 ) switches to the high state and the P1 signal switches to the +A1 level. In other words, the rising edge of the S1 signal causes the start of a CMD1 pulse and a P1 pulse.

[0097] From time t1, because the INT circuit receives the positive pulse P1, the signal RES1 varies, in this example increases, with a slope proportional to the level of the pulse P1, each pulse P1 having here a level equal to +A1.

[0098] At a time t2 later than time t1, signal S2 switches to the high state. The rising edge of signal S2 causes signal CMD1 (not shown in figure 3 ) switches to the low state and the signal P1 returns to its zero level. In other words, the rising edge of the signal S2 causes the CMD1 and P1 pulses to terminate. As a result, the signal RES1 ceases to vary and retains its value at time t2.

[0099] Furthermore, the end of the CMD1 pulse (not shown in figure 3 ), that is, the falling edge of the CMD1 signal received by the flip-flop 206, causes the switch to the high state of the run signal.

[0100] An instant t3 after instant t2 corresponds to the first rising edge of the clk signal following the end of the P1 pulse. This rising edge of the clk signal causes the CMD2 signal to switch to the high state (not shown in figure 3 ) and at the -A2 level of the P2 signal. In other words, this edge of the clk signal causes the start of a CMD2 pulse and a P2 pulse. Furthermore, the start of the CMD2 pulse causes the run signal to switch to the low state.

[0101] From time t3, because the INT circuit receives the negative pulse P2, the RES1 signal varies, in this example decreases, with a slope proportional to the level of the pulse P2, each pulse P2 having here a level equal to -A2.

[0102] An instant t4 after instant t3 corresponds to the next rising edge of the clk signal. This rising edge of the clk signal causes the CMD2 signal (not shown in figure 3 ) switches to the low state and the P2 signal returns to its zero level. In other words, the rising edge of the clk signal causes the CMD2 and P2 pulses to terminate. Furthermore, this rising edge of the clk signal causes the CMD3 signal to switch to the high state (not shown in figure 3 ), therefore the update of bit OUT1 and the start of a P3 pulse.

[0103] In this example, when it is updated at time t4, the OUT1 bit switches to the high state because the RES1 signal is greater than the ref level at time t4.

[0104] In this example, the high state of bit OUT1 results in a negative pulse P3 of amplitude A3, that is, a pulse with a level of -A3, and the low state of bit OUT1 results in a positive pulse P3 of amplitude A3, that is, a pulse with a level of +A3. Thus, in this example, the pulse P3 starting at time t4 has a level of -A3 because bit OUT1 is in the high state.

[0105] From time t4, because the INT circuit receives the pulse P3, the signal RES1 varies with a slope proportional to the level of the pulse P3. More specifically, in this example, the signal RES1 decreases with a slope proportional to the negative level -A3 of the pulse P3.

[0106] An instant t5 after instant t4 corresponds to the next rising edge of the clk signal. This rising edge of the clk signal causes the CMD3 signal to switch to the low state, thus ending the P3 pulse, i.e., returning the P3 signal to zero level.

[0107] Furthermore, from time t5 onwards, as long as the INT circuit no longer receives pulse P1, P2 or P3, the RES1 signal memorizes, or retains, its value at time t5.

[0108] After time t5, each new rising edge of the signal S1 causes a new operating cycle of the converter 1, i.e. a new succession of pulses P1, P2 and P3, a modification of the signal RES1 from its current value, and an update of the bit OUT1 on the basis of the signal RES1.

[0109] There figure 4 illustrates an example of a phase-locked loop in all digital 4, according to one embodiment, where the phase-locked loop 4 includes the converter 1.

[0110] The phase-locked loop 4 is configured to receive a clkref signal at a first frequency and to provide the clk signal at a second frequency equal to N / D times the first frequency, where N and D are two positive values. Preferably, D is greater than or equal to 1, and N is greater than 1 and generally greater than D.

[0111] Phase-locked loop 4 includes converter 1. Converter 1 includes an input configured to receive the clkref signal, which then corresponds to the S1 signal described in relation to the figures 1 et 2 and a second input configured to receive the clk signal. In the example embodiment illustrated by the figure 4 , the S2 signals (see figures 1 et 2 ) and clk of converter 1 are confused.

[0112] Converter 1 provides an output signal TDCOUT. When converter 1 is of the type described in relation to the figure 1 or the figure 2 , the TDCOUT signal is for example equal to the OUT bit.

[0113] In figure 4 , the phase-locked loop 4 includes an accN circuit, an accD circuit, a reg register, a digital arithmetic circuit 400, a digital low-pass filter 402 and a digitally controlled oscillator 404.

[0114] The accN circuit is configured to provide a digital signal accNOUT incremented by the value N at the frequency of the clkref signal. In other words, at each active edge of the clkref signal, the accNOUT signal is incremented by the value N. Put another way, the accNOUT signal represents the accumulated phase of the clkref signal.

[0115] The accD circuit is configured to provide a digital signal accDOUT incremented by the value D at the frequency of the clk signal. In other words, at each active edge of the clk signal, the accDOUT signal is incremented by the value D.

[0116] The reg circuit is configured to sample the accDOUT signal synchronously with the clkref signal, for example, synchronously with the active edges of the clkref signal, and to provide an accDOUT' signal corresponding to the stored sampling. In other words, the reg circuit copies the accDOUT signal to its accDOUT' output at each active edge of the clkref signal. Put another way, the accDOUT' signal represents the accumulated phase of the clk signal sampled by clkref.

[0117] The accD and reg circuits thus form a circuit configured to provide the accDOUT signal incremented by the value D at the frequency of the clk signal, and the accDOUT' signal corresponding to the sampling of the accDOUT signal by the clkref signal. In other words, the accD and reg circuits form a circuit configured to provide the accDOUT' signal corresponding to the sampling, by the clkref signal, of the accDOUT signal incremented by the value D at the frequency of the clk signal.

[0118] The digital filter 402, in practice a low-pass filter, is configured to receive and filter a FIN result of a subtraction of the output signal TDCOUT of converter 1 and the accDOUT' signal from the accNOUT signal, and to control the oscillator 404. Thus, the circuit 400 is configured to receive the signals TDCOUT, accNOUT and accDOUT' and to provide, at the input of the filter 402, the digital signal FIN corresponding to the digital signal accNOUT from which the digital signals TDCOUT and accDOUT' have been subtracted.

[0119] Filter 402 provides a DCOCTRL digital control signal to oscillator 404. The DCOCTRL signal corresponds to the result of the low-pass filtering of the FIN signal by filter 402. As an example, the z-transfer function of filter 402 can be of the type a+ (b / (1-z -1< )).

[0120] The oscillator 404 is configured to provide the clk signal at a frequency determined by the output value of the filter 402, i.e. by the value of the DCOCTRL signal.

[0121] In phase-locked loop 4, the subtraction of the accDOUT' signal from the accNOUT signal represents the phase error of the loop, affected by a residual phase error PhiError between the frequency of the clkref signal and that of the clk signal. This error PhiError is practically equal to the ratio of a value DeltaT to a period Tclk of the clk signal, where DeltaT is the time separating each edge of the clkref signal from the next edge of the clk signal. The prediction of converter 1 and the subtraction of the TDCOUT signal from the result of the subtraction of the accDOUT' signal from the accNOUT signal eliminates the residual phase error PhiError in the FIN signal, which represents the phase error of loop 4.

[0122] Although not illustrated here, converter 1 can be implemented in all-digital phase-locked loops different from that of the figure 4 . For example, converter 1 can be implemented in an all-digital phase-locked loop not including the accN, accD, reg and 400 circuits, in which the output TDCOUT of converter 1 is directly supplied to filter 402, converter 1 receives the clkref signal or a signal obtained by dividing the frequency of the clk signal by D and the clk signal or a signal obtained by dividing the frequency of the clk signal by N.

[0123] There figure 5 represents, schematically, details of an example embodiment of converter 1 of the figure 1 , in a case where the converter is implemented in a phase-locked loop of the type of that of the figure 4 .

[0124] In this example embodiment, the S2 signals ( figures 1 et 2 ) and clk are confused, and the S1 signals ( figures 1 et 2 ) and clkref are identical. Furthermore, in this example, the duration of pulses P2 and P3 is equal to one period Tclk of the signal clk (K2=K3=1), and the amplitudes A2 and A3 are equal to 0.5 times the amplitude A1. Thus, the maximum duration Dmax of pulses P1 is equal to Tclk, and, in this example where pulses P1 begin with the rising edges of signal S1 and end with the rising edges of signal S2, the dynamic range of converter 1 is also equal to Dmax=Tclk.

[0125] Converter 1 of the figure 5 is similar to converter 1 of the figure 3 and only the differences between these converters are highlighted here.

[0126] In particular, because the S2 and clk signals are confused, flip-flop 206 ( figure 2 ) of circuit C1 is omitted, and the data input D of the flip-flop 208 of circuit C1 directly receives the CMD1 signal.

[0127] There figure 6 illustrates, through timing diagrams, the operation of converter 1 of the figure 5 .

[0128] The timelines of the figure 6 are similar to those of the figure 3 , and only the differences between the latter will be highlighted here. In particular, the figure 6 does not understand the run signal because converter 1 of the figure 5 does not understand this signal. In the example of the figure 6 , as in the example of the figure 3 , a positive, respectively negative, pulse P1, P2 or P3 at the input of the integrator 214 causes an increase, respectively a decrease, of the RES1 signal, and the OUT1 bit is updated to the high, respectively low state, when at the time of this update the RES1 signal is greater, respectively less, than the ref level.

[0129] In figure 6 , an instant t10 corresponds to the instant t0 described in relation to the figure 3 .

[0130] In figure 6 , a time t11 subsequent to time t10 corresponds to time t1 described in relation to the figure 3 , that is to say at an active front (in this example a rising front) of the clkref signal.

[0131] In figure 6 An instant t12, subsequent to instant t11, corresponds to the first active edge (in this example, a rising edge) of the clk signal following the rising edge of the clkref signal at instant t11. This rising edge of the clk signal terminates the pulses P1 and CMD1; the CMD1 signal is not shown in the diagram. figure 6 Furthermore, this rising edge of the clk signal triggers the start of the CMD2 and P2 pulses, the CMD2 signal not being represented in figure 6 .

[0132] Put another way, in figure 6 , the instants t2 (end of pulse P1) and t3 (beginning of pulse P2) described in relation to the figure 3 are coincident and correspond to time t12.

[0133] In figure 6 , a time t13 subsequent to time t12 corresponds to time t4 described in relation to the figure 3 (rising edge of the clk signal, end of pulse P2 and beginning of pulse P3), and a time t14 subsequent to time t13 corresponds to time t5 described in relation to the figure 3 (rising edge of the clk signal and end of the P3 pulse).

[0134] After time t14, each new rising edge of the clkref signal causes a new operating cycle of converter 1, i.e. a new succession of pulses P1, P2 and P3, a modification of the RES1 signal from its current value, and an update of the OUT1 bit on the basis of the RES1 signal.

[0135] The person in the trade is able to understand that, in the example illustrated by the figure 6 , the frequency of the clk signal is at least three times greater than that of the clkref signal so that the converter 1 has time to generate and integrate three successive pulses P1, P2 and P3 after each active edge of the clkref signal and before the next active edge of the clkref signal.

[0136] In converter 1 of the figure 5 Because the peak-to-peak amplitude of signal P3 is equal to 2*A3 and is equal to that of signal P1, namely A1, the converter effectively normalizes the value of bit OUT1 over one period of signal clk. In other words, bit OUT1 represents the value of the residual phase error PhiError and can be supplied as is to the input of circuit 400 of the phase-locked loop 4 described in relation to the figure 4 .

[0137] There figure 7 represents, schematically, details of another example of an embodiment of the digital-to-time converter of the figure 1 , in a case where the converter is implemented in a phase-locked loop of the type of that of the figure 4 .

[0138] In particular, the method of implementation of the figure 7 differs from that of the figure 5 in that the S2 signal ( figures 1 et 2 ) is obtained by dividing the frequency of the clk signal by two.

[0139] Furthermore, in this example, the duration of pulses P2 and P3 is equal to one period Tclk of the signal clk (K2=K3=1), and the amplitudes A2 and A3 are equal. In this example, where pulses P1 begin with the rising edges of signal S1 and end with the rising edges of signal S2, the maximum duration Dmax of pulses P1 is then equal to 2*Tclk. Therefore, the amplitude A1 is equal to the amplitude A2 and the amplitude A3, and the dynamic range of converter 1 is also equal to Dmax=2*Tclk.

[0140] More specifically, converter 1 of the figure 7 differs from that of the figure 5 by the implementation of its C2 and C1 circuits, and by the fact that it also includes a 700 circuit. The 700 circuit is a frequency divider. In other words, the 700 circuit is configured to provide a signal at a frequency divided by the frequency of an input signal to the 700 circuit.

[0141] The 700 circuit is configured to receive the clk signal and to provide the S2 signal, the latter having, in this example, a frequency half that of the clk signal. In other, unillustrated embodiments, a person skilled in the art could use a different ratio of two between the frequency of the clk signal and that of the S2 signal, by adjusting the amplitudes of the P1, P2, and / or P3 pulses and / or the durations of the P2 and P3 pulses so that the entire dynamic range of the P1 pulses can be converted by converter 1.

[0142] For example, as illustrated in figure 7 The 700 circuit includes a 702 D-type flip-flop. The 702 flip-flop has a clock input C configured to receive the clk signal, with input C being sensitive to the active edges of the clk signal (rising edges in this example), an output Q configured to provide the S2 signal, and a data input D configured to receive the inverse of the Q output. As an example, the inverse of the Q output is provided to the D input of the 702 flip-flop by a 704 inverter. The 704 inverter, for example, has one input connected to the Q output of the 702 flip-flop and one output connected to the D input of the flip-flop.

[0143] In this example, circuit C1 of the figure 7 , and more specifically its 202 circuit, differ from those of the figure 5 in that the P1 pulses they provide each have an amplitude A1 equal to the amplitudes A2 and A3, and not twice the amplitudes A2 and A3 as was the case in the example of the figure 5 As an example, circuit 202 includes one or more resistive elements and / or a switch controlled by the CMD1 signal.

[0144] Compared to converter 1 described in relation to the figures 2 And 5 , in converter 1 of the figure 7 The pulses P1, each beginning on an active edge of signal S1 and ending on the next active edge of signal S2, have a maximum duration Dmax equal to two periods Tclk of signal clk. Thus, circuit C2 is modified so that for each pulse P1, the corresponding pulse P2 only begins once pulse P1 has ended.

[0145] In the example of the figure 7 , compared to what has been described in relation to the figure 5 The CMD2 signal is not directly available at the output of flip-flop 208 in circuit C2. More specifically, in figure 7 The 208 flip-flop always has an input D configured to receive the CMD1 signal and an input C configured to receive the clk signal and to be sensitive to the rising edges of the clk signal. However, circuit C2 includes a logic circuit configured to provide a CMD2 pulse only when the Q output of the 208 flip-flop has switched following a P1 pulse and that P1 pulse has ended. For example, this logic circuit is configured to implement the logical AND between the inverse of the CMD1 signal and the Q output of the 208 flip-flop, the result of this logical operation being the CMD2 signal. As an example, illustrated by the figure 7 This logic circuit includes an AND gate 706 with one input connected to the Q output of a flip-flop 208 and another input connected to the output of an inverter 708 whose input receives the CMD1 signal, and whose output provides the CMD2 signal. Of course, a person skilled in the art can foresee other implementations of this logic circuit.

[0146] As in figures 2 And 5 , the CMD2 signal is supplied to the D input of the 210 flip-flop of circuit C1.

[0147] There figure 8 illustrates, through timing diagrams, an example of the operation of converter 1 of the figure 7 In figure 8 , the S2 signal is obtained by dividing the frequency of the clk signal by two, and the S1 and clkref signals are coincident.

[0148] In the example of the figure 8 , as in the examples of figures 3 And 6, a positive, respectively negative, pulse P1, P2 or P3 at the input of the integrator 214 causes an increase, respectively a decrease, of the RES1 signal, and the OUT1 bit is updated to the high, respectively low state, when at the time of this update the RES1 signal is greater, respectively less, than the ref level.

[0149] For example, at time t20, the output RES1 of the INT circuit is at a constant or stored value, in this example negative with respect to the ref level. In addition, the signals P1, P2 and P3 are at their zero levels, the clkref signal is low, and the OUT1 bit is high.

[0150] At a time t21 after time t20, the clkref signal switches to the high state, which causes a rising edge of the CMD1 signal (not shown in figure 8 ) and the transition of the P1 signal to the +A1 level. In other words, the rising edge of the clkref signal causes the start of a CMD1 pulse and a P1 pulse.

[0151] From time t21, due to the fact that the INT circuit ( figure 7 ) receives the positive pulse P1, the signal RES1 varies, in this example increases, with a slope proportional to the level +A1 of the pulse P1. Each pulse P1 here has an amplitude equal to A1.

[0152] At a time t22 later than time t21, signal S2 switches to the high state. The rising edge of signal S2 causes signal CMD1 (not shown in figure 8 ) switches to the low state and the signal P1 switches to its zero level. In other words, the rising edge of the signal S2 causes the end of the pulse CM1 and the pulse P1.

[0153] Furthermore, the end of the CMD1 pulse (not shown in figure 8 ), triggers the start of a CMD2 pulse (not shown in figure 8 ), therefore the beginning of a P2 pulse.

[0154] From time t22, due to the fact that the INT circuit ( figure 7 ) receives the negative pulse P2, the RES1 signal varies, in this example decreases, with a slope proportional to the level -A2 of the pulse P2. Each pulse P2 here has an amplitude equal to A2.

[0155] An instant t23 after instant t22 corresponds to the next rising edge of the clk signal. This rising edge of the clk signal causes the CMD2 signal (not shown in figure 8 ) switches to the low state and the P2 signal switches to its zero level. In other words, this edge of the clk signal causes the end of the CMD2 and P2 pulses.

[0156] Furthermore, the rising edge of the clk signal at time t23 causes the CMD3 signal to switch to the high state (not shown in figure 8 ), therefore the update of bit OUT1 and the start of a P3 pulse.

[0157] In this example, at time t23, the OUT1 bit switches to a low state because, at that time t23, the RES1 signal is lower than the ref level. Furthermore, in this example, the low state of the OUT1 bit results in a positive P3 pulse of level +A3, and the high state of the OUT1 bit results in a negative P3 pulse of level -A3. Thus, in this example, the P3 pulse starting at time t23 has a level of +A3 because the OUT1 bit is low from time t23 onward.

[0158] From time t23, because the INT circuit receives the positive pulse P3, the signal RES1 varies with a slope proportional to the +A3 level of the pulse P3. More specifically, in this example, the signal RES1 increases with a slope proportional to the +A3 level of the pulse P3.

[0159] An instant t24 after instant t23 corresponds to the next rising edge of the clk signal. This rising edge of the clk signal causes the CMD3 signal to switch to the low state, thus ending the P3 pulse.

[0160] Furthermore, from time t24, as long as the INT circuit does not receive any more pulses P1, P2 or P3, the RES1 signal memorizes its value at time t24.

[0161] After time t24, each new rising edge of the signal S1 (for example at time t25 after time t24) causes a new operating cycle of the converter 1, that is to say a new succession of pulses P1, P2 and P3, a modification of the signal RES1 from its current value, and an update of the bit OUT1 on the basis of the signal RES1.

[0162] The person in the trade is able to understand that, in the example illustrated by the figure 8 , the frequency of the clk signal is at least four times greater than that of the clkref signal so that the converter 1 has time to generate and integrate three successive pulses P1, P2 and P3 after each active edge of the clkref signal and before the next active edge of the clkref signal.

[0163] When converter 1 of the figure 7 is implemented in a phase-locked loop of the type of that of the figure 4 Because the maximum duration Dmax that the P1 pulses can take is equal to two periods Tclk of the clk signal, the OUT1 bit of converter 1 then represents a residual phase error proportional to twice the residual phase error PhiError between the clk and clkref signals. The phase-locked loop 4 described in relation to the figure 4 is then modified accordingly.

[0164] For example, the accD circuit is modified to be clocked by the S2 signal rather than by the clk signal, that is to say that the accDOUT signal is then incremented at the frequency of the S2 signal.

[0165] Furthermore, when the accD circuit is modified in this way, so that loop 4 retains the same frequency transfer function as with converter 1 of the figure 5 The accD circuit can then be configured to increment the accDOUT signal by the value D / 2 on each rising edge of the S2 signal, if the value of D is even. Alternatively, to maintain the same frequency transfer function in loop 4, for example when the value of D is odd, the accN circuit can then be configured to increment the accNOUT signal by twice the value N on each rising edge of the clkref signal.

[0166] Although it has been described in relation to the figures 7 And 8In the case where the signal S2 is obtained by dividing the frequency of the signal clk by two, a person skilled in the art is able to adapt this description to the case where the signal S2 is obtained by a non-two integer division of the signal clk, for example by modifying accordingly the durations and / or amplitudes of the pulses P1, P2 and P3 so that the entire dynamic range of the pulses P1 can be converted by the converter 1.

[0167] Furthermore, it was described in relation to the figures 7 And 8 , an example of an embodiment of converter 1 in the case where it is implemented in a phase-locked loop of the type of that of the figure 4 The skilled person is able to adapt converter 1 of the figure 7 to an implementation in a circuit other than a phase-locked loop. For example, for this purpose, the C2 circuit of converter 1 of the figure 7 is modified to understand the flip-flop 206 in order to generate the run signal, this run signal being supplied as input to the flip-flop 208 and the logic circuit 708, 706 in place of the CMD1 signal.

[0168] The sigma-delta type converter 1 described in relation to the figures 1 à 8 is of order 1, meaning that the quantization error is integrated only once in each operating cycle. In this case, the noise shaping slope is, for example, 20dB per decade.

[0169] Converter 1 can be modified according to a multi-stage noise shaping (MASH) architecture, such that Converter 1 is of order higher than 1, the order of Converter 1 corresponding to the number of quantization error integrations per operating cycle of Converter 1. In this case, Converter 1 comprises a first stage including the circuits INT, C1, C2, C3, and C4 described previously, and a second stage configured to receive the output signal RES1 from the INT circuit of the first stage, and to generate, at the output of the second stage, a digital signal from the RES1 signal, preferably by implementing an integration of a signal determined by the RES1 signal. The digital output signal TDCOUT of Converter 1 is then determined at least in part by the OUT1 bit and the digital output signal of the second stage.

[0170] According to one embodiment, the second floor is configured to: generate, after each pulse P3, a pulse CMD4 starting in synchronism with the clk signal; integrate, during each pulse P4, a sum of the RES1 output signal of the INT circuit and a CR feedback signal, quantize on one bit a result RES2 of said integration and store on one bit OUT2 said binary quantization at the end of the pulse CMD4; generate, during each pulse P3, a pulse P4 from the bit OUT2, and the CR signal by integrating the pulse P4; and store the bit OUT2 on a bit OUT2-1 at each active edge of the signal S2, the digital output signal of the second stage being generated from the bits OUT2 and OUT2-1 or corresponding to the bits OUT2 and OUT2-1.

[0171] In other words, the second stage is configured to receive as input the residual quantization error available at the output of the INT circuit after each P3 pulse, and to integrate it again. Furthermore, the second stage implements negative sigma-delta feedback using the CR signal determined from the OUT2 bit. The CR signal is determined after each converter cycle and before the start of the corresponding CMD4 pulse. During each CMD4 pulse, the CR signal is summed with the RES1 signal, and the second stage integrates the sum S of the RES1 and CR signals. The result RES2 of this integration is quantized and stored on the OUT2 bit.

[0172] As an example, the TDCOUT output of the second-order converter 1 is obtained by summing the OUT1 output of the first stage with the mathematical derivative of the OUT2 signal of the second stage.

[0173] As an example, negative feedback, i.e., the determination of the CR signal, involves integrating the P4 pulse, the sign of which is determined by the state of the OUT2 bit. The result of this integration corresponds to the CR signal and is reset before each new integration of a P4 pulse, therefore at each operating cycle of converter 1. As an example, since each P4 pulse is generated during a CMD3 pulse, the duration of each P4 pulse is equal to K4*Tclk, with K4 a strictly positive integer equal to K3.

[0174] Because the second stage implements a second integration of the quantization error, the noise shaping slope is, for example, at least 40dB per decade and depends on the number of cascaded stages in converter 1, the slope being, for example, equal to 40 dB per decade when the MASH-type sigma-delta converter 1 comprises exactly two stages.

[0175] The increased noise shaping resulting from raising the converter order to 1 further reduces low-frequency noise. In addition, raising the converter order to 1 results in a cleaner frequency spectrum for the clk signal.

[0176] Higher-order MASH converters of type 1 are constructed by cascading the stages in the same way as described for the first and second stages of the second-order converter 1. For example, the integrator output of the Nth stage (N) is fed into the input of the N+1st stage, and the quantized and derivative output of the N+1 stage is summed to the quantized output of the N stage. For each additional stage, an extra pulse is added to the operating cycle of converter 1 to synchronize the operation of that stage with the other stages of converter 1.

[0177] There figure 9 illustrates a variant implementation of converter 1 of the figure 1 More specifically, the figure 9 illustrates an example of the implementation of converter 1 when it is of type MASH of order 2. In this figure 9 , the first stage of converter 1 is referenced STAGE1 and delimited by dotted lines, the second stage of converter 1 is referenced STAGE2 and delimited by dotted lines.

[0178] The STAGE1 stage comprises circuits C1, C2, C3, C4 and INT, shown and connected in figure 9 in the same way as in figure 1 The output signal of STAGE1 is the OUT1 bit. As an example, circuits C1, C2, INT, C3, and C4 are implemented as described in relation to the figure 2 .

[0179] In this example, the STAGE2 level comprises circuits C5, INT2, C6, C7, and DER, examples of whose implementation are described in more detail below. However, a person skilled in the art should be able to anticipate other implementation examples for at least one of these circuits (C5, INT2, C6, C7, and DER) based on the functional description that will be provided.

[0180] Circuit C5 is configured to generate a corresponding CMD4 pulse after each P3 pulse. Each CMD4 pulse has a duration equal to K4*Tclk, where K4 is a strictly positive integer equal to K3. For example, circuit C5 receives the CMD3 signal indicating the start and end of each P3 pulse, ensuring that all pulses received by circuit C5 have the same sign. In the example illustrated by the figure 9 , the C5 circuit includes a 900 flip-flop, for example of type D. As an example, the 900 flip-flop includes an input D receiving the CMD3 signal, a clock input C receiving the clk signal, and an output Q providing the CMD4 pulses in this example where K4=K3=1.

[0181] The INT2 circuit is an integrator circuit configured to integrate, during each CMD4 pulse, the sum S of the RES1 signal and the CR signal. The INT2 circuit provides a RES2 signal corresponding to the result of this integration.

[0182] As an example, the INT2 circuit receives the RES1, CR and CMD4 signals. At each CMD4 pulse, for the entire duration of the P4 pulse, the INT2 circuit is configured, for example, to sum the RES1 and CR signals and to integrate this sum S.

[0183] As an example of implementation illustrated by the figure 9 The INT2 circuit comprises two switches, 902 and 904, controlled by the CMD4 signal (for example, configured to be on during each CMD4 pulse), a 906 circuit, and an integrator circuit, 908 (for example, implemented from an operational amplifier). More specifically, switch 902 is configured to receive the RES1 signal and transmit this signal to circuit 906 only during each CMD4 pulse; switch 904 is configured to receive the RES1 signal and supply this signal to circuit 906 only during each CMD4 pulse; circuit 906 is configured to supply the signal S, which is equal to the sum of the signals it receives from switches 902 and 904; and circuit 908 is configured to integrate the signal S. Circuit 908 supplies the RES2 signal.

[0184] According to another example not shown, in the INT2 circuit, the RES1 and CR signals are first summed, and the signal corresponding to this sum is supplied to the integrator circuit 908 during each CMD4 pulse, for example by means of a switch controlled by the CMD4 pulses.

[0185] Circuit C6 is configured to quantize the RES2 signal to one bit and to store the result of this binary quantization in bit OUT2 at the end of each P4 pulse. The quantization of the RES2 signal is performed by comparing the RES1 signal to the ref level. As an example, circuit C6 generates a comp2 bit corresponding to the result of the binary quantization of the RES2 signal, and updates bit OUT2 from this comp2 bit.

[0186] As an example of implementation illustrated by the figure 9 Circuit C6 includes a comparator 910 configured to receive the RES2 signal and the ref level, or potential, and to output the comp2 bit. For example, the comp2 bit is in a first binary state when the RES2 signal is above the ref level, and in a second binary state when the RES2 signal is below the ref level. Circuit C6 also includes a memory element 912, for example a flip-flop, such as a D-type flip-flop, configured to output the OUT2 bit from the comp2 signal and update the state of the OUT2 bit at the end of each P4 pulse. In other words, the 912 element is configured to sample the comp2 bit, for example, at each falling edge of the CMD4 signal, and store the sampled level of the comp2 bit in the OUT2 bit.For example, the D-type 912 flip-flop includes an input D configured to receive the comp2 signal, a rising-edge-sensitive clock input C configured to receive a CMD4b signal complementary to the CMD4 signal, and an output Q configured to provide the OUT2 signal, the CMD4b signal being available, for example, at the output of a 914 inverter receiving the CMD4 signal as an input signal.

[0187] Circuit C7 is configured to provide the CR signal from bit OUT2. More specifically, circuit C7 is configured, at each operating cycle of converter 1 and before the start of the CMD4 pulse of that operating cycle (for example, during the CMD3 pulse of that operating cycle), to generate a P4 pulse of the same duration as the P3 pulses and to integrate this P4 pulse. Furthermore, each P4 pulse is signed, and its sign is determined by the binary state of the OUT2 signal. In other words, circuit C7 is configured, at each CMD3 pulse, to provide the CR signal by integrating, during that CMD3 pulse, the P4 pulse determined from bit OUT2. The P4 pulses all have an amplitude A4, for example, equal to the amplitude A3 of the P3 pulses.

[0188] As an example of implementation illustrated by the figure 9 The C7 circuit includes an INTP circuit configured to integrate the P4 pulses, and a 915 circuit (block +A4 / -A4 in figure 9 configured to provide P4 pulses from bit OUT2 and signal CMD3. Circuit 915 provides P4 pulses to the INTP circuit. Unlike INT integrator circuits (not shown in figure 9 and INT2, the output of the INTP integrator circuit is reset after each CMD4 pulse, for example, during the following P2 pulse. For example, the INTP circuit receives the CMD2 signal and its output is reset with each CMD2 pulse.

[0189] Consider, as an example, the case where a positive or negative pulse S at the input of integrator 908 causes a decrease or increase in the signal RES2, respectively, and where a positive or negative pulse P4 at the input of integrator INTP causes a decrease or increase in the signal CR, respectively. In this example, the P4 pulses are negative and have a level of -A4 when bit OUT2 is in a binary state indicating that the signal RES2 is above the ref level, and are positive and have a level of +A4 when bit OUT2 is in a binary state indicating that the signal RES2 is below the ref level. The amplitude A4 of the P4 pulses is preferably determined such that K3*A2=K4*A4, and is therefore equal to the amplitude A3 of the P3 pulses in this example, where K3=K4.

[0190] A person skilled in the art will be able to deduce from the above example the polarity of the P4 pulses as a function of the state of the OUT2 bit in cases where a positive, respectively negative, S pulse at the input of the integrator 918 causes an increase, respectively a decrease, of the RES2 signal and / or a positive, respectively negative, P4 pulse at the input of the integrator INTP causes an increase, respectively a decrease, of the CR signal.

[0191] In this example, the second stage, STAGE2, provides a digital output signal, NUM, from bits OUT2 and OUT2-1. The DER circuit is configured to provide the NUM signal from bit OUT2. More specifically, the DER circuit is configured to generate bit OUT2-1 from bit OUT2, and to provide the NUM signal from bits OUT2 and OUT2-1. The DER circuit performs a derivative function on the OUT2 signal, resulting in the digital signal NUM. The DER circuit is a digital circuit clocked by signal S1. In other words, the DER circuit is a differentiator circuit clocked by signal S1 and configured to provide the NUM signal from signal OUT2.

[0192] Since bit OUT2 represents the result of a double integration while bit OUT1 represents the result of a single integration, implementing a derivative function on signal OUT2 to obtain signal NUM ensures that signal NUM is consistent with signal OUT1.

[0193] As an example implementation, the DER circuit includes a 920 D-type flip-flop with an input D configured to receive the OUT2 signal, a clock input C configured to receive the S1 signal, and an output Q configured to provide the OUT2-1 signal. The DER circuit further includes a 922 circuit configured to subtract the OUT2-1 signal from the OUT2 signal, the result of this subtraction corresponding to the NUM output bits of the STAGE2 stage. For example, the NUM signal is two bits long and is encoded in two's complement.

[0194] In this example, where the second stage provides the NUM signal, which corresponds to the derivative of bit OUT2, converter 1 also includes a 984 circuit configured to provide the output TDCOUT signal of converter 1 from the signals, or bits, OUT1 and NUM. For example, the 984 circuit is configured to sum the NUM and OUT1 signals and provide the TDCOUT signal, which is the result of this sum. For example, the TDCOUT signal is a three-bit binary word, encoded in two's complement.

[0195] In another example, not illustrated in figure 9 The second stage, STAGE2, does not include the 922 circuit and therefore provides a digital output signal corresponding to the two bits OUT2 and OUT2-1. Furthermore, converter 1 does not include the 984 circuit, but instead includes an arithmetic circuit configured to provide the output signal TDCOUT from the bits OUT1, OUT2, and OUT2-1. This arithmetic circuit is configured to simultaneously perform the mathematical derivative of the OUT2 signal from the bits OUT2 and OUT2-1, and the sum of this derivative with the bit OUT1.

[0196] We considered, in relation to the figure 9 , the case where the S1 signal does not correspond to the clkref signal received by a phase-locked loop of the type of that of the figure 4 Based on the descriptions made in relation to the figures 4 à 9 The person in the trade will be able to adapt the description made in relation to the figure 9 in cases where: the duration Dmax of the P1 pulses is different from one period Tclk of the clk signal and is, for example, equal to two periods Tclk of the clk signal, and / or the signal S1 corresponds to the clkref signal of a phase-locked loop of the type described in relation to the figure 4 , and / or the S2 signal corresponds to the clk signal of a phase-locked loop of the type described in relation to the figure 4 or is obtained by integer division, for example equal to two, of the frequency of this signal clk, and / or the converter 1 is of order greater than 2.

[0197] For example, the person in the trade will be able to modify, based on the description made in relation to the figures 5 à 8 , converter 1 of the figure 9 to implement it in a phase-locked loop of the type described in relation to the figure 4 .

[0198] For example, when the second-order converter describes in relation to the figure 9 is implemented in a phase-locked loop of the type of that of the figure 4 , and that the first stage STAGE1 of the second-order converter corresponds to the first-order converter described in relation to the figure 5 , the frequency of the clk signal then being at least 4 times greater than that of the S1 signal. Alternatively, when the second-order converter 1 describes in relation to the figure 9 is implemented in a phase-locked loop of the type of that of the figure 4 , and that the first stage STAGE1 of the second-order converter corresponds to the first-order converter described in relation to the figure 7 , the frequency of the clk signal being then at least 5 times greater than that of the S1 signal.

[0199] There figure 10 illustrates an example of the implementation of part of converter 1 from the previous figures. More specifically, the figure 10 illustrates an example of an implementation of an RS flip-flop, for example the RS flip-flop of circuit C1, configured to take into account possible metastability problems.

[0200] In this example, the RS flip-flop is active on rising edges, or, put another way, the S and R inputs of the flip-flop are both sensitive to the rising edges of the signals they receive.

[0201] The flip-flop includes a NAND gate 1000 with one input connected to input S and one input configured to receive a signal sig1. The output of gate 1000 provides a signal sig2.

[0202] The flip-flop comprises three identical sets RS1, RS2 and RS3 of two NAND gates 1002 and 1004. Each set RS1, RS2 and RS3 comprises an input s connected to a first input of its gate 1002 and an input r connected to a first input of its gate 1004, the output of gate 1002 being connected to a second input of gate 1004, and the output of gate 1004 being connected to a second input of gate 1002.

[0203] The input s of the RS1 assembly receives the signal sig2, and the output of gate 1002 of the RS1 assembly constitutes the output Q of the RS flip-flop of the figure 10 In addition, the r input of the RS1 assembly receives a sig3 signal.

[0204] The s input of RS2 is connected to the output of gate 1004 of RS1, the r input of RS2 is connected to the S input of the RS flip-flop. figure 10 , and the output of gate 1004 of the RS2 assembly provides the signal sig1.

[0205] The s input of RS3 is connected to the output of gate 1002 of RS1, therefore to the Q output of the flip-flop, the r input of RS3 is connected to the R input of the flip-flop, and the output of gate 1002 of RS3 provides a sig4 signal.

[0206] The flip-flop further includes a circuit 1006, for example a chain of inverters in series, having an input connected to the R input of the flip-flop and an output providing a signal sig5. The circuit 1006 is configured to delay the signal received by the R input by a duration DT, the sig5 signal corresponding to this delayed signal.

[0207] The RS switch of the figure 10 further includes a NAND gate 1008 having one input connected to the R input of the flip-flop, another input connected to the output of circuit 1006 so as to receive the sig5 signal, and an output configured to provide a sig6 signal.

[0208] The flip-flop also includes an OR gate having an input receiving the signal sig6, an input receiving the signal sig4 and an output providing the signal sig3.

[0209] Assuming that output Q is initially low, signal sig1 is high. This allows a high input at S to propagate through gate 1000, which then provides a low input for signal sig2. RS1 then switches output Q high. Signal sig3 is initially high, and switching it low will cause output Q to switch back to low (0). Simultaneously, since signal sig3 is still high, input s of RS2 receives a low input. Because input r of RS2 is connected to the high input S, signal sig1 switches low, causing signal sig2 to switch high. This mechanism makes the flip-flop sensitive only to rising edges of S, with output Q remaining high until signal sig3 goes low.To reactivate output Q, input S must switch low and signal sig1 must switch high. Simultaneously, the RS3 system initially provides signal sig4 high because output Q is initially low. When signal Q switches high, two possibilities exist. Either input R was already high at that moment, and signal sig4 remains high, or input R was low, in which case signal sig4 switches low. This mechanism is important because the rising edge of input R can occur at any time relative to the rising edge of output Q. In particular, output Q and input R can have a rising edge at the same time. In this case, the RS3 system enters a metastable state, in which signal sig4 takes longer to "choose" between a low and a high level.In the worst-case scenario, the sig4 signal will only switch due to electronic noise present in the circuit, and therefore at a random instant. Since the standard deviation of this noise can be known, it is possible to determine the maximum time Tmax that the sig4 signal can take to switch. The purpose of circuit 1006 and the sig6 signal is to allow time for the RS3 system to recover from metastability and switch. Gate 1008 sets the sig6 signal to low only when the R input has been high for a duration at least equal to Tmax. Since the sig3 signal is the result of a logical OR operation between the sig4 and sig6 signals, if sig6 has finally switched to a low level, it will be necessary to wait for the duration DT for the sig3 signal and then the Q output to go low. If it can be guaranteed that the duration DT is greater than the duration Tmax, the sig3 signal will not undergo the random delay due to metastability but only a constant delay equal to DT.In this way the falling edge of the pulse on the Q output can avoid being marred by jitter which is detrimental to the result.

[0210] For example, when flip-flop 200 of circuit C1 is implemented as described in relation to the figure 10 The duration Dmax of the P1 pulses is increased by DT, and this duration DT must be compensated by the P2 pulses, by increasing the duration of the P2 pulses by a duration DT2. It follows that DT*A1=DT2*A2, therefore DT2=(DT*A1) / A2. For example, in the case where A1=2*A2, then DT2=2*DT.

[0211] Of course, although the switch described in relation to the figure 10 or particularly suited to implementation in circuit C1 of converter 1, a simpler flip-flop, for example an RS flip-flop similar to one of the RS1, RS2 and RS3 sets, but not addressing metastability problems, can be used to implement circuit C1.

[0212] There figure 11 illustrates an example of the implementation of another part of converter 1 from the previous figures. More specifically, the figure 11 illustrates an example of the implementation of circuit 214, it being understood that circuit 912 can be implemented in the same way.

[0213] In this example, circuit 214 includes an operational amplifier 1100 having a first input, in this example the inverting input -, configured to receive the pulses to be integrated, and a second input, in this example the non-inverting input +, receiving any potential, preferably the ref potential as illustrated in figure 11 , and an output providing the result of the integration, namely the RES1 signal for the circuit 214. A capacitor C is connected between the output of amplifier 1100 and the non-inverting input of amplifier 1100.

[0214] In this example, circuit 214 receives the pulses to be integrated on the inverting input of amplifier 1100. As a result, a positive pulse, respectively negative, causes a decrease, respectively an increase, of the signal RES1 with a slope proportional to the amplitude of the pulse.

[0215] In practice, circuit 214 of the figure 11 is a low-pass filter with a cutoff frequency f0 that behaves like a pure integrator for frequencies higher than f0. The frequency f0 depends in particular on the value of the capacitance C. Thus, it will always be possible to choose the frequency f0 sufficiently low compared to the frequency of the signal clk so that the circuit 214 behaves, in converter 1, like a pure integrator.

[0216] Note that if the inverting input - of amplifier 1100 is left in high impedance state, no current flows in capacitor C and, as leakage currents are low, the amplifier output memorizes its state, that is to say it remains constant and equal to the value it had at the moment the inverting input - was switched to high impedance state.

[0217] There figure 12 illustrates an example of the implementation of yet another part of converter 1 from the previous figures. More specifically, the figure 11 illustrates an example of the implementation of the INTP circuit.

[0218] The INTP circuit differs from circuit 214 in that the output of amplifier 1100 provides the CR signal and in that a switch 1200 is connected in parallel with capacitor C. Switch 1200, when in the conducting state, is configured to reset to the non-inverting input +, preferably the ref level, as illustrated in figure 12 , the output of amplifier 1100. Switch 1200 is, for example, controlled by the CMD2 signal and is then configured to be conducting at each CMD2 pulse.

[0219] In this example, as in figure 10 The INTP circuit receives the pulses to be integrated on the inverting input of amplifier 1100. As a result, a positive pulse, respectively negative, causes a decrease, respectively an increase, of the CR signal with a slope proportional to the amplitude of the pulse.

[0220] The implementation of circuits 214, 912, and INTP is not limited to the examples described in relation to the figures 11 et 12 and a person skilled in the art will be able to use conventional integrators to implement the INT, INT2, and INTP circuits. In particular, a person skilled in the art is able to design integrators whose output signal increases, respectively, decreases when they receive a positive, respectively, pulse to be integrated, as described by way of example in relation to the figures 3 , 6 And 8 .

[0221] There figure 13 illustrates an example of the implementation of yet another part of converter 1 from the previous figures. More specifically, the figure 13 This illustrates an example of circuit implementation 218, with the understanding that circuit 910 can be implemented in the same way. In this example, the low supply level of converter 1, and therefore of comparator 218, is ground (GND), and the reference level is equal to Vdd / 2.

[0222] In this example, circuit 218 includes a classic 1300 differential amplifier (shown in dotted lines). figure 13 ) having an inverting input in1, an inverting input in2, and an N output.

[0223] In this example, circuit 218 further includes, connected to the N-channel output of amplifier 1300, a stage 1302 comprising an inverter 1304 and two transistors 1306 and 1308, respectively P-channel and N-channel. Inverter 1304 has an input connected to the N-channel output of stage 1300 and an output providing the output signal comp1 of circuit 218. Transistor 1306 is connected between the N-channel node and the Vdd potential, while transistor 1308 is connected between the N-channel node and the low supply potential, here ground (GND). Transistors 1306 and 1308 are controlled by the output of inverter 1304, that is, by the output of circuit 218.

[0224] Transistors 1306 and 1308 implement positive feedback from the output of inverter 1304 to the N output of stage 1300, which speeds up the switching of the comp1 signal. This results in a comp1 signal with clearly distinct high and low levels, even when the value of input in1 is close to that of input in2.

[0225] Of course, the implementation of circuits 218 and 910 is not limited to the example illustrated in figure 13 and a person skilled in the art can use other common threshold comparators to implement circuits C3 and C6. In particular, the implementation of threshold comparators is not limited to the case where ref is equal to half the comparator supply voltage.

[0226] There figure 14 illustrates a detailed example of the implementation of converter 1 described in relation to the figure 9 In this example, the STAGE1 stage corresponds to converter 1 described in relation to the figure 5 That is to say, signal S1 corresponds to signal clkref and signal S2 corresponds to signal clk. In this example, K2=K3=1.

[0227] In this example, the low supply potential of converter 1 is ground GND, and the ref level is equal to Vdd / 2. However, a person skilled in the art can adapt the following description to the case where the low supply potential is a potential Vss equal to -Vdd and the ref level is ground GND, and, more generally, to the case where the ref level is different from half the supply voltage of converter 1.

[0228] In this example, circuit C1, as in figure 5 This includes the RS-type flip-flop 200 configured to provide the CMD1 signal. Furthermore, in this example, circuit 202 of circuit C1 includes a switch IT1 in series with a resistor R1, between the high supply potential Vdd and node 216, with switch IT1 preferably connected to the Vdd potential. Switch IT1 is controlled by the CMD1 signal so that it is only conducting during CMD1 pulses. Thus, each CMD1 pulse results in a positive current pulse P1 at node 216, at level +A1. The amplitude A1 of the P1 pulses is the difference between the Vdd and ref potentials divided by the value of resistor R1.

[0229] In this example, circuit C2 is implemented in the manner described in relation to the figure 5 Furthermore, the circuit 212 of circuit C2 includes, in this example, a switch IT2 in series with a resistor R2, between the low supply potential, here ground (GND), and node 216, with switch IT2 preferably connected to the low supply potential (GND). Switch IT2 is controlled by the signal CMD2 so that it is only conducting during CMD2 pulses. Thus, each CMD2 pulse results in a negative current pulse P2 at node 216, at level -A2. The amplitude of the P2 pulses is determined by the difference between the ref and GND potentials divided by the value of resistor R2. In this example, where the amplitude A1 of the P1 pulses is equal to twice the amplitude A2 of the P2 pulses, resistor R2 has a value twice that of resistor R1.

[0230] In this example, the INT circuit is implemented in the manner described in relation to the figure 11 and therefore includes an amplifier 1100 and a capacitor C. The inverting input - of amplifier 1100 of circuit INT is connected to node 216, the non-inverting input + of amplifier 1100 of circuit INT being connected to the ref potential. Thus, in this example, the signal RES1 increases, respectively decreases, when amplifier 1100 of circuit INT receives a negative, respectively positive, pulse on its input -.

[0231] In this example, the C3 circuit is implemented in the manner described in relation to the figure 5 As an example, circuit 218 is implemented as described in relation to the figure 13 and receives the ref level on its inverting input (in1 in figure 13 and - in figure 14 ) and the RES1 signal on its non-inverting input (in2 in figure 13 and more in figure 14 Thus, in this example, the comp1 signal is at a high level, respectively low, when the RES1 signal is above, respectively below, the ref level, and the OUT1 bit is updated with the level of the comp1 signal at the start of each CMD3 pulse. It follows that, compared to the operation described in relation to the timing diagrams of the figures 3 , 6 And 8 , the direction of variation of the RES1 signal as a function of the polarity of the pulses received by the INT circuit is reversed, which causes an inversion of the OUT1 bit.

[0232] In this example, circuit C4 (or 222 or block - A3 / +A3) includes a switch IT3 and a resistor R3 in series between the output of circuit C3 and node 216. Switch IT3 is controlled by the signal CMD3 so that it is only conducting during CMD3 pulses. Thus, each CMD3 pulse results in a pulse P3 at node 216, which has a negative level (-A3) or a positive level (+A3) depending on whether the output of circuit C3 (bit OUT1) is respectively at a low level equal to the low supply potential or a high level equal to the high supply potential. In this example, because the variations of signal RES1 with respect to the pulse polarity are reversed, and therefore the state of bit OUT1 is reversed, compared to the operation described in relation to the figures 3 , 6 And 8 , the polarity of the P3 pulses relative to the high or low state of the OUT1 signal is also reversed compared to what has been described in relation to the figures 3 ,6 And 8 Furthermore, the amplitude A3 of the P3 pulses is determined by half the difference between the potentials Vdd and GND divided by the value of the resistance R3. In this example, where the amplitude A1 of the P1 pulses is equal to twice the amplitude A3 of the P3 pulses, the resistance R3 has a value twice that of the resistance R1.

[0233] In this example, the C5 circuit is implemented as described in relation to the figure 9 that is to say by the 900 rocker.

[0234] In this example, the C6 circuit is implemented as described in relation to the figure 9 The 910 circuit, for example, is implemented by a comparator as described in relation to the figure 13 having its inverting input (-in figure 14 , in1 in figure 13 receiving the ref level, its non-inverting input (+ in figure 14 , in2 in figure 13 ) receiving the RES2 output signal from the INT2 circuit, and its output providing the comp2 signal.

[0235] In this example, circuit C7 is implemented as described in relation to the figure 9 .

[0236] In this example, the INTP circuit is implemented as described in relation to the figure 12 The inverting input - of amplifier 1100 of the INTP circuit receives the ref potential and the non-inverting input + of this amplifier 1100 receives the P4 pulses. The switch 1200 of the INTP circuit is, for example, controlled by the CMD2 signal, so as to be conducting during each CMD2 pulse.

[0237] In this example, the INT2 circuit is implemented as described in relation to the figure 9 More specifically, circuit 908 is implemented as described in relation to the figure 11 The circuit consists of an operational amplifier 1100 and a capacitor C. The inverting input of amplifier 1100 receives the ref signal, the non-inverting input of amplifier 1100 receives the S signal, and the output of amplifier 1100 provides the RES2 signal. Furthermore, circuit 906, in this example, consists of two resistors R5 and R6 of equal value, each connected between a respective input of circuit 906 and the inverting input of amplifier 1100 in circuit 908. The S signal is available at the inverting input of amplifier 1100. Circuit 902, in this example, consists of a switch IT5 connected between the output of circuit INT and an input of circuit 906. Switch IT5 is controlled by CMD4 pulses, so that it is only conducting during CMD4 pulses. Thus, the RES1 signal is only provided as input to the 906 circuit during each CMD4 pulse.Similarly, in this example, circuit 904 corresponds to a switch IT6 connected between the output of circuit C7 and another input of circuit 906. Switch IT6 is controlled by the CMD4 pulses so that it is only conducting during CMD4 pulses. Thus, the CR signal is only supplied to the input of circuit 906 during each CMD4 pulse. Consequently, the S signal, corresponding to the sum of the CR and RES1 signals, is only supplied to the input of circuit 908—that is, to the inverting input of amplifier 1100 in circuit 908—during each CMD4 pulse.

[0238] In this example, the 915 circuit, or +A4 / -A4 block, includes an IT4 switch, a 1402 inverter, and a resistor R4 in series between the output of the C6 circuit and the INTP circuit. The IT4 switch is controlled by the CMD3 signal so that it is only conducting during CMD3 pulses. Thus, each CMD3 pulse results in a P4 pulse supplied to the INTP circuit, which has a negative level of -A4 when the OUT2 bit is high and a positive level of +A4 when the OUT2 bit is low. The amplitude A4 of the P4 pulses is determined by half the difference between the potentials Vdd and GND divided by the value of the resistor R4. In this example, where the amplitude A1 of the P1 pulses is equal to twice the amplitude A4 of the P4 pulses, the resistor R4 has a value twice that of the resistor R1.

[0239] In this example, the RES2 signal increases, respectively decreases, when the 908 circuit receives a negative, respectively positive, S pulse; the comp2 signal is in a binary high state, respectively low, when the RES2 signal is above, respectively below, the ref level; the OUT2 signal is updated with the state of the comp2 signal at the end of each CMD4 pulse; and the CR signal increases, respectively decreases, when the P4 pulse received by the INTP circuit is negative, respectively positive. Thus, a person skilled in the art understands that, to implement negative feedback in the STAGE2 stage (not referenced in figure 14 ) according to the example of the figure 14 The P4 pulses must be negative when the OUT2 bit is in a high binary state, and positive when the OUT2 bit is in a low binary state. A person skilled in the art is able to modify the polarity of the P4 pulses relative to the binary state of the OUT2 bit in cases where, compared to the example of the figure 14 , the RES2 signal increases, respectively decreases, when the S pulses are positive, respectively negative, and / or the comp2 signal is in the binary high state, respectively low, when the RES2 signal is below, respectively above, the ref level, and / or the OUT2 bit is updated with the complementary binary state of the comp2 signal at each end of the CMD4 pulse, and / or the CR signal increases, respectively decreases, when the P4 pulses are positive, respectively negative.

[0240] In this example, the DER circuit and the 984 circuit described in relation to the figure 9 are partly confused, or, put another way, the output of the STAGE2 stage of converter 1 of the figure 14 corresponds to the two bits OUT2 and OUT2-1. More precisely, the 922 circuit of the DER circuit and the 984 circuit are implemented by a 9224 circuit configured to receive the OUT, OUT2, and OUT2-1 signals and to provide the TDCOUT signal, in this example encoded in two's complement using three bits: TDCOUT0, TDCOUT1, and TDCOUT2. The 9224 circuit is a digital logic circuit, implemented from combinational logic gates, for example, from XOR gates and / or inverter gates and / or AND gates and / or OR gates, etc. figure 14 , the 9224 circuit is represented in the form of a block, its implementation being within the reach of a person in the trade.

[0241] In the detailed implementation example illustrated by the figure 14 For example, the 9224 circuit is configured to provide the TDCOUT0, TDCOUT1, and TDCOUT2 bits from the OUT1, OUT2, and OUT2-1 bits, as shown in Table 1 below. In this example, the binary state '1', or '0', of a bit corresponds to a high or low level, respectively, of that bit, and the TDCOUT2 bit represents the sign of the TDCOUT signal that corresponds to the concatenation of the TDCOUT2, TDCOUT1, and TDCOUT0 bits. [Table 1] OUT1 OUT2 OUT2-1 TDCOUT2 TDCOUT1 TDCOUT0 TDCOUT value '1' '0' '0' '0' '0' '0' 0 '0' '0' '0' '0' '0' '1' 1 '1' '1' '0' '0' '0' '1' 1 '0' '1' '0' '0' '1' '0' 2 '1' '0' '1' '1' '1' '1' -1 '0' '0' '1' '0' '0' '0' 0 '1' '1' '1' '0' '0' '0' 0 '0' '1' '1' '0' '0' '1' 1

[0242] As with the second-order converter described in relation to the figure 9 based on the descriptions made in relation to the figures 1 to 9 The person in the trade will be able to adapt the description made in relation to the figure 14 in cases where: the duration Dmax of the pulses P1 is different from one period Tclk of the signal clk and is, for example, equal to two periods Tclk of the signal clk, and / or converter 1 is not implemented in a phase-locked loop in all digital, and / or converter 1 is of order higher than 2.

[0243] Various embodiments and variations have been described. A person skilled in the art will understand that some features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0244] In particular, a person skilled in the art is able to adapt the description given above in the case where all the polarities of the pulses are reversed. More generally, a person skilled in the art is able to reverse the high and low states of any of the binary signals and / or any of the pulses CMD1, CMD2, CMD3 and CMD4 and / or the signs of the pulses P1, P2, P3 and P4 by adapting the circuits that receive or supply these signals so that the functionalities implemented by these circuits remain those described in this application.

[0245] In addition, the person skilled in the art will be able to foresee other example values ​​for the numbers K1, K2, K3 and K4 by adapting the amplitudes A1, A2, A3 and A4 according to the dynamics of converter 1.

[0246] A person skilled in the art will also be able to foresee other examples of implementing the circuits described above. For example, circuits C3 and C6 could each be implemented solely by a D flip-flop whose output Q is set to a first binary state, respectively a second binary state, if its input D is below, respectively above, the ref level when its input C receives an edge to which this input C is sensitive, the flip-flop then simultaneously implementing binary quantization and storing this quantization.

[0247] Finally, the practical implementation of the described methods and variants is within the reach of the person in the trade, based on the functional indications given above.

Claims

1. Time-to-digital converter of sigma-delta type comprising: a first circuit (C1) configured to supply, at each active edge of a first signal (S1), a first pulse (P1) of duration determined by an interval between said active edge of the first signal (S1) and an immediately successive active edge of a second signal (S2); an integrator circuit (INT) configured, at each first pulse (P1), to integrate: - the first pulse (P1), - a second pulse (P2) starting after the first pulse (P1) and in synchronism with a clock signal (clk), and - a third pulse (P3) starting after the second pulse (P2) and in synchronism with the clock signal (clk); a second circuit (C2) configured to generate, for each first pulse (P1), the corresponding second pulse (P2); a third circuit (C3) configured to quantize over one bit (comp1) an output signal (RES1) of the integrator circuit (INT) and, at the beginning of each third pulse, store over a first bit (OUT1) said binary quantization; and a fourth circuit (C4) configured to generate, for each first pulse (P1), the third corresponding pulse (P3) based on the first bit (OUT1), wherein the second circuit (C2) is configured to receive the clock signal (clk) and to generate at least one third signal (CMD3) configured to control the storages by the third circuit (C3) and the generations of the third pulses (P3) by the fourth circuit (C4), and wherein the first circuit (C1) is configured to supply a fourth signal (CMD1) indicating a beginning and an end of each first pulse (P1), the second circuit (C2) being configured to receive the fourth signal (CMD1) and to generate the third signal (CMD3) based on the clock signal (clk) and based on the fourth signal (CMD1).

2. Converter according to claim 1, wherein: the first (C1) and second (C2) circuits are configured so that the second pulses (P2) place a conversion zero of the converter (1) in the middle of the dynamic range of the converter (1) ; and the fourth circuit (C4) is configured so that the integration of each third pulse (P3) implements a subtraction of the binary quantization (OUT1) stored at the beginning of said third pulse (P3).

3. Converter according to claim 1 or 2, wherein: the first (C1) and second (C2) circuits are configured so that each second pulse (P2) causes, on the output signal (RES1) of the integrator circuit (INT), a variation of identical amplitude and of a sign opposite to an amplitude variation that would be caused by a first pulse (P1) of duration determined by half the dynamic range of the converter (1); and the fourth circuit (P4) is configured so that each third pulses (P3) implements a negative sigma-delta feedback.

4. Converter according to any of claims 1 to 3, wherein: the first, second, and third pulses (P1, P2, P3) are signed; the first and second circuits (C1, C2) are configured so that a sign of the second pulses (P2) is opposite to a sign of the first pulses (P1) and that a maximum duration of the first pulses that the converter (1) can convert multiplied by an amplitude of the first pulses (P1) is equal to twice a duration of the second pulses (P2) multiplied by an amplitude of the second pulses (P2); and the fourth circuit is configured so that a sign of each third pulse (P3) is determined by a state of the first bit (OUT) and that an amplitude of the third pulses (P3) multiplied by a duration of the third pulses is equal to the duration of the second pulses (P2) multiplied by the amplitude of the second pulses (P2).

5. Converter according to any of claims 1 to 4, wherein the second and third pulses (P2, P3) each have a duration which is a multiple of a period of the clock signal (clk), preferably equal to one period of the clock signal (clk).

6. Converter according to any of claims 1 to 5, wherein an output (TDCOUT) of said converter (1) is at least partly determined by the first bit (OUT1).

7. Converter according to any of claims 1 to 6, wherein the converter (1) is of sigma-delta multi-stage noise shaping type, the converter (1) comprising a first stage (STAGE1) comprising the integrator circuit (INT) and the first, second, third, and fourth circuits (C1, C2, C3, C4), and a second stage (STAGE2) configured to receive an output signal (RES1) of the integrator circuit (INT) of the first stage (STAGE1) and to supply a digital output signal (NUM; OUT2, OUT2-1) of the second stage based on the output signal (RES1) of the integrator circuit (INT) of the first stage, an output (TDCOUT) of said converter (1) being at least partly determined by the first bit (OUT1) and the output digital signal (NUM; OUT2, OUT2-1) of the second stage (STAGE2).

8. Converter according to claim 7, wherein the second stage (STAGE2) is configured to: generate, after each third pulse (P3), a fourth pulse (CMD4) starting in synchronism with the clock signal (clk) ; integrate, during each fourth pulse (CMD4), a sum (S) of the output signal (RES1) of the integrator circuit (INT) of the first stage (STAGE1) and of a feedback signal (CR), quantize over one bit (comp2) a result of said integration and store over a second bit (OUT2) said binary quantization (comp2) at the end of the fourth pulse (CMD4); generate, during each third pulse (P3), a fifth pulse (P4) from based on the second bit (OUT2), and the feedback signal (CR) by integrating said fifth pulse (P4); and store the second bit (OUT2) over a third bit (OUT2-1) at each active edge of the first signal (S1), the digital output signal (NUM; OUT2, OUT2-1) of the second stage (STAGE2) being generated based on the second and third bits or corresponding to the second and third bits.

9. Converter according to claim 7, wherein the second stage (STAGE2) comprises: a fifth circuit (C5) configured to generate, after each third pulse, a fourth pulse (CMD4) starting in synchronism with the clock signal (clk); an integrator circuit (INT2) configured to integrate, during each fourth pulse (CMD4), a sum (S) of the output signal (RES1) of the integrator circuit (INT) of the first stage (STAGE1) and of a feedback signal (CR); a sixth circuit (C6) configured to quantize over one bit (comp2) an output (RES2) of the integrator circuit (INT2) of the second stage (STAGE2) and to store said binary quantization (comp2) over a second bit (OUT2), at the end of each fourth pulse (CMD4); a seventh circuit (C7) configured, at each third pulse (P3), to supply said feedback signal (CR) by integrating, during said third pulse (P3), a fifth pulse (P4) determined based on the second bit (OUT2); and a circuit configured to store the second bit (OUT2) over a third bit (OUT2-1) at each active edge of the first signal (S1), the digital output signal (NUM; OUT2, OUT2-1) of the second stage (STAGE2) being generated based on the second and third bits or corresponding to the second and third bits.

10. Converter according to any of claims 1 to 9, wherein the converter (1) comprises a first input configured to receive the first signal (S1) and a second input configured to receive the clock signal (clk), and wherein: the second signal (S2) and the clock signal (clk) are one and the same, or the converter (1) comprises a circuit (700) for dividing the frequency, preferably by two, configured to receive the clock signal (clk) and to supply the second signal (S2).

11. All digital phase locked loop (4) configured to receive a signal (clkref) at a first frequency and to supply a signal (clk) at a second frequency equal to N / D times the first frequency, N and D being two positive values, the phase-locked loop (4) comprising a converter (1) according to claim 10, the first input of the converter being configured to receive the signal (clkref) at the first frequency and the second input of the converter being configured to receive the signal (clk) at the second frequency.

12. Phase-locked loop (4) according to claim 11 comprising a circuit (accN) configured to supply a first digital signal (accNOUT) incremented by value N at the first frequency; a circuit (accD, reg) configured to supply a second digital signal (accDOUT) incremented by value D at the second frequency and a third digital signal (accDOUT') corresponding to a storage of the second digital signal (accDOUT) clocked at the first frequency; a digital filter (402) configured to receive a subtraction of an output (TDCOUT) of the converter (1) and of the third digital signal (accDOUT') to the first digital signal (accNOUT) and to control an oscillator (404) configured to supply the signal (clk) at the second frequency, wherein the second signal (S2) of the converter (1) is on and the same with the signal (clk) at the second frequency.

13. Phase-locked loop according to claim 11 comprising either a circuit (accN) configured to supply a first digital signal (accNOUT) incremented by value N at the first frequency, and a circuit configured to supply a second digital signal incremented by value D / 2 at the second frequency, D being even, or a circuit configured to supply a first digital signal incremented by value 2N at the first frequency and a circuit (accD) configured to supply a second digital signal (accDOUT) incremented by value D at the second frequency; a circuit (reg) configured to supply a third digital signal (accDOUT') corresponding to a storage of the second digital signal (accDOUT) clocked by the second signal (S2) of the converter; a digital filter (402) configured to receive a subtraction of an output (TDCOUT) of the converter (1) and of the third digital signal (accDOUT') to the first digital signal (accNOUT) and to control an oscillator (404) configured to supply the signal (clk) at the second frequency, wherein the second signal (S2) of the converter (1) is obtained by dividing by two the frequency of the signal (clk) at the second frequency.