Microelectronic arrangement with two field effect transmitters with a common electrode

Description

TECHNICAL FIELD

[0001] The present invention relates to the field of microelectronics and more particularly to advanced CMOS (Complementary Metal Oxide Semiconductor) technologies. It may also find advantageous applications in the field of machine learning. STATE OF THE ART

[0002] Different types of transistors are currently used in electronic circuits to perform many functions (logic circuits, amplification, signal modulation, etc.).

[0003] One of the most widely used structures today is the FDSOI transistor (from the English "Fully Depleted Silicon On Insulator"), represented in Figure 10This technology involves placing a thin insulating layer beneath the semiconductor layer, such as silicon, to create a barrier that prevents current leakage. FDSOI transistors are preferred in low-power applications. Examples of this type of structure are provided by US 2014 / 167167 A1. Other known devices are disclosed in documents WO 2021 / 050194 A1 and US 2011 / 187412 A1.

[0004] Z2< FET transistors are notably used for memory applications. They consist of a forward-biased PIN diode whose intrinsic channel is only partially covered by a front gate.

[0005] One objective of the present invention is to offer an alternative to existing devices while providing at least equivalent performance and / or enabling the performance of functions for which all current devices cannot be used. SUMMARY

[0006] To achieve this objective, the first aspect concerns a microelectronic device comprising: a first field-effect transistor comprising a first drain, a first source, a first gate and a first gate dielectric, a first doped region, constituting one of the first drain and the first source, a second doped region, constituting the other of the first drain and the first source,

[0007] The system also includes: a second field-effect transistor comprising a second drain, a second source, a second gate and a second gate dielectric, a third doped region, constituting the second source if the first doped region constitutes the first drain, or the second drain, if the first doped region constitutes the first source, a fourth doped region, constituting the other of the second drain and the second source, a dielectric layer having a top face in contact with the first doped region, the second doped region, the third doped region and the fourth doped region, a back gate in contact with a bottom face of the dielectric layer,

[0008] It also has the particularity that the second doped zone and the fourth doped zone form a common electrode.

[0009] The object thus defined constitutes a microelectronic device capable of replacing currently used transistors in many applications. This device may also offer new functionalities compared to existing devices. Advantageously, it allows the generation of current-voltage characteristics with a Gaussian shape, usable, for example, in memory or machine learning applications.

[0010] A second object relates to a non-volatile memory storage unit comprising a device as defined previously.

[0011] A third object relates to a method of controlling the device or storage unit in which the first control voltage V 110 is applied to the first doped zone and the second control voltage V 210 is applied to the first doped zone, and in which: The first control voltage V 110 constitutes a source voltage VS of the device and the second control voltage V 210 constitutes a drain voltage VD of the device, or The second control voltage V 210 constitutes the source voltage VS of the device and the first control voltage V 110 constitutes the drain voltage VD of the device. BRIEF DESCRIPTION OF THE FIGURES

[0012] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which: THE Figures 1A to 1F Each represents a device according to an embodiment of the invention. Figures 2A , 2C , 3A , 3C , 4A , 4C , 5A And 5Crepresent current-voltage characteristics of the device according to one of the embodiments of the invention obtained by simulation. The curves of Figures 2A , 2C 3A And 3C are represented on a linear scale; therefore, the scale to consider is the scale shown to the right of each of these graphs. Figures 2B , 2D , 3B , 3D , 4B , 4D , 5B And 5D are tables summarizing the parameters applied during the simulations of Figures 2A , 2C , 3A , 3C , 4A , 4C , 5A And 5C . There figure 6 illustrates the characteristic curve of polarization as a function of the applied field of a ferroelectric material in its ferroelectric phase. figures 7A , 7C , 7E And 7Grepresent current-voltage characteristics of the device according to one of the embodiments of the invention obtained by simulation. The curves of figures 7A And 7C are represented on a logarithmic scale, so the scale to consider is the one shown on the left of each of these graphs. The curves of figures 7E And 7G are represented on a linear scale; therefore, the scale to consider is the scale shown on the right of each of these graphs. Figures 7B , 7D , 7F And 7H are tables summarizing the parameters applied during the simulations of figures 7A , 7C , 7E And 7G . THE Figures 8A and 8B illustrate an application that can be made of the device according to one of the embodiments of the invention. figure 9 represents the Gaussian mixture obtained by linear combination of several Gaussian components. Figure 10represents an FDSOI transistor as known from the prior art.

[0013] The drawings are provided as examples and are not intended to limit the scope of the invention. They are schematic representations of the principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality. DETAILED DESCRIPTION

[0014] Before beginning a detailed review of embodiments of the invention, optional features which may possibly be used in combination or alternatively are stated below: According to one embodiment, the second doped zone and the fourth doped zone are electrically connected by an electrically conductive layer, preferably metallic.

[0015] In one example, the electrically conductive layer is based on metallic silicide.

[0016] In one example, the electrically conductive layer directly covers at least part of an upper face of the second doped zone and at least part of an upper face of the fourth doped zone.

[0017] In one example, the electrically conductive layer directly covers part of the top face of the dielectric layer and separates the second doped zone from the fourth doped zone.

[0018] According to one example, the second doped zone and the fourth doped zone exhibit distinct dopings among an N-type doping and a P-type doping.

[0019] According to one embodiment, the device comprises a first electrode and a second electrode, the first doped area is in contact with the first electrode which is configured to receive a first control voltage V 110 and the third doped area is in contact with the second electrode which is configured to receive a second control voltage V 210.

[0020] For example: The first control voltage V110 constitutes a source voltage VS of the device and the second control voltage V210 constitutes a drain voltage VD of the device, or The second control voltage V210 constitutes a source voltage VS of the device and the first control voltage V110 constitutes a drain voltage VD of the device.

[0021] According to one embodiment, the device comprises a first grid electrode and a second grid electrode, the first grid is in contact with the first grid electrode which is configured to receive the application of a first grid voltage V G1 and the second grid is in contact with the second grid electrode which is configured to receive the application of a second grid voltage V G2.

[0022] According to one embodiment, the device includes a back grid electrode and the back grid is in contact with the back grid electrode which is configured to receive the application of a back grid voltage VBG.

[0023] According to one embodiment, the device further includes a control circuit configured to apply: the first control voltage V 110 on the first electrode, the second control voltage V 210 on the second electrode, the first grid voltage V G1 on the first electrode, the second grid voltage V G2 on the second electrode, the rear grid voltage V BG on the rear grid electrode, the first control voltage V 110 the second control voltage V 210 , the first grid voltage V c1 , the second grid voltage V G2 and the rear grid voltage V BG which can take different values ​​and at least values ​​between -5 and 5 V.

[0024] According to an example, V G2 = ± V G1 + ΔV G , and with ΔV G between -5 and +5 V.

[0025] According to an example, V G2 = V G1.

[0026] According to an example, V G2 = -V G1 .

[0027] According to one example, the first transistor and the second transistor are separated by a distance L greater than 50 nm, and / or less than 500 nm.

[0028] According to one embodiment, the second doped zone and the fourth doped zone have doping of the same type among type N doping and type P doping, and the first doped zone and the third doped zone have doping of the other type.

[0029] According to one example, the dielectric layer has a thickness e 300 between its lower face and its upper face less than or equal to 25 nm, preferably less than 5 nm.

[0030] According to one embodiment, the first grid dielectric and the second grid dielectric are based on a ferroelectric material.

[0031] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0032] A layer can also be composed of several sub-layers of the same material or of different materials.

[0033] A substrate, layer, or device "based" on a material M is defined as a substrate, layer, or device comprising only that material M, or that material M and possibly other materials, such as alloying elements, impurities, or dopants. Thus, a material based on a IV-IV (or III-N) material may comprise a IV-IV (or III-N, respectively) material with added dopants. Similarly, a GaN-based layer typically comprises GaN and AlGaN or InGaN alloys.

[0034] The term "III-V material" refers to a semiconductor composed of one or more elements from columns III and V of Mendeleev's periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus.

[0035] In the context of this invention, an "electrically conductive" material is understood to mean a material having an electrical conductivity level greater than 0.5×10 6< S / m (1 Siemens = 1 S = 1 m -2< .kg -1< .s 3< .A 2< ).

[0036] A coordinate system, preferably orthonormal, comprising the x, y, z axes is represented in Figure 1A This reference point can be applied by extension to other figures.

[0037] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Thickness is measured along a direction normal to the principal plane of extension of the layer, and height is measured perpendicular to the XY base plane. Thus, a layer typically has a thickness along the z-axis when it extends primarily along an XY plane, and a projecting element, for example, an insulation trench, has a height along the z-axis. The relative terms "on," "under," and "below" preferentially refer to positions measured along the z-direction.

[0038] The device, according to different embodiments of the invention, will now be described with reference to Figures 1A to 1F .

[0039] THE Figures 1A and 1B are derived from numerical simulations. They constitute maps of doping within device 1. The figures 1C to 1FThese are schematic representations of device 1. It should be noted that on the figures 1C to 1F N-doped areas are illustrated by a pattern in the shape of a cross and P-doped areas by a pattern in the shape of a dash.

[0040] Device 1 includes a first field-effect transistor 100 and a second field-effect transistor 200. Preferably, it does not include any other transistors or at least no other transistors whose doped region forms a common electrode with a doped region of either of the first two transistors.

[0041] The first transistor 100 includes a first drain, a first source, a first gate 101 and a first gate dielectric 102. As will be detailed later, it can be an n-MOS transistor, a p-MOS transistor or a TFET transistor (from the English "Tunnel Field-Effect Transistor", which can be translated as "tunnel effect transistor").

[0042] The first grid dielectric 102 extends beneath the first grid 101. The first doped region 110 and the second doped region 120 are each in contact with a first channel 103, called a conduction channel but which can also be a carrier-free zone, separating them. This first channel 103 is in contact with the underside of the first grid dielectric 102.

[0043] The first transistor 100 also typically includes spacers 104 that isolate the first gate 101 from the first drain on one side and from the first source on the other. These spacers 104 typically cover the lateral sides of the first gate 101. Among other things, they are intended to limit parasitic capacitive coupling between the first gate 101 and the first source on the one hand, and the first drain on the other.

[0044] The second transistor 200 comprises a second drain, a second source, a second gate 201, a second gate dielectric 202, and a second channel 203, also called a conduction channel but which can also be a carrier-free region. The characteristics of the first transistor 100 can be transposed mutatis mutandis to the second transistor 200.

[0045] The first transistor 100 and the second transistor 200 are separated by a distance L measured in the XY plane and defined as the distance between a side 106 of the first transistor 100 and a side 206 of the second transistor 200 facing it. The sides 106 and 206 of transistors 100 and 200 typically correspond to the sides of spacers 104 and 204. Due to technological limitations during device fabrication, the distance L is preferably greater than 50 nm. To optimize the density of devices that can be integrated onto a chip, it is preferably less than 500 nm.

[0046] The first 110-doped zone and the second 120-doped zone can respectively constitute the first drain and the first source, or vice versa.

[0047] Similarly, the device includes a third 210-doped zone and a fourth 220-doped zone that can respectively constitute the second drain and the second source, or vice versa.

[0048] The second doped zone 120 and the fourth doped zone 220 form a common electrode 1000.

[0049] If these two areas have the same type of doping, either N-type doping or P-type doping, the mere fact that they are in contact allows the creation of the common electrode 1000.

[0050] If, on the other hand, the second doped zone 120 and the fourth doped zone 220 have different types of doping, they are short-circuited to form the common electrode 1000. Typically, to achieve this short circuit, an electrically conductive layer 500, preferably metallic, is provided in contact with both the second doped zone 120 and the fourth doped zone 220. This electrically conductive layer 500, also called the metallic layer 500, is a continuous layer ensuring the electrical connection between these two zones 120 and 220. It is advantageously based on a silicide, that is, a material composed of silicon and one or more metallic elements. For example, it can be based on NiPtSi or NiSi. It advantageously exhibits an electrical resistivity level of less than 150 µΩ.cm and typically greater than 5 µΩ.cm.

[0051] The term "layer" is used here in a broad sense. It can refer to a deposit extending mainly along the XY plane, or to an element with small dimensions in this plane.

[0052] According to an embodiment illustrated in the figure 1D The metallic layer 500 can separate the second and fourth doped zones 120 and 220 in the XY plane. According to another advantageous embodiment illustrated in Figures 1A and 1BThe second and fourth doped zones 120, 220 are in contact, and the metal layer 500 directly covers at least part of each of their upper surfaces 121, 221. Preferably, in this embodiment, the metal layer 500 extends in the XY plane from a flank 106 of the first transistor 100 to a flank 206 of the second transistor 200. Advantageously, the metal layer 500 covers the entirety of the upper faces 121, 221 of the doped zones 120, 220. It is also possible for the layer 500 to separate the second and fourth doped zones while also covering them. It is also possible, as illustrated in the figure 1C, that the second doped zone 120 and the fourth doped zone 220 are separated in the XY plane by an insulating element 600 and electrically connected via the metallic layer 500 covering this time both the upper surfaces 121, 221 of the second and fourth doped zones 120, 220 and the upper face 601 of the insulating element 600.

[0053] If the electrically conductive layer 500 is not necessary in the case where the second doped zone 120 and the fourth doped zone 220 have the same type of doping (case illustrated in Figures 1E and 1F ), however, it is conceivable that she is present.

[0054] The doped regions 110, 120, 210, and 220 are preferably all located within an active layer 10. The same is preferably true for the first channel 103 and the second channel 203. Thus, preferably, the doped regions 110, 120, 210, and 220, and the channels 103 and 203, are all based on the same material: that of the active layer 10. The active layer 10 is preferably based on at least one IV-IV material. For example, this material is silicon-based. The active layer 10 can also be based on at least one III-V material, preferably at least one III-N material. For example, this material is GaN-based. The active layer 10 can also be formed by transition metal dichalcogenide monolayers (commonly referred to by the English acronym TMD, "Transition-Metal Dichalcogenide monolayers"), for example of the MoS2 or WS2 type. It can be a homogeneous layer, typically formed of a single material.The active layer 10 typically has a top face 11 and a bottom face 12, both extending mainly in the XY plane of the orthogonal XYZ coordinate system. It has a thickness e10 along the z-direction. If the active layer 10 is silicon-based, the thickness e10 typically ranges from 5 nm to 50 nm. If, on the other hand, it is made of two-dimensional materials such as TMD monolayers, the active layer 10 can have a thickness e10 as small as a few nanometers.

[0055] Some components of transistors 100, 200 may have been at least partially formed from a continuous layer called the fabrication layer. For example, some regions of the fabrication layer may have been transformed to form the gate dielectrics 103, 203 and / or the spacers 104, 204. The fabrication layer may also have been etched, and then various deposits may have been made on this fabrication layer to form the gate dielectrics 103, 203, spacers 104, 204 and / or gates 101, 201. The untransformed or unetched regions of the fabrication layer then form part of the active layer 10. The active layer 10 may also include areas that have been epitaxially grown from the fabrication layer.

[0056] Device 1 further comprises a dielectric layer 300 having an upper face 301 and a lower face 302, both extending primarily in planes parallel to the XY plane of the orthogonal coordinate system. The upper face 301 of the dielectric layer 300 is in contact with the first doped zone 110, the second doped zone 120, the third doped zone 210, and the fourth doped zone 220. The dielectric layer 300 thus constitutes a common buried dielectric for the two transistors 100 and 200, and therefore, in general, a buried dielectric for Device 1. It has a thickness e 300 along the z-direction.

[0057] The device 1 further includes a rear grid 400 in contact with the lower face 302 of the dielectric layer 300.

[0058] Device 1 may include the following electrodes or contact points: a first electrode 115 in contact with the first doped zone 110, a second electrode 215 in contact with the third doped zone 210, a first grid electrode 105 in contact with the first grid 101, a second grid electrode 205 in contact with the second grid 201, a rear grid electrode 405 in contact with the rear grid 400, Each of these electrodes is configured to receive the application of a voltage. These electrodes are typically metallic layers deposited in contact with each of the doped zones 110, 210 and grids 101, 201, 400.

[0059] More specifically, it is anticipated that the following may be applied: a first control voltage V 110 on the first electrode 115, a second control voltage V 210 on the second electrode 215, a first grid voltage V G1 on the first electrode 105, a second grid voltage V G2 on the second electrode 205, a rear grid voltage V BG on the rear grid electrode 405.

[0060] Preferably, all electrodes 115, 215, 105, 205, and 405 are accessible—that is, voltages can be applied to them—from the same face, referred to as the front face of the device 1. To this end, the rear grid 400 advantageously protrudes from the dielectric layer 300 to allow contact to be re-established between the rear grid 400 and the front face of the device 1. The dielectric layer 300 may also have an additional thickness at this point of re-establishment. This additional thickness typically corresponds to the sum of the thickness e 300 of the dielectric layer 300 and the thickness e 10 of the active layer 10. The rear grid electrode 405 is then level along the z-direction with the first electrode 115 and the second electrode 215. This facilitates their simultaneous fabrication.It is therefore advantageous to provide for the presence of at least one shallow isolation trench (commonly designated STI, English acronym for "Shallow Trench Isolation") to electrically isolate the rear grid 400 from the active layer 10.

[0061] Thus, the behavior of device 1 can be controlled at five control points. FDSOI transistors, commonly used in the microelectronics industry, which have a single gate on the front panel, can only be controlled at four control points (drain, source, front gate, rear gate, visible on the Figure 10 Thanks to this additional control point, it is possible to more precisely control the electrical behavior of device 1 compared to a conventional FDSOI transistor. This also gives device 1 additional functionality and allows it to be used for other applications, as will be detailed later.

[0062] The first control voltage V110 and the second control voltage V210 constitute, for device 1, respectively a drain voltage VD and a source voltage VS, or vice versa. More precisely: If the first doped zone 110 constitutes the first source and the third doped zone 210 the second drain, then the first control voltage V110 constitutes the source voltage VS of device 1 and the second control voltage V210 constitutes the drain voltage VD of device 1. This scenario is considered in the Figure 1A If the first doped region 110 constitutes the first drain and the third doped region 210 the second source, then the first control voltage V110 constitutes the drain voltage VD of device 1 and the second control voltage V210 constitutes the source voltage VS of device 1. This scenario is considered in the figure 1B .

[0063] Depending on the type of transistors 100, 200 (n-MOS, p-MOS, TFET), and therefore the type of doping of the doped regions 110, 120, 210, and 220, the operation of device 1 is itself similar to the operation of an n-MOS, p-MOS, or TFET transistor. In the example illustrated in the Figure 1A The first transistor 100 is an n-MOS type transistor, the second transistor 200 is a p-MOS type, the source of device 1 is at the first doped area 110, which is here an N-doped area, and the drain at the third doped area 210, here P-doped. In this configuration, device 1 in operation will therefore have an n-TFET type behavior.

[0064] In the example illustrated in the figure 1B , transistors 100, 200 are of the same type as in the embodiment of the Figure 1A, but the applied control voltages V 110 , V 210 are such that the source of device 1 is at the level of the third 210 doped area, here P doped, and the drain is at the level of the first 110 doped area, here N doped. In this configuration, device 1 in operation will have a p-TFET type behavior.

[0065] It should be noted that the source or drain function of zones 110, 120, 210 and 220 depends on the voltages applied to them, and more precisely on the sign of the voltages V 110 - V 120 and V 210 - V 220. Thus, it is possible to switch device 1 from an n-TFET behavior to a p-TFET behavior, and vice versa, simply by changing the sign of these voltage differences.

[0066] There figure 1EThis illustrates a configuration in which transistors 100 and 200 are both TFETs and are arranged so that the common electrode 1000 is formed by the contact of the P-doped regions of each transistor. In this example, the operation of device 1 is similar to that of an n-MOS transistor. Conversely, in the example illustrated in the figure 1F The common electrode 1000 is formed by the contact of the N-doped regions of two TFET-type transistors 100 and 200. The operation of the device is then comparable to that of a p-MOS transistor.

[0067] The rear grid tension plays a major control role in device 1.

[0068] Like a prior art transistor, device 1 can be in a conducting or blocking state. In the conducting state, the assembly consisting of the first channel 103, the common electrode 1000, and the second channel 203 constitutes a conduction channel for device 1. Current can then flow between the source and the drain of device 1. In the blocking state, the first channel 103 and the second channel 203 act as depleted channels for their respective transistors 100 and 200. The assembly consisting of the first channel 103, the common electrode 1000, and the second channel 203 is then devoid of charge carriers. No current flows in device 1.

[0069] All the simulations presented in the figures 2A to 5C And 7A à 9 The following, which will now be described, were carried out for a device 1 with the following characteristics: The first transistor, 100, is an n-MOS transistor. The second transistor, 200, is a p-MOS transistor. The first doped region, 110, constitutes the source of the n-MOS transistor 100, and the third doped region, 210, constitutes the drain of the p-MOS transistor 200 (n-FET-like behavior). The drain-source voltage VDS = VD - VS of device 1 is therefore defined by V210 - V110. It should be noted that simulations of a device 1 exhibiting behavior similar to a p-FET, n-MOS, or p-MOS transistor would yield similar insights into the functions it performs.

[0070] THE Figures 2A And 2C show current-voltage characteristics ID = f(V BG ) of device 1 obtained from an analytical model. During this simulation: The first grid voltage VG1 and the second grid voltage VG2 were set to the same value. The simulation was performed for several values ​​of VG1 = VG2, varying from 0 to -0.5V ( figure 2A ) and from 0 to 0.5V ( figure 2C These different simulations correspond to the different curves on the Figures 2A And 2C The drain-source voltage VDS was set to a value of 0.5V. More precisely, Vs=0V and VD=0.5V were set. The back-gate voltage VBG varies from -1V to 1V. The evolution of the drain-source current IDS flowing in device 1 is recorded as a function of VBG.

[0071] These elements are summarized in the tables presented in figure 2B And 2D .

[0072] These figures illustrate the possibility of generating a Gaussian-type characteristic from device 1. FDSOI transistors commonly used in industry do not allow for this type of curve. In particular, they do not allow for obtaining a negative differential resistance as is the case here. Furthermore, as these figures illustrate, varying the bias of the two gates 101 and 201 allows for adjusting the average value of the Gaussian curve. More precisely, here, decreasing the value of VG1 = VG2 decreases the average value of the curve, and vice versa. The applications of these device properties will be detailed later.

[0073] THE Figures 3A And 3C show current-voltage characteristics ID = f(VBG) obtained from an analytical model of device 1 for other relationships linking VG1 and VG2. During these simulations: the first grid voltage V G1 and the second grid voltage V G2 are related by the following relations: i. Figure 3A : VG2 = VG1 + ΔV with VG1 = 0V. The simulation was performed for several values ​​of ΔV, varying from 0 to 0.25V. These different simulations correspond to the different curves on the figure 3A ii. Figure 3C : V G1 = -V G2. The simulation was performed for several values ​​of V G1 = -V G2, varying from 0 to 0.05V. These different simulations correspond to the different curves on the figure 3C The drain-source voltage VDS was set to a value of 0.5V. More precisely, Vs=0V and VD=0.5V were set. The back-gate voltage VBG varies from -1V to 1V. The evolution of the drain-source current IDS flowing in device 1 is recorded as a function of VBG.

[0074] It is noted that for these other relationships between V G1 and V G2, we also obtain Gaussian type characteristics.

[0075] These figures further illustrate that the choice of voltages applied to grids 101 and 201 on the front panel allows control of both the average value, as previously shown for VG1 = VG2, and the height of the Gaussian distribution. This is particularly noticeable on the figure 3C that for VG1 = -VG2, an increase in the absolute value of the grid voltages VG1, VG2 allows the height of the Gaussian to be lowered while maintaining a constant average value. figure 3A illustrates the combination of a variation in the mean value and the height of the Gaussian.

[0076] Thus, the presence of two grids 101, 201 on the front panel allows very precise control of the shape and characteristic values ​​of the current response of device 1 to a voltage stimulus.

[0077] THE Figures 4A , 4C , 5A And 5Cconstitute a study of the influence of the thickness e 300 of the dielectric layer 300 on the operation of device 1 via current-voltage characteristics ID = f(V BG ) obtained by TCAD simulation (from the English "Technology Computer Aided Design"). During these simulations: the first grid voltage V G1 and the second grid voltage V G2 are related by the following relations: i. Figures 4A And 4C : VG1 = VG2. Simulations were performed for several values ​​of VG1 = VG2, ranging from -1V to 1V. These different simulations correspond to the different curves on the... Figures 4A And 4C ii. Figure 5A And 5C : V G1 = -V G2. The simulations were performed for several values ​​of V G1 = -V G2, varying from -1V to 1V. These different simulations correspond to the different curves on the Figures 4A And 4C The drain-source voltage VDS was set to a value of 0.5V. The back-gate voltage VBG varies from -2V to 2V. The thickness e300 of the dielectric layer 300 was set to: i.e., 10nm (1nm = 10-9 m) during the simulations shown in Figures 4A And 5A ii. 5nm during the simulations represented in figures 4C And 5C . we record the evolution of the drain-source current I DS circulating in device 1 as a function of V BG .

[0078] These elements are summarized in the tables presented in figure 4B , 4D , 5B And 5D .

[0079] It is particularly noticeable that, regardless of the relationship between VG1 and VG2, the thinner the dielectric layer 300, the smaller the full width at half maximum (FWHM) – and therefore the standard deviation – of the Gaussian distribution. In other words, the thinner the buried dielectric 300, the better the electrostatic control of the back grid 400 on the current response of device 1. For the intended applications, it is advantageous for the standard deviation to be as small as possible. The thickness e 300 of the dielectric layer 300 is therefore advantageously minimized.

[0080] It should also be noted that, as illustrated by the Figures 3A And 3C The thinner the dielectric layer 300, the more closely spaced the Gaussian curves obtained for different values ​​of VG1 = VG2. Varying the thickness e300 therefore also allows control over the average value of the Gaussian curve.

[0081] Thus, the thickness e300 of the dielectric layer 300 is another lever for adjusting the characteristics of the Gaussian that can be generated by device 1. However, this is a parameter fixed during its manufacture and therefore intrinsic to the device. Typically, the thickness e300 is greater than 2 nm and preferably less than 25 nm.

[0082] According to one embodiment, the gate dielectrics 102, 202 are based on a ferroelectric material. For example, they can be based on HfO 2 , HfZrO 2 , BaTiO3 , Pb(Zr,Ti)O 3 (commonly designated by the acronym PZT), SrBi 2 Ta 2 O 9 (SBT), BiFeO 3 (BFO), a silicon-doped hafnium oxide (HZO), or a material of the type Al x Sc 1-x N.

[0083] Ferroelectric materials are characterized by their spontaneous polarization, the direction of which can be reversed and changed by an electric field. These materials are notably characterized by: their temperature T c below which they have ferroelectric behavior, their remanent polarization P r , which is the value of the polarization at zero field, their coercive field E c , which is the value of the field to apply to reverse the polarization, and finally their saturation polarization P s .

[0084] The characteristic of the polarization of a ferroelectric material in its ferroelectric phase (i.e., for T <T c ) en fonction du champ électrique lui étant appliqué est illustrée en figure 6We observe a hysteresis phenomenon that is commonly used in microelectronics for memory applications. Indeed, there are transistors called FeFETs, which have a ferromagnetic gate on their front face and can store one bit of information each. In these devices, a brief pulse of the potential applied to the front gate of the FeFET induces a permanent and constant current IDS. More precisely, this potential pulse, greater than (or less than) the coercive potential +VC (respectively -VC), causes a constant bias +Pr (respectively -Pr) of the ferroelectric material. This bias permanently induces a source-drain current, the intensity of which, a function of the bias state of the ferromagnetic material, constitutes a memory state that can be read without data loss. In particular, the bias state, and therefore the information, is preserved when the gate potential is removed.

[0085] For example, after applying a gate voltage VGS greater than the coercive potential +VC, the transistor channel becomes conductive and the resulting current codes for a first piece of information (e.g., a bit "1"). This information can be erased and changed to a second piece of information, such as a bit "0", by applying a gate voltage VGS less than -VC. figures 7A And 7C represent the current-voltage characteristics of a state-of-the-art transistor, respectively without and with ferromagnetic material. Both states, which can be used for memory applications, are clearly visible on the figure 7C .

[0086] This principle can be applied to device 1 according to the invention and even optimized. It is indeed possible to parameterize the gate voltages VG1 and VG2 so that the two Gaussian curves of the current-voltage characteristic ID = f(VBG) of the device have average values ​​at voltage levels that allow the implementation of logic gates. For example, the bias state of the front-panel gates 101 and 201 (i.e., the voltages VG1 and VG2) can constitute an input A, and the rear-panel gate voltage VBG an input B. It is then possible to encode: A first Gaussian, corresponding to a first bias state, for an input value A "1", A second Gaussian, corresponding to a second bias state, for an input value A "0", A first back-gate voltage value VBG,1 for an input value B "0", and A second back-gate voltage value VBG,2 for an input value B "1".

[0087] All the basic logic gates can then be implemented. For example, the figure 8A This illustrates the implementation of an "exclusive OR" logic gate (commonly referred to by the English acronym "XOR"). In this configuration: The average value of the first Gaussian is equal to V BG,1 , and the average value of the second Gaussian is equal to V BG,2 .

[0088] Thus, if device 1 is in the first bias state (input A = "1") and the back-gate voltage is set to VBG,1 (input B = "0"), device 1 is conducting and a current ID can be measured, thus encoding a bit "1". Conversely, for any other value of VBG, the current ID will be zero (or at least significantly lower), thus encoding a bit "0". If, this time, device 1 is in the second bias state (input A = "0") and the back-gate voltage is set to VBG,2 (input B = "1"), device 1 is conducting and a current ID can be measured, thus encoding a bit "1". Conversely, for any other value of VBG, the current ID will be zero (or at least significantly lower), thus encoding a bit "0". These different scenarios are summarized in Table 1.As shown in the last column of this table, this configuration does indeed allow for the implementation of a logical "XOR" function. Physical parameter V G1, V G2 V BG ID Logical equivalent A B A XOR B Value 0 0 0 0 1 1 1 0 1 1 1 0

[0089] There figure 8B This illustrates the implementation of a "NOT-OR" logic gate (commonly referred to by the English acronym "NOR"). In this configuration: The average value of the first Gaussian is different from VBG,1 and VBG,2, and the average value of the second Gaussian is equal to VBG,1.

[0090] Thus, if device 1 is in the first bias state (input A = "1"), regardless of the value of the back gate voltage (input B = "0" or "1"), device 1 is blocked. No current can be measured (or only a very small current), thus encoding a "0" bit. If, this time, device 1 is in the second bias state (input A = "0") and if the back gate voltage is set to VBG,1 (input B = "0"), device 1 is conducting and a current ID can be measured, thus encoding a "1" bit. Conversely, for any other value of VBG, the current ID will be zero (or at least significantly lower), thus encoding a "0" bit. These different scenarios are summarized in Table 2. As the last column of this table shows, this configuration does indeed allow the implementation of a "NOR" logic function. Physical parameter V G1, V G2 V BG ID Logical equivalent A B A NOR B Value 0 0 1 0 1 0 1 0 0 1 1 0

[0091] It has been shown that device 1 could enable the realization of XOR and NOR logic gates, but it is understood that all other elementary logic gates (AND, OR, NOT, NAND, XNOR) can be realized by adapting the position of the first and second Gaussians.

[0092] Thus, by simply adjusting the two gate voltages V G1, V G2, device 1 makes it possible to efficiently implement all the elementary logic gates, which is not possible with classic FDSOI transistors which can only be controlled at the level of a single front gate.

[0093] According to one embodiment, the device 1 includes a control circuit for applying the aforementioned voltages to each of the electrodes. The control circuit also allows the voltages V110, V210, VG1, VG2 and VBG to be varied, for example within a given range such as [-5V, 5V].

[0094] The control circuit is advantageously configured to be able to generate characteristics exhibiting a Gaussian shape.

[0095] The generation of a Gaussian-type characteristic can be particularly useful in in-memory computing applications. For example, it is possible to create non-volatile memory cells for performing elementary logical operations by exploiting device 1 as described previously.

[0096] Device 1 could also be used for classification applications, for example in the field of machine learning. Classification is an important aspect of exploratory and decision-making data analysis. Its goal is to determine whether a set of objects is homogeneous and, if not, to partition this collection into homogeneous subsets called classes. The Gaussian mixture model, illustrated in figure 9 A Gaussian mixture is a linear combination (solid curve) of several Gaussian components (dashed curves). It is particularly useful when the data under study cannot be modeled by a simple Gaussian distribution. In other words, if the data structure naturally consists of several groups, it is necessary to represent them by a Gaussian mixture model rather than a simple Gaussian distribution.

[0097] Still within the framework of machine learning, the Gaussians generated by device 1 could also be used to define the synaptic weight between two neurons, particularly in the study of Bayesian neural networks.

[0098] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

1. Microelectronic device (1) comprising: • a first field-effect transistor (100) comprising a first drain, a first source, a first gate (101), a first gate dielectric (102), and a first channel (103), • a first doped zone (110), constituting one from among the first drain and the first source, • a second doped zone (120), constituting the other from among the first drain and the first source, • a second field-effect transistor (200) comprising a second drain, a second source, a second gate (201) and a second gate dielectric (202), and a second channel (203), • a third doped zone (210), constituting the second source if the first doped zone (110) constitutes the first drain, or the second drain, if the first doped zone (110) constitutes the first source, • a fourth doped zone (220), constituting the other from among the second drain and the second source, • a dielectric layer (300) having an upper face (301) in contact with the first doped zone (110), with the second doped zone (120), with the third doped zone (210) and with the fourth doped zone (220), • a rear gate (400) in contact with a lower face (302) of the dielectric layer (300), in which the second doped zone (120) and the fourth doped zone (220) form a common electrode (1000), and in which the first doped zone (110), the second doped zone (120), the first channel (103), the third doped zone (210), the fourth doped zone (220) and the second channel (203), are with the basis of the same material, the device being characterised in that the second doped zone (120) and the fourth doped zone (220) have a doping of the same type from among an N-type doping and a P-type doping, and in that the first doped zone (110) and the third doped zone (210) have a doping of the other type.

2. Device (1) according to the preceding claim, wherein the second doped zone (120) and the fourth doped zone (220) are electrically connected by an electrically conductive layer (500), preferably metallic.

3. Device (1) according to the preceding claim, wherein the electrically conductive layer is metal silicide-based.

4. Device (1) according to any one of claims 2 and 3, wherein the electrically conductive layer (500) directly covers at least one part of an upper face (121) of the second doped zone (120) and at least one part of an upper face (221) of the fourth doped zone (220).

5. Device (1) according to any one of claims 2 to 4, wherein the electrically conductive layer (500) directly covers a part of the upper face (301) of the dielectric layer (300) and separates the second doped zone (120) from the fourth doped zone (220).

6. Device (1) according to any one of the preceding claims comprising a first electrode (115) and a second electrode (215), and wherein the first doped zone (110) is in contact with the first electrode (115) which is configured to receive a first control voltage V110 and the third doped zone (210) is in contact with the second electrode (215) which is configured to receive a second control voltage V210.

7. Device (1) according to the preceding claim, wherein: • The first control voltage V110 constitutes a source voltage VS of the device (1) and the second control voltage V210 constitutes a drain voltage VD of the device (1), or • The second control voltage V210 constitutes a source voltage VS of the device (1) and the first control voltage V110 constitutes a drain voltage VD of the device (1).

8. Device (1) according to any one of the preceding claims comprising a first gate electrode (105) and a second gate electrode (205), and wherein the first gate (101) is in contact with the first gate electrode (105) which is configured to receive the application of a first gate voltage VG1 and the second gate (201) is in contact with the second gate electrode (205) which is configured to receive the application of a second gate voltage VG2.

9. Device (1) according to any one of the preceding claims comprising a rear gate electrode (405), and wherein the rear gate (400) is in contact with the rear gate electrode (405) which is configured to receive the application of a rear gate voltage VBG.

10. Device (1) according to claims 6, 8 and 9 combined, further comprising a control circuit configured to apply: • the first control voltage V110 on the first electrode (115), • the second control voltage V210 on the second electrode (215), • the first gate voltage VG1 on the first electrode (105), • the second gate voltage VG2 on the second electrode (205), • the rear gate voltage VBG on the rear gate electrode (405), the first control voltage V110, the second control voltage V210, the first gate voltage VG1, the second gate voltage VG2 and the rear gate voltage VBG being able to take different values and at least values of between -5 and 5V.

11. Device (1) according to the preceding claim, wherein VG2 = ± VG1 + ΔVG, and with ΔVG between -5 and +5V.

12. Device (1) according to claim 10, wherein VG2 = VG1.

13. Device (1) according to claim 10, wherein VG2 = -VG1.

14. Device (1) according to any one of the preceding claims, wherein the first transistor (100) and the second transistor (200) are separated by a distance L greater than 50nm, and / or less than 500nm.

15. Device (1) according to any one of the preceding claims, wherein the dielectric layer (300) has a thickness e300 between its lower face (302) and its upper face (301) less than or equal to 25nm, preferably less than 5nm.

16. Device (1) according to any one of the preceding claims, wherein the first gate dielectric (102) and the second gate dielectric (202) are with the basis of a ferroelectric material.

17. Non-volatile memory storage unit comprising at least one device (1) according to the preceding claim.

18. Method for controlling the device (1) according to any one of claims 2 to 16 or the storage unit according to the preceding claim, wherein the first control voltage V110 is applied to the first doped zone (110) and the second control voltage V210 is applied to the first doped zone (210), and wherein: • The first control voltage V110 constitutes a source voltage VS of the device (1) and the second control voltage V210 constitutes a drain voltage VD of the device (1), or • The second control voltage V210 constitutes the source voltage VS of the device (1) and the first control voltage V110 constitutes the drain voltage VD of the device (1).