ELECTRONIC CIRCUIT BASED ON RRAM CELLS

Description

[0001] The present invention relates to an electronic circuit suitable for implementing computational operations, each providing a binary output.

[0002] The invention relates to any type of application using operations applied to binary operands, in particular applications using binary artificial neural networks, also called BNNs (from the English Binary Neural Network ).

[0003] A neural network is generally composed of a succession of layers of neurons, each taking its inputs from the outputs of the previous layer. More precisely, each layer comprises neurons whose inputs are derived from the outputs of the neurons in the preceding layer. Each layer is connected to the next by a plurality of synapses. A synaptic weight is associated with each synapse. This is a number, such as a binary number, or a distribution, that takes on both positive and negative values. In the case of a dense layer, the input of a neuron is the weighted sum of the outputs of the neurons in the preceding layer, the weighting being determined by the synaptic weights, followed by activation via an activation function.

[0004] It is therefore desirable to develop dedicated hardware architectures, intertwining memory and computing, to create fast, low-power neural networks capable of learning in real time.

[0005] Such dedicated hardware architectures are generally designed to efficiently perform operations applied to binary operands.

[0006] A neural network based on optical technologies is known.

[0007] Another area of ​​research focuses on the realization of neurons and synapses of neural networks based on CMOS-type technology (from the English Complementary Metal-Oxide-Semiconductor The acronym CMOS refers both to a manufacturing process and to a component obtained by such a manufacturing process.

[0008] However, with each of these technologies, each neuron occupies several tens of micrometers on each side. Furthermore, each synapse also occupies several tens of micrometers on each side. Consequently, on a limited surface area, such as an electronic chip, the number of neurons and synapses that can be integrated is limited, resulting in reduced performance of the neural network.

[0009] Therefore, to reduce clutter, architectures in which synapses are memritive are specifically studied.

[0010] Memoristic synapses are synapses that utilize memristors. In electronics, a memristor (or memristor) is a passive electronic component. The name is a portmanteau of the English words "memory" and "resistor." A memristor is a non-volatile memory component; its electrical resistance changes when a voltage is applied for a certain duration and remains at that value when the voltage is removed.

[0011] Examples of such an implementation are provided in the following articles: “A Fully Integrated Analog ReRAM Based 78.4TOPS / W Compute-In-Memory Chip with Fully Parallel MAC Computing” by Q. Liu et al. (2020); « A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors” by C. Xue et al. (2019); «A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS / W for Tiny AI Edge Devices” by C. Xue et al. (2021); « A 16Mb dual-mode ReRAM macro with sub-14ns computing-in-memory and memory functions enabled by self-write termination scheme” by W. Chen et al. (2017); and “Embedded 1-Mb ReRAM-Based Computing-in-Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors” by C. Xue et al. (2019).

[0012] According to these articles, the approach consists of storing the weights of a neuron within a column of memory cells called RRAM or ReRAM (from the English Resistive Random-Access Memory ) , and to apply the entries (activations) to the word lines, usually denoted WL (from English Word Line ), of this column (a positive voltage being applied to an associated bit line), usually denoted BL (from English Bit Line Input voltages can be binary (open-access or closed-access transistors), or take on several possible values ​​in the case of multi-bit inputs. A weight of 1 is generally encoded by a low-resistance state, denoted LRS (from the English Low Resistance State ), and a weight equal to 0 by a state of high resistance, denoted HRS (from English High Resistance State If the input value corresponding to a given weight is 1, then—according to Ohm's law—a current will flow through the cell carrying the weight, equal to the product of the input value and the weight value. If the weight is 1, the current is high (because the resistance is low), and if the weight is 0, the current is low.

[0013] The cells are connected via source lines, usually denoted SL (from English Source Line ), the currents add up via Kirchhoff's law, resulting in a MAC operation (from the English Multiply And Accumulate ) well known for neural network inference. A comparator circuit calculates the effective output of the neuron by comparing the result of the MAC operation to a reference value.

[0014] However, these neuromorphic circuits currently suffer from the excessive variability of resistive memory cells, due to the immaturity of their manufacturing process. Consequently, these approaches are limited in terms of the number of operands in a MAC operation, typically to 9 inputs. Furthermore, again due to the high variability of memory cells, these approaches require complex circuitry to compare the MAC operation to different possible threshold values, resulting in significant surface area and power consumption.

[0015] Another approach is presented in the article "Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control" by L. Wang et al. (2021). This approach performs accumulation via a resistive bridge rather than current accumulation. It uses columns of RRAM memory cells resulting from the merging of the source line SL of two columns (a 2T2R structure for 2 transistors and 2 resistors, a pair of switches, and a pair of memristors). Each column thus has a pair of complementary bit lines BL, BLb, and a source line SL. Two resistors are used to encode each weight in differential (HRS-LRS or LRS-HRS). A voltage is then applied between the complementary bit lines BL, BLb of the column, creating a resistive bridge between the resistors on the left and right sides of the column. The resulting voltage corresponds to the result of the MAC operation.Although allowing greater robustness against the variability of neurons, this approach presents the same disadvantages as the previous one in terms of complexity and surface area of ​​the comparators needed at the bottom of the column, and still seems limited to 9 inputs.

[0016] Finally, a last approach is presented in the article "Low-Overhead Implementation of Binarized Neural Networks Employing Robust 2T2R Resistive RAM Bridges" by M. Ezzadeen et al. (2021). It consists of applying differential inputs to the complementary bit lines BL, BLb (rather than to the word lines WL), by activating a respective word line of the memory cell matrix. The weights are differentially encoded in 2T2R cells. This results in a resistive bridge structure within each 2T2R cell, leading to an exclusive-OR (XOR) operation at the output of each source line SL. Since the binary multiplication operation is equivalent to an exclusive-OR (XNOR) operation, a simple inverter at the end of the source line SL produces the result of the XNOR operation.Accumulation is performed using a capacitive bridge, connecting each inverter output to a capacitor, and connecting all the other capacitors together to form the bridge. This approach has the advantage of being extremely robust to cell variability (thanks to the use of capacitors, a mature technology) despite a low area footprint (a single inverter per column). Its robustness also allows for the implementation of very large neurons (up to 513 inputs), performing the summation of contributions from a large number of inputs in a single computation cycle, since all columns are activated simultaneously to perform the calculation for a neuron associated with a row of the matrix. Furthermore, the memory cells encoding the weights are more compact in practice, as only a single 2T-2R cell and a single word row are required per row.However, only one neuron can perform a calculation during a given cycle, because only one row of the memory cell matrix is ​​activated for each calculation. Depending on the application context, the "one neuron per row" or "one neuron per column" solution will be preferred, particularly based on the number of inputs to each neuron, the number of neurons per layer, the available surface area, etc.

[0017] There is therefore a need for an electronic circuit that allows, in particular, the creation of a binary neural network that is less bulky and has better integrability into a set of memory cells.

[0018] For this purpose, the invention relates to an electronic circuit according to claim 1.

[0019] With the electronic circuit according to the invention, the reading module comprising a logic unit for each column and the modification unit capable of modifying, for at least one logic unit and according to the calculation operation, the difference between the column value and the threshold value, makes it possible to determine more efficiently a resulting value corresponding to the voltage of the respective source line.

[0020] Preferably, each memory cell comprises two pairs of memristors and two pairs of switches, with a first pair of switches connected to a first word line assigned to an input, and respectively a second pair of switches connected to a second word line assigned to the inverse of said input; and with a first pair of memristors associated with the first pair of switches and storing a synaptic weight, and respectively a second pair of memristors associated with the second pair of switches and storing the inverse of the same synaptic weight.

[0021] According to this clever implementation, each memory cell then allows a non-exclusive-or, or XNOR, operation to be performed directly between an input and the corresponding synaptic weight of a respective neuron, and an inference value of said neuron is then obtained directly from the resulting value corresponding to the voltage of the respective source line, or from the resulting values ​​corresponding to the voltages of the respective source lines when the synaptic weights of said neuron are encoded on several columns of the matrix-shaped memory cell set.

[0022] According to other advantageous aspects of the invention, the electronic circuit is according to any one of claims 2 to 17.

[0023] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following features, taken individually or in all technically possible combinations: Each logic unit performs a logic function of the inverter type; each logic unit preferably being a simple inverter; the simple inverter preferably comprising only two transistors.

[0024] These features and advantages of the invention will become clearer upon reading the following description, given solely by way of non-limiting example, and made with reference to the accompanying drawings, in which: there figure 1 is a schematic representation of an electronic circuit, according to the invention, suitable for implementing computational operations, each providing a binary output, the circuit comprising word lines, pairs of complementary bit lines, source lines, a set of memory cells organized according to a matrix comprising rows and columns, each memory cell comprising at least one pair of memristors and at least one pair of switches, and a read module implemented during each computational operation, the read module comprising a logic unit for each column, each logic unit performing a logical operation with toggling between a low value and a high value based on a comparison of a column value with a toggling threshold value, and a modification unit, for at least one logic unit and based on the computational operation,of a difference between the column value and the switching threshold value; the , figure 2 is a schematic representation of a respective memory cell according to a first example of its implementation, where it comprises two pairs of memristors and two pairs of switches; the figure 3 is a graph showing the effect of the variability of the resistance values ​​of the states of a memristor; the figure 4 is a schematic view illustrating an XNOR operation performed via the memory cell of the figure 2 ; there figure 5 is a schematic representation of a respective logical unit of the figure 1 , and the output voltage of said logic unit, taking into account the variability effect represented at the figure 3 , for an example with five rows of memory cells; the figure 6 is a schematic representation illustrating the modification, for the logical unit of the figure 5 , the difference between the column value and the toggle threshold value; the figure 7 is a representation of the electronic circuit according to the invention with the memory cells of the figure 2 , in an example where the electronic circuit forms a neuromorphic circuit implementing a binary output neural network, each memory cell being associated with a respective synaptic weight of a neuron, and the word lines being capable of receiving input voltages during a neuronal computation operation; the figure 8 is a schematic representation of the electronic circuit according to the invention with a particular implementation of a controller for complementary bit-line pairs, adapted to reset a respective column value after detection by the logic unit of a toggle for said column; the figure 9 is a schematic representation of the electronic circuit according to the invention and an associated timing diagram, the circuit further comprising a register at the output of each logic unit, each register being suitable for transcribing in binary form the result of the calculation operation for the column, by recording - until the resulting value corresponding to the result of the calculation operation is reached - each successive value at the output of the corresponding logic unit, as illustrated on the timing diagram; the figure 10 is a schematic representation of a respective memory cell according to a second example embodiment, where it comprises a single pair of memristors and a single pair of switches; the figure 11 is a view analogous to that of the figure 5 , further representing examples of switching thresholds, when the calculation performed is the logical AND operation, or respectively the logical OR operation; and the figure 12 is a schematic representation of the electronic circuit according to the invention, the circuit further comprising a flip-flop at the output of each logic unit, each flip-flop being suitable for performing a combination of results of logic operations performed successively by a respective logic unit, to implement a combined logic operation, such as an exclusive-OR operation or an exclusive-OR operation.

[0025] It should be noted that the expression "specific to" followed by a verb is considered equivalent to the expression "configured for" followed by the same verb. The expression "specific to" may therefore be replaced, if necessary, by the expression "configured for," without altering the content and substance of the present invention.

[0026] On the figure 1 An electronic circuit 10 is designed to implement computational operations, each providing a binary output. Examples of computational operations performed by the electronic circuit 10 include neural computing operations, such as counting the number of 1s in a series of bits. popcount ), or even MAC operations (from English Multiply And Accumulate well known for neural network inference; AND operations on binary operands; OR operations on binary operands; Majority operations among binary operands.

[0027] The electronic circuit 10 comprises a set of memory cells 12, that is to say a plurality of memory cells 12, the memory cells 12 being arranged according to a two-dimensional matrix 14 comprising rows 16 and columns 18.

[0028] In addition, the electronic circuit 10 comprises several distinct sets of memory cells 12 designed to operate in parallel, as illustrated in particular in the example of the figure 7 .

[0029] Matrix 14 will be referred to as the matrix of cells 14 in the following description. A memory cell 12 has the coordinates (i,j) when said memory cell 12 is positioned at the intersection of the i-th row 16i and the j-th column 18j, where i and j are two integers.

[0030] In the example of the figure 1 The number of rows (16) and columns (18) is equal to N, so the indices i and j are between 1 and N. In the example of the figure 1 , a matrix of 14 cells has been represented for which N is equal to 9. Alternatively, the number of rows 16 and columns 18 can of course be different.

[0031] More generally, in the example of the figure 7 , the number of rows 16 is equal to n and respectively the number of columns 18 is equal to m, so that the index i is between 1 and n, and respectively the index j is between 1 and m.

[0032] The electronic circuit 10 also includes WL word lines (visible on the figures 2 , 7 And 10 ), pairs of complementary bit lines BL and BLb, source lines SL and two controllers 20 and 22.

[0033] The electronic circuit 10 also includes a read module 24 implemented during each calculation operation, which will be described in more detail later in the description.

[0034] In the preceding notations, a word line is referenced WL (from English Word Line ); the complementary bit lines BL and BLb use the abbreviation BL (from English Bit Line ) and the source lines are referenced with the abbreviation SL (from English Source Line ).

[0035] In the example of the figure 1 , each memory cell 12 is connected to a respective input line IN, a respective source line SL and a respective pair of complementary bit lines BL and BLb.

[0036] Each IN input line is specifically designed to receive or select an operand to which the calculation operation is to be applied. For example, each IN input line is specifically designed to receive an input value for the calculation operation.

[0037] Each input line IN is itself connected to a respective word line WL or to a respective pair of complementary word lines WL and WLb, depending on the memory cell topology 12. In the examples of figures 2 , 4 And 7 Each input line IN is connected to a respective pair of complementary word lines WL and WLb. In the example of the figure 10 , each IN input line is connected to a single respective WL word line.

[0038] Each memory cell 12 in the same row 16 shares the same input line IN, itself connected to a respective word line WL or to a respective pair of complementary word lines WL and WLb, so that the input lines IN, and respectively the word lines WL, WLb, can also be indexed with the index i. Thus, the first input line IN, that is to say the one which links the memory cells 12 of the first row 16, is referenced IN 1; and the word line(s) associated with this first input line IN 1 are referenced WL 1, or respectively WL 1 and WLb 1.

[0039] Memory cells 12 in the same column 18 share the same pair of complementary bit lines BL and BLb and the same source line SL. These three lines can therefore also be indexed with the index j.

[0040] For clarity, all source lines SL are shown, but only the complementary bit line pairs BL and BLb from the first column 181, the fifth column 185, and the ninth column 189 are shown as dashed lines on the figure 1 .

[0041] Memory cells 12 in the same row 16 are then selectable by at least one word line WL, and memory cells 12 in the same column 18 are linked to a pair of complementary bit lines BL, BLb and a source line SL.

[0042] The first controller 20 allows the selection of memory cells 12 of a row 16 which are linked to the same WL word line.

[0043] The first controller 20 is designed to control each input line IN, and by transitivity each word line WL, WLb. Indeed, when each input line IN is connected to a respective pair of complementary word lines WL and WLb, the input line IN is connected directly to one of the WL word lines, and via an inverter 26, hereafter called word line inverter 26, to the other WLb word line; and controlling the value applied to the input line IN also entails controlling the value applied to the respective pair of complementary word lines WL and WLb.Indeed, a person skilled in the art will understand that the value applied to the input line IN is then the same as that applied to the word line WL which is directly connected to the input line IN, and consequently that the value applied to the input line IN is then the inverse of that applied to the complementary word line WLb which is connected to the input line IN via the word line inverter 26. Of course, this applies when each input line IN is directly connected to a single respective word line WL, as in the example of the... figure 10 , then the value applied to the IN input line is the same as that applied to said WL word line connected directly to the IN input line.

[0044] The "inverse" of a binary value is its complement to 1. In other words, if a binary value is equal to 0, its inverse is equal to 1; and conversely, if a binary value is equal to 1, its inverse is equal to 0.

[0045] The second controller 22 is specifically designed to control the complementary bit line pairs BL and BLb and the source lines SL.

[0046] The second controller 22 is connected to the pairs of bit lines BL, BLb and allows different voltages to be applied to each pair of bit lines BL, BLb, the voltages applied during the calculation operation being advantageously symmetrical with respect to an average voltage, the voltage applied on a bit line BL being greater or less than that applied on the associated complementary bit line BLb.

[0047] The first controller 20 and the second controller 22 are configured to be driven in a coordinated manner to control the memory cells 12 using the lines they control according to the desired operation.

[0048] In particular, the first controller 20 is configured to bring the input values ​​flowing on each of the IN input lines. These input values ​​will, for example, feed the neural network implemented, if applicable, by the electronic circuit 10.

[0049] Inverter 26 is designed to receive an incident signal at an input 26E and perform a logic inversion calculation to output a signal at an output 26S that is the inverse of the incident signal. Here, the input 26E of inverter 26 is connected to the input line IN, and the output 26S of inverter 26 is connected to the complementary word line WLb.

[0050] Each memory cell 12 is designed to store at least one binary value, such as a binary weight, in particular a respective binary synaptic weight of the neural network when the computational operation performed is a neural computational operation.

[0051] The structure of a memory cell 12 is represented more precisely on the figure 2 for the case of memory cell 12 having coordinates (i,j).

[0052] Each memory cell 12 has at least one pair of memristors 28, 30, where each pair of memristors is formed of two memristors, namely a first memristor 28 and a second memristor 30, and at least one pair of switches 32, 34, where each pair of switches is formed of two switches, namely a first switch 32 and a second switch 34.

[0053] In the examples of figures 2 , 4 And 7, each memory cell 12 has two pairs of memristors 28, 30, i.e. two first memristors 28 and two second memristors 30, and two pairs of switches 32, 34, i.e. two first switches 32 and two second switches 34.

[0054] In the example of the figure 10 , each memory cell 12 has a single pair of memristors 28, 30, i.e. a single first memristor 28 and a single second memristor 30, and a single pair of switches 32, 34, i.e. a single first switch 32 and a single second switch 34.

[0055] Because memristors 28 and 30 are present, such a memory cell 12 is a resistive random-access memory cell. Memory cell 12 is more often referred to by the acronym RRAM or ReRAM (from the English Resistive random-access memory ).

[0056] Furthermore, such an arrangement is generally called a 4T4R structure, referring to the presence of four switches (designation 4T) and four memristors (designation 4R) in the examples of figures 2 , 4 And 7 By analogy, such an arrangement is generally called a 2T2R structure, referring to the presence of two switches (designated 2T) and two memristors (designated 2R) in the example of the figure 10 Memory cell 12 is also sometimes referred to as cell 4T4R in the examples of figures 2 , 4 And 7 , or respectively cell 2T2R in the example of the figure 10 .

[0057] Each memristor 28, 30 of a respective memory cell 12 is connected to the same source line SL and to a respective switch 32, 34, and each pair of memristors 28, 30 is configured to store a binary value by having different first and second resistance values. Those skilled in the art will observe that the source line SL to which the memristors 28, 30 of the respective memory cell 12 are connected is likely to be formed from two separate source lines connected together during the computation operation.

[0058] Each memristor 28, 30 is a component whose electrical resistance changes permanently when a current is applied. Thus, data can be recorded and rewritten by a control current. Such behavior is observed in phase-change materials, ferroelectric tunnel junctions, and oxide-based redox memories, such as HfO₂ₓ or TiO₂ₓ. The resistance change of a memristor depends on the amplitude and duration of the voltage pulses applied across the memristor, as well as the maximum current that can flow through the memristor, for example, during a "SET" operation, i.e., the transition from a high resistance to a low resistance.

[0059] Each memristor 28, 30 thus exhibits two states: a high state and a low state. The high state corresponds to a high resistance and is generally designated by the abbreviation HRS. The high state is therefore referred to as the high HRS state hereafter. The low state corresponds to a low resistance and is generally designated by the abbreviation LRS. The low state is therefore referred to as the low LRS state hereafter.

[0060] However, due to the variability of the memristors 28, 30 in operation, the resistance in the high state HRS may be less than the resistance in the low state LRS, which generates errors if the information (weight) is coded in a single memristor 28, 30.

[0061] This variability is presented schematically on the figure 3 This figure shows the probability that a memristor 28, 30 will exhibit a resistance value in practice, depending on the memristor's state. More precisely, the first curve, labeled 36, schematically represents the probability for all the values ​​observed in practice for the low state (LRS), while the second curve, 38, represents the same curve for the high state (HRS).

[0062] The graph of the figure 3 This shows that there is an overlap zone 40. Within this overlap zone 40, distinguishing between low LRS and high HRS states may be impossible. This overlap may be more significant with long-term temporal drifts of memristors 28, 30.

[0063] To overcome this problem, the information is encoded by the ratio between the resistances of the two states, thanks to a differential configuration of the two memristors 28 and 30. Furthermore, memristors 28 and 30 are series-connected and complementary, exhibiting the same logic encoding. By complementary, it is understood that memristors 28 and 30 have different states: a low state (LRS) for one and a high state (HRS) for the other.

[0064] According to the examples of figures 2 , 4 , 7 And 10 A strong weight, i.e. a logical "1", is represented by a high HRS state of the first memristor 28, and respectively a low LRS state of the second memristor 30. As a corollary, a weak weight, i.e. a logical "0", is represented by a low LRS state of the first memristor 28, and respectively a high HRS state of the second memristor 30.

[0065] Furthermore, in the examples of figures 2 ,4 And 7 where each memory cell 12 has two pairs of memristors 28, 30, the pairs of memristors 28, 30 are preferably coded in a complementary manner from one pair to the other. In other words, within each memory cell 12, one pair of memristors 28, 30 is preferably configured to encode a binary value, while the other pair of memristors 28, 30 is preferably configured to encode the inverse of said binary value.

[0066] Also, in the aforementioned coding logic example, if the binary value to be encoded is equal to 1 for the first pair of memristors 28, 30, the left memristor, i.e. the first memristor 28, is coded as high resistance (high state HRS), and the right memristor, i.e. the second memristor 30, is coded as low resistance (low state LRS), while for the second pair of memristors 28, 30 encoding the inverse of said binary value, i.e. 0, the left memristor, i.e. the first memristor 28, is coded as low resistance (low state LRS) and the right memristor, i.e. the second memristor 30, is coded as high resistance (high state HRS).

[0067] A first pair of switches 32, 34 is connected to a first word line assigned to an input IN, namely the word line WL, which is directly connected to the input IN. A second pair of switches 34, 32 is connected to a second word line assigned to the inverse of said input IN, namely the complementary word line WLb, which is connected to the input IN via the word line inverter 26. The first pair of memristors 28, 30 is associated with the first pair of switches 32, 34 and stores a binary value w; and the second pair of memristors 28, 30 is associated with the second pair of switches 34, 32 and stores the inverse of the same binary value w.

[0068] In addition, as previously described, the first pair of memristors 28, 30 and the first associated pair of switches 32, 34 will have their word line WL assigned to the input corresponding to the binary value, while the second pair of memristors 28, 30 and the second associated pair of switches 32, 34 will have their complementary word line WLb assigned to the inverse of the same input, by the word line inverter 26.

[0069] Switches 32, 34 are connected, for their activation, to a respective WL, WLb word line and connected respectively to a pair of complementary BL, BLb bit lines, the two switches 32, 34 of a respective pair being connected to the same WL, WLb word line.

[0070] Each of the two switches 32 and 34 is, for example, a transistor, such as a field-effect transistor, also called a FET (from the English Field-Effect Transistor ).

[0071] Thus, each switch 32 and 34 has three electrodes, a gate G, a source S and a drain D. In general, for a transistor whose reference sign is X, where X designates the reference 32 or 34, the electrodes will be noted on the figures according to the following notation: the gate XG, the source XS and the drain XD.

[0072] This notation is chosen here to simplify the representation, given that the positions of the source XS and the drain XD are defined relative to the principal polarization direction, that is, the one most commonly used for the circuit. Of course, if the polarization is reversed, those skilled in the art know that the roles and positions of the source XS and the drain XD are reversed.

[0073] According to the example described, the two switches 32 and 34 are insulated-gate field-effect transistors, also called MOSFETs (from the English Metal Oxide Semiconductor Field Effect Transistor ).

[0074] Each grid 32G and 34G of the two switches 32 and 34 is connected to the word line WL. Depending on the voltage level present on the word line, switches 32 and 34 are either conducted or blocked. The first controller 20 will, in practice, select one or more rows 16 of memory cells 12 by conducting the switches 32 and 34 of the memory cells 12 in that row or those rows 16.

[0075] Each first switch 32 is connected to its respective first memristor 28, and each second switch 34 is connected to its respective second memristor 30. The drain 32D of the first switch 32 is connected to one terminal of the first memristor 28, with the other terminal of the first memristor 28 connected to the common source line SL. The drain 34D of the second switch 34 is connected to one terminal of the second memristor 30, with the other terminal of the second memristor 30 connected to the common source line SL. The source 32S of the first switch 32 is connected to the bit line BL, while the source 34S of the second switch 34 is connected to the complementary bit line BLb.

[0076] The second controller 22 will control the supply of the bit line pairs, so that the voltage presented on a bit line BL j is different and complementary to the voltage presented on the complementary bit line BLb j. Thus, when a memory cell 12 of coordinate i,j, in particular a pair of memristors 28, 30, is selected (its switches being made conducting by the activation voltage presented on the associated word line WL i or WLb i), the memristors 28 and 30 of this pair are in series and constitute a resistive bridge between the bit lines BL j and BLb j.

[0077] In this particular case, the memristors 28 and 30 of this pair are thus powered by voltages present on the bit lines BL j and BLb j symmetrical with respect to a voltage equal to [V(BL)+V(BLb)] / 2, called the midpoint voltage, where V(BL) represents the voltage of the bit line BL, and V(BLb) represents the voltage of the complementary bit line BLb.

[0078] In the examples of figures 2 , 4 And 7 With the coding logic defined above, if the binary value, such as a weight, in particular a synaptic weight of a binary neural network, stored in a given memory cell 12 is equal to 0, then for the first pair of memristors 28, 30, the first memristor 28 (corresponding to the one in the top left among the four memristors of memory cell 12) is in the low state LRS and the second memristor 30 (corresponding to the one in the top right) is in the high state HRS; and conversely, for the second pair of memristors 28, 30, the first memristor 28 (corresponding to the one in the bottom left) is in the high state HRS and the second memristor 30 (corresponding to the one in the bottom right) is in the low state LRS.

[0079] The person skilled in the art will of course understand that the coding is reversed if the binary value stored in memory cell 12 is equal to 1, and for the first pair of memristors 28, 30, the first memristor 28 (corresponding to the one in the upper left) is the high state HRS and the second memristor 30 (corresponding to the one in the upper right) is in the low state LRS; and conversely, for the second pair of memristors 28, 30, the first memristor 28 (corresponding to the one in the lower left) is in the low state LRS and the second memristor 30 (corresponding to the one in the lower right) is the high state HRS.

[0080] The person skilled in the art will also observe that in the examples of figures 2 , 4 And 7and by the word line inverter 26, only one pair of memristors 28, 30 out of the two pairs of memristors 28, 30 is activatable at a time. In particular, in these examples, and given that the word line inverter 26 is connected to the complementary word line WLb associated with the second pair of memristors 28, 30, if the input value received on the input line IN is equal to 1, then the first pair of memristors 28, 30 is activated since the value on the word line WL connected directly to the input line IN is also equal to 1 and the switches 32, 34 associated with this first pair are therefore conducting, while the second pair of memristors 28, 30 is not activated since the value on the complementary word line WLb is then equal to 0, the word line inverter 26 inverting the input value equal to 1 to the value 0, and the switches 32, 34 associated with this second pair are therefore non-conducting, i.e. blocked.Conversely, if the input value received on the input line IN is equal to 0, then the first pair of memristors 28, 30 is not activated since the value on the word line WL is also equal to 0 and the switches 32, 34 associated with this first pair are therefore non-conducting, while the second pair of memristors 28, 30 is in this case activated since the value on the complementary word line WLb is then equal to 1, the word line inverter 26 inverting the input value equal to 0 into the value 1, and the switches 32, 34 associated with this second pair are therefore conducting.

[0081] Furthermore, when a voltage is applied between the bit line BL and the complementary bit line BLb, with a higher potential VH for the bit line BL than VL for the complementary bit line BLb, this results in a resistive bridge between the first and second memristors 28, 30 of the activated memristor pair 28, 30, as explained previously. The memristor 28, 30, which is in the high state HRS, then systematically pushes the midpoint voltage, i.e., that of the source line SL, back towards the bit line BL, BLb, which is connected to the memristor 28, 30, which is in the low state LRS.

[0082] Also, in the examples of figures 2 , 4 And 7, with this clever implementation of the two pairs of memristors 28, 30 coupled to the two complementary word lines WL, WLb, one of the word lines being connected to the input line IN via the word line inverter 26, each memory cell 12 then allows to directly perform a non-exclusive-or, or XNOR, operation between the binary input received on the input line IN and the binary value, such as the corresponding synaptic weight of a respective neuron, stored in the memory cell 12, and the result of the XNOR operation is then obtained via the comparison of the voltage of the source line SL with the mid-voltage.

[0083] In the example of the figure 4 With the coding logic defined above, if the voltage of the source line SL is less than the midpoint voltage [V(BL)+V(BLb)] / 2, then the result of the XNOR operation is equal to 1; if the voltage of the source line SL is greater than the midpoint voltage [V(BL)+V(BLb)] / 2, then the result of the XNOR operation is equal to 0.

[0084] The four possible situations, depending on whether the binary input value, also called binary input, received on the input line IN i is equal to 0 or 1, and whether the binary value w ji stored in memory cell 12 is equal to 0 or 1, are then represented in a synthetic way on the right-hand side of the figure 4 .

[0085] In the first situation, where the binary input received on the input line IN i is equal to 0 and the binary value w ji stored in memory cell 12 is equal to 0, the second pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the high state HRS while the second memristor 30 (corresponding to the one on the right) is in the low state LRS. The first memristor 28 in the high state HRS then pushes the voltage from the source line SL j to the complementary bit line BLb j connected to the second memristor 30 in the low state LRS, as represented by arrow F1. The voltage of the source line SL j is then closer to the low potential VL for the complementary bit line BLb j than to the high potential VH of the bit line BL j, and is therefore less than the mid voltage [V(BL)+V(BLb)] / 2, so that the result of the XNOR operation is equal to 1. This therefore verifies XNOR(0,0) = 1.

[0086] In the second situation, where the binary input received on the input line IN i is equal to 1 and the binary value w ji stored in memory cell 12 is equal to 1, the first pair of memristors 28, 30 is activated. The first memristor 28 (corresponding to the one on the left) is in the high state HRS, while the second memristor 30 (corresponding to the one on the right) is in the low state LRS. The first memristor 28 in the high state HRS then pushes the voltage of the source line SL j towards the complementary bit line BLb j connected to the second memristor 30 in the low state LRS, as represented by arrow F1. The voltage of the source line SL j is then less than the midpoint voltage [V(BL)+V(BLb)] / 2, and the result of the XNOR operation is therefore equal to 1. This thus verifies XNOR(1,1) = 1.

[0087] In the third situation, where the binary input received on the input line IN i is equal to 1 and the binary value w ji stored in memory cell 12 is equal to 0, the first pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the low LRS state, while the second memristor 30 (corresponding to the one on the right) is in the high HRS state. The second memristor 30 in the high HRS state then pushes the voltage from the source line SL j back to the bit line BL j connected to the first memristor 28 in the low LRS state, as represented by arrow F2. The voltage of the source line SL j is then closer to the high potential VH of the bit line BL j than to the low potential VL for the complementary bit line BLb j, and is therefore greater than the mid-voltage [V(BL)+V(BLb)] / 2, so that the result of the XNOR operation is equal to 0. This therefore verifies XNOR(1,0) = 0.

[0088] In the fourth and final situation, where the binary input received on the input line IN i is equal to 0 and the binary value w ji stored in memory cell 12 is equal to 1, the second pair of memristors 28, 30 is activated, and the first memristor 28 (corresponding to the one on the left) is in the low LRS state, while the second memristor 30 (corresponding to the one on the right) is in the high HRS state. The second memristor 30 in the high HRS state then pushes the voltage from the source line SL j back to the bit line BL j connected to the first memristor 28 in the low LRS state, as represented by arrow F2. The voltage of the source line SL j is then greater than the midpoint voltage [V(BL)+V(BLb)] / 2, and the result of the XNOR operation is therefore equal to 0. This therefore verifies XNOR(0,1) = 0.

[0089] Those skilled in the art will of course understand that, also with an inverted coding logic where the binary value 1 stored in memory cell 12 is encoded as the first memristor 28 in the low state LRS and the second memristor 30 in the high state HRS, and consequently the binary value 0 is encoded as the first memristor 28 in the high state HRS and the second memristor 30 in the low state LRS, each memory cell 12 in the examples of figures 2 , 4 And 7 always allows the XNOR operation to be performed, and the result of the XNOR operation is then equal to 0 if the voltage of the source line SL is less than the mid-voltage [V(BL)+V(BLb)] / 2, and conversely equal to 1 if the voltage of the source line SL is greater than the mid-voltage [V(BL)+V(BLb)] / 2, this always assuming that the high potential VH is applied to the bit line BL, while the low potential VL is applied to the complementary bit line BLb.

[0090] Of course, assuming that the potentials were applied to the complementary bit lines BL, BLb in reverse order compared to the above, with the high potential VH applied to the complementary bit line BLb and the low potential VL applied to the bit line BL, then the logic of comparing the voltage of the source line SL with the mid voltage to determine the result of the XNOR operation would also be reversed.

[0091] There figure 5 This then concerns the overall voltage distributions obtained on the source line SL j, that is, at the bottom of the source line SL j in the examples of figures 1 And 7 , when several input lines IN i are used simultaneously, the voltage distribution graph shown in the figure 5 illustrating the case where five IN i input lines are used simultaneously.

[0092] This example of the figure 5 This particularly concerns the case of inference in a binary neural network. To better understand what follows, it can be observed that a binary neural network exhibits a specific characteristic in inference compared to a classical neural network.

[0093] When a classical neural network is applied to an input vector to calculate an output vector, each neuron receives input values ​​corresponding to output values ​​from neurons in a previous layer. a j and calculates a weighted sum Σ j W ij . a j and the neuron then applies a non-linear function f to the result of the weighted sum.

[0094] In contrast, in a binary neural network, the weighted sum is obtained by performing the following operation: a j = sign popcount i XNOR w ji x i − T j Or a j represents the output value calculated by the neuron, x i represent the input values ​​for said neuron, w ji represent the respective binary weights associated with said neuron for each of the inputs; XNOR is the logical operation of not-exclusive-or; popcount i is the function that counts the number of 1s in a series of bits, when i varies between 1 and the number n of inputs; T j is a predefined threshold, and sign is a function that associates the value 1 with a positive input and associates -1 with a negative value.

[0095] When input values ​​are applied to the n input lines IN i, where n represents the number of input lines IN i, n word lines are activated from among the 2n complementary word lines WL i, WLb i. This then forms a divider bridge between bit line BL j and the complementary bit line BLb j, as shown in the upper part of the figure 5 , where a first equivalent resistance R BL corresponds to the equivalent resistance for the portion of the divider bridge connected between the bit line BL j and the source line SL j , and a second equivalent resistance R BLb corresponds to the equivalent resistance for the portion of the divider bridge connected between the complementary bit line BLb j and the source line SL j .

[0096] Based on the above, particularly in light of the example of the figure 4 If the result of the XNOR operation is equal to 1, then the first memristor 28 to the left of the SL j source line is in the high (HRS) state and the second memristor 30 to the right of the SL j source line is in the low (LRS) state. Conversely, if the result of the XNOR operation is equal to 0, then the first memristor 28 to the left of the SL j source line is in the low (LRS) state and the second memristor 30 to the right of the SL j source line is in the high (HRS) state.

[0097] For the first equivalent resistance R BL corresponding to the portion of the voltage divider to the left of the source line SL j, the number of high-state memristors HRS, denoted #HRS on the figure 5 , is then equal to pop, where pop is equal to the result of the function popcount in the preceding equation (1) where the input values ​​xi are the input values ​​applied to the n input lines IN i, and for the first equivalent resistance R BL the number of low-state memristors LRS, denoted #LRS on the figure 5 , is then equal to n-pop, n representing the number of input lines IN i .

[0098] In the example of the figure 5 The first equivalent resistance RBL then satisfies the following equation: 1 R BL = pop HRS + n − pop LRS = pL + H n − p HL = p L − H + nH HL where R BL represents the first equivalent resistance, pop, or the abbreviated notation p, is equal to the result of the function popcount of the previous equation (1), n ​​representing the number of input lines IN i, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or the abbreviated notation L, represents the resistance of the memristor 28, 30 in the low state LRS.

[0099] As a corollary, for the second equivalent resistance R BLb corresponding to the portion of the divider bridge to the right of the source line SL j, the number #LRS of memristors in the low state LRS is then equal to pop, the number #HRS of memristors in the high state HRS is then equal to n-pop.

[0100] In the example of the figure 5 , the second equivalent resistance R BLb then satisfies the following equation: 1 R BLb = pop LRS + n − pop HRS = pH + L n − p HL = p H − L + nL HL where R BLb represents the second equivalent resistance, pop, or the abbreviated notation p, is equal to the result of the function popcount of the previous equation (1), n ​​representing the number of input lines IN i, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or the abbreviated notation L, represents the resistance of the memristor 28, 30 in the low state LRS.

[0101] According to the previous equations (2) and (3), the voltage of the source line SL then satisfies the following equation: V SL − V BLb = R BLb R BL + R BLb ∗ ΔBL = HL p H − L + nL ∗ 1 HL p L − H + nH + HL p H − L + nL ∗ ΔBL = 1 p H − L + nL p L − H + nH + 1 where V(SL) represents the voltage of the source line SL, V(BLb) represents the voltage of the complementary bit line BLb, and ΔBL represents the voltage differential between the voltage of the bit line BL and the voltage of the complementary bit line BLb according to the following equation: ΔBL = V BL − V BLb

[0102] After simplification, the voltage of the source line SL then satisfies the following equation: V SL = n ∗ HRS + pop ∗ LRS − HRS n L + H ∗ ΔBL + V BLb where V(SL) represents the voltage of the source line SL, V(BLb) represents the voltage of the complementary bit line BLb, ΔBL represents the voltage difference between the voltage of the bit line BL and the voltage of the complementary bit line BLb according to equation (5), pop is equal to the result of the function popcount of the previous equation (1), n ​​representing the number of input lines IN i, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or the abbreviated notation L, represents the resistance of the memristor 28, 30 in the low state LRS.

[0103] A person skilled in the art will observe that the preceding equation (6) depends on the value pop, that is, the result of the function popcount from equation (1) above. The larger the pop value, the larger the term |pop * (LRS - HRS)| will be, and since the term pop * (LRS - HRS) is negative because HRS > LRS, the smaller the term n * HRS + pop * (LRS - HRS) will be. Therefore, the larger the pop value, the lower the voltage of the source line SL will be, and the closer it will be to the voltage of the complementary bit line BLb.

[0104] Due to the variability of memristors in operation, as described previously with regard to the figure 3 A distribution 40 of the voltages of the source line SL according to the preceding equation (6) comprises a plurality of lobes 42, each lobe 42 representing a probability density of the voltage of the source line SL for a given value pop. The number of lobes 42 contained in the distribution 40 is then equal to the number of possible values ​​of the value pop, that is to say n+1, with n representing the number of input lines IN i.

[0105] The number of threshold values ​​needed to determine the voltage value of the source line SL among these n+1 lobes 42 is then equal to n, these threshold values ​​th being denoted respectively th=0 to th=n-1 in the example of the figure 5 , with n=5.

[0106] The reading module 24 will now be described in more detail, with regard to the figures 5 à 9 .

[0107] The reading module 24 includes a logic unit 50 for each column 18, each logic unit 50 comprising at least one input terminal 52 connected to a respective source line SL to receive an input value called the column value, and an output terminal 54. The logic unit 50 is suitable for performing a logic operation having a switch between a low value and a high value, depending on a comparison of the column value with a switching threshold value INV th, during the calculation operation, the result, denoted a, of the logic operation being delivered to the output terminal 54.

[0108] According to the invention, the reading module 24 further comprises a modification unit 60 adapted to modify, for at least one logic unit 50 and according to the desired calculation operation, a difference between the column value and the INVth switching threshold value. In other words, the modification unit is adapted to modify, for at least one logic unit 50 and according to the desired calculation operation, the INVth switching threshold value relative to the column value.

[0109] The logical operation performed by the logic unit 50 is preferably an inversion, the logic unit 50 typically being a simple inverter. The logic unit 50 is then designed to receive an incident signal at its input terminal 52 and to perform a logical inversion calculation in order to output at its output terminal 54 an output signal that is the inverse of the incident signal.

[0110] Logic unit 50 may have other "inputs" besides input terminal 52 connected to the source line SL, but these other inputs must have a neutral value during the calculation operation; they are therefore neutralized. Consequently, the output value of logic unit 50 depends solely on the value present on the source line SL during the calculation operation, that is, the value received at input terminal 52. Outside of calculation operations, any other inputs of logic unit 50 may have non-neutral values.

[0111] As an example from the previous paragraph, logic unit 50 is an XOR gate with an input set to 0. XOR is the English name for the logical operation "exclusive OR". In another example, logic unit 50 is a NAND gate with an input set to 1. NAND is the English name for the "not AND" operand. In yet another example, logic unit 50 is a NOR gate with an input set to 0. NOR is the English name for the "not OR" operand.

[0112] A person skilled in the art will understand that logic unit 50 does not necessarily perform an inversion operation in its entirety, but may contain two inverters in series to form a non-inverting logic gate. That being said, logic unit 50 includes the equivalent of at least one inverter, and the switching threshold value against which the source line voltage SL is compared corresponds to the switching threshold value INVth of the inverter or the equivalent inverter of a more complex logic gate whose other inputs are disabled.

[0113] A person skilled in the art will then observe that if the reading module 24 comprises only the modification unit 60 in the form of a simple inverter, then the reading module 24 can compare the voltage of the source line SL with a single switching threshold value INV th, as shown as an example of the prior art in the lower part of the figure 5 In this example, the single INV threshold value, also called the inversion threshold or switching threshold, is chosen to be 0.6 V, the midpoint between the chosen complementary bit line BLb voltage of 0.3 V and the chosen bit line BL voltage of 0.9 V. In this example, if the pop value, that is, the result of the function popcount, If the value is greater than a midpoint threshold, i.e., equal to 3, 4, or 5, then the voltage of the source line SL is less than 0.6V, and logic unit 50 will output a value of 1 at its output terminal 54, with the voltage U50 at output terminal 54 (represented by a dashed line) being VDD. If the value pop is less than the midpoint threshold, i.e., equal to 0, 1, or 2, then the voltage of the source line SL is greater than 0.6V, and logic unit 50 will output a value of 0 at its output terminal 54, with the voltage U50 at output terminal 54 being 0.

[0114] Thus, with a simple inverter, it is possible to compare the pop value with a threshold, such as the midpoint threshold. However, this is insufficient for performing neural network operations, where the threshold value is not fixed to the average value. This is why the prior art generally uses a full bottom-column comparator to compare the pop value to any threshold defined during training. However, using a bottom-column comparator requires a large area (much larger than a simple inverter), significant power consumption, and low parallelism due to bottom-column multiplexing.

[0115] According to the invention, the modification unit 60 then allows modification, for at least one logic unit 50 and according to the desired calculation operation, of the difference between the column value and the INV th switching threshold value, that is to say, to modify the INV th switching threshold value with respect to the column value.

[0116] The modification unit 60 then allows, in particular, the comparison of the pop value, that is to say the result of the function popcount, at any threshold value, with only the logic unit 50 at the bottom of the column, typically in simple inverter form, as illustrated on the figures 7 à 9 .

[0117] The modification unit 60 is, for example, suitable for modifying the difference between the column value and the INV th flip value for a respective logic unit 50, by commanding a modification of the complementary voltages applied to the complementary bit line pair BL, BLb for column 18 associated with said logic unit 50.

[0118] In the example of the figure 6 , to obtain the first threshold th=0 of the figure 5 The voltage of the complementary bit line BLb is controlled to the value INV th - 5*Δth, i.e., for example, 0.1 V, and the voltage of the bit line BL is controlled to the value INV tn +Δth, i.e., for example, 0.7 V, while the switching threshold value INV th remains unchanged, remaining equal to 0.6 V in this example. To obtain the second threshold th=1 of the figure 5 The voltage of the complementary bit line BLb is controlled to the value INV th - 4*Δth, i.e., for example, 0.2 V, and the voltage of the bit line BL is controlled to the value INV th + 2*Δth, i.e., for example, 0.8 V, while the switching threshold value INV th remains unchanged, for example, at 0.6 V. To obtain the third threshold th=2 of the figure 5 The voltage of the complementary bit line BLb is controlled to the value INV th - 3*Δth, i.e., for example, 0.3 V, and the voltage of the bit line BL is controlled to the value INV th + 3*Δth, i.e., for example, 0.9 V, while the switching threshold value INV th remains unchanged, for example, at 0.6 V. To obtain the fourth threshold th=3 of the figure 5 The voltage of the complementary bit line BLb is controlled to the value INV th - 2*Δth, i.e., for example, 0.4 V, and the voltage of the bit line BL is controlled to the value INV th + 4*Δth, i.e., for example, 1 V, while the switching threshold value INV th remains unchanged, for example, at 0.6 V. Finally, to obtain the fifth threshold th=4 of the figure 5 , the voltage of the complementary bit line BLb is controlled to the value INV th -Δth, i.e. for example 0.5 V, and the voltage of the bit line BL is controlled to the value INV th +5*Δth, i.e. for example 1.1 V, while the switching threshold value INV th , is unchanged, i.e. 0.6 V.

[0119] The person skilled in the art will observe that in this example of the figure 6 , the modification of the complementary voltages of the complementary bit line pair BL, BLb is carried out with a variation according to a variation step Δth from one threshold to the next.

[0120] The step size Δth satisfies, for example, the following equation: Δth = p + 1 L + H n − p − 1 n L + H − pL + H n − p n L + H ∗ ΔBL = H − L n L + H ∗ ΔBL where ΔBL represents the voltage difference between the voltage of the bit line BL and the voltage of the complementary bit line BLb according to equation (5), pop, or the abbreviated notation p, is equal to the result of the function popcount of the previous equation (1), n ​​representing the number of input lines IN i, HRS, or the abbreviated notation H, represents the resistance of the memristor 28, 30 in the high state HRS, and LRS, or the abbreviated notation L, represents the resistance of the memristor 28, 30 in the low state LRS.

[0121] Alternatively, not shown, the modification unit 60 is suitable for modifying the difference between the column value and the INV th switching threshold value for a respective logic unit 50, by commanding a modification of the INV th switching threshold value of said logic unit 5.

[0122] According to this variant, the INV th switching threshold value is modified for example via a change in the supply voltage of said logic unit 50, or via a change in the bias voltage of a back gate of at least one transistor of said logic unit 50, or via both the change in supply voltage and the change in bias voltage.

[0123] As an optional complement, the modification unit 60 is used to incrementally modify, according to a predefined increment step, the difference between the column value and the switching threshold value INV th, to determine—from among a plurality of possible predefined values—a resulting value corresponding to the voltage of the respective source line SL, i.e., corresponding to the column value. The increment step depends on the plurality of possible values. According to this optional complement, the increment step is, for example, equal to the variation step Δth defined previously.

[0124] When the computational operation performed is a neural computation operation, such as the MAC operation, the electronic circuit 10 according to the invention, with the set of memory cells 12 organized according to the matrix 14 comprising n rows 16 and m columns 18, then makes it possible to implement a neural network 65 with n inputs and m outputs, such as a fully connected neural network (from the English fully connected ), as represented in the figure 7 In the example of the figure 7 , the electronic circuit 10 then comprises n*m memory cells 12, each comprising two pairs of memristors 28, 30 and two pairs of switches 32, 34, i.e. n*m 4T4R type cells; as well as n pairs of complementary word lines WL, WLb, i.e. 2*n word lines WL, WLb; m source lines SL; and m pairs of complementary bit lines BL, BLb, i.e. 2*m bit lines BL, BLb.

[0125] Due to the high variability of memristors 28 and 30, the electronic circuit 10 is preferentially limited to 9 simultaneously activated inputs, i.e., n equals 9. In cases where the neural networks used require neurons larger than 9 inputs (which is very common), it is advantageous to divide the overall neuron into segments of 9 inputs and sum the MAC results of each segment to obtain the overall pop count, which is then compared to the neuron's own threshold. This division of the overall neuron into segments of 9 inputs is well-known and even has a practical application, since standard convolution filters have a size of 3 by 3, i.e., 9 inputs in total.

[0126] Therefore, the generation of the voltages of the complementary bit-line pairs BL, BLb is advantageously shared across all columns 18 of the matrix 14, thus reducing the complexity of generating the voltage shifts of the complementary bit-line pairs BL, BLb, described previously to successively modify the INV switching threshold value th relative to the column value. All thresholds th=0 to th=n-1 are then preferentially tested successively in ascending order, or alternatively in descending order, resulting at the output of each logic unit 50 in a bit sequence that corresponds to the value of the 9-input partial MAC. This bit sequence can also be interpreted using a thermometric-type encoding, similar to one-hot encoding. This bit sequence contains a series of 1s that correspond to thresholds lower than the pop value (result of the function popcount ).

[0127] As an optional complement, the reading module 24 further includes an extinction unit 70 for each column 18, each extinction unit 70 being suitable - after determination of the resulting value for the respective column 18 and pending the determination of all the resulting values ​​for a respective group of columns 18 - for controlling the application of the same voltage to the pair of complementary bit lines BL, BLb for the circulation of substantially zero current in the source line SL of the respective column 18.

[0128] Each extinction unit 70 then limits the current consumption at the output of the corresponding source line SL by "switching off" the corresponding column as soon as it obtains its first "1" at the output of the logic unit 50. Furthermore, a complete one-hot encoding is then achieved, as shown in the figure 8 , without the unnecessary continuation of 1.

[0129] The second controller 20, which controls the complementary bit line pairs BL, BLb, generally contains two two-input multiplexers 72, one for each bit line BL, BLb. Each multiplexer 72 is useful for conventional read and write operations. These multiplexers 72 are controlled by control bits stored in registers. Each extinction unit 70 is then obtained, for example, by connecting the output of each logic unit 50 to the reset signal clr (from the English clear Or reset ), of a control flip-flop 74 of its respective complementary bit line BLb, this via an AND logic gate 76, which is also connected to a global erase signal CLR_G, as shown in the example of the figure 8 In the example of the figure 8 , the other flip-flop 78 is a control flip-flop for the respective BL bit line.

[0130] In the example of the figure 8 At the end of each voltage shift of the complementary bitline pairs BL and BLb, if the output of logic unit 50 is a "1", this output will clear the control flip-flop 74 for the respective complementary bitline BLb in the following cycle, thus setting the voltages of the two complementary bitline pairs BL and BLb to the voltage of the BL bitline, i.e., to the high voltage VH, and resulting in zero current in the relevant column 18, and then a "0" at the output of the corresponding logic unit 50. In this example, it is simply necessary to start with the highest threshold, decrementing towards the lowest threshold. On the figure 8 , the direction of the temporal evolution for the succession of bits at the output of each logic unit 50 is represented by the arrow F3.

[0131] As an optional addition, the successive outputs of the logical units 50 are stored in registers specific to each column 18.

[0132] As an optional addition, the reading module 24 also includes a memory unit 80 for each column 18, each memory unit 80 being used to store the resulting value determined for the respective column 18, pending the determination of all the resulting values ​​for a respective group of several columns 18.

[0133] Each memory unit 80 preferably includes a bit register 82 for storing the determined resulting value in binary form. Each memory unit 80 is advantageously in the form of the bit register 82.

[0134] According to this optional addition, in the example of the figure 9 Each logic unit output 50 is connected to a respective bit register 82, each output driving the "enable" signal 84 of the associated register 82. This register 82 typically contains 4 bits, as only 4 bits are needed to encode a MAC operation whose value varies between 0 and 9. The registers 82 also have a clock input 85 receiving a clock signal CLK and a common input 86 parallel to all registers 82. This common input 86 is driven by a counter (or down-counter) 88. The counter (or down-counter) 88 is advantageously the same as that used in the control of the complementary bit line pairs BL, BLb.

[0135] There figure 9 illustrates the overall operation of such memory units 80, with a chronogram showing two cases: in dark grey a column with a MAC equal to 9, and in light grey a column with a MAC equal to 3.

[0136] After selecting the IN input lines corresponding to the neuron inputs, the voltages of the complementary bitline pairs BL, BLb corresponding to the first desired threshold (for example, here the highest threshold) are first applied to the complementary bitline pairs BL, BLb. The output, denoted inv[0], of logic unit 50 in the shaded column is set to 1, because its MAC operation, denoted MAC[0], is at its maximum and equal to 9. Therefore, when the CLK clock of registers 82 goes high, register 82 in the shaded column captures the binary code of counter 88, which corresponds to the value 9.Subsequently, at the edge of the global clear signal CLR_G, the control flip-flop 74 for the complementary bit line BLb of the hatched column is cleared, equalizing—for example, at the high potential VH—the voltages of the complementary bit line pairs BL, BLb of this column 18, to "turn it off" in the subsequent calculations with the remaining thresholds, setting the output of its logic unit 50, denoted inv[0], to 0. As for the column filled with dots, the output, denoted inv[1], of its logic unit 50 remains at 0 until the threshold cycle "3", where it toggles to 1 because its MAC operation, denoted MAC[1], is equal to 3, and then follows the same sequence as the hatched column.

[0137] Simulations of this 9-input neuron show excellent results. Indeed, when the variability of the transistors forming switches 32 and 34 is not simulated, the error rate at the output of logic unit 50 is zero in all cases, that is, regardless of the pop value resulting from the function popcount and whatever the value of the threshold. When said variability of the transistors is simulated, the error rate at the output of the logic unit 50 is similar to that of a classical approach, while observing that the power consumption with the electronic circuit 10 according to the invention is then significantly lower, typically more than 80 times lower, than that of the prior art circuit, for better or equivalent latency.

[0138] A person skilled in the art will then observe that the electronic circuit 10 according to the invention makes it possible to efficiently perform the neural computing operation, such as the MAC operation according to the preceding equation (1), while requiring a small area for the components implementing said operation, while also having low power consumption, and offering an increased possibility of parallelism, as shown in the figure 7 notably.

[0139] In the example of the figure 10 , each memory cell 12 has a single pair of memristors 28, 30, i.e. a single first memristor 28 and a single second memristor 30, and a single pair of switches 32, 34, i.e. a single first switch 32 and a single second switch 34.

[0140] Following the example of the figure 10 , each memory cell 12 is also capable of storing at least one binary value, such as a binary weight, in particular a respective binary synaptic weight of the neural network when the computational operation performed is a neural computational operation.

[0141] The encoding of each memory cell 12 is, for example, that described in the article « Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control » from L. Wang et al. (2021). Each column 18 also has a pair of complementary bit lines BL, BLb and a source line SL. Each row 16 then has a single word line WL. The first and second memristors 28, 30 are used to encode each weight in differential (HRS-LRS or LRS-HRS), analogously to what was described previously. A voltage is then applied between the complementary bit lines BL, BLb of column 18, creating a resistive bridge between the memristors on the left and right sides of column 18. The resulting voltage corresponds to the result of the MAC operation, this time performed with an AND operation. AND ), rather than the XNOR operation described earlier.

[0142] To avoid having an even number of 12 memory cells activated at times, a WL_p parity word line is added. This WL_p parity word line is configured to activate 2T2R type 12 memory cells (encoded as HRS, LRS), which would activate if the number of IN inputs is even. Therefore, the voltage distributions will always be on either side of the logic unit threshold. This WL_p parity word line is particularly advantageous when the calculation operation is a Logic Majority operation.

[0143] Once this symmetry issue is resolved, the number of threshold shifts via variations in the voltages of the complementary bitline pairs BL, BLb is adapted to the number of active WL word lines. The maximum value of the counter (or down-counter) 88 is then equal to the number of active WL word lines plus one. The voltages of the complementary bitline pairs BL, BLb that are symmetrical with respect to the inverter threshold correspond to the middle threshold; an upward shift will correspond to a lower threshold, and a downward shift will correspond to a higher threshold. In the case where the number of WL word lines is even, those skilled in the art will understand that the "lowest" threshold, which simply corresponds to memory cell 12 associated with the parity word line WL_p, should not be considered.

[0144] The advantage of this example of the figure 10 is that by activating only the necessary WL word lines, the current in columns 18 is greatly reduced. Furthermore, the memory cell 12 used is a 2T2R cell, rather than a 4T4R memory cell as in the examples of figures 2 , 4 And 7 Furthermore, this example of the figure 10 allows the number of threshold shifts to be reduced via variations in the voltages of the complementary bit line pairs BL, BLb, this number adapting according to the number of word lines WL activated.

[0145] Alternatively, no parity word line is added, and the electronic circuit 10 then further includes a control unit configured to adapt in an analog way the voltages of the pairs of complementary bit lines BL, BLb in the case where the number of activated word lines WL is odd.

[0146] In the example of the figure 11 , the calculation operation performed by the electronic circuit 10 is an AND operation on binary operands, or an OR operation on binary operands, or a Majority operation among binary operands.

[0147] In the example of the figure 11 The distribution of voltages in the SL source line 40 is similar to that of the figure 5 , described previously, and comprises the plurality of lobes 42, each lobe 42 representing a probability density of the source line voltage SL for a given pop value. The number of lobes 42 contained in the distribution 40 is then equal to the number of possible values ​​of the source line voltage S(VL), i.e. n+1, with n representing the number of input lines IN i .

[0148] The number of threshold values ​​needed to determine the voltage value of the source line SL among these n+1 lobes 42 is then equal to n, these threshold values ​​th being denoted respectively th=0 to th=n-1 in the example of the figure 11 , with n=5.

[0149] However, when the calculation operation performed is the AND operation on binary operands, or the OR operation on binary operands, or the Majority operation among binary operands, a person skilled in the art will observe that only one threshold is necessary each time.

[0150] Indeed, the AND operation on a plurality of binary operands equals 1 if and only if all binary operands are equal to 1, and equals 0 in all other cases. The threshold is then positioned to detect this voltage probability density lobe corresponding to the case where all operands are equal to 1, and then determine whether all operands are equal to 1 or not, and finally deduce the result of the AND operation.

[0151] Conversely, the OR operation on a plurality of binary operands is equal to 0 if and only if all binary operands are equal to 0, and equal to 1 in all other cases. The threshold is then positioned so as to detect this voltage probability density lobe corresponding to the case where all operands are equal to 0, and then determine whether all operands are equal to 0 or not, and then deduce the result of the OR operation.

[0152] In the aforementioned coding logic example where the binary value is encoded as 1, with the first pair of memristors being 28, 30 (or the single pair in the example of the figure 10 ), the left memristor, i.e. the first memristor 28, is coded as high resistance (high state HRS), and the right memristor, i.e. the second memristor 30, is coded as low resistance (low state LRS), the only threshold used is then the lowest threshold to implement the AND operation (from the English AND ), and respectively the highest threshold for implementing the OR operation (from English OR ), and respectively still the middle threshold for the Majority operation, as represented on the figure 11 .

[0153] The calculation operation then allows a logical AND, OR, or Majority operation to be performed separately for each column 18 across all rows 16 of the matrix 14, but only for those rows whose WL word lines are activated. The electronic circuit 10, according to this example of the invention, thus allows several rows 16 to be activated in parallel to perform the Boolean calculation—namely, a logical AND, OR, or Majority operation—bit by bit on several parallel inputs.

[0154] In general, the value of the INV th switching threshold depends on the associated calculation operation.

[0155] In the example of the figure 11 , when the associated computational operation is the AND operation or the OR operation, the value of the INV th switching threshold is typically one voltage step away from a corresponding bit line voltage BL, BLb, the corresponding bit line voltage BL, BLb being one of the complementary bit line voltages BL, BLb for the AND operation and the other of said voltages for the OR operation.

[0156] The voltage step typically satisfies the following equation: P = ΔBL OPD + 1 where P represents the voltage step; ΔBL represents the voltage differential between the voltage of the bit line BL and the voltage of the complementary bit line BLb, and OPD represents the number of operands to which the computation operation is applied.

[0157] In the example of the figure 11 When the associated calculation operation is the Majority operation, the value of the INV switching threshold th is typically the median value of the complementary bit line voltages BL, BLb. All cases where the result of the Majority operation is equal to 1 then correspond to 42 voltage probability density lobes arranged on the same side of this median threshold; and all cases where the result of the Majority operation is equal to 0 then correspond to 42 voltage probability density lobes arranged on the other side of said median threshold.

[0158] As an optional addition, the reading module 24 also includes a combination unit 90 for at least one column 18. Each combination unit 90 is used to combine the results of logical operations performed successively by a respective logical unit 50, in order to implement a combined logical operation. The combined logical operation is typically chosen from the group consisting of: an exclusive-OR operation and an exclusive-OR operation.

[0159] Each combination unit 90 preferably includes a flip-flop 92 connected to the output of the respective logic unit 50. Each combination unit 90 is advantageously in the shape of the flip-flop 92.

[0160] According to this optional addition, in the example of the figure 12 Each logic unit output 50, denoted inv[0] for the first column 18, then inv[1] for the second column 18, and so on, is connected to a respective flip-flop 92. Each inv[i] output drives the "enable" signal 94 of the associated flip-flop 92, where i is an integer index between 0 and the number of columns 18 minus one. The flip-flops 92 also have a clock input 95 receiving a clock signal CLK and a common input 96 parallel to all the flip-flops 82. This common input 96 is driven by a control unit 98. The control unit 98 is advantageously shared with the one used in controlling the complementary bit-line pairs BL, BLb. (A vérifier par l'inventrice)

[0161] There figure 12 illustrates the overall functioning of such combination units 90, with for example a three-step sequence.

[0162] In an initial first step, marked by a circled 1, the contents of all 92 flip-flops are reset to 0 via the application of an erase signal (from English clear ), as known in itself.

[0163] In a second step, marked by a circled 2, the two operands in each column 18 to which the combined logical operation, such as an exclusive-or operation, or XOR, is to be applied are first selected via the corresponding WL word lines.

[0164] In the example of the figure 12 , during this second step, an OR operation is then performed with the two operands of each column 18, and via each respective logical unit 50, in the manner described previously opposite the figure 11 The result of each OR operation is then applied to the Enable input of the corresponding flip-flop 92 and on a subsequent edge of the clock signal CLK, by applying the value 1 to the common input 96 of the flip-flops 92. As a result, the flip-flops 92 whose Enable input is at "1" take the value "1" and the other flip-flops 92 whose Enable input is at "0" retain the value "0" corresponding to the previous reset step.

[0165] In a third step, marked by a circled 3, a new logical operation is performed with the two operands of each column 18, and via each respective logical unit 50.

[0166] In the example of the figure 12 , during this third step, an AND operation is then performed with the two operands of each column 18, and via each respective logical unit 50, in the manner described previously opposite the figure 11 An AND operation between the result of the previous OR operation and the inverse result of each AND operation (i.e., the 1's complement result of each AND operation) is then obtained in the flip-flop 92 corresponding to the next edge of the clock signal CLK, by applying the value 0 to the common input 96 of the flip-flops 92. Indeed, on the next edge of the clock signal CLK, the value 0 on the common input 96 will be forced in the flip-flops 92 for which the "enable" signal 94 is 1, that is, those for which the result of the AND operation performed in the third step is equal to 1. In other words, if the NAND operation applied with the two operands of each column 18 is equal to 1, then the "enable" signal 94 is 0, and the result of the OR operation of the second step is then retained in the corresponding flip-flop 92.

[0167] In other words, in the example of the figure 12 , the combination unit 90 then allows us to perform an exclusive OR operation, denoted XOR, with the two operands of each column 18, given the following equation: XOR a b = a OR b AND a AND b ¯ = a + b ⋅ a ⋅ b ¯ where XOR denotes the exclusive OR operation; a and b represent the two operands; OR, or "+", denotes the logical OR operation; AND, or ".", denotes the logical AND operation; and - represents the NOT operator.

[0168] In the example of the figure 12 , the result of the combined logic operation, obtained in each flip-flop 92 at the end of the sequence is then noted OP[i], with i an integer index between 0 and the number of columns 18 minus one, i.e. OP[0] for the first column 18, then OP[1] for the second column 18, and so on.

[0169] A person skilled in the art will then understand that the 92 flip-flops more generally allow the implementation of any type of combination of AND or OR logical operations to perform combined logical operations, the AND or OR logical operations being carried out via the 50 logic units, as described previously in relation to the figure 11 .

[0170] The person skilled in the art will also observe that, if only the first two steps identified by the circled 1 and 2 are implemented, the flip-flops 92 then form a means of storing the result of the logical operations performed by the logical units 50.

[0171] According to an optional complementary aspect, the electronic circuit 10 according to the invention further comprises additional switches, not shown, configured to connect together the source lines SL of a group of several columns 18, and then perform the logical operations by group of columns 18, rather than by group of rows 16.

[0172] According to this additional aspect, the logical unit 50 used to perform the logical operation for said group of columns 18 is preferably the one connected to the source line SL which is able to be connected to all the other source lines SL of the columns 18 of the group.

[0173] According to this complementary aspect, all source lines SL are optionally connected to each other via the additional switches, which are then advantageously configured to be all closed during each calculation operation. If necessary, the second controller 22 inhibits the column(s) 18 not belonging to the group of columns 18 for which the logical operation is to be performed, by applying a high-impedance potential to the complementary bit line pairs BL, BLb of said column(s) 18 not belonging to the group of columns 18. This then simplifies the control of the additional switches.

[0174] It should be noted that it is possible in practice to combine, at the same time, the two possibilities of "combining operands" in columns 18 or in rows 16 by selecting operands on several rows 16 and linking the columns 18 as described above via a connection between their SL source lines.

[0175] In the examples of figures 2 , 4 , 7 And 10 , each memristor 28, 30 of a respective memory cell 12 is connected to the same source line SL and to a respective switch 32, 34.

[0176] Those skilled in the art will understand that, in an alternative (not shown), each memory cell 12 in a respective column 18 comprises at least one pair of subcells (not shown), each subcell having a memristor 28, 30 and a switch 32, 34, each memristor 28, 30 of a respective subcell being connected to a source line and to a respective switch 32, 34. Similarly, the memristors 28, 30 of each pair of subcells then store a binary value by presenting different first and second resistance values. Likewise, the switches 32, 34 are connected, for their activation, to a respective word line WL and are connected respectively to a pair of complementary bit lines BL, BLb, the two switches 32, 34 of a respective pair of subcells being connected to the same word line WL.

[0177] According to this variant, the two source lines associated with a respective pair of sub-cells are then connected together during each calculation operation via an auxiliary switch, not shown, to form the same source line SL, also called the common source line for the memory cells 12 of the same column 18, to which each memristor 28, 30 of a respective memory cell 12 is connected during each calculation operation.

[0178] It is thus understood that the electronic circuit 10 according to the invention makes it possible to determine more efficiently a resulting value corresponding to the voltage of the respective source line SL, by virtue of its reading module 24 comprising a logic unit 50 for each column 18 and the modification unit 60 suitable for modifying, for at least one logic unit 50 and according to the calculation operation, the difference between the column value and the switching threshold value INV th of the corresponding logic unit 50.

Claims

1. An electronic circuit (10) suitable for implementing computation operations each providing a binary output, the circuit comprising: - word lines (WL); - pairs of complementary bit lines (BL, BLb); - source lines (SL); - a set of memory cells (12) organized in a matrix (14) including rows (16) and columns (18), the memory cells (12) of the same row (16) being selectable by at least one word line (WL), the memory cells (12) of the same column (18) being linked to a pair of complementary bit lines (BL, BLb) and at least one source line (SL); each memory cell (12) having at least one pair of memristors and at least one pair of switches, each memristor of a respective memory cell (12) being connected to a respective switch and linked to the same source line (SL) during each computation operation, each pair of memristors correspondingly storing a binary value presenting, correspondingly, first and second different resistance values; the switches being linked, for activation, to a respective word line (WL) and correspondingly linked to a pair of complementary bit lines (BL, BLb), the two switches of a respective pair being linked to the same word line (WL); - a reading module (24) implemented during each computation operation, the reading module (24) including: + a logic unit (50) for each column (18), each logic unit (50) comprising at least one input terminal (52) connected to a respective source line (SL), for receiving an input value called a column value, the logic unit (50) being suitable for performing a logic operation which toggles between a low value and a high value depending on a comparison of the column value with a toggle threshold value (INVth), during the computation operation, the logic unit (50) forming a logic inverter during the computation operation, characterized in that the reading module (24) includes: + a modification unit (60) suitable for modifying, for at least one logic unit (50) and according to the desired computation operation, a difference between the column value and the toggle threshold value (INVth).

2. The electronic circuit (10) according to claim 1, wherein the modification unit (60) is suitable for modifying the difference between the column value and the toggle value (INVth) for a respective logic unit (50), by commanding a modification of the complementary voltages applied to the pair of complementary bit lines (BL, BLb) for the column (18) associated with said logic unit (50).

3. The electronic circuit (10) according to claim 1 or 2, wherein the modification unit (60) is suitable for modifying the difference between the column value and the threshold value for a respective logic unit (50), by commanding a modification of the threshold value of said logic unit (50); said threshold value being preferentially modified via by change in the supply voltage of said logic unit (50) and / or by a change in the bias voltage of a rear gate of at least one transistor of said logic unit (50).

4. The electronic circuit (10) according to any of the preceding claims, wherein the modification unit (60) is suitable for modifying, incrementally according to a predefined incrementation step, said difference between the column value and the toggle threshold value (INVth), for determining - among a plurality of predefined possible values - a resulting value corresponding to the voltage of the respective source line (SL) corresponding to said column value; the incrementation step depending on said plurality of possible values.

5. The electronic circuit (10) according to claim 4, wherein the reading module (24) further includes a storage unit (80) for at least one column (18), each storage unit (80) being suitable for storing the resulting value determined for the respective column (18), pending the determination of all the resulting values for a respective group of a plurality of columns (18); each storage unit (80) preferentially including a bit register (82) for storing said determined resulting value in binary form.

6. The electronic circuit (10) according to claim 4 or 5, wherein the reading module (24) further includes an extinction unit (70) for each column (18), each extinction unit (70) being suitable - after determining the resulting value for the respective column (18) and pending determination of all the resulting values for a respective group - for commanding the application of the same voltage to the pair of complementary bit lines (BL, BLb) for the circulation of a substantially zero current in the source line (SL) of the respective column (18).

7. The electronic circuit (10) according to any of the preceding claims, wherein each memory cell (12) includes two pairs of memristors and two pairs of switches.

8. The electronic circuit (10) according to claim 7, wherein a first pair of switches (32, 34) is linked to a first word line (WL) assigned to an input (IN), and a second pair of switches (34, 32), respectively, is linked to a second word line (WLb) assigned to the inverse of said input (IN); and wherein a first pair of memristors (28, 30) is associated with the first pair of switches (32, 34) and storing a binary value (w), and a second pair of memristors (30, 28), respectively, being associated with the second pair of switches (34, 32) and storing the inverse of the same binary value (w);9. The electronic circuit (10) according to any of claims 1 to 6, wherein each memory cell (12) includes only one pair of memristors and only one pair of switches, each pair of memristors correspondingly storing a synaptic weight.

10. The electronic circuit (10) according to any of the preceding claims, wherein the logic operation performed by the logic unit (50) is an inversion, and the associated computation operation is chosen from: a neural computation operation, such as the MAC operation; an AND operation; an OR operation; a Majority operation.

11. The electronic circuit (10) according to any of the preceding claims, wherein the value of the toggle threshold (INVth) depends on the associated computation operation; when the associated computation operation is the AND operation or the OR operation, the value of the toggle threshold (INVth) being preferentially at a voltage step of a voltage of a corresponding bit line (BL, BLb), the corresponding voltage of the bit line (BL, BLb) being one of the voltages of the complementary bit lines (BL, BLb) for the AND operation and the other of the voltages complementary bit lines for the OR operation, the voltage step satisfying the following equation: P = ΔBL OPD + 1 where P represents the voltage step; ΔBL represents the voltage differential between the voltage of the bit line (BL) and the voltage of the complementary bit line (BLb), and OPD represents the number of operands to which the computation operation is applied; when the associated computation operation is the Majority operation, the value of the toggle threshold (IN th) preferentially being a median value of the voltages of the complementary bit lines (BL, BLb).

12. The electronic circuit (10) according to claim 10 or 11, wherein the reading module (24) further comprises a combination unit (90) for at least one column (18), each combination unit (90) being suitable for combining the results of logic operations performed successively by a respective logic unit (50), for implementing a combined logic operation; each combination unit (90) preferentially including a flip-flop (92) connected to the output of the respective logic unit (50); the combined logic operation being preferentially further chosen from the group consisting of: an exclusive OR operation and an exclusive NOR.

13. The electronic circuit (10) according to any of the preceding claims, wherein the logic unit (50) is a logic gate having an output and performing a Boolean function between a plurality of inputs, one input being the input terminal (52) connected to the source line (SL) and the other input(s) being positioned in a neutral logic state during the computation operation, so that the logic unit (50) behaves as an inverter between the input terminal (52) connected to the source line (SL) and the output.

14. The electronic circuit (10) according to any of the preceding claim, wherein each memory cell (12) of a respective column (18) comprises at least one pair of sub-cells, each sub-cell including a memristor and a switch, each memristor of a respective sub-cell being connected to a respective source line and switch, the memristors of each pair of sub-cells correspondingly storing a binary value by correspondingly presenting first and second different resistance values; the switches being linked, for the activation thereof, to a respective word line (WL) and correspondingly linked to a pair of complementary bit lines (BL, BLb), the two switches of a respective pair of sub-cells being linked to the same word line (WL); the two source lines associated with a respective pair of sub-cells being connected to each other via an auxiliary switch during each computation operation and then forming the same source line (SL) to which each memristor of a respective memory cell (12) is linked during each computation operation.

15. The electronic circuit (10) according to any of the preceding claims, wherein the electronic circuit (10) is a neuromorphic circuit suitable for implementing a neural network with binary output, each memory cell (12) being associated with a respective synaptic weight of a neuron, and the word lines (WL) being apt to receive input voltages during a neural computation.

16. The electronic circuit (10) according to any of the preceding claims, comprising a first controller (20) for selecting the memory cells (12) of a row (16) which are linked to the same word line (WL), and comprising a second controller (22) linked to the pairs of bit lines (BL, BLb) and used for applying different voltages to each pair bit line (BL, BLb) and symmetrical with respect to a middle voltage, the voltage applied to a bit line (BL) being either higher or lower than the voltage applied to the associated complementary bit line (BLb).

17. The electronic circuit (10) according to any of the preceding claims, wherein the electronic circuit (10) includes a plurality of distinct sets of memory cells (12) suitable for operating in parallel.