CONTACTLESS LOAD MODULATION COMMUNICATION DEVICE WITH DYNAMIC THRESHOLD HOUR SIGNAL EXTRACTION CIRCUIT

Description

technical field

[0001] This description generally concerns the field of wireless communications between a reader and a contactless communication device using active charge modulation, particularly between a reader and such a device emulated in card mode (or CE for "Card Emulation"). This description may specifically concern the field of contactless communications implemented using NFC (Near Field Communication) technology. Previous technique

[0002] Near field communication, or NFC, is a wireless connectivity technology that enables communication over a short distance, for example on the order of ten centimeters, between electronic devices, such as a contactless smart card and a reader, or an EC device (for example a mobile phone or a connected object) and a reader.

[0003] A contactless communication device is a device capable of exchanging information via an antenna with another contactless device, for example a reader, according to a contactless communication protocol.

[0004] An NFC device, which is a contactless device, is a device compatible with NFC technology. NFC technology is an open technology platform standardized in ISO / IEC 18092 and ISO / IEC 21481, but it incorporates many existing standards, such as the Type A and Type B protocols defined in ISO 14443, which can be used as communication protocols within NFC technology.

[0005] A CE device can be used to exchange information with another contactless device, for example a contactless reader, using a contactless communication protocol usable in NFC technology.

[0006] During information transmission between a reader and an EC device or an NFC card, the reader generates an electromagnetic field via its antenna, which is generally, according to commonly used standards, a sinusoidal wave with a frequency of 13.56 MHz. Each of the NFC devices (reader and EC device) transmits data using a modulation scheme, for example, amplitude shift keying (ASK) or on-off keying (OOK).

[0007] Two operating modes are possible: a passive mode, which corresponds to the mode used by an NFC card, or an active mode, which generally corresponds to the mode used by a CE device.

[0008] In passive mode, also known as PLM or Passive Load Modulation, only the reader generates the electromagnetic field, and the card is therefore passive. The card's antenna modulates the electromagnetic field generated by the reader by modifying a load connected to the antenna terminals. This changes the output impedance of the reader's antenna due to magnetic coupling between the two antennas. This results in a change in the amplitudes and / or phases of the voltages and currents present at the reader's and card's antennas. Information is thus transmitted from the card to the reader by modulating the reader's antenna currents.

[0009] In active mode, also known as ALM or Active Load Modulation, both the reader and the CE device generate an electromagnetic field. This operating mode is used when the CE device has its own power source, such as a battery.

[0010] Generally, an EC device has a smaller antenna than an NFC card, and this is why active charge modulation is often used in such a device.

[0011] During active charge modulation, the electromagnetic fields emitted by the reader and the CE device are in phase with each other so that the detection sensitivity of the device is not reduced. The CE device may include a phase-locked loop (PLL) and a transmission circuit whose output is electrically coupled to the antenna.

[0012] The CE device can be configured to extract a clock signal from the electromagnetic field emitted by the player and lock the PLL on the rising or falling edges of this signal. This clock signal extraction is achieved, for example, by a differential comparator electrically coupled to the output of the passive array of the CE device's antenna and including, for example, a high-gain amplifier operating in saturation. The PLL's output signal can then be used to perform a digital conversion to decode the player's modulation signal.

[0013] In order for the CE device to respond to the reader, the CE device's response signal must be in phase with the electromagnetic field emitted by the reader. The clock signal extracted from the reader's electromagnetic field must therefore follow the phase and frequency of the reader's electromagnetic field and must be free from spurious variations.

[0014] In the case of OOK modulation, the electromagnetic field containing the modulation signal alternates between a high and a low state. However, noise may be present in the electromagnetic field received by the CE device when the modulation signal is low, due to coupling between the player and the CE device. The clock signal extracted from this field may then contain parasitic variations, or instabilities, which can lead to phase shifts and errors in the resulting output signal.

[0015] US patent application 2014 / 159870 A1 describes a contactless communication device by active load modulation, comprising a clock signal extraction circuit configured to receive a receive signal as input and deliver a clock signal as output having a first value when the receive signal is above a threshold of the clock signal extraction circuit and having a second value when the receive signal is below the threshold. Summary of the invention

[0016] There is a need to propose a solution that addresses the problems encountered with existing solutions.

[0017] One embodiment overcomes all or part of the drawbacks of known solutions and proposes a contactless communication device using active load modulation, comprising at least: a clock signal extraction circuit configured to receive a receive signal as input and deliver a clock signal as output having a first value when the receive signal is greater than a threshold of the clock signal extraction circuit and having a second value when the receive signal is less than the threshold; a threshold value modification circuit, configured to decrease the threshold value when the value of the clock signal is equal to the first value, or to increase the threshold value when the value of the clock signal is equal to the second value.

[0018] According to a particular embodiment, the threshold of the clock signal extraction circuit has a value of zero.

[0019] According to a particular embodiment, the clock signal extraction circuit and the threshold value modification circuit are configured such that the reduced threshold value is between 10% and 20% of a minimum amplitude of the received signal.

[0020] According to a particular embodiment, the clock signal extraction circuit includes a differential pair.

[0021] According to a particular embodiment, the clock signal extraction circuit further comprises a first current mirror electrically coupled in parallel to the differential pair.

[0022] According to a particular embodiment, the threshold value modification circuit is configured to unbalance a bias of the first current mirror of the clock signal extraction circuit or a bias of the differential pair and the first current mirror of the clock signal extraction circuit.

[0023] According to a particular embodiment, the clock signal extraction circuit further comprises an amplifier whose input is electrically coupled to one of the branches of the first current mirror.

[0024] According to a particular embodiment, the threshold value modification circuit includes a second current mirror electrically coupled to one of the branches of the first current mirror and switches configured to electrically couple the second current mirror to an electrical supply potential of the device and to a current source, itself coupled to an electrical reference potential of the device, according to the value of the clock signal.

[0025] According to a particular embodiment, the threshold value modification circuit includes a transistor and a switch configured to electrically couple the threshold value modification circuit transistor in parallel with a transistor of the differential pair when the clock signal value is equal to the first or second value.

[0026] According to a particular embodiment, the device further comprises a phase-locked loop, one input of which is electrically coupled to an output of the clock signal extraction circuit.

[0027] In one particular embodiment, the device may also include: a digital conversion circuit comprising an input electrically coupled to an output of the phase-locked loop; a transmission circuit comprising an output electrically coupled to the antenna and on which a modulation signal in phase with the received signal is intended to be delivered, and comprising a first input electrically coupled to an output of the phase-locked loop and a second input electrically coupled to an output of the digital conversion circuit. Brief description of the drawings

[0028] These features and advantages, along with others, will be described in detail in the following non-exhaustive descriptions of specific implementation examples, in relation to the attached figures, among which: there figure 1schematically represents an example of a contactless communication device using active charge modulation communicating with a contactless reader, according to a particular embodiment; the figure 2 schematically represents the operation of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit in a contactless communication device using active load modulation, according to a particular embodiment; figure 3 schematically represents a first example of the implementation of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit; figure 4 schematically represents a second example of the implementation of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit; figure 5schematically represents a variant of the second example of the implementation of a clock signal extraction circuit and a circuit for modifying the threshold value of the extraction circuit. Description of the implementation methods

[0029] The same elements have been designated by the same references in the different figures. In particular, structural and / or functional elements common to the different embodiment examples may have the same references and may have identical structural, dimensional and material properties.

[0030] For the sake of clarity, only the steps and elements necessary for understanding the described implementation methods and examples have been shown and detailed. In particular, the implementation of the various components and circuits (adaptation circuit, phase-locked loop, digital conversion circuit, transmission circuit, etc.) of the device is not detailed. A person skilled in the art will be able to implement the various functions of the device in detail based on the functional description provided here.

[0031] Unless otherwise specified, when referring to two connected elements, this means directly connected without any intermediate elements other than conductors, and when referring to two coupled elements, this means that these two elements can be connected or linked through one or more other elements.

[0032] Unless otherwise specified, the expressions "approximately", "roughly", "about", and "on the order of" mean within 10%, preferably within 5%.

[0033] An example of a 100 contactless communication device using active load modulation, according to a particular embodiment, is described below in connection with the figure 1 .

[0034] Device 100 is an NFC-enabled device, meaning it is configured to use a communication protocol compatible with NFC technology. In the example described, device 100 corresponds to a card-emulated (CE) device. On the figure 1 , device 100 is represented during communication with a contactless NFC type reader 200.

[0035] In the described embodiment, device 100 and reader 200 communicate with each other using OOK modulation. Thus, the electromagnetic field emitted by reader 200 and received by device 100 is made to change state, and to be either in a high state, transmitted as a sinusoidal signal for example with a frequency of 13.56 MHz (carrier frequency), or in a low state transmitted as a zero signal.

[0036] In the described embodiment example, the device 100 includes an antenna 102 intended to exchange data with an antenna 202 of the reader 200 via the emission of electromagnetic fields by these antennas 102, 202 and the magnetic coupling between these antennas 102, 202.

[0037] In the particular configuration shown on the figure 1The device 100 further includes an adaptation circuit 104 electrically coupling the antenna 102 to the other elements of the device 100. The circuit 104 may include passive components, and may be used in particular to adapt the impedance of the antenna 102 to interface the input and output signals of the antenna 102.

[0038] The device 100 further includes a clock signal extraction circuit 106 configured in particular to receive as input a reception signal from a magnetic field intended to be received by the antenna 102 and delivered at the output of the matching circuit 104. The circuit 106 is also configured to deliver at output a clock signal having a first value, for example "1" or high state, when the reception signal is greater than a threshold value of the circuit 106 and having a second value, for example "0" or low state, when the reception signal is less than the threshold value of the circuit 106. In this example, the circuit 106 therefore forms a comparator delivering at output a clock signal extracted from the reception signal applied to its input.

[0039] In the example described, when the signal received by antenna 102 corresponds to a high state transmitted as a sinusoidal signal, the value of the clock signal delivered at the output of circuit 106 alternates between the first and second values ​​at a frequency equal to the frequency of the sinusoidal signal for the entire duration of this high state. When the signal received by antenna 102 corresponds to a low state transmitted as a zero signal, the value of the clock signal delivered at the output of circuit 106 is also zero for the entire duration of this low state.

[0040] Device 100 also includes a circuit 108 for modifying the threshold value of circuit 106, configured to decrease the threshold value when the value of the clock signal delivered at the output of circuit 106 is equal to the first value, or to increase the threshold value when the value of the clock signal is equal to the second value. For example, figure 1, an input of circuit 108 is electrically coupled to the output of circuit 106, and an output of circuit 108 is electrically coupled to an input of circuit 106.

[0041] In the described embodiment, the device 100 further includes a phase-locked loop 110, or PLL, one input of which is electrically coupled to the output of the circuit 106. The PLL 110 is intended to receive as input the clock signal emitted at the output of the circuit 106 and to deliver at output a signal synchronized and in phase with the clock signal received at its input.

[0042] Device 100 may also include a digital conversion circuit 112 comprising an input electrically coupled to an output of the PLL 110. Circuit 112 is specifically intended to decode the signal transmitted by reader 200.

[0043] In the described embodiment, the device 100 further includes a transmission circuit 114 comprising an output electrically coupled to the antenna 102, to which a modulation signal intended to be transmitted by the antenna 102 and in phase with the received signal is delivered. The circuit 114 may also include a first input electrically coupled to an output of the PLL 110 and a second input electrically coupled to an output of the digital conversion circuit 112.

[0044] On the diagram of the figure 1 Only some of the elements of device 100 are shown. Device 100 includes, in addition to those visible on the figure 1 , other circuits and elements not described here.

[0045] The operation of an example implementation of circuit 106 and circuit 108 for modifying the threshold value of circuit 106 is described below in relation to the figure 2 .

[0046] Reference 120 designates a first example of a received signal received at the input of circuit 106. This first example of a received signal can be obtained when the antennas of reader 200 and device 100 are close and strongly coupled to each other, and has, for example, a peak-to-peak amplitude of the order of 1 V.

[0047] Reference 122 designates a square wave signal representing the clock signal used by reader 200 for data transmission. The phase and frequency of signal 120 are therefore similar to those of signal 122, which was used to obtain the unmodulated electromagnetic field emitted by reader 200.

[0048] In the example implementation described in connection with the figure 2Circuit 106 is configured such that the clock signal output from circuit 106 is in state "1", or high state, when the received signal is above the threshold of circuit 106 (which is 0 V in this example), and in state "0", or low state, when the received signal is below the threshold of circuit 106. Furthermore, in this embodiment, circuit 108 is configured to reduce the threshold value of circuit 106 when the clock signal output from circuit 106 is in state "1". For example, the reduced threshold value could be between 10% and 20% of the minimum amplitude of the received signal (which is, for example, on the order of 0.2 V).

[0049] Reference 124 designates the clock signal obtained at the output of circuit 106 when the receive signal 120 is applied to the input of circuit 106.

[0050] In this example, because the threshold value of circuit 106 is equal to 0 when the clock signal delivered by circuit 106 is in state "0", the transition from state "0" to state "1" of the clock signal 124 occurs at the same time as the transition from a negative value to a positive value of the received signal 120. On the other hand, because the threshold value of circuit 106 is reduced when the clock signal delivered by circuit 106 is in state "1", the transition from state "1" to state "0" of the clock signal 124 occurs with a delay relative to the transition from a positive value to a negative value of the received signal 120. When the peak-to-peak amplitude of the signal 120 is large (as is the case here), this delay is very small.

[0051] Reference 126 designates a second example of a received signal received at the input of circuit 106. This second example of a received signal can be obtained when the antennas of reader 200 and device 100 are far apart and weakly coupled to each other, and has, for example, a peak-to-peak amplitude of the order of 0.2 V.

[0052] Reference 128 designates the clock signal obtained at the output of circuit 106 when the receive signal 126 is applied to the input of circuit 106.

[0053] As when the receive signal 126 is applied to the input of circuit 106, the transition from state "0" to state "1" of signal 128 occurs at the same time as the transition from a negative to a positive value of signal 126, and the transition from state "1" to state "0" of signal 128 occurs with a delay relative to the transition from a positive to a negative value of signal 126. Because the peak-to-peak amplitude of signal 126 is small, this delay is greater than in the case of a receive signal with a high peak-to-peak amplitude such as signal 120. On the figure 2 , this greater delay results in a longer duration of state “1” of signal 128 at each period of signal 128.

[0054] Whether the amplitude of the received signal is high or low, lowering the threshold of circuit 106 by circuit 108 when the clock signal delivered by circuit 106 is in state "1" prevents the appearance of parasitic variations, switching, or instabilities in the clock signal delivered by circuit 106. These instabilities correspond, for example, to self-oscillations when the information transmitted by the received signal is in a low state. Such parasitic variations could be generated by glitches, or failures, caused by noise in the received signal at that moment in the absence of circuit 108. On the figure 2These parasitic transient phenomena correspond to the attenuation occurring on the received signal because the transition from high to low state of the information transmitted on the received signal is not instantaneous. This lowering of the threshold of circuit 106, performed by circuit 108 when the clock signal is in state "1", also prevents parasitic switching of the clock signal delivered by circuit 106 when noise is present in the received signal, for example, when its value is close to 0.

[0055] Furthermore, because the threshold value remains unchanged when the clock signal is at state "0", the transition from state "0" to state "1" of the clock signal obtained at the output of circuit 106 occurs without any delay relative to the transition from a negative to a positive value of the received signal. Thus, when the PLL 110 is synchronized with the rising edges of the signal applied to its input (which corresponds to the clock signal delivered at the output of circuit 106), this absence of delay ensures that the response signal from device 100 is ultimately in phase with the electromagnetic field emitted by the reader 200. Moreover, the delay in the output clock signal of circuit 106 during the transition from a positive to a negative value of the received signal has no impact when the PLL 110 is synchronized with the rising edges of the clock signal.

[0056] In the examples above, circuit 108 is configured to reduce the threshold value of circuit 106 when the clock signal is high (1). In this case, when the clock signal is low (0), circuit 108 does not modify the threshold value of circuit 106, which operates at its nominal accuracy, thus preventing any degradation of the intrinsic phase shift of device 100. In this example, only the falling edges of the clock signal are affected by a phase shift that has no impact when the PLL 110 is synchronized with the rising edges of the clock signal.

[0057] According to another example, for instance when the PLL 110 is synchronized with the falling edges of the clock signal, the circuit 108 can be configured to increase the threshold value of the circuit 106 when the clock signal is in the "0" state. In this case, when the clock signal is in the "1" state, the circuit 108 does not modify the threshold value of the circuit 106, which operates at its nominal accuracy (threshold value, for example, equal to 0 V), thus preventing degradation of the intrinsic phase shift of the device 100. In this case, only the rising edges of the clock signal are affected by a phase shift that has no impact when the PLL 110 is synchronized with the falling edges of the clock signal.

[0058] A first example of the implementation of circuit 106 and circuit 108 is described below in connection with the figure 3 .

[0059] In this first example, circuit 106 comprises a differential pair formed by two first transistors 130, 132, each including one of their source / drain electrodes electrically coupled to a first current source 134. In the example of the figure 3 The first transistors, 130 and 132, are NMOS transistors, and their first source / drain electrode corresponds to the source electrode. In this first example, the received signal at the input of circuit 106 is applied to the gate of transistor 130, and the signal opposite to the received signal is applied to the gate of transistor 132.

[0060] The circuit 106 according to this first example further comprises a first current mirror including two second transistors 136, 138, each having one of its source / drain electrodes electrically coupled to one of the source / drain electrodes of the first two transistors 130, 132. In the example of the figure 3The second transistors 136 and 138 are, for example, NMOS transistors, and their first source / drain electrode corresponds to the drain electrode. The second source / drain electrodes of the first transistors 130 and 132 correspond to the drain electrodes. The first source / drain electrode of the second transistor 136 is also coupled to the gate of the second transistor 136. The first source / drain electrodes of the second transistors 136 and 138 are also electrically coupled to second current sources 140 and 142, ensuring the biasing of this first current mirror and supplying the current necessary for the correct biasing of the differential pair formed by the first two transistors 130 and 132.

[0061] The circuit 106 in this first example also includes a high-gain amplifier 144 whose input is electrically coupled to the first source / drain electrode of transistor 138, and whose output forms the output of circuit 106, to which the clock signal is intended to be delivered. The amplifier 144 can operate in saturation so that the resulting clock signal corresponds to a square wave.

[0062] The differential pair formed by the first two transistors 130, 132 converts the potential difference applied to the gates of transistors 130, 132 into a current difference appearing at the junction of the input of amplifier 144 with one of the branches of the first current mirror formed by the second two transistors 136, 138 (the one including transistor 138 on the figure 3The use of the first current mirror thus allows the input of amplifier 144 to be supplied with a voltage whose value is proportional to this current difference. Finally, amplifier 144, which is high-gain and operates in saturation, converts the voltage applied to its input into a square wave signal (a clock signal in the "1" state when the input voltage of amplifier 144 is positive, and in the "0" state when the input voltage of amplifier 144 is negative).

[0063] Circuit 108 can be configured to unbalance a bias of the first current mirror formed by the second transistors 136, 138.

[0064] In this first example, circuit 108 includes third transistors 146, 148 forming a second current mirror electrically coupled to one of the branches of the first current mirror formed by the second transistors 136, 138. In the example of the figure 3, the third transistors 146, 148 are for example PMOS transistors.

[0065] The circuit 108 according to this first example also includes a first switch 150 configured to electrically couple or not the electrical supply potential of the device 100 to the gates of the third transistors 146, 148 forming the second current mirror, and a second switch 152 configured to electrically couple or not the second current mirror to the electrical reference potential of the device 100 through a third current source 154.

[0066] In this first example, circuits 106 and 108 can be electrically powered between a first electrical potential V1 (applied to the first switch 150, the third transistors 146 and 148, and the second current sources 140 and 142) and a second electrical potential V2 (applied to the third current source 154, the second transistors 136 and 138, and the first current source 134). By choosing these electrical potentials such that V1 = -V2, the common-mode voltage, corresponding to the midpoint of the amplifier, is zero. More generally, the common-mode voltage Vmc is expressed by the equation: Vmc = V 1 + V 2 / 2

[0067] In the example shown on the figure 3The first switch 150 is in the open state when the clock signal delivered by circuit 106 and applied to its control input is in the state "1", and is in the closed state when the clock signal is in the state "0". Conversely, the second switch 152 is in the open state when the clock signal applied to its control input is in the state "0", and is in the closed state when the clock signal is in the state "1".

[0068] Thus, when the clock signal is at state "0", circuit 108 has no impact on the threshold value of circuit 106 (circuit 106 functions as if circuit 108 were absent). No current flows through the current mirror of circuit 108 shown in the diagram. figure 3 .

[0069] When the clock signal is high, connecting circuit 108 to one of the branches of the first current mirror formed by the second transistors 136 and 138 modifies the threshold value of circuit 106. Specifically, when the first switch 150 is open and the second switch 152 is closed, the electrical coupling of circuit 108 to one branch of the first current mirror adds an additional current to that branch compared to the other branch. This current asymmetry in the branches of the first current mirror is present at the junction between the input of amplifier 144 and one of the branches of the differential pair, resulting in an offset, or shift, in the threshold value of circuit 106.

[0070] The voltage at the input of amplifier 144 is proportional to the difference in currents (i140 - i130) - (i142 - i132), where i130, i140, i132, and i142 correspond to the currents flowing through components 130, 140, 132, and 142, respectively. Thus, the change in the threshold voltage of circuit 106 is achieved through the current difference between the source formed by current source 140 + circuit 108 and source 142.

[0071] When circuit 108 is inactive (first switch 150 in the closed state), the bias current flowing in the drain of the second transistor 136 is equal to the current supplied by the current source 140 less the bias current flowing in transistor 130, and which is then equal to the current supplied by the current source 142 less the bias current flowing in transistor 132. The threshold voltage of circuit 106 is then not modified.

[0072] When circuit 108 is active (first switch 150 in the open state), the bias current flowing in the drain of the second transistor 136 is equal to the current supplied by the current source 140 minus the bias current flowing in transistor 130, plus the current supplied by circuit 108. The current supplied by the current source 140 is no longer equal to that supplied by the current source 142 minus the bias current flowing in transistor 132, which causes the threshold voltage of circuit 106 to change.

[0073] Alternatively, circuit 108, according to this first example, can be configured to increase the threshold value of circuit 106 when the clock signal is at state "0", and to leave the threshold value of circuit 106 unchanged when the clock signal is at state "1". Circuit 108, according to this variant, includes, for example, the same elements as those shown in the diagram. figure 3 except for the first switch 150, which in this case is configured to be closed when the clock signal applied to its control input is high (1), and open when the clock signal is low (0). In this variant, the second switch 152 is also configured to be closed when the clock signal applied to its control input is low (0), and open when the clock signal is high (1). Furthermore, in this variant, compared to the example previously described in connection with the figure 3 , the output of circuit 108 is not electrically coupled to the branch of the first current mirror formed by transistor 136 but is electrically coupled to the output branch of the first current mirror formed by transistor 138, and therefore to the input of amplifier 144.

[0074] A second example of the implementation of circuit 106 and circuit 108 is described below in connection with the figure 4 .

[0075] In this second example, circuit 106 has the same components as circuit 106 in the first example of implementation described previously.

[0076] The circuit 108 according to this second example includes a fourth transistor 156 and a switch 158 configured to electrically couple or not the fourth transistor 156 in parallel with the transistor 132 of the circuit 106. More specifically, in this example, the switch 158 is configured to be in the open state when the clock signal is in the state "0", and to be in the closed state when the clock signal is in the state "1".

[0077] In this second example, an imbalance of one of the branches of the differential pair is achieved by connecting the fourth transistor 156 in parallel with transistor 132, increasing the transconductance of the transistor seen at the level of this branch of the differential pair, and modifying the value of the threshold of circuit 106.

[0078] Alternatively, circuit 108 in this second example can be configured to increase the threshold value of circuit 106 when the clock signal is at state "0", and to leave the threshold value of circuit 106 unchanged when the clock signal is at state "1". Circuit 108 in this variant includes, for example, the same elements as those shown in the diagram. figure 4 with the exception of the fourth transistor 156 and the switch 158, which is configured to electrically couple or not the fourth transistor 156 in parallel with the transistor 130 of circuit 106, the switch 158 is configured to be in the closed state when the clock signal applied to its control input is in the state "0", and to be in the open state when the clock signal is in the state "1". Such a variant of circuits 106 and 108 is shown in the figure 5 .

[0079] In the example circuit 106 described above in connection with the figures 3 to 5It is possible to modify the threshold value of circuit 106 by modifying the current values ​​delivered by each of the current sources 140 and 142. Thus, when the currents delivered by sources 140 and 142 are equal, the nominal threshold value (i.e., without the intervention of circuit 108) of circuit 106 can be equal to 0. When the current delivered by source 140 is greater than that delivered by source 142, the nominal threshold value of circuit 106 can be less than 0. When the current delivered by source 140 is less than that delivered by source 142, the nominal threshold value of circuit 106 can be greater than 0.

[0080] In the various examples described above, circuit 108 and circuit 106 can be seen as together forming a dynamic threshold comparator, in which a variation of the threshold is present only when the output signal of the comparator is in the high or low state.

[0081] In the examples of figures 3 and 4 As previously described, each of the source / drain electrodes of one of the transistors can correspond to the source electrode or the drain electrode of that transistor, depending on the type, or conductivity, n or p of the transistor.

[0082] In addition, one or more components different from circuit 106 and / or circuit 108 described above may be used to perform functions analogous to those described.

[0083] In the various embodiment examples described above, each of the switches 150, 152, 158 can correspond to a MOS transistor.

[0084] In the various embodiment examples, the state "1" of a signal can correspond to an amplitude equal to the supply voltage of device 100, and the state "0" of a signal can correspond to an amplitude equal to the reference potential of device 100, for example ground whose electrical potential is zero.

[0085] In the description above, device 100 refers to a contactless communication device using active charge modulation, which, during communication with a reader, is emulated in card mode. Device 100 may have functionalities other than those described above. Device 100 could, for example, be a mobile phone or a connected object such as a watch.

[0086] Various examples of implementation and variations have been described. Those skilled in the art will understand that certain features of these various examples of implementation and variations could be combined, and other variations will become apparent to them.

[0087] Finally, the practical implementation of the described examples and variants is within the reach of a person in the trade, based on the functional indications given above.

Claims

1. Device (100) of contactless communication by active load modulation, comprising at least: - a clock signal extraction circuit (106) configured to receive as an input a reception signal and to output a clock signal having a first value when the reception signal is greater than a threshold of the clock signal extraction circuit (106) and having a second value when the reception signal is smaller than the threshold; - a circuit (108) for modifying the value of the threshold, configured to decrease the value of the threshold when the value of the clock signal is equal to the first value, or to increase the value of the threshold when the value of the clock signal is equal to the second value.

2. Device (100) according to claim 1, wherein the threshold of the clock signal extraction circuit (106) has a zero value.

3. Device (100) according to any of the foregoing claims, wherein the clock signal extraction circuit (106) and the circuit (108) for modifying the value of the threshold are configured so that the decreased value of the threshold is in the range from 10% to 20% of a minimum amplitude of the reception signal.

4. Device (100) according to any of the foregoing claims, wherein the clock signal extraction circuit (106) comprises a differential pair (130, 132).

5. Device (100) according to claim 4, wherein the clock signal extraction circuit (106) further comprises a first current mirror (136, 138) electrically coupled in parallel with the differential pair (130, 132).

6. Device (100) according to claim 5, wherein the circuit (108) for modifying the value of the threshold is configured to unbalance a biasing of the first current mirror (136, 138) of the clock signal extraction circuit (106) or a biasing of the differential pair (130, 132) and of the first current mirror (136, 138) of the clock signal extraction circuit (106).

7. Device (100) according to one of claims 5 or 6, wherein the clock signal extraction circuit (106) further comprises an amplifier (144) having an input electrically coupled to one of the branches of the first current mirror (136, 138).

8. Device (100) according to one of claims 4 to 7, wherein the circuit (108) for modifying the value of the threshold comprises a second current mirror (146, 148) electrically coupled to one of the branches of the first current mirror (136, 138) and switches (150, 152) configured to electrically couple the second current mirror (146, 148) to an electric power supply potential of the device (100) and to a current source, itself coupled to a reference electric potential of the device (100), according to the value of the clock signal.

9. Device (100) according to one of claims 4 to 7, wherein the circuit (108) for modifying the value of the threshold comprises a transistor (156) and a switch (158) configured to electrically couple the transistor (156) of the circuit (108) for modifying the value of the threshold in parallel with a transistor (130) of the differential pair (130, 132) when the value of the clock signal is equal to the first value or to the second value.

10. Device (100) according to any of the foregoing claims, further comprising a phase-locked loop (110) having an input electrically coupled to an output of the clock signal extraction circuit (106).

11. Device (100) according to claim 10, further comprising: - a digital conversion circuit (112) comprising an input electrically coupled to an output of the phase-locked loop (110); - a transmission circuit (114) comprising an output electrically coupled to the antenna (102) and on which a modulation signal in phase with the reception signal is intended to be delivered, and comprising a first input electrically coupled to an output of the phase-locked loop (110) and a second input electrically coupled to an output of the digital conversion circuit (112).