Memory control for performing efficient error correction code (ECC) decoding
DE602024002448T2Active Publication Date: 2026-02-11SAMSUNG ELECTRONICS CO LTD
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Patent Information
- Application Number
- DE602024002448
- Authority / Receiving Office
- DE · DE
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2023-09-12
- Filing Date
- 2024-03-21
- Publication Date
- 2026-02-11
- Estimated Expiration
- 2044-03-21
AI Technical Summary
Technical Problem
Existing memory controllers require longer error correction times and additional buffer space due to the sequential processing of hard and soft decision data for error correction, leading to inefficiencies in ECC decoding.
Method used
A memory controller that optimizes ECC decoding by rearranging the order of hard and soft decision data processing, allowing simultaneous or sequential input of data to the ECC circuit, and applying data formatting to reduce decoding time.
Benefits of technology
This approach reduces ECC decoding time and improves the operating performance of memory systems by minimizing the need for additional buffer space and optimizing data formatting for faster error correction.
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