Radio frequency voltage limiter for an RFID transponder

Description

BackgroundField

[0001] This disclosure relates generally to electronic circuits, and more particularly, to a radio frequency (RF) voltage limiter for radio frequency identification (RFID) transponders.Related Art

[0002] Ultra-high frequency (UHF) RFID transponders, commonly referred to as RFID tags, are widely used to identify objects to which the tags are attached. The most common application examples of RFID tags are retail, supply chain management, shipping services, airline luggage tracking, laundry services, etc. An RFID tag typically includes an antenna and an integrated circuit (IC) (commonly referred to herein as a "chip"). An RFID transponder may communicate inductively with an RFID reader via an electrical, magnetic, or electromagnetic field generated by the RFID reader. In some circumstances, a UHF RFID transponder frontend implementation may experience an overvoltage caused by high levels of received antenna power when receiving an amplitude modulated reader signal. In complementary metal-oxide semiconductor (CMOS) technologies of advanced process nodes, the received high voltage at the transponder frontend may exceed the maximum voltage ratings of the IC, resulting in damage due to overvoltage stress. An RF voltage limiter may be used to avoid overvoltage conditions at the integrated RF frontend at high received antenna power levels. The RF limiter of an RFID tag chip may operate with a high peak detector discharge time to minimize distortions when receiving an amplitude-modulated signal from a reader. Implementing a high peak detector discharge time in the order of several hundred micro seconds (µs) by means of passive components can occupy a large chip area.

[0003] CN 114 648 084 A describes an RFID tag that comprises: an antenna for receiving a high-frequency signal; a capacitor bank coupled with the antenna; a charge pump coupled with the antenna and configured to convert the high frequency signal into a direct current (DC) signal; an envelope detector to measure a peak voltage of the high frequency signal; and a detector to compare an output of the charge pump to an output of the envelope detector. The RFID tag also includes an impedance tuning circuit coupled with the charge pump and the envelope detector and configured to vary a capacitance of the capacitor bank based on an output of the detector and the envelope detector.

[0004] US 2023 / 135571 A1 describes a voltage regulator that includes a shunt transistor and a feedback circuit. The shunt transistor has a first current electrode coupled to a first voltage source terminal, a second current electrode coupled to a second voltage source terminal, a control electrode coupled to receive a reference voltage, and a body electrode. The feedback circuit has an input terminal coupled to the body electrode of the shunt transistor, and an output terminal coupled to the control electrode of the shunt transistor. The voltage regulator is suitable for use in a passive RFID device to protect the device from overvoltage damage.Brief Description of the Drawings

[0005] The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. FIG. 1 illustrates a block diagram of a differential ultra-high frequency (UHF) RFID frontend in accordance with an embodiment. FIG. 2 illustrates the RF voltage limiter of the UHF RFID frontend of FIG. 1 according to an embodiment. FIG. 3 illustrates the RF voltage limiter of the UHF RFID frontend of FIG. 1 according to another embodiment. FIG. 4 illustrates the RF voltage limiter of the UHF RFID frontend of FIG. 1 according to another embodiment. FIG. 5 illustrates the RF voltage limiter of the UHF RFID frontend of FIG. 1 according to another embodiment. FIG. 6 illustrates various signal waveforms of the RF voltage limiter of FIG. 5. FIG. 7A illustrates RF voltage amplitude versus received antenna power for the RF voltage limiter of FIG. 5. FIG. 7B illustrates modulation depth versus received antenna power for the RF voltage limiter of FIG. 5. FIG. 8 illustrates radio frequency identification (RFID) tag according to an embodiment. Detailed Description

[0006] Generally, there is provided, a RF voltage limiter for a UHF RFID transponder that includes an envelope detector, a peak detector, and a shunt circuit. The envelope detector provides an envelope signal that tracks a voltage envelope of a signal received at an antenna. The peak detector stage includes a current mirror acting as a rectifying buffer, and a current sink and a small filter capacitor to provide a control signal in response to the envelope signal to control the shunt circuit. The shunt circuit provides an impedance to control the maximum voltage at the antenna in response to the control signal. Use of the RF voltage limiter in a UHF RFID tag provides an area-efficient implementation of a peak detector with a high discharge time to minimize signal envelope distortions when receiving an amplitude-modulated signal from a reader.

[0007] In accordance with a first aspect of the present disclosure, there is provided a radio frequency (RF) voltage limiter for a radio frequency identification (RFID) transponder, as defined in claim 1. In accordance with a second aspect of the present disclosure, there is provided an RFID transponder comprising said RF voltage limiter. In accordance with a third aspect of the present disclosure, there is conceived a method for limiting an RF voltage at an antenna of a radio frequency identification RFID transponder, as defined in claim 11.

[0008] FIG. 1 illustrates a block diagram of differential ultra-high frequency (UHF) RFID frontend 10 for a RFID transponder in accordance with an embodiment. In one embodiment, RFID frontend 10 is implemented in one or more complementary metal-oxide semiconductor (CMOS) integrated circuits. RFID frontend 10 includes buffer capacitor 11, direct current (DC) limiter 12, RF charge pump 13, demodulator 14, modulator 15, antenna tuning circuit 16, RF voltage limiter 17, and electrostatic discharge (ESD) protection circuit 18. RF charge pump 13, demodulator 14, modulator 15, antenna tuning circuit 16, RF limiter 17, and ESD protection 18 are coupled to differential antenna terminals RF 1 and RF 2 . DC limiter 12 has an input connected to an output of RF charge pump 13, and an output connected to a power supply voltage terminal labeled "VDD". Buffer capacitor 11 has a first terminal connected to VDD and a second terminal connected to a ground terminal.

[0009] RF charge pump 13 provides rectification and transformation of the received RF voltage from an antenna connected to antenna terminals RF 1 and RF 2 to provide a DC supply voltage for circuits of an integrated circuit (IC), e.g., a digital part and a non-volatile memory. Modulator 15 provides modulation of an input impedance to modulate the signal that is scattered back from the antenna to transmit information to a reader. Demodulator 14 provides for demodulation of an amplitude modulated signal transmitted by a reader and received at the antenna connected to antenna terminals RF 1 and RF 2 . Antenna tuning circuit 16 provides tuning of the input capacitance to maximize the power transfer from the antenna to the chip input. Electrostatic discharge protection 18 may be implemented in various ways. One example implementation of ESD protection 18 includes anti-parallel pn-junction diodes. The anti-parallel diodes provides a path for high currents generated by an electrostatic discharge event at the antenna terminals that can damage circuits on the integrated circuit. DC limiter 12 regulates and limits the output voltage of RF charge pump 13.

[0010] RF voltage limiter 17 is connected between antenna terminals RF 1 and RF 2 to limit the RF voltage amplitude at high power levels received from an antenna to prevent overvoltage conditions of the RFID frontend circuits. In order to react quickly to rapidly rising power levels transmitted by an RFID reader during power-up of the RFID IC, RF limiter 17 can operate in a self-sustained mode at power-up when no accurate reference voltage or reference bias current has been generated yet.

[0011] As will be described below, several disclosed embodiments of RF voltage limiter 17 provide area-efficient implementations with high discharge time to minimize signal envelope distortions. Furthermore, the circuit topology facilitates a minimization of the quiescent current consumption. Note that even though a differential RFID frontend implementation is shown and described, a single-ended frontend implementation may be provided in which either terminal RF 1 or RF 2 corresponds to the chip ground.

[0012] FIG. 2 illustrates RF voltage limiter 20 for use in UHF RFID frontend 10 of FIG. 1 according to an embodiment. RF voltage limiter 20 includes RF voltage envelope detector circuit 21, peak detector circuit 22, and shunt circuit 23. RF envelope detector 21 has an input connected to antenna terminals RF 1 and RF 2 and an output to provide an envelope signal labeled "env" that tracks the voltage envelope of the differential RF voltage at antenna terminals RF 1 and RF 2 . Shunt devices 23 includes a controllable load impedance to load the RF signals at antenna terminals RF 1 and RF 2 to reduce a high RF input voltage amplitude to below the maximum operating voltage of the RFID frontend circuits. The shunt load impedance is controlled by a control signal labeled "ctrl." The impedance value with respect to antenna terminals RF 1 and RF 2 decreases with an increasing level of control signal ctrl.

[0013] Peak detector circuit 22 includes two N-channel metal-oxide semiconductor (NMOS) transistors M 1 and M 2 connected as a current mirror, current sources I b1 and I b2 ,and capacitor C 1 . Current source I b1 has a first terminal connected to power supply voltage terminal VDD, and a second terminal connected to the drain of first NMOS transistor M 1 . First NMOS transistor M 1 is diode-connected and is biased by current source I b1 . The source of first transistor M 1 is connected to receive RF envelope signal env. Second transistor M 2 is biased with a gate-to-source voltage (V GS ) of first transistor M 1 . The drain of second transistor M 2 is connected to power supply voltage terminal VDD and the source of second transistor M 2 is connected to provide shunt device control signal ctrl to an input of shunt circuit 23. Filter capacitor C 1 and a current sink I b2 are both connected between the source of second transistor M 2 and a ground terminal. Control signal ctrl follows fast rising voltage levels of envelope signal env, but control signal ctrl follows falling voltage levels of envelope signal env more slowly with a signal slope defined by C 1 and I b2 . Providing a high discharge time minimizes signal envelope distortions. The use of peak detector 22 provides an area-efficient implementation and facilitates a lower quiescent current consumption as compared with a classic filter implementation.

[0014] FIG. 3 illustrates RF voltage limiter 30 for use in UHF RFID frontend 10 of FIG. 1 according to another embodiment. RF voltage limiter 30 includes RF envelope detector 31, peak detector circuit 32, and shunt circuit 33. Peak detector circuit 32 is essentially the same as peak detector circuit 22 except that peak detector circuit 32 includes a bypass switch S1 coupled between the sources of first and second transistors M 1 and M 2 . Switch S1 is controlled by a control signal labeled BP.

[0015] When switch S1 is open RF voltage limiter 30 operates the same as described above for RF voltage limiter 20. When switch S1 is in a closed state, envelope signal env from RF envelope detector circuit 31 is provided directly to shunt circuit 33 as control signal ctrl, thus bypassing peak detector circuit 32 and the shunt circuit 33 is controlled by envelope signal env. In this way, the inclusion of switch S1 provides RF voltage limiter circuit 30 with the ability to operate in a self-sustained mode, e.g., during power-up when there are no accurate reference voltages or bias currents, and even if bias currents I b1 and I b2 are equal to zero amperes.

[0016] Switch S1 is controlled by digital input signal BP. The switch control signal BP may be derived, for example, from a power-on reset signal generated by another circuit of the RFID transponder IC to reset the digital part of the IC to a defined state if the supply voltage becomes too low. In this way, switch S1 may be switched to the closed state during the power-up of the IC, when bias currents I b1 and I b2 are still undefined, and switch S1 may be switched to the open state once the chip power-up is completed to enable operation of peak detector circuit 32. This will allow peak detector circuit 32 to operate shunt circuit 33 with a discharge time as defined by control signal ctrl. Alternatively, switch control signal BP may be used to temporarily close switch S1 during chip operations to refresh the voltage level of control signal ctrl in order to track rapidly occurring changes of the RF voltage envelope at antenna terminals RF 1 and RF 2 . In another embodiment, switch S1 may be controlled with a different control signal and for a different reason than described above for control signal BP.

[0017] FIG. 4 illustrates RF voltage limiter 40 for use in UHF RFID frontend 10 of FIG. 1 according to another embodiment. RF voltage limiter 40 includes RF envelope detector 41, peak detector circuit 42, and shunt circuit 43. Peak detector circuit 42 is essentially the same as peak detector circuit 22 except that peak detector circuit 42 includes current source I b3 connected between power supply voltage terminal VDD and the drain of the current mirror transistor M 2 .

[0018] Current source I b3 limits the charging current of capacitor C 1 at rising voltage levels of control signal env, and thus limits the rising voltage slope of control signal ctrl. This can limit the impact of short transients, such as overshoots. More time is required to charge capacitor C 1 providing better control.

[0019] FIG. 5 illustrates RF voltage limiter 50 of the UHF RFID frontend of FIG. 1 according to another embodiment. RF voltage limiter 50 includes RF envelope detector 51, peak detector circuit 52, and shunt circuit 53. RF envelope detector 51 includes two cross-coupled charge pump stages, a load resistor R 1 and a filter capacitor C 2 . A first charge pump stage includes a pair of cross-coupled NMOS transistors M 9 and M 10 , a pair of cross-coupled PMOS transistors M 11 and M 12 , and capacitors C 3 and C 4 for capacitively connecting the pairs of cross-coupled transistors to antenna terminals RF 1 and RF 2 . A second charge pump stage includes a pair of cross-coupled NMOS transistors M 13 and M 14 , a pair of cross-coupled PMOS transistors M 15 and M 16 , and capacitors C 5 and C 6 for capacitively connecting the pairs of cross-coupled transistors to antenna terminals RF 1 and RF 2 . An input of the first charge pump is connected to a ground terminal, and an output of the second charge pump provides envelope signal env. At RF voltage amplitudes of higher than a threshold voltage of the charge pump switching devices M 9 - M 16 , envelope signal env tracks the envelope of the differential RF voltage at antenna terminals RF 1 and RF 2 . The charge pump stages are used to provide rectification and amplification.

[0020] Shunt circuit 53 is implemented using two NMOS transistors M 7 and M 8 . Source terminals of NMOS transistors M 7 and M 8 are connected to antenna terminals RF 1 and RF 2 , respectively. Drain terminals are connected to chip ground, and the gates of transistors M 7 and M 8 are connected to receive control signal ctrl.

[0021] Peak detector 52 is derived from peak detector 22 of FIG. 2. Current sources I b1 and I b2 of peak detector 22 of Fig. 2 are implemented by PMOS transistor M 5 and NMOS transistor M 6 biased by bias voltages V b1 and V b2 , respectively. Bias voltages V b1 and V b2 are generated using a bias circuit (not shown). Switch S 1 is implemented by a transmission gate consisting of transistors M 3 and M 4 , and control signal BP of FIG. 2 is replaced with complementary control signals BP and BP. Note that in another embodiment, the conductivity types of the transistors may be reversed such that the resulting circuit is essentially a mirror of the illustrated RF voltage limiter. In addition, in another embodiment the type of transistors may be different. Also note in another embodiment, the current sources may be implemented differently, e.g., with a resistor or another type of device.

[0022] FIG. 6 illustrates various signal waveforms of RF voltage limiter 50 of FIG. 5. Assume that switch S 1 is open, and peak detector 52 is therefore enabled. The time constant of an envelope detector output filter defined by R 1 C 2 is much lower than the pulse width of the amplitude-modulated signal 61 received at antenna terminals RF 1 and RF 2 . As can be seen, envelope signal env 62 tracks the received modulation envelope 61. For example, the envelope detector filter time constant may be in a range of 10 nano seconds (ns), while the minimum modulation pulse width of a signal transmitted by an RFID reader according to the EPC Generation-2 UHF RFID specification equals, e.g., 2 µs. The discharge voltage slope of control signal ctrl 63 is defined by I b2 / C 1 , where I b2 is the current through M 6 and C 1 represents the capacitance of capacitor C 1 . The discharge voltage slope is very low compared to the modulation pulse width. The voltage of control signal ctrl 63 therefore appears to remain mostly constant during a modulation pulse, as shown in Fig. 6. The discharge time slope of peak detector 52 may be, for example, in a range of about 1mV / µs.

[0023] Figures 7A and 7B illustrate characteristics of a received RF voltage signal at antenna terminals of a UHF RFID tag chip. FIG. 7A illustrates RF voltage amplitude versus received antenna power in decibel milliwatts (dBm) for the RF voltage limiter of FIG. 5. Curve 71 illustrates RF voltage amplitude versus received antenna power for no RF voltage limiter. Curves 72 illustrates RF voltage amplitude versus received antenna power for RF voltage limiter 50 with the peak detector 52 both bypassed and not bypassed.

[0024] FIG. 7B illustrates modulation depth versus received antenna power for RF voltage limiter 50 of FIG. 5. Curve 73 illustrates modulation depth versus received antenna power for a UHF RFID tag chip with no RF voltage limiter. Curve 74 illustrates modulation depth versus received antenna power for the RF voltage limiter with the peak detector bypassed. Curve 75 illustrates modulation depth versus received antenna power for the RF voltage limiter with the peak detector not bypassed.

[0025] As illustrated in Figures 7A and 7B, RF limiter 50 with enabled peak detector 52 limits the peak RF voltage amplitude at received power levels of larger than 5 dBm and enhances the modulation depth of the received amplitude-modulated signal, which facilitates demodulation.

[0026] FIG. 8 illustrates radio frequency identification (RFID) tag 80 according to an embodiment. RFID tag 80 includes IC 81 (chip) and antenna 82 connected to an antenna connection of IC 81. RFID tag 80 may be a transponder for communicating wirelessly with a reader. There are various frequency ranges that can be used depending on the application. RFID tag 80 may be passive and receive power to operate wirelessly from a reader device (not shown) via antenna 82, or may be active and have its own power source. There are various ways RFID tag 80 may be implemented. In one embodiment, RFID tag 80 is implemented on a flexible tape with an adhesive on one side to allow RFID tag 80 to be attached to an object to be identified. There are also various ways to implement antenna 82 depending on the application.

[0027] Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below.

[0028] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The term "coupled," as used herein, is not intended to be limited to a direct coupling or a mechanical coupling.

Claims

1. A radio frequency, RF, voltage limiter (20, 30, 40, 50) for a radio frequency identification, RFID, transponder, the RF voltage limiter (20, 30, 40, 50) comprising: an envelope detector (21, 31, 41, 42) having an input coupled to an antenna, the envelope detector (21, 31, 41, 42) configured to track an envelope of a signal received at the antenna, the envelope detector (21, 31, 41, 42) having an output for providing an envelope signal; the radio frequency voltage limiter being characterized in that it further comprises: a peak detector (22, 32, 42, 52) having an input coupled to the output of the envelope detector (21, 31, 41, 42), wherein the peak detector (22, 32, 42, 52) comprises a current mirror for detecting a voltage level of the envelope signal, said current mirror having an input coupled to the output of the envelope detector (21, 31, 41, 42), and an output configured to provide a control signal that has a rising edge that rises with a rising edge of the envelope signal, and the control signal having a falling edge that follows more slowly than a falling edge of the envelope signal; and a shunt circuit (23, 33, 43, 53) coupled to provide an impedance to the antenna in response to the control signal, wherein the impedance decreases with an increasing voltage magnitude of the control signal.

2. The RF voltage limiter (20, 30, 40, 50) of claim 1, wherein the current mirror comprises: a first transistor having a first current electrode and a control electrode both coupled to receive a reference current, and a second current electrode coupled to the output of the envelope detector (21, 31, 41, 42); a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to provide the control signal to the shunt circuit (23, 33, 43, 53), and wherein the peak detector (22, 32, 42, 52) further comprises a first current source coupled between the first current electrode of the first transistor and a power supply voltage terminal, the first current source for providing the reference current.

3. The RF voltage limiter (20, 30, 40, 50) of claim 2, further comprising a capacitor coupled between the second current electrode of the second transistor and ground.

4. The RF voltage limiter (20, 30, 40, 50) of claim 3, further comprising: a second current source having a first terminal coupled to the second current electrode of the second transistor, and a second terminal coupled to a ground terminal; and a third current source having a first terminal coupled to the power supply voltage terminal, and a second terminal coupled to the first current electrode of the second transistor.

5. The RF voltage limiter (20, 30, 40, 50) of any preceding claim, wherein the envelope detector (21, 31, 41, 42) comprises two cross-coupled charge pump stages.

6. The RF voltage limiter (20, 30, 40, 50) of claim 5, wherein each of the cross-coupled charge pump stages comprises a pair of cross-coupled P-channel metal-oxide semiconductor transistors, PMOS, and a pair of cross-coupled N-channel metal-oxide semiconductor transistors, NMOS, both pairs capacitively coupled to a first antenna terminal and a second antenna terminal of the RFID transponder.

7. The RF voltage limiter (20, 30, 40, 50) of any preceding claim, wherein the antenna comprises a first terminal and a second terminal, and the shunt circuit (23, 33, 43, 53) comprises first and second transistors coupled between the first and second antenna terminals, and wherein a control electrode of both the first and second transistors is coupled to receive the control signal.

8. The RF voltage limiter (20, 30, 40, 50) of any preceding claim, further comprising a switch having a first terminal coupled to the output of the envelope detector (21, 31, 41, 42), and a second terminal coupled to the output of the peak detector (22, 32, 42, 52), the switch configured to selectively bypass the peak detector (22, 32, 42, 52) during a power-up of an integrated circuit of the RFID transponder.

9. The RF voltage limiter (20, 30, 40, 50) of claim 8, wherein the switch is a transmission gate responsive to a power-on reset signal.

10. A radio frequency identification, RFID, transponder comprising the RF voltage limiter (20, 30, 40, 50) of any preceding claim.

11. A method for limiting a radio frequency, RF, voltage at an antenna of a radio frequency identification RFID transponder, the method comprising: tracking, by an envelope detector (21, 31, 41, 42), an envelope of an RF signal at the antenna to produce an envelope signal; detecting, by a peak detector (22, 32, 42, 52) comprising a current mirror, a voltage level of the envelope signal using the current mirror, and providing a control signal, using the current mirror, that has a rising edge that rises with a rising edge of the envelope signal, and the control signal having a falling edge that follows more slowly than a falling edge of the envelope signal; and providing, by a shunt circuit (23, 33, 43, 53), an impedance to the antenna in response to the control signal, wherein the impedance decreases with an increasing voltage magnitude of the control signal.

12. The method of claim 11, wherein the current mirror comprises: a first transistor having a first current electrode and a control electrode coupled to receive a first reference current, and a second current electrode coupled to the output of the envelope detector (21, 31, 41, 42); and a second transistor having a first current electrode, a control electrode coupled to the control electrode of the first transistor, and a second current electrode coupled to provide the control signal to the shunt circuit (23, 33, 43, 53).

13. The method of claim 12, wherein the falling edge of the control signal follows the falling edge of the envelope signal more slowing using: a first current source having a first terminal coupled to the second current electrode of the second transistor, and a second terminal coupled to a ground terminal; and a capacitor having a first terminal coupled to the second current electrode of the second transistor, and a second terminal coupled to the ground terminal.

14. The method of any one of claims 11 to 13, wherein tracking the envelope further comprises using a charge pump to produce the envelope signal.

15. The method of any one of claims 11 to 14, wherein the shunt circuit (23, 33, 43, 53) comprises first and second transistors coupled between first and second antenna terminals of the antenna, and wherein a control electrode of both the first and second transistors is coupled to receive the control signal.