Low-loss dc-dc converter and associated control method

Abstract

The invention relates to a low-loss DC-DC converter (100), the chokes (L1, L2) of which are wound in opposite directions and are magnetically coupled by means of a magnetic core (Fe), and the leakage inductances (LSig1, LSig2) of which, which form on account of the magnetically coupled chokes (L1, L2), are adapted to the predefined switching frequency (fs) for switching the switches (S1, S2) of the DC-DC converter, in such a way that at least one discontinuous conduction phase (ΔL) is always established in the switching periods (Ts) resulting from the switching frequency (fs).

Description

[0001] Low-loss DC-DC converter and associated control method

[0002] The present invention relates to an electrical DC-DC converter with an input, an output, and a reference potential for converting an input DC voltage drop between the input and the reference potential into an output DC voltage drop between the output and the reference potential. The DC-DC converter comprises a first and a second sub-voltage converter, each of which contains an electrical choke, each with a choke input and a choke output, a switch, each switched at a predetermined switching frequency, each with a switch input and a switch output, and a current valve, each with a current valve input and a current valve output.The chokes provided in the sub-voltage converters are electrically connected to the input of the DC-DC converter via the respective choke input, and via the respective choke output via a node of the respective sub-voltage converter to the switch input of the respective switch and to the current valve input of the respective current valve. The switch output of the respective switch is electrically connected to the reference potential, and the respective current valve output of the respective current valve is electrically connected to the output of the DC-DC converter.

[0003] In power electronics, switching losses refer to the electrical power losses dissipated by an electronic switch during switching on and off. Electrical power is defined as the product of electrical current and electrical voltage. In relation to an electronic switch, such as a semiconductor switch in particular, switching losses are therefore the product of the voltage drop across the switch and the current flowing through it.

[0004] When a switch is in a non-conductive, i.e., blocking, off, or open state, a (usually non-negligible) voltage drops across the switch. In the blocking state, the voltage drop across the switch is at its maximum, while the current through the semiconductor switch is at its minimum – ideally, zero. Accordingly, in an open switch, no power is dissipated. When a switch is in a conductive, i.e., on or closed state, the current flowing through the switch is at its maximum, while the voltage drop across the switch is at its minimum – ideally, zero. Thus, even in the conductive state, (little to) no power is dissipated at the switch.

[0005] However, between the conducting and the non-conducting state, where, according to the above explanations, minima occur with regard to the resulting power loss, in a real switch neither the voltage drop across the switch nor the current flowing through the switch are usually zero, which can lead to significant power losses during these so-called "switching times".

[0006] In this context, it is important to note that real electronic switches, such as bipolar transistors, IGBTs ("insulated-gate bipolar transistors"), field-effect transistors, or even thyristors, have finite switching times, meaning they cannot switch instantaneously from a conducting to a non-conducting state and vice versa. This applies regardless of the semiconductor material used in the electronic switches. Both silicon-based (Si) electronic switches and electronic switches constructed with new semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN), exhibit finite switching times.

[0007] When a switch is turned on or off, it inevitably passes through the region in which both voltage and current are non-zero, resulting in power losses. There are a number of reasons for this real-life behavior, namely that a switch is neither completely off nor completely conducting during a switching process and therefore generates power losses. These are well known to those skilled in the field of power electronics. For example, in field-effect transistors, the gate capacitance must first be recharged before the field-effect transistor can switch on or off. In bipolar transistors, for example, the remaining charge carriers must first be cleared from the base when switching off, which delays the switch-off process.

[0008] Since the switching frequency, i.e., the frequency at which a switch is turned on and off, determines the number of switching operations that occur in a given time interval, switching losses are also directly proportional to the specified switching frequency. This is particularly relevant for DC-DC converters, since switching at high switching frequencies in DC-DC converters enables the use of small and cost-effective components, such as small and cost-effective chokes (i.e., small and cost-effective coils), and / or small and cost-effective capacitors.

[0009] A DC-DC converter, also called a "DC-DC converter" and well-known in the art, allows the conversion of an input DC voltage applied to the input of the DC-DC converter into an output DC voltage output at the output of the DC-DC converter. The output DC voltage can have a higher, lower, inverted, or even the same voltage level compared to the input DC voltage. Due to the diverse applications of DC-DC converters, e.g., in PC power supplies, household appliances, electric motors, etc., the problem of reducing switching losses in DC-DC converters remains a key research issue in the field of power electronics.

[0010] One way to reduce switching losses in a DC-DC converter is to reduce the switching times of the switches used in the DC-DC converter. This can be achieved, for example, by increasing the drive currents used. However, increased drive currents usually result in a deterioration in the EMC ("electromagnetic compatibility") properties of a DC-DC converter, which is why this approach is often not applicable in practice.

[0011] The problem of reducing switching losses while simultaneously increasing the switching frequency in DC-DC converters is known in the prior art. WO 2020 / 011786 A1 discloses a topology of a DC-DC converter in which a compensating capacitor and another bidirectional short-circuiting switch are connected downstream of the switches used for DC-DC conversion to reduce switching losses. Through the interaction of the chokes provided in the DC-DC converter, the aforementioned compensating capacitor, and the aforementioned bidirectional short-circuiting switch, the current and voltage at the switches are shifted in time such that there is only a slight overlap between large voltage values ​​and large current values ​​at the switches, which directly reduces the switching losses.However, the additional bidirectional short-circuit switch provided in WO 2020 / 011786 A1 for switching relief entails increased costs and, in particular, increased control complexity. Furthermore, the bidirectional short-circuit switch introduces another source of switching losses into the DC-DC converter under consideration. In the concept described in WO 2020 / 011786 A1, an additional evaluation or detection circuit must also be provided to determine or determine at which times the bidirectional short-circuit switch should be switched.

[0012] CN 103095114 B also describes a topology of a DC-DC converter for low-loss operation at high switching frequencies. For this purpose, CN 103095114 B proposes an additional load-suppression circuit, which also entails additional costs and increased circuit complexity.

[0013] All approaches proposed in the cited publications therefore lead to increased circuit complexity and increased costs. It is therefore an object of the present invention to provide a cost-effective, low-loss, and easy-to-control DC-DC converter and an associated control method to enable low-loss conversion of an input DC voltage into an output DC voltage.

[0014] This problem is solved by the features of the independent claims. The independent claims describe a DC-DC converter and an associated control method.

[0015] The DC-DC converter according to the invention has an input, an output and a reference potential for converting an input DC voltage falling between the input and the reference potential into an output DC voltage falling between the output and the reference potential, as well as a first and a second sub-voltage converter.

[0016] Each sub-voltage converter contains an electrical choke, each with a choke input and a choke output, a switch, which is switched in a switching period recurring at a predetermined switching frequency, each with a switch input and a switch output, and a current valve, particularly in the form of a suitably selected diode, such as a Schottky diode, a Zener diode, or another diode, each with a current valve input and a current valve output. The chokes provided in the sub-voltage converters are electrically connected to the input of the DC-DC converter via the respective choke input and are electrically connected via the respective choke output via a node of the respective sub-voltage converter to the switch input of the respective switch and to the current valve input of the respective current valve.The switch output of the respective switch is electrically connected to the reference potential, and the respective current valve output of the respective current valve is electrically connected to the output of the DC-DC converter.

[0017] According to the invention, the chokes provided in the sub-voltage converters are magnetically coupled by means of a magnetic core and wound in opposite directions. The opposite winding of the chokes (i.e., opposite winding direction, winding start and winding end of the respective chokes are arranged oppositely) ensures that the directions of the magnetic fluxes caused by the chokes in the magnetic core are opposite. The transformation ratio between the chokes provided in the sub-voltage converters, which in particular describes the relationship between the number of turns of the chokes, and the stray inductances formed by these chokes are selected according to the invention such that the effect of the main inductance formed by the coupled chokes on the currents flowing in the respective sub-voltage converters is eliminated.In this way, the dynamics of the currents flowing in the respective sub-voltage converters can be determined solely by the stray inductances that develop due to the magnetic coupling of the chokes in the respective sub-voltage converters. Since stray inductances are significantly smaller (typically 1%-5% of the total inductance) than the usual main inductances, a significantly faster current dynamic response can be achieved.

[0018] The stray inductances, which develop due to the magnetic coupling of the chokes in the respective sub-voltage converters, are further adapted to the specified switching frequency in such a way that a gap phase occurs in the currents flowing through the chokes during the switching periods for switching the switches. A gap phase is understood to be a temporal phase or a temporal interval in which the currents flowing through the chokes become zero at at least one point in time. By ensuring a gap phase in the course of the currents flowing in the sub-voltage converters, it is possible to switch the provided switches on current-free, or at least almost current-free, without an additional bidirectional short-circuit switch, without the required evaluation or detection circuitry, and without increased control complexity.In this way, switching losses can be eliminated or at least significantly reduced in a cost-effective and easy-to-implement manner. The efficiency of the DC-DC converter can thus be significantly increased.

[0019] Increasing switching frequencies lead to shorter switching periods. Gap phases can only be achieved in short switching periods through steep current increases and decreases. These steep current increases and decreases are made possible by the invention by determining the dynamics of the given currents through the significantly smaller stray inductances, instead of the otherwise comparatively large main inductances.

[0020] The resulting leakage inductances depend on the core size of the magnetic core, the core geometry, the number of windings of the chokes, and also the power to be transmitted. Using numerical and / or simulation-based design methods familiar to a person skilled in the field of electrical engineering, these parameters can be appropriately selected and optimized to appropriately design the resulting leakage inductances.

[0021] In a preferred manner, a relief capacitor can be connected between the node point of the first sub-voltage converter and the node point of the second sub-voltage converter in order to be able to switch off the given switches almost voltage-free.

[0022] A snubber capacitor can contribute to sometimes significant further improvements in the operating behavior of the DC-DC converter according to the invention. Specifically, the coupled chokes and a snubber capacitor, advantageously connected between them, act synergistically and together determine the resulting current dynamics of the choke currents flowing through the chokes: On the one hand, the inductance values ​​of the chokes influence the steepness of the resulting current edges; on the other hand, the capacitance of the snubber capacitor determines how quickly the voltages across the chokes change.

[0023] As is well known, the change in a choke current i through a choke L i = u, with the voltage u dropping across the choke, so that by choosing the inductance values ​​L of the chokes and the capacitance value of the relief capacitor (which influences the voltage u), all variables that affect the dynamics, i.e. the temporal behavior, of the choke currents can be influenced.

[0024] In an advantageous manner, the relief capacitor and the chokes can be matched to each other to realize the gap phases according to the invention. The relief capacitor can also be matched to the switching frequency for operating the DC-DC converter or to the stray inductances of the chokes to ensure the best possible operating behavior of the DC-DC converter.

[0025] For the transformation ratio between the chokes provided in the sub-voltage converters, i.e., the relationship between their number of turns, a target transformation ratio adapted to the switching frequency can be specified. Based on a specified target transformation ratio, the chokes, their windings, and their number of turns, as well as the remaining electronic components provided in the DC-DC converter, can be designed such that the transformation ratio actually achieved in practice corresponds as closely as possible to the specified target transformation ratio. Reasons for a deviation of the actual transformation ratio from a specified target transformation ratio can include manufacturing tolerances, dirt effects, component variations, or other nonlinear effects.Additionally, a maximum deviation can be specified for the transformation ratio, which determines the maximum upward and downward deviation of the actual transformation ratio from the specified target transformation ratio. When implementing the DC-DC converter according to the invention, it must be ensured that the deviation between the actual transformation ratio and the target transformation ratio does not exceed the specified maximum deviation.

[0026] Specifically, it is advantageous in this context to select a value of 1 for the target transformation ratio. This corresponds to a ratio of the number of turns of the chokes provided in the sub-voltage transformers of 1:1. A relative value of 10% can preferably be selected as the maximum deviation from such a target transformation ratio. In such a case, the transformation ratio may not deviate by more than ±10% from the selected target transformation ratio (ideally the value 1). Likewise, a relative value of 20% or even 30% can be selected for the maximum deviation from the target transformation ratio.

[0027] If the transformation ratio is equal to the value 1, a particularly effective elimination of the effect of the main inductance on the current curves or dynamics is possible, whereby the desired gap phases can be ensured solely by a suitable choice of the stray inductances.

[0028] Similarly, a target ratio can be specified for the ratio of the leakage inductances, and a tolerable maximum deviation can also be specified for this target ratio, such as 10%, 20%, or 30%. It is advantageous to select the ratio of the leakage inductances in the respective sub-voltage transformers as close to 1 as possible, i.e., a ratio of the leakage inductances of 1:1. This ensures that a similar, ideally even identical, current dynamic is achieved in the sub-voltage transformers.

[0029] In an equally advantageous manner, smoothing capacitors can be connected in parallel to the output of the DC-DC converter according to the invention, but also in parallel to the input of the DC-DC converter. This allows both the output voltage and the input voltage to be further smoothed, and, for example, voltage ripples that would otherwise remain in the output voltage to be reduced.

[0030] The DC-DC converter according to the invention can be controlled according to a control sequence. Advantageously, the switch of the first sub-voltage converter and the switch of the second sub-voltage converter are first closed simultaneously. Then, the switch of the first sub-voltage converter is opened, and after that, the switch of the second sub-voltage converter is also opened. Subsequently, the switch of the first sub-voltage converter and the switch of the second sub-voltage converter are again closed simultaneously. Then, the switch of the second sub-voltage converter is opened first, and finally, the switch of the first sub-voltage converter is opened.

[0031] Preferably, such a control sequence for controlling the electrical DC-DC converter is performed cyclically by starting a new, further control sequence with the closing of the switches of the two sub-voltage converters after the switch of the second sub-voltage converter is opened. Advantageously, a predetermined waiting time can be allowed between two consecutively executed control sequences, which can in turn be selected depending on the switching frequency and load of the DC-DC converter.

[0032] A further advantageous aspect of the present invention allows, beyond the advantages already mentioned, a further improvement in the efficiency of the DC-DC converter according to the invention. For example, the fact that an advantageously provided discharge capacitor is not short-circuited by a short-circuiting switch within the scope of the present invention can lead to small, but nevertheless present, voltages developing on the discharge capacitor even during the gap phases provided according to the invention. It has been recognized here that these voltages usually exist in the form of oscillations, since the discharge capacitor forms an oscillating circuit with the chokes of the sub-voltage converter. In a particularly advantageous manner, the switches can always be closed at times when a voltage oscillation dropping across the discharge capacitor reaches a local minimum in terms of its temporal progression.For this purpose, the voltage oscillation across the discharge capacitor can be measured, and it can be determined whether the measured voltage oscillation is reaching a local minimum or is close to a local minimum. By optimizing the switching times when closing the switches in this way, the efficiency of the DC-DC converter according to the invention can be improved, particularly in the partial load range.

[0033] The present invention will be explained in more detail below with reference to Figures 1 to 10, which show exemplary, schematic and non-limiting advantageous embodiments of the invention.

[0034] Fig. 1 shows a DC-DC converter according to the state of the art,

[0035] Fig. 2 shows a DC-DC converter according to the invention,

[0036] Fig. 3-8 shows a sequence of control steps according to the invention, Fig. 9 shows points in the time course of a voltage drop across a switch at which the switches of the DC-DC converter can be switched with particularly low losses,

[0037] Fig. 10 two efficiency curves determined by measurement.

[0038] Fig. 1 shows a DC-DC converter 300 according to the prior art, as described in particular in WO 2020 / 011786 A1. The DC-DC converter 300 has an input E, an output A, and a reference potential G for converting an input DC voltage Ue dropped between the input E and the reference potential G into an output DC voltage U dropped between the output A and the reference potential G. aas well as a first sub-voltage converter 11A and a second sub-voltage converter 11B. The basic functioning of a DC-DC converter 300 is well known, which is why it will not be discussed in more detail here.

[0039] In the sub-voltage converters 11 A, 11 B of the DC-DC converter 300 there are provided an electrical choke Li, l_2 each with a choke input LEi, LE2 and a choke output LAi, LA2, a switch Si, S2 each, which is switched in a switching period Ts recurring with a predetermined switching frequency fs, each with a switch input SEI, SE2 and a switch output SAI, SA2, and furthermore a current valve Di, D2 each with a current valve input DEI, DE2 and a current valve output DA1, DA2.The chokes Li, L2 provided in the sub-voltage converters 11 A, 11 B are electrically connected to the input E of the DC-DC converter via the respective choke input LE1, LE2 and are electrically connected via the respective choke output LAi, LA2 via a node K1, K2 of the respective sub-voltage converter 11 A, 11 B to the switch input SE1, SE2 of the respective switch Si, S2 as well as to the current valve input DE1, DE2 of the respective current valve Di, D2. The switch output SA1, SA2 of the respective switch Si, S2 is electrically connected to the reference potential G, and the respective current valve output DA1, DA2 of the respective current valve Di, D2 is electrically connected to the output A of the DC-DC converter.

[0040] Further features of the DC-DC converter 300 shown in Fig. 1 and known from the prior art are the discharge capacitor CB and the bidirectional short-circuit switch SB. Furthermore, the smoothing capacitors C e and C a , which, however, are not a mandatory requirement for the functioning of the DC-DC converter 300 in question. Furthermore, Fig. 1 shows a load RL, which can be supplied by the DC-DC converter 300 and is therefore not a component of the DC-DC converter 300 itself. For this reason, the (ohmic) load R is shown in dashed lines.

[0041] Fig. 2 shows an example of a circuit of a DC-DC converter 100 according to the invention. Features such as the switches Si, S2, the chokes Li, L2, or the current valves Di, D2, which are provided in the same way in the DC-DC converter 300 shown in Fig. 1, are assigned the same reference numeral in Fig. 2. Furthermore, Fig. 2 shows the choke currents i flowing through the chokes Li, L2. Li , ii2, the switch currents flowing through the switches Si , S2 isi , is2, the valve currents flowing through the current valves Di , D2 i Di , io2, the switch voltages usi, us2 dropped across the switches Si, S2, and the voltage Uc dropped across the relief capacitor CB, which is generally optional but provided in this exemplary embodiment, as well as the current ic flowing into the relief capacitor CB are shown. The DC-DC converter 100 according to the invention can also supply a resistive load R, which is indicated by dashed lines as in Fig. 1.

[0042] Accordingly, the DC-DC converter 300 shown in Fig. 1 and the DC-DC converter 100 shown in Fig. 2 differ by the coupling of the chokes Li , L2 by an iron core Fe, by the opposite winding of the chokes Li , L2, by a special tuning of the resulting leakage inductances L ffl ,L ff2 , as well as by omitting the bidirectional relief switch SB. In addition, the smoothing capacitors C shown in Fig. 1 e , C a are not provided, as they are not essential for the function of the inventive DC-DC converter 100. However, these can be added without limiting the functionality of the inventive DC-DC converter 100.

[0043] Central to the DC-DC converter 100 according to the invention is that, with the aid of the magnetic coupling of the chokes Li, L2, their opposite winding and the selection of a suitable transformation ratio a, the effect of the main inductance Lh, which is formed by the coupled chokes Li, L2, on the currents i flowing in the respective sub-voltage converters 11 A, 11 B L i, ii_2 disappears.

[0044] This effect is particularly evident when considering Kirchhoff's mesh equation for the first sub-voltage transformer 11A. Specifically, the corresponding voltage equation is given as into which the second inductor current ii_2 enters with a negative sign due to the opposite winding. Now, the temporal change of the currents i Li and ii_2 is equal, so ^i L1= which can be ensured by a suitable specification of equal stray inductances, results for the dynamics of the current i Li

[0045] Since stray inductances L ffl ,L ff2 are significantly lower than main inductances L h , in the manner described, much steeper current increases ^i L1 can be achieved and, ultimately, gap phases can be ensured even in short switching periods Ts. Thus, simply by appropriate parameterization / design of the chokes Li, l_2, a nearly current-free closing of the switches Si, S2 is possible.

[0046] This important aspect of the present invention, current-free switching, is also possible without a relief capacitor CB, which is why the relief capacitor CB is marked as "optional" in Fig. 2. However, a relief capacitor CB can advantageously be provided to enable voltage-free opening of the switches Si, S2. In this case, however, the bidirectional short-circuit switch SB shown in Fig. 1 can be omitted, since the inventive coupling of the chokes always automatically renders the relief capacitor CB almost voltage-free. This circumstance also represents a significant advantage for practical application.

[0047] In addition, the relief capacitor CB influences the current dynamics of the currents flowing through the chokes Li , L2 i Li , ii2, so that the discharge capacitor CB provides a further possibility of intervention on the slopes ^iL2 these currents i L i, ii_2. A relief capacitor CB can therefore not only be used to enable voltage-free opening of the switches Si, S2, but also to compensate for the stray inductances L ffl ,L ff2 be tuned to achieve a given current dynamics or given edge gradients to realize and bring about the desired gap phases.

[0048] In the DC-DC converter 100 according to the invention, the provided chokes Li , L2 delay the build-up of the switch currents i flowing through the switches Si , S2 starting from a current-free state (“gap phase”, currents through the chokes Li , L2 are zero). Si , is2 such that the switch currents i Si, is2 only reach their maximum values ​​when the switching voltages usi, us2 dropping across the switches Si, S2 have long since collapsed. The fact that gap phases occur in each switching period Ts is prevented, as described, by a suitable choice of the leakage inductances resulting in the sub-voltage converters When opening the switches S1, S2, it is advantageous to delay the build-up of the switching voltages usi, us2 across the switches. This can, as described, be achieved in a preferred manner by installing the relief capacitor CB between the nodes Ki, K2 of the first and the second sub-voltage converter 11 A, 11 B. In order to build up a switching voltage usi, us2 across a switch Si, S2, the relief capacitor CB must first be charged, which is why the build-up of the switching voltages usi, us2 across the switches is only completed when the switching currents i flowing across the switches Si, S2 Si , is2 have already collapsed.

[0049] In order for the described approaches to reducing switching losses to work as well as possible, it must be ensured that those energy storage devices (chokes Li, L2, discharge capacitor CB) that are used to shift currents i Si, is2 and switching voltages usi, us2 applied to switches Si, S2 are (if possible) uncharged during the corresponding switching operations. This ensures that, when using a discharge capacitor CB to reduce switching losses, the discharge capacitor CB can always contribute to the voltage delay and thus to the reduction of switching losses without itself introducing a voltage that leads to losses.

[0050] How the chokes Li, L2 can be tuned to enable current-free closing of the switches Si, S2 and almost voltage-free opening of the switches Si, S2 is explained below. The design of the chokes Li, L2 can preferably be based on a prior design of the leakage inductances L ffl ,L ff2 be derived, since the main inductance Lh, as described, has no effect on the currents i Li, ii_2 and the design attention is therefore initially focused on the leakage inductances L ffl ,L ff2 Specifically, the stray inductances L ffl ,L ff2 of the chokes Li, L2 based on specified parameters (e.g. output voltage, power, switching frequency, ...). If you want to achieve a given input voltage range with a given minimum input voltage U e ,min and a given maximum input voltage U e ,max, in the case of an ohmic load R of the DC-DC converter 100, depending on the input voltage U e the so-called critical inductance according to the formula D represents the duty cycle, which is well known from power electronics and is known to be the duty cycle of a switch in relation to the switching period T sThe inverse of the switching period T s sets the switching frequency f s = — fixed. The input eyelet provided in the above formula

[0051] DC voltage U e , the output DC voltage U a and the load resistance R also correspond to the values ​​known from the previous explanations.

[0052] The critical inductance L C rit specifies a limit value for the inductances used, below which discontinuous operation occurs in a DC-DC converter 100, and above which continuous operation occurs. In an advantageous way, the

[0053] Leakage inductances L ffl ,L ff2 be selected by first calculating all possible input voltage values ​​U e the smallest possible critical inductance L critimin This is calculated for the smallest input voltage U e min j D2 R L ii Ug üf m ilL i L n iL

[0054] CViM = U a (U a - U e , min )2f s

[0055] The stray inductances L ffl ,L ff2 can now be chosen by determining this smallest possible critical inductance L critimin on the stray inductances L ffl ,L ff2 is divided, so This choice ensures that the stray inductances L ffl ,L ff2 for each input voltage U e under which for the respective input voltage U e resulting critical inductance L crit lay.

[0056] To determine the transmission ratio a between the gears specified in the sub-

[0057] Voltage transformers 11 A, 11 B provided chokes Li , L2, which determines the ratio the

[0058] By specifying the number of turns of the two chokes Li, L2, a target transmission ratio a* can be specified. Ideally, the target transmission ratio a* is chosen to be equal to 1, i.e., a ratio of the number of turns of the chokes Li, L2 of 1:1 is selected.

[0059] In practical implementation, however, the actual gear ratio a may deviate from the specified target gear ratio a* (preferably a*=1). However, deviations of the gear ratio a from the specified target gear ratio a* can often be tolerated, especially if these deviations are smaller than a specified maximum deviation. As mentioned above, a relative value of 10% can preferably be selected as the maximum deviation from a target gear ratio a*. In such a case, the gear ratio a may not deviate by more than ±10% from the selected target gear ratio a* (ideally a*=1). Likewise, a relative value of 20% or even 30% can be selected for the maximum deviation from the target gear ratio a*. When designing a DC-DC converter 100 according to the invention, care must be taken to ensure that a specified maximum deviation is not exceeded.

[0060] For transmission ratios a in a value range of 0.9 to 1.1 - i.e. for deviations of less than 10% from a target transmission ratio a*=1 - almost symmetry is achieved with regard to the choke currents i Li , ii_2 is achieved. Symmetry with respect to the inductor currents i Li , ii_2 means that the time characteristics of the choke currents i Li , ii_2 do not differ except for a time shift. However, at a transformation ratio a of 0.5, i.e., a deviation of 50% from a target transformation ratio a*=1, the aforementioned symmetry is lost. In such cases, discontinuous operation can no longer be guaranteed with certainty. On the contrary, in such cases, a so-called "continuous current mode" (CCM) can occur, in which the inductor currents i Li, ii_2 through the chokes Li, l_2 do not cease to flow. With regard to the switching losses under consideration, such a situation is disadvantageous for obvious reasons, in particular because in such a scenario, current-free closing of the switches Si, S2 can no longer be guaranteed.

[0061] The ratio of the leakage inductances L ffl ,L ff2 The respective sub-voltage transformers 11 A, 11 B are ideally also assigned the value 1. Deviations in the ratio of leakage inductances L ffl ,L ff2 from a predetermined target ratio (e.g. the value 1) of less than ±20%, but preferably of less than ±10%, can be tolerated in the usual practical cases, so that despite deviations, low-loss operation of the DC-DC converter 100 according to the invention can be ensured.

[0062] Figures 3-8 show exemplary current and voltage waveforms that can occur during operation of a DC-DC converter 100 according to the invention with a discharge capacitor CB. The following discussion also addresses the control sequence of the switches Si, S2 used to generate the current and voltage waveforms shown.

[0063] According to the above-mentioned control sequence, in a first control step 1, the switch S1 of the first sub-voltage converter 11A and the switch S2 of the second sub-voltage converter 11B are closed. In this situation, the choke outputs LAi, LA2 are electrically connected to the reference potential G, as shown in Fig. 3a (left). As a result, the total input DC voltage U e at the chokes Li , L2 and the choke currents i Li, ii_2 in the chokes Li , L2 increase. The corresponding current waveforms are shown in Fig. 3b in the interval Ai.

[0064] In a second control step 2, switch S1 of the first sub-voltage converter 11 A is opened, as shown in Fig. 4a. This results in the current path for the first sub-voltage converter via the initially uncharged discharge capacitor CB. The resulting current waveforms are shown in Fig. 4b; the corresponding interval is now A21.

[0065] During the second control step 2, the current path for the sub-voltage converter 11A also changes, as shown in Fig. 5a. As soon as the discharge capacitor CB is charged, i.e., the potential at node K1 of the sub-voltage converter 11A rises above that of output A, the current valve D1 becomes conductive, resulting in the situation shown in Fig. 5a. The corresponding currents can again be seen in Fig. 5b, where the corresponding curves in interval A22 are highlighted.

[0066] In a third control step 3, switch S2 of the second sub-voltage converter 11B is now also opened, which initially creates the current path shown in Fig. 6a. The current path shown in Fig. 6a initially runs via the discharge capacitor CB. During the third control step 3, as in the second control step 2, the current path also changes.

[0067] Accordingly, as soon as the discharge capacitor CB is discharged and the current control valve D2 becomes conductive, the situation shown in Fig. 7a arises. The corresponding time interval in Fig. 7b is A3. In time interval A3, the inductor currents i flowing through the inductors Li, L2 decrease. Li , ii_2. The gradient of the choke currents i Li , ii_2 is determined by the leakage inductances L in the sub-voltage transformers ffl ,L ff2 The gradients must be large enough so that before the end of a control period T s the currents can be reduced to zero. Only in this way is it possible to switch on or close the switches Si, S2 without current, which is precisely what the topology of the invention ensures.

[0068] After the third control step 3, essentially the first to third control steps 1 to 3 are repeated, which is shown in Figures 3-8 by the bracketed numbers 4-6 and the bracketed intervals 1 4-6to identify a fourth to sixth control step 4 to 6. In this regard, Fig. 8 shows how a new switching period can be started by closing the switches Si, S2 again. The only difference between the sequence of the first to third control steps 1-3 and the sequence of the fourth to sixth control steps 4-6 is that in a fifth control step 5, switch S2 of the second sub-voltage converter 11B is opened first and only in a sixth control step 6 is switch S1 of the first sub-voltage converter 11A opened. In this sense, for example, in the fifth control step 5, the switch current iSi would increase and the switch current is2 would go to zero, and not the other way around as in the second control step 2. As described, the time interval A3 begins at the time at which the discharge capacitor CB is discharged.As is well known, a capacitor is discharged when it no longer holds any electrical charge and, consequently, when no further electrical voltage drops across it. If no further voltage drops across the discharge capacitor CB, this means that the nodes K1 and K2 have the same electrical potential. Since the respective choke outputs LAi and LA2 also have the same electrical potential, and since the respective choke inputs LE1 and LE2 already have the same electrical potential due to their electrically conductive connection to the input E, from this point onward, the same electrical voltage drops across both chokes Li and L2.

[0069] If the inductances of the chokes Li , L2 are also identical, identical falling current edges of the choke currents i result. Li , ii_2. If the choke currents i Li, ii_2 at the beginning of the time interval A3 also have the same value, which is usually the case within the scope of the invention, both choke currents i Li , ii_2 simultaneously have the value zero. This means that there is at least one time point in time when both inductor currents i Li , ii_2 and thus also the total current across both chokes Li, L2 are simultaneously zero. The total current across both chokes Li, L2 is simultaneously the input current into the DC-DC converter 100, which thus becomes zero at least at one point in time, which further contributes to a reduction in losses.

[0070] Independently of the specific embodiments, the invention generally applies that a particularly advantageous embodiment can be achieved by the inductor currents i flowing through the inductors Li, L2 L i, ii_2 during the gap phases A provided according to the invention Lbe brought to zero at least at one time.

[0071] From the above explanations, it is also clear that the electrical state of the discharge capacitor CB, i.e., the electrical charge it holds or the electrical voltage drop across it, is advantageously taken into account during operation of the DC-DC converter 100. In particular, the time at which the switches Si, S2 are simultaneously closed can be selected depending on the discharge capacitor CB and / or its electrical state, or the pause between the opening of the switches Si, S2 can be adapted to the discharge capacitor CB and / or its electrical state.

[0072] A control unit can be provided in the DC-DC converter 100 to control the switches Si, S2. Such a control unit can determine ignition pulses or control signals in a manner well known in the field of power electronics and supply them to the switches Si, S2 for control. However, a control unit can also be implemented separately from a DC-DC converter 100 and only be wired to the switches Si, S2 for control. Possible implementations of such a control unit include microprocessor-based hardware, such as microcontrollers and integrated circuits (ASICs, FPGAs).

[0073] A further aspect of the present invention allows, in addition to the advantages mentioned, an additional improvement in the efficiency TJ of the DC-DC converter 100. Thus, the fact that a relief capacitor CB is not short-circuited by a short-circuit switch SB within the scope of the present invention can lead to small, but nevertheless existing voltages u even in the gap phases mentioned. c at the discharge capacitor CB, which is shown in Fig. 9. Fig. 9 shows a gap interval A taken from the previous figures L . The tensions and c are in the gap interval A shown Lin the form of oscillations, since the discharge capacitor CB forms an oscillating circuit with the chokes Li, L2. Since the discharge capacitor CB is in turn connected between the switch inputs SE1, SE2 of the switches Si, S2, oscillations in the voltage Uc dropped across the discharge capacitor CB have a direct effect on the switch voltages usi, us2 dropped across the switches Si, S2, so that oscillations also occur in the switch voltages usi, us2.

[0074] In an advantageous manner, oscillations in the switch voltages usi, us2 can be used to close the switches Si, S2 with particularly low losses. Thus, the first and fourth control steps 1 and 4 of the control sequence described above, i.e., the closing of the switches Si, S2, can take place at switching times VP (“valley points”, “valley switching”), in which the switch voltages usi, us2 are lower than the input voltage U eassume only low voltage values. If the switch voltages usi, us2 are present in the form of a (sinusoidal) oscillation, the times at which the switch voltages usi, us2 assume only low values ​​are, in particular, those times at which the switch voltages usi, us2 are in an oscillation valley of the corresponding (sinusoidal) oscillation. In oscillation valleys, the switch voltages usi, us2 assume local minima with regard to their temporal characteristics, as shown exemplarily in Fig. 9b.

[0075] In order to determine suitable switching times VP, the switching voltages usi, us2 dropping across the switches Si, S2 can be measured. Measured values ​​of the switching voltages usi, us2 can subsequently be transmitted to a control unit, which can check whether the switching voltages usi, us2 are sufficiently low, or whether they even assume a local minimum, or whether they are close to a local minimum. With such an optimization of the switching times VP when closing the switches Si, S2, the efficiency TJ of the DC-DC converter 100 according to the invention can be improved, particularly in the partial load range.

[0076] For the concrete implementation of the aforementioned steps for optimizing the switching times VP, the switching voltages usi, us2 dropping across the switches S1, S2 can be measured in a form of valley switching applied to the DC-DC converter 100 according to the invention. The measured switching voltages usi, us2 can be transmitted to a control unit via a suitable interface, and a comparator signal UK can be determined or generated in the control unit from the measured switching voltages usi, us2, for example by comparing one of the switching voltages usi, us2 with a predetermined threshold U xA comparator signal UK can also correspond to one of the measured switch voltages usi, us2. A comparator signal can also correspond to a filtered, for example, low-pass filtered, version of one of the measured switch voltages usi, us2. The switch voltages usi, us2 can also be combined into a comparator signal, for example, by averaging the two switch voltages usi, us2.

[0077] A circuit for implementing the steps described above is shown in Fig. 9a. A measured switch voltage usi, us2 is first compared with a given threshold U xcompared. The result of this comparison is then logically ANDed with the signal UPWM. The signal UPWM is a pulsed control signal with a predetermined switching frequency with which the switches Si, S2 are opened and closed within the framework of PWM (pulse width modulation). However, a different control method could just as easily be used, such as PFM (pulse frequency modulation). The result of this AND operation is then again combined with the inverse of the signal UPWM in the subsequent flip-flop, so that the actual control signal is only passed on to the switches Si, S2 when the control signal UPWM and the comparator signal UK simultaneously assume a logical high level. The resulting signal waveforms and the resulting control signal uc are shown in Fig. 9b.

[0078] The barrier U x can, for example, be expressed in the form of a relative value of the input voltage Ue For a barrier U x in the form of a relative value of the input voltage U e It may be required that the comparator signal must fall below the threshold in order to switch the switches Si, S2. For example, a relative value of 30% of the input voltage U can be used for the threshold. e or a relative value of 20% of the input voltage U e be specified, or a relative value of 10% of the input voltage U e be specified, or preferably a relative value of 1% of the input voltage U e be specified. If the comparator signal UK falls below this threshold, the switches Si , S2 can be closed. By falling below a threshold U xThe comparator signal can be used to ensure in a simple and robust manner that the switch voltages usi, us2 dropped across the switches Si, S2 have only low values ​​and thus a low-loss closing of the switches Si, S2 is enabled.

[0079] How the described measures can affect the efficiency of a DC-DC converter 100 is finally shown in Fig. 10. Therein, achievable efficiencies TJ are shown over an input power P fed into a DC-DC converter 100, 300. in The efficiency J / 100 is shown here in solid lines, the efficiency J / 300 dashed. It can be seen that significant improvements in efficiency TJ are possible, especially in the lower power range.

Claims

Patent claims 1. Electrical DC-DC converter (100) with one input (E), one output (A) and one reference potential (G) for converting an input DC voltage (U) dropping between the input (E) and the reference potential (G). e ) into an output DC voltage (U) dropping between the output (A) and the reference potential (G). a), comprising a first and a second sub-voltage converter (11A, 11B), each containing an electrical inductor (Li, L2) with one inductor input (LE1, LE2) and one inductor output (LAi, LA2), each containing a switch (Si, S2) which is switched at a switching period (Ts) recurring with a predetermined switching frequency (fs), with one switch input (SE1, SE2) and one switch output (SA1, SA2), and each containing a current valve (Di, D2) with one current valve input (DE1, DE2) and one current valve output (DA1, DA2), wherein the inductors (Li, L2) provided in the sub-voltage converters (11A, 11B) are electrically connected to the input (E) of the DC-DC converter (100) via the respective inductor input (LE1, LE2) and via the respective Choke output (LAi, LA2) via a node (Ki, K2) of the respective sub-voltage converter (11 A, 11 B) with the switch input (SE1, SE2) of the respective switch (Si,S2) and are electrically connected to the current valve input (DE1, DE2) of the respective current valve (Di, D2), and wherein the switch output (SA1, SA2) of the respective switch (Si, S2) is electrically connected to the reference potential (G), and wherein the respective current valve output (DA1, DA2) of the respective current valve (Di, D2) is electrically connected to the output (A) of the DC-DC converter (100), characterized in that the chokes (Li, L2) provided in the sub-voltage converters (11A, 11B) are wound in opposite directions and magnetically coupled by means of a magnetic core (Fe), that the turns ratio a between the chokes (Li, L2) provided in the sub-voltage converters (11A, 11B) and the leakage inductances (L, S igi , L Sig2), which are formed in the respective sub-voltage converters (11A, 11B) due to the magnetically coupled chokes (Li, L2), are adapted to the specified switching frequency (fs) in such a way that the effect of the main inductance (Lh), which is formed by the coupled chokes (Li, L2), on choke currents (ii, ii_2) flowing in the respective sub-voltage converters (11A, 11B) is eliminated and that at least one gap phase (A) occurs during the switching periods (Ts) for switching the switches (Si, S2). L ) sets the throttle currents flowing through the throttles (i i , ii_2) become zero at at least one time point, and that the in the sub- Voltage transformers (11 A, 11 B) provided switch (Si, S2) in such a gap phase ( A L ) will be closed.

2. Electrical DC-DC converter (100) according to claim 1, characterized in that a load shear capacitor (CB) is connected between the node (K1) of the first sub-voltage converter (11A) and the node (K2) of the second sub-voltage converter (11B).

3. Electrical DC-DC converter (100) according to one of the preceding claims, characterized in that the turns ratio a between the chokes (Li, L2) provided in the sub-voltage converters (11A, 11B) deviates by no more than a predetermined maximum deviation from a predetermined target turns ratio a*.

4. Electrical DC-DC converter (100) according to claim 3, characterized in that the target transformation ratio a* corresponds to a value of 1 and that the specified maximum deviation from the target transformation ratio a* corresponds to a relative value of 30%, or a relative value of 20%, or a relative value of 10%.

5. Electrical DC-DC converter (100) according to one of the preceding claims, characterized in that the ratio of the leakage inductances L ffl ,L ff2 in the respective sub-voltage converters (11 A, 11 B) deviates by no more than a specified maximum deviation from a specified target ratio.

6. Electrical DC-DC converter (100) according to claim 5, characterized in that the nominal ratio of the leakage inductances L ffl ,L ff2 that corresponds to a value of 1 and that the specified maximum deviation from the target ratio corresponds to a relative value of 30%, or a relative value of 20% or a relative value of 10%.

7. Electrical DC-DC converter (100) according to one of the preceding claims, characterized in that a smoothing capacitor (C) is connected between the output (A) and the reference potential (G). a) is switched to adjust the output DC voltage (U) generated by the DC-DC converter (100). a ) to smooth it out.

8. Method for controlling the electrical DC-DC converter (100) according to one of claims 1 to 7, characterized in that the electrical DC-DC converter (100) is controlled according to a control sequence in which the switch (S1) of the first sub-voltage converter (11A) and the switch (S2) of the second sub-voltage converter (11B) are closed simultaneously (1), then first the switch (S1) of the first sub-voltage converter (11A) is opened (2), then the switch (S2) of the second sub-voltage converter (11 B) is opened (3), then again the switch (S1) of the first sub-voltage converter (11A) and the switch (S2) of the second sub-voltage converter (11 B) are closed simultaneously (4), then first the switch (S2) of the second sub-voltage converter (11 B) is opened (5), and then the switch (S1) of the first sub-voltage converter (11 A) is opened (6).

9. Method according to claim 8, characterized in that the control sequence for controlling the electrical DC voltage converter (100) is carried out cyclically.

10. Method according to claim 8 or 9, characterized in that the switches (Si , S2) of the respective sub-voltage transformers (11A, 11B) are closed at switching times (VP) in which a comparator signal (UK), which has been determined from the switch voltages (usi, US2) dropping across the switches (Si , S2), exceeds a predetermined limit (U x) falls below.

11. Method according to claim 10, characterized in that the predetermined limit (U x ) as the relative value of the input voltage (U e ) as 1% of the input voltage (Ue), or as 10% of the input voltage (U) e ), or as 20% of the input voltage (U e ), is specified.

12. Method according to claim 8 or 9, characterized in that the switches (Si , S2) of the respective sub-voltage transformers (11 A, 11 B) are closed at switching times (VP) in which the time profiles of the switch voltages (usi, us2) dropping across the switches (Si , S2) assume a local minimum in their time profile or in which the switch voltages (usi, US2) deviate by no more than 10% from a local minimum in their time profile.

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