Substrate for electronic device

Abstract

The invention relates to a substrate for a power or radiofrequency electronic device, comprising: • a support substrate (30) made of polycrystalline silicon carbide, having a front face (10) and a rear face (20), said support substrate (30) being self-supporting, and • a surface layer (1) of monocrystalline silicon carbide that extends over the front face (10) of said support substrate (30), said substrate being characterised in that the support substrate (30) has at least one porous portion (3) extending from the rear face (20), said porous portion (3) having a degree of porosity of greater than 5%.

Description

[0001] SUBSTRATE FOR ELECTRONIC DEVICE

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to a substrate for an electronic device, in particular for application to power or radiofrequency electronics. The invention also relates to an electronic device comprising such a substrate, and to a method of manufacturing such a substrate.

[0004] STATE OF THE ART

[0005] Silicon carbide (SiC) is widely used in the manufacture of power and radio frequency electronic components.

[0006] A substrate for making such components typically comprises a support substrate, which may be polycrystalline SiC (p-SiC), and a surface layer of monocrystalline SiC (m-SiC) extending over the support substrate. Electronic components are fabricated in or on the monocrystalline SiC layer. The structure is diced into chips, each comprising one or more electronic components. Each chip is soldered to a heat sink stack, comprising metal layers, a heat-conducting ceramic, and a heat sink.

[0007] The heat is thus evacuated mainly by the heat dissipation stack, involving significant thermal stresses on the filler material soldering the electronic component and the upper metal layer of the heat dissipation stack.

[0008] However, the coefficient of thermal expansion (CTE) and Young's modulus of SiC and the thermal stack, especially copper, are very different. Temperature variations therefore cause deformations of unequal magnitude in the different layers above and below the solder.

[0009] Thus, the filler material is highly stressed, which leads to cracks, delaminations, or crumbling at the solder interface, resulting in a shortened device life.

[0010] To reduce these mechanical constraints, it is known to thin the layers of the composite structure, particularly the polycrystalline SiC base substrate. However, the abrasion of such a base substrate is long and laborious, resulting in a high cost of the electronic component. In addition, thinning involves a risk of breakage, making the composite structure unusable.

[0011] Another solution is to modify the materials used to carry out the brazing, which is difficult to implement, in particular while preserving the mechanical strength and the electrical and thermal conductivity of the brazing. DISCLOSURE OF THE INVENTION

[0012] An aim of the invention is to propose a composite structure for the production of electronic devices, exhibiting better resistance to temperature cycles, while avoiding cracks, delaminations and crumbling at the soldering interface.

[0013] To this end, the invention provides a substrate for a power or radiofrequency electronic device, comprising

[0014] • a polycrystalline silicon carbide support substrate having a front face and a rear face, said support substrate being self-supporting, and

[0015] • a surface layer of monocrystalline silicon carbide extending over the front face of said support substrate, said substrate being characterized in that the support substrate has at least one porous portion extending from the rear face, said porous portion having a porosity rate greater than 5%.

[0016] The support substrate has a thickness greater than 50 pm, advantageously greater than 80 pm, more advantageously greater than 100 pm and even more advantageously greater than 150 pm.

[0017] Preferably, the porous portion comprises a layer of porosified SiC.

[0018] In some embodiments, the support substrate comprises a non-porous portion between the surface layer of monocrystalline SiC and the porous portion.

[0019] In some embodiments, the porous portion has a rear portion having a first porosity level and a front portion having a second porosity level lower than the first level.

[0020] The porous portion may have a decreasing porosity gradient from the back face to the front face.

[0021] The porous portion may have pores filled with a material having a Young's modulus lower than the Young's modulus of silicon carbide.

[0022] Advantageously, the average distance between the pores is greater than 10nm, preferably greater than 50nm.

[0023] The invention also relates to an electronic device comprising a substrate as described above and at least one electronic power or radiofrequency component formed in or on the surface layer of monocrystalline silicon carbide.

[0024] Preferably, the electronic device further comprises a heat removal device, the substrate being brazed to the heat removal device via a filler material such that the filler material is in integral contact with at least a portion of the porous portion on the rear face of the support substrate. Another subject of the invention relates to a method for manufacturing a power or radiofrequency electronic device comprising:

[0025] • a self-supporting polycrystalline silicon carbide support substrate having a front face and a rear face, and

[0026] • a surface layer of monocrystalline silicon carbide extending over the front face of said support substrate, the method being characterized in that it comprises a step of forming, in the support substrate, at least one porous portion extending from the rear face, said porous portion having a porosity rate greater than 5% and a thickness greater than 100 nm, advantageously greater than 1 μm, and more advantageously greater than 3 μm.

[0027] The method may further comprise a step of assembling the surface layer and the support substrate.

[0028] Preferably, the support substrate has a thickness greater than 50 pm, advantageously greater than 80 pm, more advantageously greater than 100 pm and even more advantageously greater than 150 pm.

[0029] Advantageously, the formation of the support substrate comprises a step of porosifying at least a portion of a non-porous silicon carbide base substrate to form the porous portion.

[0030] In some embodiments, porosification is performed across the base substrate to form a fully porous support substrate.

[0031] Porosification can be carried out so as to form a decreasing porosity gradient in the porous portion from the back face to the front face.

[0032] Porosification can be carried out so as to form a bonding zone having a porosity rate of less than 40% on the front face of the support substrate.

[0033] In some embodiments, the method comprises a step of filling at least a portion of the pores of the porous portion with a material having a Young's modulus lower than the Young's modulus of silicon carbide.

[0034] The method may further comprise a step of thinning the support substrate via the rear face, so that the thickness of the porous portion remains greater than or equal to 100 nm.

[0035] BRIEF DESCRIPTION OF THE FIGURES

[0036] Other characteristics and advantages of the invention will emerge from the detailed description which follows, with reference to the appended drawings, in which:

[0037] Figure 1 illustrates a device comprising two electronic components made from a substrate according to the invention and a heat dissipation stack. Figure 2 illustrates a substrate according to the invention comprising a surface layer of monocrystalline silicon carbide and a support substrate comprising a porous portion.

[0038] Figure 3 illustrates a substrate according to the invention comprising a surface layer of monocrystalline silicon carbide and a support substrate comprising a porous portion of porosified polycrystalline SiC and a non-porous portion.

[0039] Figure 4 illustrates a substrate according to one embodiment comprising a surface layer of monocrystalline silicon carbide and a support substrate comprising a porous portion of sintered SiC and a non-porous portion.

[0040] Figure 5 illustrates a substrate according to another embodiment comprising a surface layer of monocrystalline silicon carbide and a support substrate comprising a non-porous portion and a porous portion comprising two zones having different porosity rates.

[0041] Figure 6 is a graph of fracture resistance measurement of a porous silicon carbide substrate as a function of the porosity of said substrate.

[0042] Figures 7A to 7D illustrate the steps of an embodiment of a method for manufacturing a substrate according to the invention.

[0043] Figures 8A to 8C illustrate the steps of another embodiment of a method of manufacturing a substrate according to the invention.

[0044] Figures 8D-8C illustrate the steps of a variation of the embodiment of the method illustrated in Figures 8A-8C.

[0045] Figures 9A and 9B illustrate the steps of a third embodiment of a method for manufacturing a substrate according to the invention.

[0046] Figures 10A to 10F illustrate the steps of a fourth embodiment of a method for manufacturing a substrate according to the invention.

[0047] Figures 11 A to 11 E illustrate the steps of a fifth embodiment of a method for manufacturing a substrate according to the invention.

[0048] Figure 12 is a graph of the Young's modulus of different porous silicon carbide samples as a function of the porosity rate of the samples.

[0049] Figure 13 is a graph of the Young's modulus of different silicon carbide samples.

[0050] For reasons of readability of the figures, the structures illustrated have not necessarily been represented to scale.

[0051] DETAILED DESCRIPTION OF EMBODIMENTS

[0052] Figure 1 illustrates a power or radiofrequency electronic device comprising one or more electronic chips 11, 12 produced from a substrate according to the invention. The chips can be linked by interconnections. In the case of a radiofrequency device, the electronic chip can carry a lateral device made of gallium nitride.

[0053] The electronic chips 11, 12 are mounted on a heat-dissipating structure by solders 21, 22. This heat-dissipating structure (DBC, acronym for Direct Bonded Copper) comprises two copper metallizations 17, 19 and a substrate 18 made of a heat-conducting and electrically insulating ceramic, for example aluminum nitride. Electrical connections 27, 28 are fixed to the copper metallization 17 by means of solders 25, 26.

[0054] A solder 29 fixes the device to a heat sink 34 and a base plate 32. A layer of thermal grease 31 provides thermal contact between the sink 34 and the base plate 32. The power electronic or radio frequency device is encapsulated in a housing 39 which is typically made of plastic.

[0055] Each chip is formed from a substrate comprising a silicon carbide support substrate and a surface layer of monocrystalline silicon carbide in or on which is formed at least one power electronic component or one radio frequency electronic component.

[0056] The surface layer of monocrystalline silicon carbide typically has a thickness of between 100 nm and 1500 nm. On this surface layer, a monocrystalline layer of silicon carbide with a thickness of between 1 pm and 150 pm can be deposited by epitaxy, in which at least part of the electronic component is formed.

[0057] The support substrate has a front face, on which the surface layer extends, and a rear face opposite the front face.

[0058] The surface layer may have been assembled on the support substrate, which may then be polycrystalline, according to embodiments which will be described below.

[0059] The support substrate may itself be a single piece or consist of a stack of at least two layers. The thickness of the support substrate is preferably chosen so that the support substrate is self-supporting without the surface layer, i.e. it is mechanically stable to be handled on its own, without the addition of support or additional handling substrate. For this purpose, the support substrate typically has a thickness greater than 150 μm, advantageously greater than 100 μm, more advantageously greater than 80 μm and even more advantageously greater than 50 μm. The use of a self-supporting support substrate facilitates the substrate manufacturing steps.

[0060] In some cases, the electronic device may be fabricated from a support substrate with no thickness limit that is not necessarily self-supporting. In this case, the heat removal device makes it possible to mechanically stabilize the electronic component. The fabrication of such a substrate may require a handling support. However, the support substrate may be made according to the same embodiments as a self-supporting support substrate.

[0061] In the case of a power electronic device, good electrical conductivity between the thin film and the supporting substrate is necessary. For such a device, the supporting substrate has, for example, an electrical resistivity of 50 mfi.cm or less, especially 20 mfi.cm or less.

[0062] In the case of a radiofrequency device, the support substrate advantageously has a high electrical resistivity, for example an electrical resistivity greater than 500 Q.cm.

[0063] The support substrate has at least one porous portion extending from the rear face. The surface layer, on the other hand, is non-porous, i.e. it has a porosity rate of less than 5% or zero.

[0064] The porosity of silicon carbide is defined as the fraction of unoccupied volume within the silicon carbide, which volume may be filled with air or another gas or with solid inclusions of another material. For example, pores in a porous silicon carbide layer may be filled with carbon inclusions.

[0065] The pores may be interconnected or separated from each other, depending in particular on the method of forming the porous portion. Typically, pores resulting from electrochemical porosification of silicon carbide are at least partially interconnected and are generally filled with air. In the case of porous silicon carbide obtained by sintering, the pores are typically separated from each other and may be at least partially filled with carbon inclusions.

[0066] In the case of interconnected, air-filled pores, porosity can be measured gravimetrically. In other cases, porosity can be measured by reflectivity of a porous silicon carbide surface. Porosity can also be measured by observing a section of porous silicon carbide under an optical or scanning electron beam microscope and estimating the quotient between the surface area occupied by pores and / or inclusions and the surface area occupied by silicon carbide.

[0067] The porosity rate of the porous portion of the support substrate is advantageously between 5% and 30%, and, in the case of a porosified silicon carbide substrate, more advantageously between 5% and 20%. The porosity rate may be constant over the entire thickness of the porous portion, or may be variable in stages or continuously according to a gradient, according to embodiments described below.

[0068] The presence of such porosity makes it possible to reduce the Young's modulus of silicon carbide. Figure 12 illustrates the Young's modulus (modulus of elasticity, E) of silicon carbide as a function of the porosity rate d> according to L.L. Snead et al. Despite the wide dispersion, it can be seen that the decrease in Young's modulus is visible even for low porosity rates, and particularly marked from a porosity rate of approximately 5%. In the case where the pores are filled by inclusions of a solid material, said solid material advantageously has a Young's modulus lower than that of silicon carbide, so as not to counterbalance the reduction in Young's modulus provided by the porosity of the silicon carbide. Furthermore, in order not to degrade the electrical conductivity of the support substrate, the solid material is advantageously electrically conductive. For example, the inclusions may comprise carbon, silicon, a metal or a metal alloy.

[0069] A porosity rate of less than or equal to 30% makes it possible to maintain acceptable breaking strength with regard to the mechanical stresses likely to be applied to the chip, particularly when the entire support substrate is porous. Figure 6 shows measurements of breaking strength in MPa ■ m 1 / 2 depending on the porosity of a porous silicon carbide sample. For a porosity rate up to about 25%, the change in fracture toughness is negligible for the behavior of the electronic chip.

[0070] In some embodiments, the porous portion extends throughout the thickness of the support substrate.

[0071] In other embodiments, the porous portion extends only over a portion of the thickness of the support substrate. In this case, a non-porous intermediate portion extends between the porous portion and the surface layer. Such a configuration typically exhibits improved resistance to fracture of the substrate.

[0072] In all cases, the porous portion has a total thickness greater than 100 nm, preferably greater than 1 pm, or even greater than 3 pm.

[0073] Thanks to such a thickness, combined with the aforementioned porosity, the porous portion of the support substrate has a Young's modulus significantly lower than that of non-porous silicon carbide and thus exhibits a behavior more favorable to the reduction of the mechanical stresses exerted on the brazing filler material during temperature variations experienced by the device.

[0074] Figure 13 is a graph (obtained by computer simulation) of the relative stress at the fatigue point in the solder as a function of the Young's modulus E for different silicon carbide substrates, having a porous portion of different thicknesses. The total thickness of each substrate is 350 μm. Curve 1 corresponds to a substrate having no porous portion, curve 2 corresponds to a porous portion thickness of 1 μm, curve 3 to 5 μm, curve 4 to 10 μm, curve 5 to 25 μm, curve 6 to 50 μm, and curve 7 corresponds to a porous portion thickness of 100 μm. Each curve presents the stress in the solder at the outermost point of contact between the solder and the porous SiC, divided by the stress in the case where no porous layer is present. The stress at the fatigue point of the solder decreases with increasing thickness of the porous portion.In the simulations, it is assumed that the Young's modulus of porous SiC depends on the porosity as shown in Figure 12. For example, in the case of a porosification rate of 5%, the Young's modulus is 400 GPa. In the case of a 10 μm thick layer (curve 4), a relative stress at the fatigue point of 0.93 is obtained, i.e. the stress is reduced by 7% compared to a substrate without a porous portion. For a porosification rate of 15%, corresponding to a Young's modulus of 300 GPa, and a porous layer with a thickness of 20 μm, the relative stress at the fatigue point is 0.8 and therefore reduced by 20% compared to a substrate without a porous portion.

[0075] The Young's modulus of the porous portion of the support substrate, which is located at the soldering interface, is closer to the Young's modulus of the DBG structure than the Young's modulus of the surface layer. This implies that the deformations caused by temperature variations are less significant and closer to those of the DBC structure and the solder. Consequently, the mechanical stresses exerted on the solder due to these deformations are less significant than in known chips. The reduction of these stresses increases the lifetime of the solder and the power or radiofrequency electronic device.

[0076] Finally, the presence of such a porous portion on the back face of the substrate does not penalize the electrical conductivity of the substrate in power applications.

[0077] Examples of embodiments

[0078] Figure 2 illustrates a first substrate according to the invention, comprising a support substrate 30 and a surface layer 1. The support substrate 30 consists of a single porous portion 3 made of porous silicon carbide, having a homogeneous porosity. This porous portion is made of sintered silicon carbide, porosified polycrystalline silicon carbide or porosified monocrystalline silicon carbide. The porous portion extends from the rear face 20 to the front face 10 of the support substrate 30. The surface layer 1 is made of non-porous monocrystalline silicon carbide. This layer is arranged on the front face of the support substrate 30. In certain embodiments, the porous portion and the surface layer are formed in one piece from a single monocrystalline silicon carbide substrate.

[0079] Figure 3 illustrates a second embodiment, in which the support substrate 30 comprises a portion 3A of porosified silicon carbide extending from the rear face 20 of the substrate. The porosity of this portion 3A is homogeneous. The pores are interconnected and filled with air. The support substrate 30 further comprises a non-porous portion 2A of polycrystalline silicon carbide arranged between the porous portion and the front face 10 of the support substrate 30. A surface layer 1 of non-porous monocrystalline silicon carbide is arranged on the front face 10 of the support substrate 30. Figure 4 illustrates a third embodiment, in which the support substrate 30 comprises a portion 3B of sintered silicon carbide extending from the rear face 20 of the substrate. The sintered silicon carbide comprises carbon inclusions which can be separated from each other. The pores are thus filled with carbon, and typically not interconnected.The porosity of this portion is homogeneous. The support substrate 30 further comprises a non-porous portion 2B made of polycrystalline silicon carbide arranged between the porous portion 3B and the front face 10 of the support substrate 30. A surface layer 1 made of non-porous monocrystalline silicon carbide is arranged on the front face 10 of the support substrate 30.

[0080] Figure 5 illustrates a fourth embodiment, in which the support substrate 30 successively comprises, from its rear face 20 to its front face, a first porous portion 3C made of porosified silicon carbide, a second porous portion 2D made of sintered silicon carbide and a non-porous portion 2C. The pores of the first porous portion 3C are interconnected and filled with air. The pores of the second porous portion 2D are filled with carbon inclusions and separated from each other. The porosity rate of the layer 3C made of porosified silicon carbide is greater than the porosity rate of the portion 2D made of sintered silicon carbide. A surface layer 1 made of non-porous monocrystalline silicon carbide is arranged on the front face 10 of the support substrate 30.

[0081] In other embodiments not shown, the porous porosified silicon carbide portion has a porosity gradient, such that the porosity decreases from the back face toward the front face of the support substrate.

[0082] In other embodiments not shown, several sintered silicon carbide or porosified silicon carbide portions may be superimposed to form a support substrate 30 or a portion of a support substrate 30. The size and shape of the pores may be similar or different in the different porous portions. Advantageously, the average distance between the pores is greater than 10 nm, preferably greater than 50 nm, in each porous portion present in the substrate in order to avoid the formation of a possible depletion zone in the SiC.

[0083] In some embodiments, a support substrate that may be non-self-supporting is used to form a power or radio frequency electronics device. Said substrate comprises a polycrystalline silicon carbide support substrate having a front face and a rear face, and a surface layer of monocrystalline silicon carbide extending over the front face of said support substrate, said substrate being characterized in that the support substrate has at least one porous portion extending from the rear face, said porous portion having a porosity rate greater than 5%. At least one power or radio frequency electronic component is formed in or on the monocrystalline silicon carbide layer.The device may further comprise a heat removal device, the substrate being brazed to the heat removal device via a filler material such that the filler material is in integral contact with at least a portion of the porous portion on the rear face of the support substrate.

[0084] Substrate manufacturing

[0085] We will now describe the steps for manufacturing a substrate according to different embodiments.

[0086] Forming a substrate according to the invention comprises forming at least one porous portion.

[0087] A porous portion may be formed by porosification of a silicon carbide substrate. Known methods of porosification of silicon carbide, some of which are described or referenced in the publications of Y. Shishkin et al. and Gautier et al., may be applied to form the porous portion. Porosification may be performed from the front or back side of the substrate.

[0088] A porosification step may, for example, be carried out by immersion in an acid bath or by electrochemical or photoelectrochemical means. An electrochemical porosification may be an electrochemical anodization in which the portion to be porosified is placed in an electrolyte such as a solution comprising hydrofluoric acid and / or ethanol. An anode and a cathode immersed in the electrolyte are connected to an electrical source in order to apply an electric current between said electrodes. The anodization electrochemically decomposes, to a certain extent, the silicon carbide crystal in the region of the porous silicon carbide layer. Instead of uniformly decomposing the silicon crystal, the electrochemical decomposition may locally remove silicon atoms from the crystal lattice of the silicon carbide, thus forming small holes or pores in the silicon carbide crystal.At the end of the treatment, the porosified portion is rinsed to remove electrolyte residue.

[0089] In a porosification step, it is possible to preserve the non-porous structure of a portion of a substrate. In this case, the portion concerned is kept outside the electrolyte bath.

[0090] In some cases, the porosity thus formed is homogeneous over the entire support substrate, with the exception of the surface layer. In other embodiments, a decreasing porosity gradient is produced from the rear face to the front face, such that the porosity rate is lower on the surface layer side and higher on the rear face side. The porosity can also be increased in stages, by adjusting the porosification parameters first for a substrate of a certain thickness, and by continuing this porosification in portions of decreasing thickness extending from the rear face of the substrate. For each successive portion, the porosification parameters can be modified so as to create a higher porosity rate than in the previous step.

[0091] The porosity rate can be modified and a gradient created by varying various parameters of the substrate such as doping, and of the porosification process such as the applied current and voltage, the temperature, the composition of the electrolyte and, in some cases, the intensity and wavelength of an applied light.

[0092] Alternatively, a porous portion may be formed by sintering silicon carbide prior to substrate assembly. Sintering is a heat treatment of a silicon carbide structure at a temperature between 1600°C and 2400°C in an atmosphere that may be, for example, argon, nitrogen, or an inert gas. Such heat treatment may alter the distribution of carbon and silicon present in the substrate, thereby forming carbon inclusions in the silicon carbide.

[0093] In some embodiments, the porous area may be formed directly in a monocrystalline silicon carbide substrate comprising the surface layer, by porosifying said substrate over a portion of its thickness. In this case, the porosification is carried out from the rear face.

[0094] In other embodiments, forming the substrate may include assembling the support substrate and the surface layer. Forming the porous region of the support substrate may be performed before or after said assembly.

[0095] In some embodiments, forming the support substrate may include one or more steps of assembling two or more porous portions, and / or a porous portion with a non-porous portion.

[0096] The assembly of said layers or portions of substrates can be carried out by bonding, for example from a donor substrate in which a weakening zone is created in order to delimit the layer to be assembled. In this case, a Smart Cut™ type process is typically used. A weakening zone is formed in a donor substrate made of monocrystalline silicon carbide to delimit the layer to be assembled on the support substrate. The weakening zone is typically created by irradiation with ions, for example hydrogen and / or helium ions. The donor substrate is then bonded to the front face of the support substrate, the layer delimited by the weakening zone being arranged in direct contact with the front face of the support substrate. The donor substrate is then detached along the weakening zone, in order to transfer the monocrystalline silicon carbide layer to the support substrate, for example using a heat treatment.

[0097] Another technique for weakening a donor substrate is to create a weakening zone with a higher porosity than the material adjacent to this zone. In such a case, after bonding to the support substrate, the donor substrate can be detached by applying mechanical stress. Such mechanical stress is, for example, the insertion of a blade or other beveled tool, or the application of an air jet or a water jet. This technique can be used when transferring a porous layer or for thinning as described below.

[0098] Another embodiment of the assembly is a deposition on a portion of the substrate provided, for example a chemical vapor deposition (CVD) or a physical vapor deposition (PVD). For example, a layer of polycrystalline silicon carbide can be deposited by CVD or PVD on the surface layer of monocrystalline silicon carbide or on another layer of polycrystalline silicon carbide (porous or not), and all or part of the deposited layer can be porosified.

[0099] The step of assembling the support substrate and the surface layer of monocrystalline silicon carbide can be carried out on a base substrate intended to form a support substrate, on a finalized support substrate, or at the end of one or more steps of forming the support substrate.

[0100] In the case of bonding two porous portions or one porous portion and one non-porous portion, the porosity rate of the bonding interfaces is preferably less than 40%, preferably less than 15% and more preferably less than 5% in order to ensure good adhesion between the two portions.

[0101] One or more optional thinning steps may be carried out in order to adjust the thickness of the support substrate or a portion of the support substrate, and the porosity on its rear face. In order to carry out this thinning step, a weakening zone may be created on the rear side of the porous zone to be formed, having a porosity rate greater than 10%, advantageously greater than 15%, particularly advantageously greater than 30% relative to the porosity of the porous zone to be formed, at a determined depth which corresponds to the thickness of the porous portion to be formed. The substrate may then, or after an assembly step with one or more layers on the front face of the substrate, be cut along the weakening zone created. The cutting may be carried out by applying a mechanical stress, for example by inserting a blade or by applying an air jet or a water jet.The stress must be adapted to propagate a fracture wave along the weakening zone, which has a lower mechanical strength than the zones surrounding the weakening zone. Advantageously, such a weakening zone is surrounded by a portion of polycrystalline silicon carbide having a lower porosity rate than the weakening zone, for example 1% or 5% less porosity, advantageously 10% less porosity. In certain embodiments, thinning of the substrate is caused by breaking a porous portion which leaves on the surface the porous zone which will be fixed to the solder of the electronic component. Such thinning avoids a polishing step which can be long and expensive.

[0102] The thinning step can also be carried out by chemical etching or a mechanical abrasion technique.

[0103] Preferably, a porous portion is retained having a thickness greater than 100 nm, advantageously greater than 1 pm, and particularly advantageously greater than 3 pm. The thickness of the layer has an influence on the deformations caused by temperature variations. The mechanical stresses applied to the solder of the electronic chip thus decrease further with a greater thickness of the porous portion.

[0104] One or more thinning steps can also be applied after the creation of a porous portion, in order to adjust the thickness of said porous portion before assembly with another portion, porous or not.

[0105] An optional step of passivation or other treatment of the back face may be carried out, for example by deposition of a dielectric layer, such as silicon oxide, which forms a barrier layer in order to avoid direct contact between the silicon carbide and the surrounding air and, consequently, to avoid the creation of a depletion zone involving a decrease in the electrical conductivity of the back face.

[0106] Examples of embodiments

[0107] Figures 7A to 7D illustrate a method of manufacturing a substrate according to the invention, in which the surface layer and the support substrate are produced from a single starting substrate 40 made of monocrystalline silicon carbide.

[0108] With reference to FIG. 7A, a front face 410 is chosen, preferably a silicon face. A treatment can be applied to the front face 410, for example polishing. The portion extending from this front face 410 is intended to form the surface layer 41.

[0109] Then, with reference to FIG. 7B, porosity is formed from the rear face 420 of the portion intended to form the support substrate 43, so that no porosity is formed in the portion intended to form the surface layer 41.

[0110] It is then possible, optionally, to assemble one or more additional layers 43B, 43C on the rear face of the support substrate 43. The assembly of a first layer 43B is illustrated in FIG. 7C. The first layer 43B has a higher porosity rate than the portion 43 extending from the rear face 420 of the single porosified substrate. Such a layer is, for example, a sintered silicon carbide layer or a porosified silicon carbide layer, or a combination of two or more porous layers. A sintered silicon carbide layer can, for example, be obtained by reaction sintering at a temperature of approximately 2000°C. A new rear face 421 of the support substrate 430 to be formed is thus formed.

[0111] The optional assembly of a second layer 43C is illustrated in FIG. 7D. This assembly forms a new rear face 422 of the substrate to be formed. The second layer 43C has a higher porosity rate than the rear face of the first layer 43B. Thus, a new support substrate 431 is formed, the porosity of which increases successively from the front face 410 to the rear face 422 of the formed support substrate 431.

[0112] It is also possible to assemble one or more layers 43B, 43C on the rear face of the substrate 420 and / or to carry out additional porosification after assembly (not shown). For example, it is possible to first bond a sintered silicon carbide layer to the rear face of the starting substrate, then deposit a polycrystalline silicon carbide layer on the rear face of the sintered silicon carbide layer, and carry out a step of porosification of the polycrystalline silicon layer deposited on the sintered silicon carbide layer.

[0113] A preferred embodiment is illustrated in FIGS. 8A to 8C. A support substrate 530 is first formed and then an assembly is made with a surface layer 51 of monocrystalline silicon carbide.

[0114] With reference to FIG. 8A, a support substrate is formed from a polycrystalline silicon carbide substrate 50. With reference to FIG. 8B, a porosification of a portion 53 intended to form the porous portion extending from the rear face 520 of the substrate to be formed is carried out. With reference to FIG. 8C, the support substrate is assembled on its front face 510 with a surface layer 51 of monocrystalline silicon carbide, typically by a method of the Smart Cut™ type as described above.

[0115] In order to illustrate the variants of such an embodiment, a more complex method is illustrated in FIGS. 8D to 8I. In this embodiment, a support substrate is first formed and then an assembly is made with a surface layer 51 of monocrystalline silicon carbide.

[0116] To form the support substrate, it is possible, with reference to FIG. 8D, to start with a polycrystalline silicon carbide substrate 50. It is then possible to carry out porosification of said substrate as described above in order to form a porous zone 53 extending from the rear face 520 of the substrate 50. With reference to FIG. 8E, the porosification can be carried out such that only a portion 53 extending from the rear face 520 of the substrate has porosity, while retaining a portion 52 extending from the front face 510 in its original state without porosity. Alternatively, a porosity gradient can be created, so that the porosity rate increases successively or in stages from the front face 510 to the rear face 520 of the substrate 50. In other cases, with reference to FIG. 8F, the porosification is carried out homogeneously over the entire thickness of the substrate as illustrated in FIG. 8B.

[0117] It is then possible, with reference to FIG. 8G, to carry out an optional step of bonding a layer 53B having a higher porosity rate on the rear face 520 of the substrate and thus creating a new support substrate 531 comprising a new rear face 521. The layer 53B has a higher porosity rate than the portion 53 extending from the rear face 520 of the single porosified substrate. Such a layer is, for example, a layer of sintered silicon carbide or a layer of porosified silicon carbide with a higher porosity rate than that of the previously porosified portion 53, or a combination of two or more porous layers. A new rear face 521 of the support substrate 531 to be formed is thus formed. With reference to FIG. 8H, an additional porosification step may optionally be performed in a portion 53C extending from the new rear face 521 of the substrate to be formed.For this additional porosification step, the parameters will be chosen so that the portion 53C has a higher porosity rate than the porous layer 53B in its initial state. Thus, the porosity of the support substrate 532 increases progressively from its front face 510 to its rear face 522.

[0118] Optionally, one or more bonds of other layers with higher porosity rates can be made on the back side of the substrate (not shown).

[0119] Optionally, one or more layers with a lower porosity rate can be assembled on the front side of the substrate (not shown).

[0120] With reference to FIG. 8I, the support substrate is assembled on its front face 510 with a surface layer 51 of monocrystalline silicon carbide.

[0121] If no layer is assembled on the front side of the substrate 532, the surface layer 51 of monocrystalline silicon carbide can be assembled to the support substrate 532 between any two steps of the process of forming the support substrate 532.

[0122] In certain embodiments not illustrated, the assembly of a portion of the support substrate and the monocrystalline silicon carbide surface layer is carried out during the formation of the support substrate, before the completion of all the steps of the formation of said support substrate.

[0123] Other embodiments are illustrated in Figures 9A to 9B. With reference to Figure 9A, the support substrate may be formed from a sintered silicon carbide substrate 60. Sintered silicon carbide generally includes carbon inclusions, and is therefore a porous material whose pores are filled with these inclusions.

[0124] With reference to FIG. 9B, it is possible to assemble the support substrate 60 of sintered silicon carbide with a surface layer 61 of monocrystalline silicon carbide on its front face 610. Thus, the sintered silicon carbide substrate forms a single porous zone 60 extending from its rear face 620.

[0125] Alternatively, with reference to Figure 10A, we start from the same starting substrate 60 made of sintered silicon carbide. With reference to Figure 10B, we can deposit a layer 62 of polycrystalline silicon carbide on the front face 610 of the substrate 60 made of sintered silicon carbide. Such a deposition can for example be carried out by chemical vapor deposition (PVD). Thus, the substrate 60 made of sintered silicon carbide is used as a support and as a crystallization seed for the polycrystalline silicon carbide. We can, optionally, create porosity in the layer 62 of silicon carbide thus deposited, as illustrated in Figure 10C. In this case, the porosity rate created in the portion 62 deposited on the front face 610 is lower than the porosity rate in the initial substrate 60 made of sintered silicon carbide. In certain cases, said layer 62 is maintained in its initial non-porous state.

[0126] Optionally, with reference to FIG. 10D, a second layer 63 of polycrystalline silicon carbide can be deposited on the rear face 620 of the sintered silicon carbide substrate, forming a new support substrate 630 comprising a new rear face 621. A step of porosification of the layer 63 of polycrystalline silicon carbide on the rear face 620 is then carried out, with reference to FIG. 10E, so that the layer 63 on the rear face has a higher porosity rate than the substrate 60 of sintered silicon carbide.

[0127] Optional steps (not shown) of bonding and / or assembling one or more layers having a higher porosity rate on the back face of the substrate, or / or one or more layers having a lower porosity rate on the front face of the substrate can then be carried out.

[0128] With reference to FIG. 10F, the support substrate thus created is assembled with a surface layer 61 of monocrystalline silicon carbide on the front face 611 of the support substrate.

[0129] In another embodiment, with reference to Figure 11 A, we start with a donor substrate 70 made of monocrystalline silicon carbide, a portion 71 of which on the front face 710 is intended to form the surface layer. We form, with reference to Figure 11 B, a weakening zone 77 to delimit the portion 71 intended to form the front face of the substrate to be formed. Preferably, the weakening zone is created by implantation of hydrogen and / or helium atoms in the donor substrate.

[0130] Referring to Figure 11C, a portion 73 made of porous polycrystalline silicon carbide is assembled on the front face 710. The porosity of the portion 73 may be formed before or after the assembly of the portion 73 on the front face 71 of the donor substrate 70. For example, the portion 73 may be made of porosified or sintered silicon carbide before bonding. Alternatively, the portion 73 made of polycrystalline silicon carbide may be deposited, for example by CVD or by PVD, on a donor substrate 70 made of monocrystalline silicon carbide, and a porosification step is carried out on the portion 73 after the deposition step.

[0131] The porosity rate of portion 73 may be homogeneous, in the form of a gradient or several levels, or only concern a certain thickness of the substrate.

[0132] With reference to FIG. 11 D, the donor substrate 70 is detached from the portion 71, for example by heat treatment. With reference to FIG. 11 E, the portion 73 forms the porous silicon carbide support substrate, and the portion 71 forms the monocrystalline silicon carbide surface layer of the finalized substrate.

[0133] In some embodiments, a monocrystalline silicon carbide substrate is used to form the surface layer. The support substrate is then formed on the monocrystalline silicon carbide substrate, such that the front face of the substrate is in contact with the monocrystalline silicon carbide substrate. The formation of the support substrate may include one or more steps of deposition, porosification, sintering, and assembly of several portions forming the support substrate. The monocrystalline silicon carbide substrate may then be thinned as described above.

[0134] Chips for power electronics and / or radiofrequency applications can then be formed from such a substrate. When the device is designed for a radiofrequency application, the electronic chips can be formed in a layer of silicon carbide or a group III-N nitride, for example a stack of GaN / AIGaN / AIGanlnN layers delimiting a two-dimensional electron gas. Such a layer or stack is carried by the surface layer of monocrystalline silicon carbide.

[0135] REFERENCES

[0136] Y. Shishkin et al: Phoroelectrochemical etching of n-type 4H silicon carbide, Journal of Applied Physics 96, 2311, 2004

[0137] Gautier et al: Electrochemical formation of porous silicon carbide for micro-device applications, Materials science forum, ISSN: 1662-9752, Vol 924, pages 943-946, 2018 LL Snead et al, Journal of Nuclear Materials 371 (2007) 329-377

Claims

DEMANDS 1. Substrate for power electronic or radio frequency device, comprising o a support substrate (30) of polycrystalline silicon carbide having a front face (10) and a rear face (20), said support substrate (30) being self-supporting, and o a surface layer (1) of monocrystalline silicon carbide extending over the front face (10) of said support substrate (30), said substrate being characterized in that the support substrate (30) has at least one porous portion (3) extending from the rear face (20), said porous portion (3) having a porosity rate greater than 5%.

2. Substrate according to claim 1, in which the supporting substrate (30) has a thickness greater than 50 pm, advantageously greater than 80 pm, more advantageously greater than 100 pm and even more advantageously greater than 150 pm.

3. Substrate according to any one of claims 1 or 2, wherein the porous portion (3) comprises a layer (3, 3A, 3C) of porosified SiC.

4. Substrate according to any one of claims 1 to 3, wherein the supporting substrate (30) comprises a non-porous portion (2A, 2B, 2C) between the surface layer (1) of single-crystal SiC and the porous portion (3).

5. Substrate according to any one of the preceding claims, wherein the porous portion (3) has a rear part (3A, 3B, 3C) having a first porosity rate and a front part (2A, 2B, 2C) having a second porosity rate lower than the first rate.

6. Substrate according to any one of the preceding claims, wherein the porous portion (3) has a decreasing porosity gradient from the back face (20) to the front face (10).

7. Substrate according to any one of the preceding claims, wherein the porous portion (3) has pores filled with a material having a Young's modulus lower than the Young's modulus of silicon carbide.

8. Substrate according to any one of the preceding claims, wherein the porous portion (3) has pores, the average distance between said pores being greater than 10nm, preferably greater than 50nm.

9. Electronic device comprising a substrate according to any one of the preceding claims and at least one power electronic or radio frequency component formed in or on the surface layer (1) of single-crystal silicon carbide.

10. Electronic device according to claim 9, further comprising a heat dissipation device, the substrate being brazed onto the heat dissipation device via a filler material such that the filler material is in solid contact with at least a part of the porous portion (3) on the rear face (20) of the support substrate (30).

11. A method for manufacturing a power electronic or radio frequency device comprising: o a self-supporting polycrystalline silicon carbide substrate (30) having a front face (10) and a rear face (20), and o a surface layer (1) of monocrystalline silicon carbide extending over the front face (10) of said substrate (30), the method being characterized in that it comprises a step of forming, in the substrate (30), at least one porous portion (3) extending from the rear face (20), said porous portion (3) having a porosity rate greater than 5%.

12. Method according to claim 11, further comprising a step of assembling the surface layer (1) and the supporting substrate (30).

13. Method according to claim 11 or claim 12, wherein the support substrate (30) has a thickness greater than 50 pm, advantageously greater than 80 pm, more advantageously greater than 100 pm and even more advantageously greater than 150 pm.

14. A method according to any one of claims 11 to 13, wherein the formation of the support substrate (30) comprises a step of porosification of at least a portion of a non-porous silicon carbide base substrate to form the porous portion (3).

15. A method according to claim 14, wherein porosification is carried out over the entire base substrate to form a fully porous support substrate (30).

16. A method according to any one of claims 14 or 15, wherein the porosification is carried out so as to form a decreasing porosity gradient in the porous portion (3) of the back face (20) towards the front face (10).

17. A method according to any one of claims 14 to 16, wherein the porosification is carried out so as to form a bonding zone having a porosity rate of less than 40% on the front face (10) of the support substrate (30).

18. A method according to any one of claims 11 to 17, comprising a step of filling at least a portion of the pores of the porous portion (3) with a material having a Young's modulus lower than the Young's modulus of silicon carbide.

19. A method according to any one of claims 11 to 18, further comprising a step of thinning the support substrate (30) from the back face (20), so that the thickness of the porous portion (3) remains greater than or equal to 100 nm.

Images