Circuit assembly with two circuit carriers and a semiconductor component
Patent Information
- Application Number
- EP2023726900
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-06-20
- Filing Date
- 2023-05-10
- Publication Date
- 2025-02-12
AI Technical Summary
Existing circuit arrangements with semiconductor components are limited by maximum current density and switching speed due to bonding wires and parasitic inductances, and require complex distance maintenance between semiconductor components and circuit carriers.
A circuit arrangement with two circuit carriers and a semiconductor component, utilizing flip-chip technology for load connections and plated-through holes to eliminate bond wire limitations, allowing for reduced distances and a more compact design.
This solution simplifies production, reduces size, and enhances current density and switching speed by eliminating bond wire constraints and maintaining required voltage distances and clearances.
Smart Images
Figure 1.1
Abstract
Description
[0001] Description
[0002] Circuit arrangement with two circuit carriers and a semiconductor component
[0003] The invention relates to a circuit arrangement comprising two circuit carriers and at least one semiconductor component. The semiconductor component is, in particular, a power semiconductor.
[0004] In the field of power electronics, semiconductor components, such as switching elements, are usually available in the form of power modules, also known as power modules, or in the form of discrete packages. The semiconductor components are usually contacted using specific wire bonding technologies, and the power modules are attached to a circuit carrier using solder, spring, or press connections, for example. The use of bond wires limits the maximum permissible current density through the semiconductor components. In addition, parasitic inductances occur, which limit the achievable switching speed of the switching elements.
[0005] WO 2020 / 249479 A1 discloses an electronic circuit which, inter alia, has a first circuit carrier, a second circuit carrier and a power electronic semiconductor component. The semiconductor component has an upper side which bears against an underside of the first circuit carrier, and a underside which bears against an upper side of the second circuit carrier. The first circuit carrier has a via which electrically connects the upper side of the first semiconductor component to a conductor track of the first circuit carrier. The second circuit carrier has, for example, an electrically conductive layer forming its upper side and an electrically insulating layer arranged on a side of the electrically conductive layer facing away from the first circuit carrier.WO 2014 / 197917 A1 discloses a power module with a printed circuit board core containing at least one electronic power component embedded in an insulating layer. The core is arranged between two heat-dissipating plates, each heat-dissipating plate having a metallic outer layer and a metallic inner layer electrically separated from the latter by a thermally conductive, electrically insulating intermediate layer.
[0006] DE 10 2021 125 094 A1 discloses a semiconductor package with a carrier and a semiconductor chip. The carrier has an electrically insulating body and a contact structure on one side of the electrically insulating body. The semiconductor chip has a pad that is attached to the contact structure of the carrier, wherein the pad is at source or emitter potential. The pad is spaced inward from an edge of the semiconductor chip by a first distance. The semiconductor chip has an edge termination region between the edge and the pad. The contact structure of the carrier is spaced inward from the edge of the semiconductor chip by a second distance that is greater than the first distance.
[0007] US 2012 / 243192 A1 discloses a three-dimensional power electronics package having a metallized substrate arrangement, a first power electronics device, and a second power electronics device. The metallized substrate arrangement comprises an insulating dielectric substrate having a current feedthrough extending completely through the insulating dielectric substrate, a first conductive layer on a first surface of the insulating dielectric substrate, and a second conductive layer on a second surface of the insulating dielectric substrate. The first conductive layer is electrically coupled to the second conductive layer through the current feedthrough. The invention is based on the object of specifying an improved circuit arrangement having two circuit carriers and at least one semiconductor component.
[0008] The object is achieved according to the invention by a circuit arrangement having the features of claim 1.
[0009] Advantageous embodiments of the invention are the subject of the dependent claims.
[0010] A circuit arrangement according to the invention comprises
[0011] - a first circuit carrier with at least two layers,
[0012] - a second circuit carrier and
[0013] - a semiconductor component arranged between the first circuit carrier and the second circuit carrier, having a first load terminal and a second load terminal, wherein
[0014] - the first load terminal has a first load terminal surface facing the first circuit carrier, around which an electrically insulating edge termination structure is arranged,
[0015] - the second load connection has a second load connection surface facing the second circuit carrier, which is larger than the first load connection surface,
[0016] - the first circuit carrier has, on a bottom side facing the semiconductor component, a first load connection contact pad which is electrically connected to the first load connection surface,
[0017] - the first circuit carrier has at least one first through-connection which connects the first load connection contact pad to at least one first conductor track which runs in the interior of the first circuit carrier or on an upper side of the first circuit carrier facing away from the semiconductor component, and
[0018] - the second circuit carrier has an upper side facing the semiconductor component, which is formed by a first electrically conductive layer which is electrically connected to the second load connection area. The terms “upper side” and “lower side” are not to be understood as restrictive, but are based on the representations in the figures. Furthermore, the wording that the circuit arrangement has one semiconductor component does not exclude the circuit arrangement having a plurality of semiconductor components. The circuit arrangement therefore has at least one semiconductor component with the specified properties.
[0019] The semiconductor component has two load connections that are arranged on different sides of the semiconductor component. The load connections are not contacted via bond wires, but rather the first load connection is contacted by the first load connection contact pad of the first circuit carrier and the second load connection is contacted by the first electrically conductive layer of the second circuit carrier (so-called flip-chip technology). The first load connection contact pad is further connected by at least one first via to at least one first conductor track that runs in an inner layer or in an outer layer of the first circuit carrier facing away from the semiconductor component. This advantageously eliminates bond wire-related limitations on the maximum permissible current density of a current through the semiconductor component and on the switching speed of the semiconductor component.The semiconductor component can be, for example, a transistor, a thyristor or a diode.
[0020] A further essential feature of the circuit arrangement according to the invention is that the first load terminal faces the first circuit carrier and the second load terminal faces the second circuit carrier, wherein the first load terminal is the load terminal whose load terminal surface is surrounded by the edge termination structure. The edge termination structure serves to reduce the potential difference between the two load terminals. In the arrangement known from the prior art according to WO 2020 / 249479 A1, in contrast, the first load terminal faces the second circuit carrier and is electrically connected to its first electrically conductive layer.Since the potential of the second load connection is applied to the outer edges of the edge termination structure, the arrangement known from the prior art requires a sufficient distance between the first load connection and the second circuit carrier, since its large-area first electrically conductive layer is at the potential of the first load connection. The required distance depends on the insulation material used and the blocking voltage of the semiconductor component. In order to maintain this distance, sinter paste deposits, sinter preforms or solder preforms with a spacer function are used, for example, and / or the edge termination structure is electrically insulated from the first electrically conductive layer of the second circuit carrier by a passivation structure and / or a suitable potting material, which has to be potted in a complex potting process adapted to and matched to the potting material.This problem is solved by the arrangement according to the invention, on the one hand, in that the second load terminal is arranged on the second circuit carrier instead of the first load terminal, and on the other hand, in that the first load terminal is connected by at least one first via to at least one conductor track which runs inside or on the top side of the first circuit carrier, as a result of which the substrate (base material) of the first circuit carrier provides an additional insulation layer between each of these conductor tracks and the edge termination structure of the semiconductor component. Compared to the arrangement known from WO 2020 / 249479 A1, this simplifies the manufacture of the circuit arrangement and enables a more compact form of the circuit arrangement, since the distances between the semiconductor component and the circuit carriers can be reduced.In one embodiment of the invention, the first load connection contact pad is arranged completely within a region of the underside of the first circuit carrier which corresponds to a region of the semiconductor component surrounded by the edge termination structure. The region of the underside of the first circuit carrier which corresponds to the region of the semiconductor component surrounded by the edge termination structure refers to a region of the underside of the first circuit carrier onto which the region of the semiconductor component surrounded by the edge termination structure is mapped by a parallel displacement along a straight line parallel to a normal vector of the underside of the first circuit carrier.The region of the underside of the first circuit carrier corresponding to the region of the semiconductor component surrounded by the edge termination structure is thus directly opposite the region of the semiconductor component surrounded by the edge termination structure and has the same area and shape as the region of the semiconductor component surrounded by the edge termination structure.
[0021] The aforementioned embodiment of the invention prevents regions of the edge termination structure and the first load connection contact pad from being directly opposite one another, and thus advantageously spaces regions of the edge termination structure lying at the potential of the second load connection from the first load connection contact pad lying at the potential of the first load connection.
[0022] In a further embodiment of the invention, at least one first via runs parallel to a first straight line which forms a non-vanishing angle with a normal vector of the underside of the first circuit carrier.
[0023] In a further embodiment of the invention, the first load connection contact pad is connected by at least one first through-contact to at least one first conductor track running inside the first circuit carrier, and this conductor track is connected by at least one further through-contact, a so-called blind via, to at least one conductor track running on the top side of the first circuit carrier.
[0024] The two aforementioned embodiments of the invention enable equalization of the connections and conductor tracks on the top side of the first circuit carrier by means of diagonally extending first vias and / or blind vias. This advantageously allows required voltage clearances, air gaps, and creepage distances to be maintained on the top side of the first circuit carrier, and the circuit arrangement can be further compacted, which in particular allows material savings.
[0025] In a further embodiment of the invention, the semiconductor component has a control connection with a control connection area facing the first circuit carrier, which control connection area is arranged within the region of the semiconductor component surrounded by the edge termination structure. Furthermore, the first circuit carrier has a control connection contact pad on its underside, which is electrically connected to the control connection area. Furthermore, the first circuit carrier has at least one second via, which connects the control connection contact pad to at least one second conductor track, which runs inside the first circuit carrier or on the top side of the first circuit carrier.
[0026] In a further embodiment of the invention, the control terminal contact pad is also arranged completely within the region of the underside of the first circuit carrier which corresponds to the region of the semiconductor component surrounded by the edge termination structure.
[0027] The two aforementioned embodiments of the invention relate to a circuit arrangement with at least one semiconductor component that can be controlled via a control terminal (gate). Such semiconductor components include, for example, transistors and thyristors. These embodiments of the invention provide contacting of the control terminal that is analogous to the contacting of the first load terminal, with the aforementioned advantages.
[0028] In a further embodiment of the invention, the control terminal contact pad extends into a region of the underside of the first circuit carrier that corresponds to the first load connection area. Analogous to the above embodiments, the region of the underside of the first circuit carrier that corresponds to the first load connection area designates a region of the underside of the first circuit carrier onto which the first load connection area is mapped by a parallel displacement along a straight line parallel to a normal vector of the underside of the first circuit carrier.
[0029] The aforementioned embodiment of the invention takes into account that the control connection of a semiconductor component is often very small. In such a case, it is advisable to design the control connection contact pad to be sufficiently large so that it projects into a region of the underside of the first circuit carrier which corresponds to the first load connection area. This also ensures that in the event of a component offset there is always sufficient overlap or coverage between the control connection contact pad and the control connection area and the control connection can therefore be contacted reliably. With this type of design of the control connection contact pad, the first load connection contact pad is designed to be correspondingly smaller.
[0030] In a further embodiment of the invention, a section of the control terminal contact pad, which extends into the region of the underside of the first circuit carrier corresponding to the first load terminal surface, has at least one non-contactable region. In a further embodiment of the invention, a region of the underside of the first circuit carrier lying between the control terminal contact pad and the first load terminal contact pad has a non-contactable region.
[0031] The two aforementioned embodiments of the invention advantageously prevent, through the non-contactable regions, an undefined connection medium outflow between the control connection contact pad and the first load connection contact pad and the risk of a short circuit between the control connection contact pad and the first load connection contact pad or the first load connection surface. A non-contactable region is created, for example, by coating with an additional material such as solder resist, by locally influencing the wettability, for example by laser oxidation, or by removing existing material, for example by step etching.
[0032] In a further embodiment of the invention, every second via runs parallel to a first via. In particular, all first and second vias can run parallel to one another. This simplifies the manufacture and arrangement of the first and second vias and prevents these vias from crossing.
[0033] In a further embodiment of the invention, the second circuit carrier has an underside facing away from the semiconductor component, which underside is formed by a second electrically conductive layer, and an electrically insulating insulation layer arranged between the first electrically conductive layer and the second electrically conductive layer. The insulation layer advantageously enables electrical insulation of the underside of the second circuit carrier from its upper side. In particular, this enables insulation from a heat sink arranged on the underside. Such a heat sink is frequently used to dissipate heat from the circuit arrangement. The second electrically conductive layer can in particular make the second circuit carrier more robust against thermal deformation.
[0034] In a further embodiment of the invention, the first circuit carrier has on its underside a second load connection contact pad which is electrically connected to the first electrically conductive layer of the second circuit carrier.
[0035] In a further embodiment of the invention, the first circuit carrier has at least one third through-contact which connects the second load connection contact pad to at least one third conductor track which runs in the interior of the first circuit carrier or on the top side of the first circuit carrier.
[0036] The two aforementioned embodiments of the invention make it possible to supply the potential of the second load terminal to the first circuit carrier and to connect the second load terminal to at least one conductor track of the first circuit carrier.
[0037] In a further embodiment of the invention, at least one third via runs parallel to a second straight line which forms a non-zero angle with a normal vector of the underside of the first circuit carrier, so that a distance of each third via from each first via in a plane parallel to the underside of the first circuit carrier increases with the distance of this plane from the underside of the first circuit carrier. This embodiment of the invention also enables equalization of the connections and conductor tracks on the upper side of the first circuit carrier by means of obliquely running third vias in order to maintain the required voltage clearances, air and creepage distances on the upper side of the first circuit carrier and to further compact the circuit arrangement.The above-described properties, features, and advantages of this invention, as well as the manner in which they are achieved, will become clearer and more readily understood in connection with the following description of exemplary embodiments, which are explained in more detail in conjunction with the drawings.
[0038] FIG 1 shows a first schematic sectional view of a first embodiment of a circuit arrangement,
[0039] FIG 2 shows a second schematic sectional view of the circuit arrangement shown in Figure 1,
[0040] FIG 3 is a schematic sectional view of a second embodiment of a circuit arrangement,
[0041] FIG 4 is a schematic sectional view of a third embodiment of a circuit arrangement,
[0042] FIG 5 is a schematic sectional view of a fourth embodiment of a circuit arrangement,
[0043] FIG 6 is a schematic sectional view of a fifth embodiment of a circuit arrangement,
[0044] FIG 7 is a schematic sectional view of a sixth
[0045] From an exemplary circuit arrangement,
[0046] FIG 8 is a schematic sectional view of a seventh embodiment of a circuit arrangement,
[0047] FIG 9 is a schematic sectional view of an eighth embodiment of a circuit arrangement,
[0048] FIG. 10 shows a schematic sectional view of a ninth exemplary embodiment of a circuit arrangement. Corresponding parts are provided with the same reference numerals in the figures.
[0049] Figure 1 (FIG. 1) shows a first schematic sectional view of a first exemplary embodiment of a circuit arrangement 1. The circuit arrangement 1 comprises a first circuit carrier 3, a second circuit carrier 5, and a semiconductor component 7 arranged between the first circuit carrier 3 and the second circuit carrier 5.
[0050] In this exemplary embodiment, the first circuit carrier 3 is a multilayer printed circuit board. The second circuit carrier 5 has a first electrically conductive layer 8, a second electrically conductive layer 9 and an electrically insulating insulation layer 10 arranged between the two electrically conductive layers 8, 9. The first electrically conductive layer 8 forms an upper side of the second circuit carrier 5 facing the semiconductor component 7. The second electrically conductive layer 9 forms an underside of the second circuit carrier 5 facing away from the semiconductor component 7. The insulation layer 10 is, for example, a ceramic layer made, for example, from aluminum oxide, aluminum nitride or silicon nitride. For example, the second circuit carrier 5 is a DCB substrate (DCB: abbreviation for Direct Copper Bonded) or an AMB substrate (AMB: abbreviation for Active Metal Brazing).
[0051] In this exemplary embodiment, the semiconductor component 7 is a transistor having a control terminal 11, a first load terminal 12, and a second load terminal 13. For example, the transistor is a bipolar transistor or an insulated-gate bipolar transistor (IGBT for short), whose first load terminal 12 is an emitter terminal and whose second load terminal 13 is a collector terminal. Alternatively, the transistor is, for example, a field-effect transistor, in particular a metal-oxide-semiconductor field-effect transistor (MOSFET for short), whose first load terminal 12 is a source terminal and whose second load terminal 13 is a drain terminal. In other embodiments, the semiconductor component 7 may be, for example, a thyristor or a diode instead of a transistor.In the case that the semiconductor component 7 is a diode, however, the control terminal 11 and the components of the circuit arrangement 1 connected to it are omitted.
[0052] The control connection 11 has a control connection surface 14 facing the first circuit carrier 3. The first load connection 12 has a first load connection surface 15 facing the first circuit carrier. The second load connection 13 has a second load connection surface 16 facing the second circuit carrier 5, which is larger than the first load connection surface 15. An electrically insulating edge termination structure 17 is arranged around the control connection surface 14 and the first load connection surface 15, which reduces a potential difference between the two load connections 12, 13.
[0053] The first circuit carrier 3 has, on an underside facing the semiconductor component 7, a control connection contact pad 18, a first load connection contact pad 19 and a second load connection contact pad 20. The control connection contact pad 18 is electrically connected to the control connection area 14. The first load connection contact pad 19 is electrically connected to the first load connection area 15. The second load connection contact pad 20 and the second load connection area 16 are each electrically connected to the first electrically conductive layer 8 of the second circuit carrier 5. The electrical connections between these components are each produced by a connecting material 30, for example a solder or sintered material, which electrically connects two components.The connecting material may depend on the connected components, but for the sake of simplicity, all of these electrical connections are designated by the same reference numeral 30 in the figures.
[0054] The first circuit carrier 3 has a plurality of through-contacts 34, 35, 36, which each connect the first load connection contact pad 19, the control connection contact pad 18 or the second load connection contact pad 20 to at least one conductor track 37 to 40, which run in the interior, that is to say in an inner layer of the first circuit carrier 3 or on an upper side facing away from the semiconductor component 7, that is to say in an upper outer layer of the first circuit carrier 3. Figure 1 shows a plurality of first through-contacts 34, which connect the first load connection contact pad 19 to a conductor track 37, which runs in the interior of the first circuit carrier 3, and to a first conductor track 38, which runs on the upper side of the first circuit carrier 3.Furthermore, Figure 1 shows a second via 35 which connects the control connection contact pad 18 to a second conductor track 39 running on the top side of the first circuit carrier 3, and a plurality of third vias 36 which each connect the second load connection contact pad 20 to a third conductor track 40 running on the top side of the first circuit carrier 3.
[0055] The control terminal contact pad 18 and the first load terminal contact pad 19 are arranged completely within a region 41 of the underside of the first circuit carrier 3, which corresponds to a region of the semiconductor component 7 surrounded by the edge termination structure 17.
[0056] A remaining space between the underside of the first circuit carrier 3 and the second circuit carrier 5 is filled by a potting material 42, for example by a casting resin.
[0057] Figure 2 (FIG 2) shows a second schematic sectional view of the circuit arrangement 1 shown in Figure 1 in the region 41 of the underside of the first circuit carrier 3, which corresponds to the region of the semiconductor component 7 surrounded by the edge termination structure 17. Figure 2 shows that the control connection contact pad 18 is surrounded on three sides by the first load connection contact pad 19, the contact pad-side ends of the first vias 34 form a two-dimensional array on the first load connection contact pad 19, and the control connection contact pad 18 can be connected to more than just one second via 35. In other exemplary embodiments, the control connection contact pad 18 can also be surrounded on four sides by the load connection contact pad 19, that is to say framed by the load connection contact pad 19.Furthermore, Figure 2 shows that the first load connection contact pad 19 and the control connection contact pad 18 are arranged completely in the region 41 and that therefore the contact pad-side ends of the first vias 34 and the second vias 35 are also located completely in the region 41.
[0058] Figure 3 (FIG 3) shows a schematic sectional view of a second embodiment of a circuit arrangement 1. This embodiment differs from the embodiment shown in Figure 1 only in that a region of the underside of the first circuit carrier 3 lying between the control connection contact pad 18 and the first load connection contact pad 19 has a non-contactable region 43, which is formed, for example, by solder resist. Therefore, Figure 3 only shows a region of the circuit arrangement 1 which comprises this region of the underside of the first circuit carrier 3. This embodiment takes into account that the control connection contact pad 18 extends into a region of the underside of the first circuit carrier 3 which corresponds to the first load connection area 15.The extension of the control connection contact pad 18 into the region of the underside of the first circuit carrier 3, which corresponds to the first load connection surface 15, advantageously increases the size of the control connection contact pad 18 and thereby enables secure electrical contact between the control connection contact pad 18 and the control connection 11 and the second vias 35. The non-contactable region 43 prevents an undefined outflow of connecting medium between the control connection contact pad 18 and the first load connection contact pad 19 and the risk of a short circuit between the control connection contact pad 18 and the first load connection contact pad 19.Instead of applying solder resist, the wettability of the connecting means 30 in the region of the underside of the first circuit carrier 3 located between the control connection contact pad 18 and the first load connection contact pad 19 can be reduced by a local additional treatment, for example by laser oxidation or step etching (the same applies to the embodiments shown in Figures 3 and 4).
[0059] Figure 4 (FIG 4) shows a schematic sectional view of a third embodiment of a circuit arrangement 1 analogous to Figure 3. This embodiment differs from the embodiment shown in Figure 3 only in that the non-contactable region 43 also comprises a region of the control connection contact pad 18 facing the first load connection contact pad 19 and the first load connection surface 15 in order to also prevent the risk of a short circuit between the control connection contact pad 18 and the first load connection surface 15.
[0060] Figure 5 (FIG 5) shows a schematic sectional view of a fourth exemplary embodiment of a circuit arrangement 1 analogous to Figures 3 and 4. This exemplary embodiment differs from the exemplary embodiments shown in Figures 3 and 4 only in that the non-contactable region 43 is only a region of the control connection contact pad 18 facing the first load connection surface 15 in order to prevent the risk of a short circuit between the control connection contact pad 18 and the first load connection surface 15. Figure 6 (FIG 6) shows a schematic sectional view of a fifth exemplary embodiment of a circuit arrangement 1.This embodiment differs from the embodiment shown in Figure 1 only in that conductor tracks 37 running inside the first circuit carrier 3 and conductor tracks 38 running on the top side of the first circuit carrier 3 are connected by additional through-contacts 47 (blind vias), which advantageously reduce the current densities of currents between the conductor tracks 37 and 38.
[0061] Figure 7 (FIG. 7) shows a schematic sectional view of a sixth exemplary embodiment of a circuit arrangement 1. This exemplary embodiment differs from the exemplary embodiment shown in Figure 6 only in that the first through-contacts 34 only extend as far as a conductor track 37 running inside the first circuit carrier 3, and that the second through-contacts 35 only extend to a further conductor track 45 running inside the first circuit carrier 3, which is connected by a further through-contact 46 (a further blind via) to a second conductor track 39 running on the top side of the first circuit carrier 3.
[0062] Figure 8 (FIG. 8) shows a schematic sectional view of a seventh exemplary embodiment of a circuit arrangement 1. This exemplary embodiment differs from the exemplary embodiment shown in Figure 1 only in that the third vias 36 run parallel to a straight line that forms a non-zero angle with a normal vector of the underside of the first circuit carrier 3.
[0063] Figure 9 (FIG. 9) shows a schematic sectional view of an eighth exemplary embodiment of a circuit arrangement 1. This exemplary embodiment differs from the exemplary embodiment shown in Figure 1 only in that the first vias 34 and the second vias 35 run parallel to a straight line that forms a non-zero angle with a normal vector of the underside of the first circuit carrier 3.
[0064] Figure 10 (FIG 10) shows a schematic sectional view of a ninth exemplary embodiment of a circuit arrangement 1. This exemplary embodiment differs from the exemplary embodiment shown in Figure 1 only in that the first vias 34 and the second vias 35 run parallel to a first straight line which forms a non-vanishing first angle with a normal vector of the underside of the first circuit carrier 3, and the third vias 36 run parallel to a second straight line which forms a non-vanishing second angle with a normal vector of the underside of the first circuit carrier 3.
[0065] 8 to 10, the angles formed by vias 34, 35, 36 with a normal vector of the underside of the first circuit carrier 3 are selected such that a distance of every third via 36 from every first via 34 and every second via 35 in a plane parallel to the underside of the first circuit carrier 3 increases with the distance of this plane from the underside of the first circuit carrier 3. As a result, the required voltage clearances, air gaps and creepage distances on the upper side of the first circuit carrier 3 can advantageously be maintained (for example distances between the conductor tracks 38, 39 and the conductor tracks 40), and the circuit arrangement 1 can be compacted.
[0066] Although the invention has been illustrated and described in detail by means of preferred embodiments, the invention is not limited by the disclosed examples and other variations can be derived therefrom by those skilled in the art without departing from the scope of the invention.
Claims
Patent claims 1. Circuit arrangement (1) , comprising - a first circuit carrier of at least two layers (3) , - a second circuit carrier (5) and - a semiconductor device (7) arranged between the first circuit carrier (3) and the second circuit carrier (5) with a first load terminal (12) and a second load terminal (13) , wherein - the first load connection (12) has a first load connection surface (15) facing the first circuit carrier (3), around which an electrically insulating edge termination structure (17) is arranged, - the second load connection (13) has a second load connection area (16) facing the second circuit carrier (5) which is larger than the first load connection area (15), - the first circuit carrier (3) has a first load connection contact pad (19) on a bottom side facing the semiconductor device (7), which is electrically connected to the first load connection surface (15), - the first circuit carrier (3) has at least one first via (34) that connects the first load terminal contact pad (19) to at least one first conductor track (37, 38) that runs inside the first circuit carrier (3) or on a top side of the first circuit carrier (3) facing away from the semiconductor device (7), - the second circuit carrier (5) has a top surface facing the semiconductor device (7) which is formed by a first electrically conductive layer (8) which is electrically connected to the second load connection surface (16), - the second circuit carrier (5) has a bottom side facing away from the semiconductor device (7), which is formed by a second electrically conductive layer (9), and an electrically insulating insulating layer (10) arranged between the first electrically conductive layer (8) and the second electrically conductive layer (9), and - the first circuit carrier (3) has a second load connection contact pad (20) on its underside, which is electrically is connected to the first electrically conductive layer (8) of the second circuit carrier (5).
2. Circuit arrangement (1) according to claim 1, wherein the first load connection contact pad (19) is arranged completely within a region (41) of the underside of the first circuit carrier (3) which corresponds to a region of the semiconductor device (7) surrounded by the edge termination structure (17).
3. Circuit arrangement (1) according to claim 1 or 2, wherein at least one first via (34) runs parallel to a first straight line which forms a non-zero angle with a normal vector of the underside of the first circuit carrier (3).
4. Circuit arrangement (1) according to one of the preceding claims, wherein the first load connection contact pad (19) is connected by at least one first via (34) to at least one first conductor track (37) running inside the first circuit carrier (3) and this conductor track (37) is connected by at least one further via (47) to at least one conductor track (38) running on the top side of the first circuit carrier (3).
5. Circuit arrangement (1) according to one of the preceding claims, wherein the semiconductor device (7) has a control terminal (11) with a control terminal area (14) facing the first circuit carrier (3), which is arranged within the area of the semiconductor device (7) surrounded by the edge termination structure (17), and the first circuit carrier (3) has a control terminal contact pad (18) on its underside, which is electrically connected to the control terminal area (14), and the first circuit carrier (3) has at least one second via (35) which connects the control terminal contact pad (18) to at least one second conductor track (39, 45) which is located in the inside the first circuit carrier (3) or on the top side of the first circuit carrier (3).
6. Circuit arrangement (1) according to claim 5, wherein the control terminal contact pad (18) is arranged completely within a region (41) of the underside of the first circuit carrier (3) which corresponds to a region of the semiconductor device (7) surrounded by the edge termination structure (17).
7. Circuit arrangement (1) according to claim 5 or 6, wherein the control terminal contact pad (18) extends into an area of the underside of the first circuit carrier (3) which corresponds to the first load terminal surface (15).
8. Circuit arrangement (1) according to claim 7, wherein a section of the control terminal contact pad (18) extending into the area of the underside of the first circuit carrier (3) corresponding to the first load terminal surface (15) has at least one non-contactable area (43).
9. Circuit arrangement (1) according to one of claims 5 to 8, wherein an area of the underside of the first circuit carrier (3) located between the control terminal contact pad (18) and the first load terminal contact pad (19) has a non-contactable area (43).
10. Circuit arrangement (1) according to one of claims 5 to 9, wherein every second via (35) runs parallel to a first via (34).
11. Circuit arrangement (1) according to one of the preceding claims, wherein the first circuit carrier (3) has at least one third via (36) which connects the second load terminal contact pad (20) to at least one third conductor track (40) which is located inside the first circuit carrier gers (3) or on the top side of the first circuit carrier (3).
12. Circuit arrangement (1) according to claim 11, wherein at least one third via (36) runs parallel to a second straight line which forms a non-zero angle with a normal vector of the underside of the first circuit carrier (3), such that the distance of this third via (36) from each first via (34) in a plane parallel to the underside of the first circuit carrier (3) increases with the distance of this plane from the underside of the first circuit carrier (3).