Voltage regulator

Abstract

The present description relates to a device (REG2) comprising a first MOS transistor (P1) connected between first and second nodes (102, 350), a selectively activatable current source (314) connected between the second node (350) and a third node (108), a circuit (302) controlling the first transistor (P1) to regulate a voltage from the second node to a first setpoint value (V1), a second MOS transistor (P2) connected between the first node (102) and a fourth node (104), and having its gate connected to that of the first transistor (P1), a third MOS transistor (N1) connected between the third and fourth nodes (108, 104), a switch (IT) connected between the second and fourth nodes (350, 104), and another circuit (310) controlling the third transistor (N1) to regulate a voltage (VDD) from the fourth node (104) to a second setpoint value (V2).

Description

Technical field

[0001] The present description relates generally to electronic circuits, for example integrated electronic circuits. The present description relates more particularly to circuits configured to receive a first supply voltage and to provide a second supply voltage from the first supply voltage, these circuits being commonly called, for example, voltage regulators. Prior art

[0002] Many known electronic systems are powered by a first direct current (DC) voltage, for example received on a power supply pad of the system. To power all or part of the internal circuits they comprise with a second DC supply voltage of lower value than the first voltage, these known systems comprise a voltage regulator configured to generate the second DC voltage from the first DC voltage.

[0003] In phases of use of these known systems, for example during development phases and / or during test phases at the end of manufacturing, it may be desirable to know the current drawn by these systems on the voltage source providing the first voltage, so as, for example, to evaluate the consumption of the internal circuits of the system which are supplied by the second voltage.

[0004] In other phases of use of these known systems, for example during phases where the system is used by an end user and / or during phases where the system is deployed in its application environment, it may be desirable for the current drawn by these systems from the voltage source providing the first voltage to be constant, so as, for example, to mask the consumption of the internal circuits of the system powered by the second voltage. For example, this makes it possible to prevent attackers from accessing confidential information based on knowledge of the consumption of the circuits powered by the second voltage. Summary of the invention

[0005] There is a need to overcome some or all of the disadvantages of known voltage regulators.

[0006] For example, there is a need to overcome some or all of the disadvantages of known voltage regulators configured to receive a first DC supply voltage and to provide a second DC supply voltage from the first DC supply voltage, the second voltage having a lower value than the first.

[0007] For example, there is a need for a voltage regulator that can operate alternately in a first mode where the current drawn from the voltage source providing the first voltage varies with the current drawn by the powered circuits and in a second mode where the current drawn from that voltage source is constant.

[0008] For example, there is a need to overcome all or part of the disadvantages of known regulators which can operate alternately according to the first and second modes described above.

[0009] One embodiment overcomes all or part of the drawbacks of known voltage regulators.

[0010] One embodiment provides a device comprising: a first MOS transistor connected between a first node configured to receive a first supply voltage, and a second node; a selectively activatable current source connected between the second node and a third node configured to receive a reference potential; a first circuit configured to control the first transistor so as to regulate a voltage of the second node to a first setpoint value determined at least in part by a first setpoint voltage; a second MOS transistor connected between the first node and a fourth node, and having its gate connected to the gate of the first transistor; a third MOS transistor connected between the fourth node and the third node; a switch connected between the second and fourth nodes;and a second circuit configured to control the third transistor so as to regulate a voltage of the fourth node to a second setpoint value determined at least in part by a second setpoint voltage.;

[0011] According to one embodiment, the fourth node is configured to provide a second supply voltage having a value determined by the first setpoint value when the switch is on, and by the second setpoint value when the switch is off.

[0012] According to one embodiment, the first circuit comprises: a first resistive voltage divider bridge connected between the second and third nodes; and an error amplifier configured to receive the first setpoint voltage and a voltage from an intermediate node of the first bridge, and to provide to the gate of the first transistor a voltage determined by the difference between the two received voltages.

[0013] According to one embodiment, the second circuit comprises: a second resistive bridge connected between the fourth and third nodes; and an error amplifier configured to receive the second setpoint voltage and a voltage from an intermediate node of the second bridge, and to provide to the gate of the third transistor a voltage determined by the difference between the two received voltages.

[0014] According to one embodiment, a ratio of a dimension ratio of the first transistor to a dimension ratio of the second transistor is greater than 1, preferably greater than 100, for example of the order of 300.

[0015] According to one embodiment, the device further comprises a control circuit configured to: deactivating the second circuit and the current source, and controlling the switch in the on state in a first operating mode; and activating the second circuit and the current source, and controlling the switch in the off state in a second operating mode.

[0016] According to one embodiment, the first and second circuits are configured so that the first setpoint value in the first steady-state mode is equal to the second setpoint value in the second steady-state mode.

[0017] According to one embodiment, the control circuit is further configured, during a transition from the first operating mode to the second operating mode, to successively: controlling the second circuit so that the second setpoint value is higher than the first setpoint value; activating the current source; controlling the switching of the switch to the open state to switch from the first operating mode to the second operating mode; and controlling the second circuit so that the second setpoint value is equal to the first setpoint value.

[0018] According to one embodiment: the first and second transistors are of the same channel type; and the third transistor is of the opposite channel type to that of the channel of the first and second transistors.

[0019] According to one embodiment, the first and second supply voltages are positive with respect to the reference potential, and the first transistor is P-channel.

[0020] According to one embodiment, the current source comprises a resistive element in series with a switch between the second and third nodes.

[0021] Another embodiment provides an integrated circuit chip comprising: a device as described above; a pad configured to receive the first supply voltage, the first supply voltage corresponding to a supply voltage of the chip; and an integrated circuit connected to the fourth node, the integrated circuit being configured to be powered by the voltage available on the fourth node of said device. Brief description of the drawings

[0022] These and other features and advantages will be set forth in detail in the following description of particular embodiments given without limitation in relation to the attached figures, among which: there figure 1represents, schematically and in the form of blocks, an example of an integrated circuit chip comprising a voltage regulator; the figure 2 represents an example of a voltage regulator; and the figure 3 represents an exemplary embodiment of a voltage regulator. Description of the embodiments

[0023] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0024] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various known electronic circuits that can be used in conjunction with a voltage regulator providing them with a supply voltage have not been detailed, the voltage regulator embodiments described below being compatible with these known circuits.

[0025] Unless otherwise specified, when referring to two elements connected together, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") together, this means that these two elements can be connected or be connected by means of one or more other elements.

[0026] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0027] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0028] There figure 1 represents, schematically and in the form of blocks, an example of an integrated circuit chip 1 comprising a voltage regulator REG.

[0029] The chip 1 includes input / output pads each configured to receive a signal from outside the chip 1 and / or to provide a signal to the outside of the chip 1. In figure 1 , a pad 100 is configured to receive a DC supply voltage VCC. The voltage VCC is supplied to the pad 100 by a voltage source external to the chip 1, and not shown in figure 1 .

[0030] The chip 1 comprises at least one integrated circuit IC configured to be powered by a DC supply voltage VDD, the value of the voltage VDD being lower than that of the voltage VCC.

[0031] For this purpose, chip 1 comprises the voltage regulator REG. The regulator REG is configured to receive the voltage VCC and to supply the voltage VDD from the voltage VCC. The regulator REG therefore comprises a node 102, corresponding to an input of the circuit REG, configured to receive the voltage VCC, and a node 104, corresponding to an output of the circuit REG, configured to supply the voltage VDD. For example, the input 102 of the circuit REG is connected to the pad 100 of chip 1. For example, the output 104 of the circuit REG is connected to an input 106 of the circuit IC, the input 106 being configured to receive the supply voltage VDD of the circuit IC.

[0032] For example, chip 1 also includes a pad 107 configured to receive a reference potential GND, for example ground.

[0033] The voltages VCC and VDD are, for example, referenced relative to the potential GND. For example, the circuit REG comprises a node 108, corresponding to an input of the circuit REG, configured to receive the potential GND, the node 108 being, for example, connected to the pad 107. For example, the circuit IC comprises a node 110, corresponding to an input of the circuit IC, configured to receive the potential GND, the node 110 being, for example, connected to the pad 107.

[0034] In this example, the voltages VCC and VDD are positive.

[0035] As indicated previously, it is desirable that, in a first operating mode REG, the current drawn by the circuit REG on the pad 100 to provide the voltage VDD varies with the consumption of the circuit IC, that is to say with the current drawn on the output 104 of the circuit REG by the circuit IC powered by the voltage VDD. It is also desirable that, in a second operating mode of the circuit REG, the current drawn by the circuit REG on the pad 100 to provide the voltage VDD is constant and therefore independent of the consumption of the circuit IC powered by the voltage VDD. In other words, it is desirable that the circuit REG can operate according to the first mode during first operating phases and according to the second operating mode during second operating phases. In other words, it is desirable that the circuit REG can operate alternately according to the first and second operating modes.

[0036] In the example of the figure 1 , only the two input / output pads 100 and 107 are shown although, in practice, chip 1 may include many other input / output pads.

[0037] Furthermore, in the example of the figure 1 , only one IC circuit is powered by the voltage VDD although, in other examples not illustrated, several integrated circuits of the chip 1 are powered by the same voltage VDD, these circuits then all being coupled, for example connected, to the node 104 of the circuit REG.

[0038] There figure 2 represents an example of a voltage regulator REG1 that can be used as a REG regulator in chip 1.

[0039] Thus, the circuit REG1 comprises the node 102 configured to receive the voltage VCC, the node 104 configured to supply the voltage VDD and the node 108 configured to receive the reference potential GND. For example, the nodes 102, 104 and 108 correspond respectively to an input, an output and an input of the circuit REG1.

[0040] The circuit REG1 further comprises a first voltage regulator 200, for example called a serial regulator. The regulator 200 is configured, when activated, for example by a control circuit not shown and forming part of the circuit REG1, to provide the voltage VDD from the voltage VCC. Thus, the regulator 200 is connected to the nodes 102 and 108 to receive the voltage VCC, and to the node 104 to provide the voltage VDD.

[0041] The regulator 200 more particularly comprises a MOS transistor P1 and a control circuit 202 configured to control the transistor P1. The transistor P1 is connected between the nodes 102 and 104. For example, the transistor P1 has its source connected to the node 102 and its drain connected to the node 104. In this example where the voltages VCC and VDD are positive, the transistor P1 is P-channel, or, in other words, the transistor P1 is a PMOS transistor.

[0042] The control circuit 202 of the transistor P1 is configured, when the regulator 200 is active, to control the transistor P1, that is to say to provide a control voltage on the gate of the transistor P1, so that the voltage VDD is at a value equal to a set value.

[0043] The set value of the voltage VDD, for the regulator 200, is at least partly determined by a set voltage V1. The voltage V1 is a DC voltage.

[0044] In this example, circuit 202 includes a resistive bridge 204 connected between nodes 104 and 108. Resistive bridge 204 is configured to provide a feedback voltage V1fb having a value determined by the value of voltage VDD. In the example of the figure 2 , the resistive bridge 204 comprises two resistive elements R1 and R2 in series between the nodes 104 and 108, the element R1 is connected to the node 104 and the voltage V1fb is available on the connection node of the element R1 to the element R2. In other examples not shown, the bridge 204 may comprise more than two resistive elements. When the circuit 202 comprises a resistive voltage divider bridge 204 as in figure 2, the resistance value of the resistive elements of the bridge 204 and the intermediate node of the bridge 204, i.e. the connection node between two resistive elements of the bridge 204, where the voltage V1fb is taken, determines, with the voltage V1, the set value of the voltage VDD for the regulator 200.

[0045] In another example not shown, the voltage VDD can be directly used as voltage V1fb and the circuit 202 is then without bridge 204. In this case, the set value of the voltage VDD for the regulator 200 is solely determined by the voltage V1.

[0046] Furthermore, still in the example of the figure 2, the circuit 202 comprises an error amplifier 206 configured to provide a voltage Vg1 whose value is determined by the difference between the voltages V1 and V1fb, or, more generally, to provide a voltage Vg1 whose value is determined by the difference between the voltage VDD and its set value. The voltage Vg1 is then the control voltage applied by the circuit 202 to the gate of the transistor P1. For example, the circuit 206 is implemented by an operational amplifier having an inverting input (-) receiving the voltage V1, a non-inverting input (+) receiving the voltage V1fb, and an output providing the voltage Vg1.

[0047] When regulator 200 is inactive, i.e., commanded to be inactive or deactivated, circuit 202 is configured so that transistor P1 is blocked.

[0048] The circuit REG1 further comprises a second voltage regulator 208, for example called a shunt regulator. The regulator 208 is configured, when activated, for example by the control circuit not shown, to provide the voltage VDD from the voltage VCC. Thus, the regulator 208 is connected to the nodes 102 and 108 to receive the voltage VCC, and to the node 104 to provide the voltage VDD.

[0049] The regulator 208 more particularly comprises a MOS transistor N1, a control circuit 210 configured to control the transistor N1, and a circuit 212 for supplying a constant current to the node 104 from the voltage VCC.

[0050] Circuit 212 includes a transistor P2 connected between nodes 102 and 104. For example, transistor P2 has its source connected to node 102 and its drain connected to node 104. In this example where voltages VCC and VDD are positive, transistor P2 is P-channel, or, put another way, transistor P2 is a PMOS transistor.

[0051] Circuit 212 is configured, when regulator 208 is active, for example when activated by the control circuit not shown, to bias the gate of transistor P2 so that current I1 in transistor P2, which corresponds to the current drawn on node 102, is constant. For example, circuit 212 is configured so that current I1 is equal to K times a reference current Iref, with K a positive factor. Thus, in figure 2, transistor P2 corresponds to the second transistor of a current mirror, transistor P2 providing the output current of the mirror, and the other transistor P3 of the mirror receiving the current Iref provided by a current source 214 of the circuit 212. The factor K is then defined by the ratio between the dimension ratio of transistor P2 and the dimension ratio of transistor P3. Transistors P2 and P3 of course have channels of the same type, namely P-type channels in this example.

[0052] More specifically, in circuit 212 of the figure 2, transistor P3 has its source connected to node 102, its gate connected to the gate of transistor P2, and its drain connected to its gate and to one terminal of current source 214, the other terminal of current source 214 being connected to node 108. In other words, transistors P2 and P3 are mounted in current mirror, transistor P3 is connected in series with current source 214 between nodes 102 and 108 and transistor P3 has its gate and drain connected.

[0053] Transistor N1 is connected between node 104 and node 108. For example, transistor N1 has its source connected to node 108 and its drain connected to node 104. Transistor N1 has its channel of the opposite type to that of the channel of transistor P2. Thus, in this example where the voltages VCC and VDD are positive, transistor N1 is N-channel, or, in other words, is an NMOS transistor.

[0054] The control circuit 210 of the transistor N1 is configured, when the regulator 208 is active, to control the transistor N1, that is to say to provide a control voltage on the gate of the transistor N1, so that the voltage VDD is at a value equal to a set value.

[0055] The set value of the voltage VDD, for the regulator 208, is at least partly determined by a set voltage V2. The voltage V2 is a DC voltage.

[0056] In this example, circuit 210 includes a resistive bridge 216 connected between nodes 104 and 108. Resistive bridge 216 is configured to provide a feedback voltage V2fb having a value determined by the value of voltage VDD. In the example of the figure 2, the resistive bridge 216 comprises two resistive elements R3 and R4 in series between the nodes 104 and 108, the element R3 is connected to the node 104 and the voltage V2fb is available on the connection node of the element R3 to the element R4. In other examples not shown, the bridge 216 may comprise more than two resistive elements. When the circuit 210 comprises a resistive voltage divider bridge 216 as in figure 2 , the resistance value of the resistive elements of the bridge 216 and the intermediate node of the bridge 216, i.e. the connection node between two resistive elements of the bridge 216, where the voltage V2fb is taken, determines, with the voltage V2, the set value of the voltage VDD for the regulator 208.

[0057] In another example not shown, the voltage VDD can be directly used as voltage V2fb and the circuit 210 is then without bridge 216. In this case, the set value of the voltage VDD for the regulator 208 is solely determined by the voltage V2.

[0058] Furthermore, still in the example of the figure 2, the circuit 210 comprises an error amplifier 218 configured to provide a voltage Vg2 whose value is determined by the difference between the voltages V2 and V2fb, or, more generally, to provide a voltage Vg2 whose value is determined by the difference between the voltage VDD and its set value. The voltage Vg2 is then the control voltage applied by the circuit 210 to the gate of the transistor N1. For example, the circuit 218 is implemented by an operational amplifier having an inverting input (-) receiving the voltage V2, a non-inverting input (+) receiving the voltage V2fb, and an output providing the voltage Vg2.

[0059] When regulator 208 is inactive, i.e., commanded to be inactive or deactivated, circuit 212 is configured so that transistor N1 is blocked, and, in addition, current source 214 is deactivated, or, in other words, switched off.

[0060] The control circuit not shown for regulators 200 and 208, which is part of regulator REG1, is configured to: activating the regulator 200 and deactivating the regulator 208 when the circuit REG1 is in a first operating mode where the current drawn on the node 102 varies with the variations in the consumption of a load connected to the node 104; and activating the regulator 208 and deactivating the regulator 200 when the circuit REG1 is in a second operating mode where the current drawn on the node 102 must be constant regardless of the variations in the consumption of a load connected to the node 104.

[0061] The REG1 circuit therefore makes it possible to supply the voltage VDD from the voltage VCC, so that the current drawn on the node 102 varies with the consumption of the loads supplied by the voltage VDD in a first operating mode, and that the current drawn on the node 102 is constant and independent of the consumption of the loads supplied by the voltage VDD in a second operating mode.

[0062] However, for this the regulator includes two transistors P1 and P2 which are relatively large and bulky compared to transistor P3. Indeed, these transistors P1 and P2 must allow the maximum current that the voltage source VCC can deliver to node 102, and therefore to node 104, to pass between their terminals. For example, for a given application, this maximum current can have a maximum value of the order of 20 mA.

[0063] It would therefore be desirable to have a REG1 voltage regulator allowing the same operation as the REG2 regulator but with reduced size.

[0064] There figure 3 represents an exemplary embodiment of such a voltage regulator REG2.

[0065] The REG2 regulator includes elements in common with the REG1 regulator of the figure 2 . Thus, unless otherwise indicated, for the same element forming part of each of the REG1 and REG2 regulators, everything that has been indicated for this element when it is part of the REG1 regulator applies to this element when it is part of the REG2 regulator. Furthermore, only the differences between the REG1 and REG2 regulators are highlighted here.

[0066] The RGE2 regulator therefore includes nodes 102, 108, and 104.

[0067] The regulator REG2 comprises a series voltage regulator 300 identical to the regulator 200 described previously. Thus, the regulator 300 comprises the MOS transistor P1 and a circuit 302 for controlling the transistor P1. The circuit 302 is for example identical to the circuit 202 described previously. For example, the circuit 302 comprises the resistive voltage divider bridge 204 and the circuit 206.

[0068] However, whereas in regulator 200 transistor P1 is connected between nodes 102 and 104, in this embodiment transistor P1 of regulator 300 is connected between node 102 and a node 350.

[0069] Furthermore, when circuit 302 includes bridge 204, the latter is connected between nodes 350 and 108 rather than between nodes 104 and 108 as is the case in circuit REG1.

[0070] The REG2 regulator further comprises a derived voltage regulator 308 similar to the regulator 208 in that it comprises: transistor P2, connected between nodes 102 and 104; transistor N1, connected between nodes 104 and 108; a circuit 310 for controlling transistor N1, for example identical to control circuit 210, supplying voltage Vg2 to the gate of transistor N1; and a current source 314.

[0071] However, regulator 308 differs from regulator 208 in that: the current source 314 is connected between the nodes 350 and 108; the regulator 308 is devoid of transistor P3; and the current source 314 is configured, when activated, for example by a control circuit CTRL forming part of the circuit REG2 and being configured to control the regulators 300 and 308, to provide a current Iref'.

[0072] Indeed, it is proposed here, when the regulator 308 is active, to use the current source and to reuse the regulator 300 to bias the gate of the transistor P2, so that the constant current I1 flows between the terminals of the transistor P2.

[0073] For this purpose, the regulator REG2 further comprises an IT switch coupling the node 350 to the node 104. In other words, the IT switch has a conduction terminal connected to the node 350 and another conduction terminal connected to the node 104. The IT switch is, for example, controlled by the CTRL circuit. For example, the IT switch is controlled to the on state when the regulator 308 is inactive, and to the off state when the regulator 308 is active.

[0074] Furthermore, the current source 314 is selectively activatable. In other words, the current source is controlled alternately in a state where it delivers the current Iref', the current source 314 then being turned on or activated, and in a state where it does not deliver the current Iref', the current source 314 then being said to be deactivated or turned off. For example, the current source 314 is controlled by the CTRL circuit. For example, the current source 314 is controlled to the active state when the regulator 308 is active, and to the inactive state when the regulator 308 is inactive.

[0075] In regulator REG2, when regulator 300 is active, regulator 308 is inactive, i.e. circuit 310 is deactivated and then controls transistor N1 to the blocked state and, in addition, current source 314 is controlled to the deactivated state. In this first operating mode where regulator 300 is active and regulator 308 is inactive, switch IT is controlled to the passing state.

[0076] For example, in this first mode of operation, to limit current leaks in the bridge 216, it is provided that the resistive element R4 of the bridge 216 has a controllable resistance value, and the element R4 is then controlled to have its maximum resistance value, preferably so that the element R4 is equivalent to an open circuit.

[0077] Alternatively, when regulator 308 is inactive, it is possible to provide a switch controlled to the open state when regulator 308 is inactive, and to the closed state when regulator 308 is active. This switch can be arranged between node 104 and transistor N1. However, when regulator 308 is active, this can lead to significant voltage drops across this switch, which is not desirable. This switch can also be arranged in series with bridge 216 between nodes 104 and 108. However, again, this can lead to significant voltage drops across this switch, which is not desirable.

[0078] Furthermore, in regulator REG2, when regulator 308 is active, regulator 300 is inactive. In this second mode of operation where regulator 308 is active, current source 314 is controlled to the active state, and switch IT is controlled to the open state. However, unlike circuit REG1 where circuit 202 controls transistor P1 to the open state when regulator 200 is inactive, in circuit REG2, control circuit 302 continues to operate and control transistor P1 so that the voltage at node 350 is regulated to the set value of regulator 300.

[0079] In the first operating mode, the transistors P1 and P2 are connected in parallel between the nodes 102 and 104, 350. The two transistors P1 and P2 therefore together deliver a current to the node 104 and the circuit 302 controls the transistor P1, therefore the transistor P2, so that the voltage VDD is regulated to the set value of the regulator 300, the latter being at least partly determined by the value of the voltage V1.

[0080] In the second mode of operation, when the set value of the voltage VDD for the regulator 308 is equal to the set value of the voltage VDD for the regulator 300, which is the case in steady state, for example by providing that the voltages V1 and V2 are equal, and that the ratio R1 / R2 is equal to the ratio R3 / R4, then the voltage on the node 350 is regulated to the same value as the voltage VDD on the node 104. Since the transistors P1 and P2 have the same gate voltage Vg1 and have the same source voltage VCC, the transistor P2 delivers the current I1 at a value determined by the current flowing in the transistor P1 and by the ratio between the dimension ratio of the transistor P2 and the dimension ratio of the transistor P1.Now, the current in transistor P1 when regulator 300 is inactive, that is to say that it does not directly regulate voltage VDD on node 104, the current in transistor P1 is equal to current Iref' if the current in bridge 204 is neglected, or to the sum of current Iref' and current in bridge 204 if the current in bridge 204 is not neglected, this current then being substantially equal to VDD / (R1+R2) in the example of the . figure 3 . Thus, the current I1 in transistor P2 is indeed equal to K times the current in transistor P1, with K determined by the size ratio between transistors P1 and P2.

[0081] For example, the ratio between the aspect ratio of transistor P1 and the aspect ratio of transistor P2 is positive and for example greater than 100, preferably greater than or equal to 300, for example equal to approximately 300. In this way, the current I1 in transistor P2 when regulator 308 is active is greater than the current in transistor P1, for example greater than 100 times the current in transistor P1, preferably greater than or equal to 300 times the current in transistor P1, for example equal to approximately 300 times the current in transistor P1.

[0082] Thus, in the REG2 circuit, the transistor P2 has dimensions similar, or even identical, to those of the transistor P2 for the same values ​​of current I1, and the transistor P1 is then smaller than the transistor P1 of the REG1 circuit, and smaller than the transistor P2 of the REG2 circuit. The REG2 circuit therefore includes one less large transistor than the REG1 circuit, and is therefore less bulky.

[0083] According to one embodiment, because in the second operating mode the voltage on the node 350 is equal to the regulated voltage VDD on the node 104, the current source 314 can be implemented by a resistor R, the current Iref' then being equal to VDD / R. By way of example, this resistor is in series with a switch controlled to the on state, respectively blocked, when the source 314 is controlled to the on state respectively blocked. By way of alternative example, the resistor R is a resistor with a controllable value and is controlled to its maximum value corresponding, preferably, to an open circuit, when the source 314 is controlled to the inactive state.

[0084] According to one embodiment, to avoid cross conduction between the two regulators 300 and 308 during a transition from the first operating mode to the second operating mode, the following method is implemented, for example by the CTRL circuit.

[0085] At an initial stage, regulator 300 is active and regulator 308 is inactive. Switch IT is therefore closed, current source 314 is inactive or off, and circuit 310 controls transistor N1 to the closed state.

[0086] In a next step, the setpoint value of the voltage VDD for the regulator 310 is modified so that, when the regulator 308 is switched to the active state, it will attempt to regulate the voltage at the node 104 to a higher value than the value to which the regulator 300 regulates the voltage VDD at the node 104. In other words, the setpoint value of the voltage VDD for the regulator 308 is set to a higher value than the setpoint value of the voltage VDD for the regulator 300. As a result, the transistor N1 is then controlled to the open state by the circuit 310.

[0087] For example, the set value for voltage VDD for regulator 308 is changed by correspondingly changing the value of voltage V2.

[0088] As an alternative example, in an embodiment where the two bridges 204 and 216 are identical and where the voltage V1fb is taken from an intermediate node of the bridge 204 corresponding to the intermediate node of the bridge 216 from which the voltage V2fb is taken, in order to avoid having to generate two different setpoint voltages V1 and V2, the setpoint value of the voltage VDD for the regulator 308 is modified by modifying the resistance value of one of the resistive elements of the bridge 216. For example, when the voltages V1 and V2 are equal and the elements R1 and R3 have the same resistance value, if the elements R2 and R4 have the same resistance value, the setpoint values ​​of the voltage VDD are the same for the two regulators 300 and 308, and, if the resistive element R4 has a smaller resistance value than that of the resistive element R2, then the setpoint value of the voltage VDD for the regulator 308 is modified by modifying the resistance value of one of the resistive elements of the bridge 216. 308 will be higher than that for the 300 regulator.

[0089] In a next step, the current source 314 is switched to the active state and begins to deliver the current Iref'.

[0090] In a next step, regulator 308 is switched to the active state. Since its setpoint voltage VDD is higher than that for regulator 300, as previously indicated, transistor N1 remains controlled in the off state.

[0091] The regulator 300 is then switched to the off state by opening the switch IT. As a result, the voltage VDD at node 104 increases until it reaches the set value of the voltage VDD for the regulator 308.

[0092] Before the VDD voltage reaches this set value or when the VDD voltage reaches this set value, the VDD voltage set value for the regulator 308 is again changed to be equal to the VDD voltage set value for the regulator 300.

[0093] It will be noted that the embodiment of the method for transitioning from the first operating mode to the second operating mode described for the circuit REG2 can be adapted and implemented in the example circuit REG1 described in relation to the figure 2 , for example in the following way.

[0094] At an initial stage, regulator 200 is active and regulator 208 is inactive.

[0095] In a next step, the set value of the voltage VDD for the regulator 208 is set to a higher value than the set value of the voltage VDD for the regulator 200.

[0096] In a next step, regulator 208 is switched to the active state. Because the set value of voltage VDD for regulator 208 is higher than the set value of voltage VDD for regulator 200, transistor N1 is held open by circuit 210.

[0097] In a next step, the regulator 200 is switched to the inactive state. As a result, the voltage VDD on the node 104 increases until it reaches the set value of the voltage VDD for the regulator 208.

[0098] Before the VDD voltage reaches this set value or when the VDD voltage reaches this set value, the VDD voltage set value for the regulator 208 is again changed to be equal to the VDD voltage set value for the regulator 200.

[0099] Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these various embodiments and variants could be combined, and other variants will be apparent to those skilled in the art. In particular, although examples have been described in which the voltages VCC and VDD are positive and the transistors P1 and P2 are then P-channel while the transistor N1 is N-channel, in other examples not illustrated, the voltages VDD and VCC are negative, the voltage VDD being lower, in absolute value, than the voltage VCC. In this case, the transistors P1 and P2 are N-channel and the transistor N1 is P-channel. Those skilled in the art will be able to adapt, if necessary, the implementation of the circuits 302 and 310, for example by inverting the voltages entering the inverting and non-inverting inputs of the circuits 206 and 218 if necessary.

[0100] Furthermore, although this has not been detailed, according to one embodiment, the regulator REG2 is implemented in chip 1, instead of the regulator REG.

[0101] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

1. Device (REG2) comprising: a first MOS transistor (P1) connected between a first node (102) configured to receive a first supply voltage (VCC), and a second node (350); a selectively activatable current source (314) connected between the second node (350) and a third node (108) configured to receive a reference potential (GND); a first circuit (302) configured to control the first transistor (P1) so as to regulate a voltage of the second node to a first setpoint value determined at least in part by a first setpoint voltage (V1); a second MOS transistor (P2) connected between the first node (102) and a fourth node (104), and having its gate connected to the gate of the first transistor (P1); a third MOS transistor (N1) connected between the fourth node (104) and the third node (108); a switch (IT) connected between the second and fourth nodes (350, 104);and a second circuit (310) configured to control the third transistor (N1) so as to regulate a voltage (VDD) of the fourth node (104) to a second setpoint value determined at least in part by a second setpoint voltage (V2).; 2. Device according to claim 1, in which the fourth node (350) is configured to provide a second supply voltage (VDD) having a value determined by the first setpoint value when the switch (IT) is on, and by the second setpoint value when the switch is off.

3. Device according to claim 1 or 2, wherein the first circuit (302) comprises: a first resistive voltage divider bridge (204) connected between the second and third nodes (350, 108); and an error amplifier (206) configured to receive the first setpoint voltage (V1) and a voltage (V1fb) from an intermediate node of the first bridge (204), and to provide to the gate of the first transistor (P1) a voltage (Vg1) determined by the difference between the two received voltages (V1, V1fb).

4. Device according to any one of claims 1 to 3, wherein the second circuit (310) comprises: a second resistive bridge (216) connected between the fourth and third nodes (104, 108); and an error amplifier (218) configured to receive the second setpoint voltage (V2) and a voltage (V2fb) from an intermediate node of the second bridge (216), and to provide the gate of the third transistor (N1) with a voltage (Vg2) determined by the difference between the two received voltages (V2, V2fb).

5. Device according to any one of claims 1 to 4, in which a ratio of a dimension ratio of the first transistor (P1) to a dimension ratio of the second transistor (P2) is greater than 1, preferably greater than 100, for example of the order of 300.

6. Device according to any one of claims 1 to 5, wherein the device further comprises a control circuit (CTRL) configured to: deactivate the second circuit (310) and the current source (314), and control the switch (IT) in the on state in a first operating mode; and activate the second circuit (310) and the current source (314), and control the switch (IT) in the off state in a second operating mode.

7. Device according to claim 6, wherein the first and second circuits (302, 310) are configured so that the first setpoint value in the first steady-state mode is equal to the second setpoint value in the second steady-state mode.

8. Device according to claim 6 or 7, wherein the control circuit (CTRL) is further configured, during a transition from the first operating mode to the second operating mode, to successively: - control the second circuit (310) so that the second setpoint value is higher than the first setpoint value; - activate the current source (314); - control the switching of the switch to the open state to switch from the first operating mode to the second operating mode; and - control the second circuit (310) so that the second setpoint value is equal to the first setpoint value.

9. Device according to any one of claims 1 to 8, in which: - the first and second transistors (P1, P2) have a channel of the same type; and - the third transistor (N1) has a channel of the opposite type to that of the channel of the first and second transistors.

10. Device according to claim 9, in which the first and second supply voltages (VCC, VDD) are positive with respect to the reference potential (GND), and the first transistor (P1) is P-channel.

11. A device according to any one of claims 1 to 10, wherein the current source (314) comprises a resistive element in series with a switch between the second and third nodes (350, 108).

12. Integrated circuit chip (1) comprising: a device (REG2) according to any one of claims 1 to 11; a pad (100) configured to receive the first supply voltage (VCC), the first supply voltage corresponding to a supply voltage of the chip (1); and an integrated circuit (IC) connected to the fourth node (104), the integrated circuit (IC) being configured to be powered by the voltage (VDD) available on the fourth node of said device (REG2).

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