Process for forming a layer based on a dielectric material on a layer based on an etched iii-v material

Abstract

The invention relates to a process for forming a layer based on a dielectric material on a layer based on an etched III-V material, the process comprising at least the following steps: - providing at least one layer based on an III-V and preferably III-N material, this layer being referred to as the III-V layer (100) and having a front side (101), - etching at least one portion of the III-V layer (100) from the front side (101) so as to expose a surface of the III-V layer, this surface being referred to as the etched surface (103), - exposing at least the etched surface (103) to an O2 or N2 plasma treatment, this step being carried out at a temperature Ttreatment with Ttreatment<100°C, - depositing a layer based on a dielectric material, this layer being referred to as the dielectric layer (200), at least on the etched surface.

Description

[0001] "Method for forming a layer based on a dielectric material on a layer based on an etched III-V material"

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the formation of a layer based on a dielectric material on a layer based on an etched III-V material, such as etched GaN. It is thus part of the manufacture of devices comprising an interface between a III-N material and a dielectric material. It finds, for example, a particularly advantageous application in the field of power electronics such as transistors integrating one or more layers of III-N materials.

[0004] STATE OF THE ART

[0005] The hunt for energy waste and increasing needs are pushing microelectronic device manufacturers to improve the efficiency and performance of their electrical energy conversion systems. Currently, conversion circuits are made from silicon and much research has been conducted to evolve architectures in order to improve efficiency and conductivity. However, these known devices are reaching the theoretical limits of silicon and new solutions are being considered. These solutions are based on the use of III-V materials such as GaN. This is the case, high electron mobility transistors, known as "High Electron Mobility Transistor" (HEMT).

[0006] The fabrication of this type of device requires numerous etching steps in III-V materials followed by the deposition of dielectric layers on the etched areas. However, the etching steps can significantly degrade the chemical and electrical properties of the etched materials. As a result, the interface between the III-V material and the dielectric often has degraded electronic properties. For example, plasma etching induces structural defects that alter the quality of the interfaces between the etched layer and the dielectric layer. The electrical properties of these interfaces and, consequently, of the electronic components, are degraded.

[0007] It is known from the state of the art to use etching processes that are intrinsically less damaging to the quality of the etched layer. Cyclic etching techniques, in particular those known as "Atomic Layer Etching" or ALE, make it possible to obtain etched layers with very little damage and good electrical properties. However, current ALE techniques are very time-consuming and have a significant impact on productivity. In addition, they are sometimes difficult to implement because it is necessary to be within the energy range, often narrow, allowing both selective and complete removal of the layer to be etched.

[0008] There is therefore a need to provide a solution to improve the productivity of the formation of a dielectric layer on a layer of etched III-V material without impacting the quality of the interface produced.

[0009] SUMMARY OF THE INVENTION

[0010] To achieve this objective, according to one embodiment, a method is provided for forming a layer based on a dielectric material on a layer based on an etched III-V material. The method comprises at least the following steps:

[0011] - Provide at least one layer based on a III-V material, preferably III-N, called III-V layer, having a front face,

[0012] - Etch at least part of the III-V layer from the front face so as to expose a surface of the III-V layer called the etched surface,

[0013] - Expose at least the etched surface to a plasma treatment of O2, N2, or a mixture of O2 and N2, this step being carried out at a temperature Treatment with Ttreatment < 100 G,

[0014] - Deposit a layer based on a dielectric material, called a dielectric layer, at least on the etched surface. The plasma treatment step implemented in the method according to the invention makes it possible to significantly improve the quality of the layer of III-V material, typically etched GaN. Working at low temperature makes it possible in particular to obtain a highly stabilized etched GaN layer, thus facilitating and accelerating the handling of the samples, which results in a gain in productivity. The samples must in fact be moved from one reactor to another, for example from the reactor where the plasma treatment took place to the reactor where the deposition of the dielectric layer in AI2O3 takes place, for example. In the context of the development of the present invention, it was noted that with higher temperatures, the layer of III-N material is less stable, which poses problems in terms of robustness of the process.Furthermore, in the context of the development of the present invention, it was unexpectedly observed that this lowering of the temperature leads to a much better quality of interface between the etched III-N material and the dielectric material than was expected. On the contrary, in this context, the person skilled in the art would have been encouraged to apply high temperatures to recrystallize the III-V material on the surface and which is altered by the etching.

[0015] The improvement in the quality of the etched GaN layer itself induces a strong improvement in the quality of the etched GaN / dielectric interface, particularly from the point of view of its electrical properties.

[0016] The method according to the invention thus makes it possible to considerably improve productivity compared to an ALE-type solution, while offering very satisfactory interface quality. However, it is possible for the method according to the invention to be used in conjunction with ALE-type etching.

[0017] It should be noted that the treatments subsequent to a non-etched epitaxial GaN deposition step are not suitable for the treatment of an etched GaN layer, or are at least much less effective. Indeed, the surface of an non-etched epitaxial GaN layer is relatively stable because the layer has generally spent a significant amount of time, often from a few hours to a few months, in air. The stoichiometry of the epitaxial GaN layer is thus stabilized, which makes the surface of the layer less reactive, unlike the surface of an etched GaN layer. Thus, the strategy of applying a plasma treatment proposed in the present application to chemically modify the GaN surface and thus improve the quality of the interface with the dielectric will have little effect on the epitaxial GaN surfaces.On non-etched epitaxial surfaces, plasma treatments are rather cleaning strategies and do not allow the structural reconstruction that the process according to the invention allows used on an etched GaN layer.

[0018] Further provided is a method of producing a microelectronic device comprising the formation of a layer based on a dielectric material on a layer based on an etched II lV material by implementing the formation method mentioned above, the microelectronic device being taken from among a transistor and an LED.

[0019] A method of producing a microelectronic device according to the above-mentioned production method is further provided, in which:

[0020] - the microelectronic device is a transistor,

[0021] - the etching of layer II lV is carried out so as to create a trench in the etched material II lV,

[0022] - the deposition of the layer based on a dielectric material is carried out on at least part of the etched surface of the trench so as to form a gate dielectric, and comprising, after the formation of the dielectric layer, the following step:

[0023] - fill the trench to define at least one gate of the transistor.

[0024] A microelectronic device is any type of device made using microelectronic means. These devices include, in addition to devices for purely electronic purposes, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (LEDs, MOEMS, etc.). It may be a device intended to perform an electronic, optical, mechanical, etc. function. It may also be an intermediate product solely intended for the production of another microelectronic device.

[0025] A method of making a transistor is also provided, the method comprising the following steps:

[0026] - forming a layer based on a dielectric material on a layer based on an etched II lV material by implementing the formation method mentioned above. The etching of the II lV layer is carried out so as to produce a trench in the etched II lV material. The deposition of the layer based on a dielectric material is carried out on at least a portion of the etched surface of the trench so as to form a gate dielectric.

[0027] - fill the trench to define at least one gate of the transistor.

[0028] A method of producing a transistor is also provided, comprising the following steps:

[0029] - Provide at least one layer based on a II lV material, preferably lll-N, called II lV layer, having a front face,

[0030] - Etch at least one trench in layer II lV from the front face and through the mask so as to expose a surface of layer II lV called the etched surface,

[0031] - Expose at least the etched surface to a plasma treatment of O2 or N2, this step being carried out at a temperature Ttreatment with Tt ra itement < 1 00 o C,

[0032] - Deposit a layer based on a dielectric material, called a dielectric layer, at least on a part of the etched surface of the trench so as to form a gate dielectric,

[0033] - Fill the trench to define at least one transistor gate.

[0034] This type of transistor features an improved interface between the III-V layer and the dielectric layer. Thus, this process features improved productivity while allowing the transistor to achieve high performance.

[0035] BRIEF DESCRIPTION OF THE FIGURES

[0036] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of an embodiment thereof which is illustrated by the following accompanying drawings in which:

[0037] Figures 1A to 1G illustrate the steps of a method according to one of the embodiments of the invention. Figure 1A illustrates the provision of a layer based on a III-V material called III-V layer.

[0038] Figure 1B illustrates the deposition of a possible masking layer over the III-V layer.

[0039] Figure 1C shows the formation of openings in the masking layer to form an etching mask on the III-V layer.

[0040] Figure 1 D illustrates a step of etching the III-V layer allowing the updating of a surface called the etched surface of the III-V layer.

[0041] Figure 1 E illustrates a step of exposing the etched surface to a plasma treatment, represented by a set of arrows pointing towards the etched surface.

[0042] Figure 1 F shows the deposition of a dielectric layer on the etched surface.

[0043] Figure 1G illustrates the removal of the possible mask.

[0044] Figure 2A represents a capacitance-voltage characteristic (CV characteristic or CV profiling) of a MOS (Metal Oxide Semiconductor) capacitor manufactured according to a method known from the prior art.

[0045] Figure 2B represents a CV characteristic of a MOS capacitor manufactured according to an embodiment of the method according to the invention.

[0046] Figure 3 summarizes the different steps of an example of a formation method according to the invention. Figure 4 is a graph illustrating the CV characteristics of MOS capacitors produced according to an embodiment of the invention, with a processing temperature for one of 40°C and for the other of 60°C.

[0047] Figure 5A is a graph showing the voltage value of flat strips of MOS capacitors made according to one embodiment of the invention, with a processing temperature for one of 40°C and for the other of 60°C.

[0048] Figure 5B is a graph representing the hysteresis value of MOS capacitors produced according to an embodiment of the invention, with a processing temperature for one of 40°C and for the other of 60°C.

[0049] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, the thicknesses of the different layers are not representative of reality.

[0050] DETAILED DESCRIPTION OF THE INVENTION

[0051] Before commencing a detailed review of embodiments of the invention, optional features which may optionally be used in combination or alternatively are set out below:

[0052] According to one embodiment, the etching step and the plasma treatment step are carried out in the same reactor.

[0053] According to one example, Tt ra itement > 40 o C.

[0054] According to one example, Tt ra itement < 80 o C.

[0055] According to an example, the plasma treatment step has a duration t tra itement, with ttreatment^Smin, OR ttreatment^SOOS, and preferably ttreatment^Smin OR ttreatment*' 120S.

[0056] According to one embodiment, the method comprises, before the step of depositing the dielectric layer, a wet cleaning step.

[0057] According to one embodiment, the step of depositing the dielectric layer is carried out under vacuum.

[0058] In one example, the etching step comprises chlorine plasma etching.

[0059] According to one example, the etching step comprises at least one ALE type etching cycle.

[0060] In one example, the etching is performed so as to etch a thickness of III-V material greater than 100 nm (10 -9 meters), preferably greater than 500 nm, preferably greater than 1 pm (10 -6 meters), preferably greater than 3 pm.

[0061] According to one example, the plasma treatment step is carried out under a zero bias voltage Vbias.

[0062] According to one example, the plasma treatment step is carried out by injecting a flow of O2, N2 or a mixture of O2 and N2 having a mass flow rate Dfi ux between 50sccm and 1000sccm, preferably between 1000sccm and 500sccm.

[0063] According to one example, the plasma treatment step is carried out by injecting a flow of O2, N2 or a mixture of O2 and N2 generated by a power source P SO source between 100W and 4000W, preferably between 300W and 1000W.

[0064] According to one example, the II lV material is one of GaN and AIGaN.

[0065] According to one example, the dielectric material is one of AlN, Al2O3 and HfO2.

[0066] It is specified that, in the context of the present invention, the terms "on", "overcomes", "covers", "underlying", "facing" and their equivalents do not necessarily mean "in contact with". Thus, for example, the deposition, transfer, bonding, assembly or application of a first layer on a second layer does not necessarily mean that the two layers are in direct contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0067] A layer can also be composed of several sub-layers of the same material or of different materials.

[0068] A substrate, a layer, a device, "based" on a material M, is understood to mean a substrate, a layer, a device comprising this material M only or this material M and possibly other materials, for example alloying elements, impurities or doping elements. Thus a material based on a III-N material may comprise a III-N material with added dopants. Similarly, a GaN-based layer typically comprises GaN and alloys of AIGaN or InGaN.

[0069] The term "III-V material" refers to a semiconductor composed of one or more elements from column III and column V of Mendeleev's periodic table. Elements in column III include boron, gallium, aluminum, and indium. Column V contains, for example, nitrogen, arsenic, antimony, and phosphorus.

[0070] The term "selective etching with respect to" or "etching exhibiting selectivity with respect to" means an etching configured to remove a material A or a layer A with respect to a material B or a layer B, and exhibiting an etching speed of the material A greater than the etching speed of the material B. The selectivity is the ratio between the etching speed of the material A and the etching speed of the material B. The selectivity between A and B is denoted SA: B. A reference frame, preferably orthonormal, comprising the axes x, y, z is shown in Figure 1A. This reference frame is applicable by extension to the other figures.

[0071] In this patent application, we will preferably speak of thickness for a layer and height for a structure or device. The thickness is taken along a direction normal to the main extension plane of the layer, and the height is taken perpendicular to the XY base plane. Thus, a layer typically has a thickness along z, when it extends mainly along an XY plane, and a projecting element, for example an isolation trench, has a height along z. The relative terms "on", "under", "underlying" preferably refer to positions taken along the z direction.

[0072] The steps of the method as claimed are understood in the broad sense and may optionally be carried out in several sub-steps.

[0073] An example of a production method will now be described with reference to FIGS. 1A to 1G and to FIG. 3. This method makes it possible to obtain the structure illustrated in FIG. 1G, comprising an interface 1000 between a layer of etched III-V material 100 and a layer of dielectric 200.

[0074] As illustrated in Figure 1A, a first step consists of providing a layer 100 based on at least one III-V material, preferably based on at least one III-N material. Typically, this material is based on GaN. This layer is called III-V layer 100. The III-V layer 100 has an upper face 101 and a lower face 102 both extending mainly in the XY plane of the orthogonal XYZ reference frame. It has a thickness e o in the z direction.

[0075] The lll-V layer 100 may be formed from a homogeneous layer, typically from a single material. Alternatively, the lll-V layer 100 may be formed from a stack of layers of lll-N material, at least some of these layers having a different composition. For example, the lll-V layer 100 may be formed from one or more layers of GaN and one or more layers of P-doped GaN, AIGaN, AIN and / or InGaN. Typically, the lll-V layer 100 may be formed from a set of one or more layers of GaN and a layer of AIGaN surmounting this set. This is for example the case in certain HEMT type transistors.

[0076] The III-V layer 100 may rest on a substrate, typically a support or growth substrate. Such a substrate is not shown in FIGS. 1A to 1G. One or more intermediate layers may be arranged between the substrate and the lower face 102 of the III-V layer 100. This may in particular be a nucleation layer.

[0077] A second step consists of etching at least a portion of the III-V layer 100 from its upper face 101 and over a thickness e g etching. This step is represented by block 31 of Figure 3. The etching is advantageously carried out so as to etch the III-V 100 layer over an etching thickness greater than 100 nm (10 -9 meters), preferably greater than 500 nm, preferably greater than 1 pm (10 -6meters), preferably greater than 3 μm. In order to etch only certain areas of the III-V layer 100, it is possible to form a mask 310 overlying the III-V layer 100, as illustrated in FIG. 1C. The presence of this mask 310 is however not mandatory to implement the etching method described below. According to one example, the mask 310 is arranged directly in contact with the upper face 101 of the III-V layer 100. The mask 310 is for example formed by lithography of a masking layer 300 deposited or transferred onto the III-V layer 100, as illustrated in FIG. 1B. Preferably, the mask 310 is a hard mask. It is preferably based on a polymer, for example a resin, or a dielectric. It is for example formed on the basis of SiC>2 or Si x N ywith x and y unaffected integers. The hard mask 310 may for example be formed by one of the following materials, or a mixture of several of the following materials: Si N , SialXL, SiOCN, SiCBN. The mask 310 has at least one opening 311 , as illustrated in FIG. 1C, through which the etching of the III-V layer 100 is carried out.

[0078] The etching can be dry or wet etching. For example, it can be a plasma etching step using chlorinated or fluorocarbon chemistry. This etching step can be carried out in a reactive ion etching (RIE) reactor, preferably an inductively coupled plasma (ICP) reactor. It is also possible to implement a self-limiting cyclic etching process such as ALE (Atomic Layer Etching), alone or in addition to conventional plasma etching. Such a process generally consists of one or more cycles comprising the following steps:

[0079] - A step of modification of a part of the layer to be etched preferably located on the surface of this same layer, for example a self-limiting chlorination by exposure to a Ch / BCh plasma,

[0080] - An etching of the part of the layer to be etched thus selectively modified to the rest of the layer to be etched, for example using an Ar-based plasma and under a non-zero bias voltage.

[0081] Self-limiting cyclic etching processes make it possible to significantly limit damage to the etched layer. In synergy with the plasma treatment step which will be described later, an etching step of the III-V 100 layer via such a process makes it possible to obtain an even better interface quality 1000. However, it is entirely possible that the etching step of the III-V 100 layer is limited to a conventional plasma etching.

[0082] The engraving techniques mentioned above are given as examples but do not constitute an exhaustive list of possible techniques.

[0083] The etching step just described makes it possible to expose a surface called the etched surface 103 of the III-V layer 100, as shown in FIG. 1 D. According to one example, this etching makes it possible, for example, to form a trench in the III-V layer 100.

[0084] A third step consists of exposing the etched surface 103 to a treatment as shown in Figure 1 E. The treatment is shown in this diagram by the vertical arrows oriented towards the etched surface 103. This treatment is by a plasma based on dioxygen (O2) and / or dinitrogen (N2). This step is represented by block 32 of Figure 3. It is advantageously carried out in the same chamber as the etching step of the III-V layer 100. This is preferably an ICP reactor. Carrying out the plasma treatment step in situ makes it possible to limit contamination due to the re-exposure of the samples to the air and to improve productivity. This also has an advantage in relation to the structural defects induced by the etching step. Indeed, following the etching step, the etched surface 103 constitutes a reactive surface which, during re-exposure to the air, reacts with the air to form defects.For example, vacancies caused by etching at the etched surface 103 may be filled by contaminants present in the air, such as carbon-based or oxygen-based contaminants. These then constitute traps that may hinder the step of deposition of a dielectric which will be detailed further and / or alter the electronic performance of a device obtained after additional subsequent steps. Subjecting the etched surface 103 to in situ plasma treatment and before any return to the air of the sample makes it possible to fill these vacancies with advantageous elements provided by the plasma, and thus to limit the filling of these same vacancies by elements present in the air. For example, the nitrogen vacancies of a GaN-based etched surface 103 may be filled by nitrogen atoms provided by an N2-based plasma treatment.

[0085] It is however possible to carry out the plasma treatment in a chamber separate from that used for etching the III-V 100 layer.

[0086] The flow of O2 or N2 is generated in the treatment chamber by a source whose power is between 100W and 4000W, preferably between 300W and 1000W. The power of the flow is a parameter having a direct impact on the reactivity of the plasma formed. In the context of the present invention, it is sought to obtain a highly chemically reactive plasma in order to ensure the good reconstitution of the etched surface 103, and this in reduced treatment times. This is characterized in particular by a high concentration of reactive radicals, and a limited quantity of ions. Increasing the power of the flow makes it possible to increase the quantity of reactive radicals, but also has the impact of increasing the ion density. The preferred values ​​mentioned thus constitute a good compromise. The flow can be pure or mixed with other minority gases. For example, it can be a flow composed of N2 and O2, N2 and Ar, or O2 and Ar.The flow rate of the species is advantageously between 50 sccm and 1000 sccm (cubic centimeters per minute), preferably between 100 sccm and 500 sccm. The duration of this plasma treatment step is advantageously between a few seconds, preferably 30s, and several hundred seconds. The bias voltage is preferably zero. Indeed, opting for a non-zero bias voltage, combined with the fact that the plasma contains ions, increases the risk of degradation.

[0087] The plasma treatment step takes place at a temperature below 100°C and not at high temperature, as is the case for common techniques for recrystallizing an etched layer. This treatment condition has made it possible to improve the quality of the interface 1000 to an unexpected extent. This low temperature level makes it possible in particular to obtain a stabilized interface 1000 after the plasma treatment step. This makes it possible to improve the robustness of the process and therefore the quality of the interface while improving productivity. In addition, in the case of an O2-based plasma treatment, working at low temperature makes it possible to avoid unwanted oxidation on the etched surface 103.

[0088] Preferably, the treatment temperature, i.e. the temperature of the substrate holder on which the III-V layer 100 rests in the plasma treatment chamber, is greater than 20°C. Preferably, it is less than 90°C. Advantageously, it is between 40°C and 80°C, preferably between 60°C and 80°C. Increasing the temperature makes it possible in particular to improve the reactivity of the etched surface 103 and therefore to optimize the structural reconstruction of the III-V layer 100.

[0089] Advantageously but optionally, after the step of exposure to the plasma treatment, wet cleaning of the etched surface 103 of the III-V layer 100 is provided. This cleaning is advantageously based on HCl, HF or a mixture of HCl and HF. This step makes it possible to clean the etched surface in preparation for the deposition of a dielectric layer 200 and constitutes a complement to the plasma treatment. It makes it possible to further improve the electrical properties of the interface between the etched III-V layer 100 and the dielectric layer 200. These electrical properties are improved to a surprising extent. This cleaning step is carried out outside the reactor which allowed the etching of the III-V layer 100. This optional step is represented by block 33, drawn in dotted lines, in FIG. 3.

[0090] A fourth step, represented in Figure 1 F and by block 34 of Figure 3, consists of the deposition of a layer based on a dielectric material at least on the etched surface 103 of the III-V layer 100. This layer is called dielectric layer 200. Preferably, it is made of a dielectric material taken from one of the following materials, or a mixture thereof: AIN, AfeOs, HfCh. Preferably, the deposition of the dielectric layer 200 is carried out by ALD (acronym for “Atomic Layer Deposition”). This may be a thermal or plasma ALD process. In the particular case where the dielectric layer 200 is an ALCh layer and where the deposition is carried out by thermal ALD, the oxygen-based precursor can be water (H2O) or ozone (O3), and the aluminum-based precursor can be trimethylaluminum (TMA).If the deposition is carried out by plasma ALD, the oxygen-based precursor may be a dioxygen (O2)-based plasma. The deposition of the dielectric layer 200 is preferably carried out under vacuum in order to avoid contamination.

[0091] The contact area between the lower face 202 of the dielectric layer 200 and the etched surface 103 of the III-V layer 100 constitutes the interface 1000 between the III-V layer 100 and the dielectric layer 200.

[0092] Figure 1G illustrates an optional step of removing the mask 310 and certain portions of the dielectric layer 200. This removal can take place before or after the step of exposing the etched surface 103 to the plasma treatment and before or after the step of depositing the dielectric layer 200. This removal can for example be concomitant with the cleaning step. In this case, a solvent based on HF or HCl and HF is preferably used. Advantageously, the mask 310 is kept until the step of exposure to the plasma treatment, during which it can again act as a mask. The mask 310 can also be kept until the step of depositing the dielectric layer 200, as illustrated in Figure 1F.

[0093] Figures 2A and 2B illustrate one of the advantages provided by the method according to the invention. The graph presented in Figure 2A is a CV (Capacitance-Voltage) characteristic of a MOS capacitor comprising an interface between an etched GaN layer and an AhOa layer and obtained by a method not including plasma treatment subsequent to the etching of the GaN layer. The graph presented in Figure 2B is a CV characteristic of a MOS capacitor having been designed by the same method and with the same materials, but whose etched GaN layer has undergone plasma treatment in an ICP reactor as well as wet cleaning based on HCl, in accordance with one of the embodiments of the invention. In each of the two Figures 2A and 2B, the CV characteristic was recorded for different frequencies of the alternating signal applied to the MOS capacitor studied.

[0094] It is noted that, particularly at low frequency (see in particular the characteristic at 5 kHz) and at high frequency (see in particular the characteristic at 500 kHz), the MOS capacitance characterized in Figure 2A exhibits poorer performance than the MOS capacitance characterized in Figure 2B. The slopes of the characteristics for each of the frequencies studied are in fact lower than their equivalents in Figure 2B, reflecting a less rapid transition from the accumulation regime to the inversion regime in response to a voltage variation. The comparison of Figures 2A and 2B therefore highlights a clear improvement, thanks to the method according to the invention, in the performance of electronic components comprising an etched II lV material / dielectric interface.

[0095] Figures 4, 5A and 5B illustrate the fact that, as previously stated, the choice of the processing temperature makes it possible to optimize the performance of the devices produced according to the invention. The graph presented in Figure 4 is a CV characteristic of a MOS capacitor comprising an interface between a dielectric and a II lV material obtained by implementing an embodiment of the method according to the invention, for two distinct processing temperatures: 40°C and 60°C. Figures 5A and 5B illustrate the value of the flat band voltage Vfb and the hysteresis AVfb for each of these two samples. It is observed that the MOS capacitor having undergone processing at a temperature of 60°C has much better electrical performance than that whose processing temperature was 40°C. In particular, its flat band voltage is much higher (approximately 1.61V compared to 1.35V for Tt raitement=40°C) while its hysteresis is significantly lower (approximately 0.56V against 0.65V for Tt ra itement=40°C). Increasing the treatment temperature to a certain extent during the plasma treatment step therefore allows a clear improvement in the performance of the device, which is explained by better resorption of surface defects.

[0096] It was noted, however, that surprisingly, for temperatures above 80°C, the performance of MOS capacitors degraded sharply and rapidly. This illustrates the fact that treating a sample at high or even very high temperature in the hope of better recrystallization, as is commonly done, is not always appropriate. Too rapid recrystallization can, on the contrary, freeze structural defects, particularly on the surface, thus inducing a degradation of device performance. These results thus illustrate the optimization of the structural reconstruction of the III-V layer in the 60°C-80°C range.

[0097] An advantage of the solution proposed by the invention is that the steps of exposing the etched III-V layer 100 to a plasma treatment and of depositing a dielectric layer 200 can be carried out after any type of etching and for any III-V material. The method according to the invention therefore constitutes a solution that could be described as universal against the problem of the quality of the interfaces between an etched III-V material and a dielectric. Such adaptability also allows a certain standardization of the manufacturing processes of electronic components in which the method according to the invention can be integrated.

[0098] Another advantage of the proposed solution is that the plasma treatment step is a rapid step that can also be carried out immediately after the etching step, in the same reactor. The method according to the invention can thus be integrated into a microelectronic device manufacturing process without affecting productivity.

[0099] Through the different embodiments described above, it clearly appears that the invention proposes an effective solution for improving the productivity of the formation of an interface between a layer of etched III / V material and a dielectric layer while ensuring good quality of this interface.

[0100] The proposed process is particularly advantageous for power applications, such as power transistors or LEDs or pLEDs. In this case, the thickness of the III-V material to be etched, such as GaN, can be from a hundred nanometers to several microns.

[0101] The invention is not limited to the embodiments previously described and extends to all embodiments covered by its spirit.

Claims

DEMANDS 1. A method for forming a layer based on a dielectric material on a layer based on an etched III-V material, the method comprising at least the following steps: • Provide at least one layer based on an lll-V material, preferably lll-N, called lll-V layer (100), having a front face (101), • Etch at least a portion of layer III-V (100) from the front face (101) so as to expose a surface of layer III-V called the etched surface (103), • Expose at least the etched surface (103) to a plasma treatment of O2, N2 or a mixture of O2 and N2, this step being carried out at a treatment temperature between 60°C and 80°C, • Deposit a layer based on a dielectric material, called a dielectric layer (200), at least on the etched surface.

2. A method according to the preceding claim in which the etching step and the plasma treatment step are carried out in the same reactor.

3. A method according to any one of the preceding claims, wherein the plasma treatment step has a treatment duration, with tt ra iteration < 5m in and preferably ttraitement^S 0 i H .

4. A method according to any one of the preceding claims comprising further, prior to the dielectric layer deposition step, a wet cleaning step.

5. A method according to any one of the preceding claims, wherein the dielectric layer deposition step is carried out under vacuum.

6. A method according to any one of the preceding claims, wherein the etching step comprises chlorinated plasma etching.

7. A method according to any one of the preceding claims wherein the etching step comprises at least one ALE type etching cycle.

8. A method according to any one of the preceding claims wherein the plasma treatment step is carried out under zero bias voltage Vbias.

9. A method according to any one of the preceding claims, wherein the engraving is carried out so as to engrave a material thickness lll-V greater than 100 nm (10 -9 meters), preferably greater than 500 nm, preferably greater than 1 pm (10' 6 meters), preferably greater than 3 pm.

10. A method according to any one of the preceding claims, wherein the plasma treatment step is carried out by injecting a flow of O2, N2, or a mixture of O2 and N2, having a mass flow rate Dfi ux between 50sccm and 100sccm, preferably between 100sccm and 500sccm.

11. A method according to any one of the preceding claims in which the plasma treatment step is carried out by injecting a flow of O2, N2 or a mixture of O2 and N2 generated by a power source Psource of between 100W and 4000W, preferably between 300W and 1000W.

12. A method according to any one of the preceding claims wherein the material II lV is one of GaN and AIGaN.

13. A method according to any one of the preceding claims wherein the dielectric material is one of AIN, AhOa and HfO2.

14. Method of making a microelectronic device comprising the formation of a layer based on a dielectric material (200) on a layer (100) based on an etched material II lV by implementing the method according to any one of the preceding claims, the microelectronic device being taken from among a transistor and an LED.

15. A method for manufacturing a microelectronic device according to the preceding claim, wherein: • The microelectronic device is a transistor, • the engraving of layer II lV (100) is carried out in such a way as to create a trench in the engraved material II lV, • the deposition of the layer based on a dielectric material (200) is carried out on at least a part of the engraved surface of the trench so as to form a grid dielectric, the process comprising, after the formation of the dielectric layer (200), the following step: • fill the trench to define at least one transistor gate.

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