Multilevel converter system
Patent Information
- Application Number
- EP2023840758
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-03-29
- Filing Date
- 2023-12-28
- Publication Date
- 2025-03-19
AI Technical Summary
Conventional multilevel converter systems are expensive due to the high number of transistors required, which occupy a large amount of space and increase manufacturing costs.
A modular multilevel converter system with energy storage modules and transistors, where adjacent transistors share N or P zones to reduce the amount of semiconductor material needed, allowing for cost savings and smaller chip size, and using a planar or trench transistor design with high-frequency switching capabilities.
Significantly reduces manufacturing costs and chip size by sharing zones between transistors, enabling more versatile configurations and efficient energy management in converter systems.
Smart Images
Figure EP2023087945_03102024_PF_FP_ABST
Abstract
Description
[0001] BAVERTIS GmbH
[0002] Multilevel converter system
[0003] The invention relates to a multilevel converter system comprising a plurality of energy storage modules and transistors, wherein each energy storage module can be connected in parallel, in series and / or bridged to the adjacent energy storage module and has at least one energy storage cell.
[0004] Current energy storage systems are typically loaded with direct current (DC). This is due to the design of conventional converter systems. The aim is to keep the alternating current components, i.e., harmonic oscillations, away from the energy storage devices.
[0005] Since many energy storage devices must be connected in series or parallel, a battery management system (BMS) is necessary. A DC link capacitor, for example, can be connected downstream of the energy storage devices. This serves to further smooth the three-phase currents of the converter and to keep high-frequency oscillations away from the energy storage devices. It also absorbs switching overshoots, as the inductance of the energy storage devices would drive the current further. The goal of this approach is to apply DC load to the energy storage devices, as this is assumed to contribute to the durability of the battery cell and reduce losses.
[0006] For example, in a conventional electric vehicle, the DC bus can house the converters that transfer the energy to the electric motor or, during braking energy recovery (recuperation), return it to the battery. Chargers that can operate with alternating current (AC) or direct current (DC) can also be connected to this bus. These converters are usually designed as two-level converters, e.g., as a B6 bridge in a three-phase version, or—especially in the field of solar systems—as three-level converters.
[0007] As an alternative to bridge circuits as converters, so-called multilevel converter systems are known.
[0008] Batteries, such as accumulators, can be used as energy storage devices or energy sources. The energy storage devices are not hard-wired together, but rather combined as individual submodules. This structure is required for each phase. Therefore, the energy storage devices are distributed across these phases and can be hard-wired in series or parallel, for example.
[0009] For example, lithium-ion cells are often used in electric vehicles.
[0010] Current transistors are mostly constructed as NPN semiconductors. This means that an area is negatively doped, then positively doped, and then negatively doped again. This semiconductor, with its three terminals (drain, gate, and source), is manufactured in a factory.
[0011] First, a silicon wafer is used, which is then converted into many individual semiconductors through various process steps. These are then tested for functionality and cut into individual discrete components. Each semiconductor—unless it is used directly as a so-called "bare die"—is then given a housing in which the external contact is made.
[0012] This approach is particularly advantageous for current semiconductors (e.g. silicon MOSFETs, i.e. silicon metal oxide semiconductor field-effect transistors), since the gates of power MOSFETs used for multilevel applications are usually planar.
[0013] Due to their better switching and conduction behavior, power MOSFETs are usually constructed as so-called “superjunction MOSFETs”.
[0014] However, the power semiconductor market has been disrupted for several years by so-called “wide bandgap devices” (WBG).
[0015] Two of these are particularly noteworthy: silicon carbide (SiC) and gallium nitride (GaN).
[0016] In the lower voltage range, for example, below 650 V, GaN is expected to prevail based on current knowledge. GaN is more cost-effective and significantly more powerful than silicon components. However, these new switches are currently not constructed as planar devices, but as lateral devices.
[0017] Conventional multilevel converter systems are still comparatively expensive. This is due, for example, to the relatively high number of transistors. These transistors also require a relatively large amount of space, so the chips used are relatively large, which negatively impacts manufacturing costs.
[0018] It is therefore an object of the invention to provide a multilevel converter system, a method for producing a multilevel converter system and a wafer for producing a multilevel converter system, in which the manufacturing costs of the multilevel converter system are reduced.
[0019] This problem is solved by the subject matter and method of the independent claims. According to the invention, the preferably modular multilevel converter system comprises a plurality of energy storage modules and transistors.
[0020] A multilevel converter system describes a type of arrangement or circuit of several energy storage modules or transistors.
[0021] Each energy storage module can have at least or exactly one battery, e.g. an accumulator.
[0022] The transistors serve, for example, as switches that can be used to select current and / or voltage paths. This allows the energy storage modules to be integrated into or excluded from a desired configuration.
[0023] Preferably, each energy storage module is assigned at least or exactly two, three, four, five, six, seven, eight, nine, ten or more transistors.
[0024] The transistor can be designed, for example, for a voltage of less than 500 V, 400 V, 300 V, 200 V, 100 V, 50 V, 40 V, 30 V, 20 V or 10 V. Preferably, the transistor can be designed for a voltage between 2 V and 8 V, e.g.
[0025] 3V, 4V, 5V, 6V or 7V.
[0026] The transistor can be a lateral, planar, or trench transistor, for example. However, any design is conceivable.
[0027] The transistor is preferably designed as a MOSFET or comprises a MOSFET.
[0028] MOSFETs can be switched at high frequencies. For example, at least one transistor can have a switching frequency of at least 1 Hz.
[0029] The semiconductor material may be, for example, silicon, gallium nitride, gallium arsenide and / or silicon carbide.
[0030] Each energy storage module can be connected in parallel to the adjacent energy storage module and / or in series and / or bypassed. Preferably, each energy storage module can be connected in series to the adjacent energy storage module. The option of parallel connection is advantageous but not necessary.
[0031] Preferably, the adjacent energy storage modules are each connected to each other via two current and / or voltage paths. A transistor can be assigned to each path.
[0032] For example, three transistors are provided between two adjacent energy storage modules. This allows the energy storage modules to be connected in parallel or in series, for example.
[0033] Each energy storage module has at least one energy storage cell.
[0034] For example, the energy storage module can have exactly one energy storage cell. However, each energy storage module preferably has multiple energy storage cells, e.g., at least 10, 20, 30, 40, 50, 60, 70, 80, 90, or 100.
[0035] For example, at least 100 energy storage cells, e.g. 140, can be provided in an energy storage module.
[0036] The energy storage cells of an energy storage module can preferably be connected in parallel. The energy storage cells of an energy storage module are preferably selected such that the same charge is present as in the mains, e.g., 230 V. Multilevel converter systems are significantly more versatile than bridge circuits. This allows for virtually any configuration to be created. For example, the energy storage modules can be connected to each other in any way, e.g., in parallel or in series. Individual energy storage modules can also be included in or excluded from a desired configuration.
[0037] At least two adjacent NPN transistors share an N-zone. Alternatively or additionally, at least two adjacent PNP transistors share a P-zone.
[0038] Thus, N-zones or P-zones of neighboring transistors are combined.
[0039] Instead of two adjacent NPN transistors, this essentially results in one NPNPN transistor, or instead of two adjacent PNP transistors, this essentially results in one PNPNP transistor.
[0040] Protection is also claimed for such transistors independently of a multilevel converter system.
[0041] By eliminating N-zones and P-zones, there are advantages in the required amount of semiconductor material when using adjacent switches, as is often the case in multilevel converter systems. This advantage is directly reflected in the price. On the other hand, the chip area is reduced, which also has a positive impact on costs.
[0042] It was surprising that the savings or shared use of adjacent zones can be achieved in multilevel converter systems, leading to a significant reduction in costs. Further developments of the invention can also be found in the dependent claims, the description, and the accompanying drawings.
[0043] According to one embodiment, at least three NPN transistors are provided, with adjacent NPN transistors sharing an N-zone.
[0044] Alternatively or additionally, at least three PNP transistors are provided, with adjacent PNP transistors sharing a P-zone.
[0045] In principle, any number of transistors can be provided, with neighboring transistors sharing a zone.
[0046] For example, three NPN transistors can be combined to form one NPNPNPN transistor or three PNP transistors can be combined to form one PNPNPNP transistor.
[0047] According to a further embodiment, the adjacent NPN transistors and / or PNP transistors are arranged next to one another.
[0048] Preferably, the transistors are arranged linearly, i.e. in a row, and do not enclose any angle, for example.
[0049] According to a further embodiment, the adjacent NPN transistors and / or PNP transistors are not arranged linearly to one another.
[0050] For example, the neighboring transistors can be oriented at right angles or obliquely to each other.
[0051] Preferably, the adjacent transistors can enclose an angle greater than 0°. The adjacent transistors can preferably extend in different spatial directions (e.g., along an X, Y, or Z axis).
[0052] According to another embodiment, the multilevel converter system is constructed as PECIN, MMSPC, M2B or BM3.
[0053] The topology PECIN stands for “Parallel Enhanced Commutation Integrated Nested”, MMSPC for “Modular Multilevel Series Parallel Converter” and M2B for “Modular Multilevel Battery”.
[0054] BM3, also called Marx topology, stands for “Battery Modular Multilevel Management”.
[0055] In principle, other topologies are also conceivable, e.g. half bridge, prior half bridge, cross-switched, cascaded cross-switched, CEBS, full bridge or ECIN.
[0056] The mentioned topologies are potential candidates for installation in an electric vehicle, for example.
[0057] The invention relates to a method for producing a multi-level converter system according to the invention, in which N-conducting and P-conducting layers are produced in a wafer in such a way that the N-conducting and P-conducting layers are always arranged alternately and / or in which P-conducting and N-conducting layers are produced in a wafer in such a way that the P-conducting and N-conducting layers are always arranged alternately.
[0058] In this way, at least two neighboring NPN transistors share an N-zone or two neighboring PNP transistors share a P-zone.
[0059] According to one embodiment, the wafer, which has an N-type conductive layer, is coated with a first non-conductive protective layer. A single-crystal silicon wafer or a single-crystal gallium wafer, for example, can be used as a starting point.
[0060] The first and / or further protective layers may, for example, comprise or consist of silicon dioxide and / or gallium oxide.
[0061] To create a P-type layer, a first window is introduced into the first protective layer.
[0062] The first window is covered with a second non-conductive protective layer.
[0063] To create an N-conducting layer, a second window is introduced into the second protective layer.
[0064] The second window is covered with a third non-conductive protective layer.
[0065] To create a P-type layer, a third window is introduced into the third protective layer.
[0066] The third window is covered with a fourth non-conductive protective layer.
[0067] To create an N-type layer, a fourth window is introduced into the fourth protective layer.
[0068] In this way, for example, an NPNPN transistor can be created.
[0069] In principle, this process can be continued indefinitely.
[0070] Preferably, additional windows are then introduced and metallic connections are attached, e.g., by vapor deposition. A corresponding manufacturing process is also known as planar technology. The windows can be introduced, for example, using a so-called mask technique, preferably by etching.
[0071] According to a further embodiment, the wafer having a P-type conductive layer is coated with a first non-conductive protective layer.
[0072] A single-crystal silicon wafer or a single-crystal gallium wafer can be used as a starting point.
[0073] The first and / or further protective layers may, for example, comprise or consist of silicon dioxide and / or gallium oxide.
[0074] To create an N-conducting layer, a first window is introduced into the first protective layer.
[0075] The first window is covered with a second non-conductive protective layer.
[0076] To create a P-type layer, a second window is introduced into the second protective layer.
[0077] The second window is covered with a third non-conductive protective layer.
[0078] To create an N-type layer, a third window is introduced into the third protective layer.
[0079] The third window is covered with a fourth non-conductive protective layer.
[0080] To create a P-type layer, a fourth window is introduced into the fourth protective layer.
[0081] In this way, for example, a PNPNP transistor can be created. This process can, in principle, be continued indefinitely.
[0082] Preferably, further windows are added and metallic connections are attached, e.g. by steaming.
[0083] A corresponding manufacturing process is also known as planar technology. The windows can be created, preferably etched, using a mask technique, for example.
[0084] The invention further relates to a wafer for producing a multilevel converter system in which N-conducting and P-conducting layers are always arranged alternately.
[0085] For example, the N-type and P-type layers can be arranged to form an NPNPN structure.
[0086] Finally, the invention relates to a wafer for producing a multilevel converter system in which P-conducting and N-conducting layers are always arranged alternately.
[0087] For example, the P-type and N-type layers can be arranged to form a PNPNP structure.
[0088] All embodiments and components of the devices described here are preferably designed to be manufactured according to one or more of the methods described here. Furthermore, all embodiments of the devices described here, as well as all embodiments of the methods described here, can be combined with one another, preferably independently of the specific embodiment in which they are mentioned. The invention is described below by way of example with reference to the drawings. They show:
[0089] Fig. 1 shows an embodiment of a multilevel converter system according to the prior art,
[0090] Fig. 2 is a schematic diagram of three NPN transistors according to the prior art,
[0091] Fig. 3 is a schematic diagram of an NPNPNPN transistor,
[0092] Fig. 4 is a schematic representation of a PECIN according to the state of the
[0093] technology, and
[0094] Fig. 5 is a schematic representation of an inventive
[0095] PECIN.
[0096] First, it should be noted that the illustrated embodiments are purely exemplary in nature. Individual features can be implemented not only in the combination shown, but also individually or in other technically feasible combinations. For example, the features of one embodiment can be combined arbitrarily with features of another embodiment. The configuration and / or number of energy storage modules, paths, and transistors shown are purely exemplary and fundamentally arbitrary.
[0097] If a figure contains a reference symbol that is not explained in the directly associated description, reference is made to the corresponding preceding or following explanations in the figure description. Thus, the same reference symbols are used for identical or comparable components in the figures and are not explained again. Fig. 1 shows a multilevel converter system with energy storage modules 10, 12, 14, 16.
[0098] Neighboring energy storage modules 10, 12, 14, 16 are each connected to each other via several paths.
[0099] In each path there is a switch designed as transistor 18.
[0100] The adjacent energy storage modules 10, 12, 14, 16 can thus be connected in series or parallel. Individual energy storage modules 10, 12, 14, 16 can also be bridged if necessary, e.g., by closing the upper switch 18, and thus excluded from a configuration.
[0101] As shown in Figs. 2 and 3, according to the invention, three NPN transistors are combined to form one NPNPNPN transistor.
[0102] The neighboring NPN transistors each share an N-zone.
[0103] The N-zones can therefore be combined here. While this slightly increases the reject rate, it also makes the semiconductor smaller and cheaper. It can now be incorporated into a package, for example.
[0104] This is feasible for all topologies. However, the effect is greatest for topologies that also allow parallel switching and thus have more switches.
[0105] The NPNPNPN transistor is preferably housed as a whole in a package, which also reduces packaging costs.
[0106] Figures 4 and 5 show the combination of adjacent zones as an example of a PECIN topology. The two upper, horizontally arranged NPN transistors share an N-zone and form an NPNPN transistor.
[0107] Likewise, the two lower, horizontally arranged NPN transistors share an N-zone and form an NPNPN transistor.
[0108] The N-zones of the two diagonally arranged NPN transistors are finally formed by the outer N-zones of the horizontal NPN transistors. The dashed lines represent an NPN connection in each case.
[0109] Thus, between the two horizontal NPNPN transistors, an NPN transistor extends from the left end of the upper NPNPN transistor to the right end of the lower NPNPN transistor, dividing the outer N-zones. Another NPN transistor extends from the right end of the upper NPNPN transistor to the left end of the lower NPNPN transistor, dividing the outer N-zones.
[0110] Accordingly, PNP transistors can also be provided in which neighboring PNP transistors share a P-zone.
[0111] By having neighboring transistors share a zone, costs can be saved.
[0112] List of reference symbols
[0113] 10 Energy storage module
[0114] 12 Energy storage module 14 Energy storage module
[0115] 16 Energy storage module
[0116] 18 transistor, switch
Claims
Claims 1. Multilevel converter system, comprising a plurality of energy storage modules (10, 12, 14, 16) and transistors (18), wherein each energy storage module (10, 12, 14, 16) can be connected in parallel, in series and / or bridged to the respectively adjacent energy storage module (10, 12, 14, 16) and has at least one energy storage cell, wherein at least two adjacent NPN transistors (18) share an N-zone and / or wherein at least two adjacent PNP Transistors (18) share a P-zone.
2. Multilevel converter system according to claim 1, characterized in that at least three NPN transistors (18) are provided, wherein adjacent NPN transistors (18) share an N-zone and / or that at least three PNP transistors (18) are provided, wherein adjacent PNP transistors (18) share a P-zone.
3. Multilevel converter system according to claim 1 or 2, characterized in that the adjacent NPN transistors (18) and / or PNP transistors (18) are arranged next to one another.
4. Multilevel converter system according to one of the preceding claims, characterized in that the adjacent NPN transistors (18) and / or PNP transistors (18) are not arranged linearly to one another.
5. Multilevel converter system according to one of the preceding claims, characterized in that the multilevel converter system is constructed as PECIN, MMSPC, M2B or BM3.
6. A method for producing a multilevel converter system according to one of the preceding claims, in which N-conducting and P-conducting layers are produced in a wafer in such a way that the N-conducting and P-conducting layers are always arranged alternately and / or in which P-conducting and N-conducting layers are produced in a wafer in such a way that the P-conducting and N-conducting layers are always arranged alternately.
7. The method according to claim 6, characterized in that a wafer with an N-conductive layer is coated with a first non-conductive protective layer, to produce a P-conductive layer a first window is introduced into the first protective layer, the first window is coated with a second non-conductive protective layer, to produce an N-conductive layer a second window is introduced into the second protective layer, the second window is coated with a third non-conductive protective layer, to produce a P-conductive layer a third window is introduced into the third protective layer, the third window is coated with a fourth non-conductive protective layer, and to produce an N-conductive layer a fourth window is introduced into the fourth protective layer.
8. The method according to claim 6, characterized in that a wafer having a P-type conductive layer with a first non-conductive protective layer is coated, to produce an N-conductive layer a first window is introduced into the first protective layer, the first window is coated with a second non-conductive protective layer, to produce a P-conductive layer a second window is introduced into the second protective layer, the second window is coated with a third non-conductive protective layer, to produce an N-conductive layer a third window is introduced into the third protective layer, the third window is coated with a fourth non-conductive protective layer, and to produce a P-conductive layer a fourth window is introduced into the fourth protective layer.
9. Wafer for producing a multilevel converter system, preferably according to one of claims 1 to 5, in which N-conducting and P-conducting layers are always arranged alternately.
10. Wafer for producing a multilevel converter system, preferably according to one of claims 1 to 5, in which P-conducting and N-conducting layers are always arranged alternately.