Pfc circuit with parallel step-up converters operated as master-slave and phase offset optimised by means of dynamic tjdn adjustment

Abstract

A circuit arrangement (1) for power factor correction comprises a control unit (100), a first strand (10), which is connected to a first control output (111) of the control unit (100), and at least one further strand (20, 30), which is connected to a further control output (121, 131) of the control unit (100). Each of the strands (10, 20, 30) contains a power factor correction member (12, 22, 32). Each of the power factor correction members (12, 22, 32) has a power input (14, 24, 34) and a power output (15, 25, 35). The power inputs (14, 24, 34) of the power factor correction members (12, 22, 32) are connected to a common power input (Pin). The power outputs (15, 25, 35) of the power factor correction members (12, 22, 32) are connected to a common power output (Pout). The control unit (100) is configured to output, via the control outputs (111, 121, 131), switching signals (S1, S2, S3) to the strands (10, 20, 30) in such a manner that, independently of the operation of the at least one further strand (20, 30), the first strand (10) is controlled as a master strand, and the at least one further strand (20, 30) is controlled as a slave strand depending on the operation of the first strand (10).

Description

[0001] PFC circuit with parallel boost converters operated as master-slave and phase shift optimized by dynamic TJDN adjustment

[0002] The invention relates to a circuit arrangement for power factor correction.

[0003] Power factor correction circuits (PFC for short) are used to increase a power factor that has been reduced by harmonics of the input current that arise in non-linear circuits, in order to thereby reduce the load on the power grid.

[0004] Such circuits are used, for example, in dimmable LED lights and, generally, in SMPS (switch-mode power supply) switching power supplies.

[0005] Power factor correction circuits, commonly referred to as power factor correction filters, are available as ASICs, for example.

[0006] It is therefore an object of the present invention to provide a circuit arrangement for power factor correction which can be easily adapted to a changed, in particular increased, power requirement.

[0007] The problem is solved by the subject matter of the independent claims. Further developments of the invention are specified in the subclaims. The subject matter of an independent claim can also be further developed by features of the subclaims of another independent claim.

[0008] The circuit arrangement according to the invention is used for power factor correction. It comprises a control unit, a first branch connected to a first control output of the control unit, and at least one further branch connected to a further control output of the control unit. Each of the branches contains a power factor correction element. Each of the power factor correction elements has a power input and a power output. The power inputs of the power factor correction elements are connected to a common power input. The power outputs of the power factor correction elements are connected to a common power output.The control unit is configured to output switching signals to the strands via the control outputs in such a way that the first strand is controlled as a master strand independently of the operation of the at least one further strand and the at least one further strand is controlled as a slave strand depending on the operation of the first strand.

[0009] Control as a slave line means that the operation of the corresponding line is not independent of the operation of the master line, but is influenced by it in some way, for example by setting a certain phase relationship to the operation of the master line or by setting a certain time period or amplitude depending on the time period or amplitude of the phase line.

[0010] Such a circuit arrangement, which is modularly constructed from two or more strands, can, for example, be easily adapted to a changed, in particular an increased, power requirement.

[0011] In an advantageous further development, the control unit is implemented as a microcontroller. This allows the control unit to be flexibly adapted to changing requirements, for example, by changing the firmware.

[0012] In an advantageous development, each phase further includes a DC-DC converter for converting the level of the respective switching signal output by the control unit to a level suitable for switching the respective power factor correction element. This allows, for example, the circuit arrangement to be flexibly adapted to different designs of power factor correction elements.

[0013] In an advantageous development, the power factor correction element contains a choke coil and a power diode, which are connected in series between a power input and a power output, and a switching element which is connected between a connection point between the choke coil and the power diode and ground. This makes it possible, for example, to achieve an output voltage which is higher than the input voltage. In an advantageous development, the power factor correction element further contains a measuring device for detecting a point in time at which a choke current flowing through the choke coil has decayed to almost zero, and for outputting a measuring signal at this point in time, wherein the measuring device is preferably designed to delay the output of the measuring signal until a voltage-free switching of the switching element in the respective power factor correction element occurs.Furthermore, the control unit can contain a trigger input for receiving the measurement signal from a phase and be configured to trigger the switching signal to the respective phase in response to the received measurement signal. This makes it possible, for example, to implement a transition mode in which a charging and discharging phase of the choke coil follow one another without a pause, with the switching element preferably being protected by the voltage-free switching.

[0014] In an advantageous development, the at least one slave branch further includes a phase detector for detecting a phase difference between the switching signal output to the master branch and the switching signal output to the slave branch, and for outputting a phase signal corresponding to the phase difference. Furthermore, the control unit can include a phase signal input for receiving the phase signal of the corresponding branch. This allows, for example, a control of the phase shift between the master branch and the slave branch to be implemented.

[0015] In an advantageous development, the circuit arrangement additionally contains one or more additional strands, wherein each of the additional strands contains a power factor correction element and is connected to an associated output of the control unit. The power inputs of the additional power factor correction elements are connected to the common power input. The power outputs of the additional power factor correction elements are connected to the common power output. The control unit is configured to control each of the additional strands as a slave strand. This allows, for example, the circuit arrangement to be flexibly adapted to increased power levels.In an advantageous development, the control unit is configured to output the switching signals of the slave lines with a time shift relative to the time profile of the switching signal of the master line, with a time shift that is an integer multiple of the period of the switching signal of the master line divided by the total number of lines. This allows, for example, a low ripple current to be achieved.

[0016] In an advantageous development, the control unit is configured to operate the master line and the at least one slave line in a transition mode. This allows, for example, symmetrical operation of the lines to be realized.

[0017] In an advantageous development, the control unit is configured to lengthen or shorten the duty cycle of the at least one slave branch depending on a detected phase shift relative to the duty cycle of the switching signal of the master branch. This allows, for example, an actuator for regulating the phase shift to be implemented.

[0018] In an advantageous development, the control unit is configured to operate the master branch in a transition mode and the at least one slave branch in a discontinuous mode. This allows, for example, an operation of the circuit arrangement to be realized that requires less circuitry than the transition mode.

[0019] In an advantageous development, the control unit is configured to shorten the duty cycle of the at least one slave phase compared to the duty cycle of the switching signal of the master phase. The control unit is preferably configured to adjust the duty cycle of the at least one slave phase such that the switching element in the respective power factor correction element is switched without voltage. This makes it possible, for example, to shorten the charging and discharging phases of the choke coil and thus to create a pause between them, with the switching element preferably being protected by the switching without voltage. The method according to the invention serves for power factor correction using a circuit arrangement according to the invention.The control unit outputs the switching signals to the strands in such a way that the first strand is controlled as the master strand independently of the operation of the at least one further strand, and the at least one further strand is controlled as the slave strand depending on the operation of the first strand. For example, the method according to the invention can achieve the same effects as the circuit arrangement according to the invention.

[0020] Further features and advantages of the invention will become apparent from the description of an embodiment with reference to the accompanying drawings.

[0021] Fig. 1 shows a block diagram of a circuit arrangement for power factor correction according to an embodiment of the present invention.

[0022] Fig. 2 shows a simplified schematic circuit diagram of a power factor correction element included in the circuit arrangement shown in Fig. 1.

[0023] Fig. 3 shows a timing diagram of signals when operating the circuit arrangement shown in Fig. 1 in a first operating mode.

[0024] Fig. 4 shows a diagram of the dependence of a period duration and an off duration of switching signals shown in Fig. 3 on time.

[0025] Fig. 5 shows a diagram of the dependence of a switching frequency of switching signals shown in Fig. 3 on time.

[0026] Fig. 6 shows a time diagram of a choke current with changed duty cycle.

[0027] Fig. 7 shows a block diagram of a functional block for setting a changed duty cycle as a function of a detected phase shift. Fig. 8 shows a timing diagram of signals when operating the circuit arrangement shown in Fig. 1 in a second operating mode.

[0028] In the following, a circuit arrangement according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0029] Fig. 1 shows a block diagram of a circuit arrangement 1. It contains an EMC mains filter 2 for damping the switching noise and a bridge rectifier 3 for full-wave rectification of the transformed alternating current.

[0030] For power factor correction, the circuit arrangement 1 comprises a first phase 10, a second phase 20, a third phase 30, and a control unit 100, which serves to control the three phases 10, 20, and 30. The control unit 100 can be implemented, for example, by a microcontroller whose functionality is defined by dedicated firmware.

[0031] The control unit 100 contains three functional blocks 110, 120, 130, each of which contains a control output 111, 121, 131 for outputting a control signal S1, S2, S3 to the respectively assigned strand 10, 20, 30.

[0032] The three strings 10, 20, 30 have a common power input Pin, whose input voltage Vin is the voltage output by the bridge rectifier 3, which consists of successive sine half-waves, and a common power output Pout, at which an output voltage Vout is output, which can be used, for example, to drive a load (not shown).

[0033] Each of the three lines 10, 20, 30 is essentially constructed identically and contains a DC-DC converter 11, 21, 31 and a power factor correction element 12, 22, 32. The control input 13, 23, 33 of each line is connected to the corresponding control output 111, 121, 131 of the control unit 100. The DC-DC converters can, for example, be designed as push-pull converters with a push-pull output stage.

[0034] Each power factor correction element 12, 22, 32 has a power input 14, 24, 34 and a power output 15, 25, 35. The power inputs 14, 24, 34 of the three strings 10, 20, 30 are connected to the common power input Pin. The power outputs 15, 25, 35 of the three strings 10, 20, 30 are connected to the common power output Pout.

[0035] The internal structure of each of the power factor correction elements 12, 22, 32 essentially corresponds to a boost converter. A simplified schematic diagram of such a power factor correction element is shown in Fig. 2.

[0036] The power factor correction circuit includes a choke coil L and a power diode D connected in series between the power input Pin and the power output Pout. Furthermore, the power factor correction circuit includes a switching element Q connected to ground GND from a connection node N between the choke coil L and the power diode D, and a charging capacitor C connected between the power output Pout and ground GND. In addition to or instead of the internal charging capacitors C, an external common charging capacitor Cg can also be connected between the common power output Pout and ground GND.

[0037] The switching element Q is designed to be electrically controllable, for example as a transistor that can be switched on or off by different levels of a control signal.

[0038] Optionally, the power factor correction element can further include a measuring device M for detecting a point in time at which an inductor current Id flowing through the inductor coil L has decayed to almost zero when the switching element Q is switched off. Such a measuring device can, for example, be designed to monitor a voltage induced in a secondary winding mounted on the inductor coil, or to monitor a voltage between the connection node N and ground GND or a voltage dropped across the switching element Q, which drops when the inductor current Id decays to almost zero.

[0039] The output signal of the measuring device M is fed via a measuring output 16, 26, 36 of the respective power factor correction element 12, 22, 32 as a measuring signal M1, M2, M3 to a trigger input 112, 122, 132 of the corresponding function block 110, 120, 130 of the control unit 100.

[0040] Optionally, the second branch 20 and the third branch 30 can each further contain a phase detector 29, 39 for detecting a phase shift between the switching signal S2, S3 output to the respective branch and the switching signal S1 output to the first branch 10. Such a phase detector can, for example, be in the form of a flip-flop that is set by a rise in the switching signal S1 and reset by a rise in the switching signal S2 or S3.

[0041] By averaging or low-pass filtering, an analog phase voltage Vph2, Vph3 can be obtained from the output signal of the flip-flop, which is fed to an ADC input 129, 139 of the control unit 100 and can be digitized by an analog-to-digital converter (not shown) contained in the control unit 100 and further processed by the control unit 100.

[0042] The control unit 100 is configured to output the switching signals S1, S2, S3 to the strings such that the first string 10 is controlled as the master string independently of the operation of the second and third strings 20, 30, and that the second and third strings 20, 30 are each controlled as slave strings depending on the operation of the first string 10. This can be accomplished in different ways.

[0043] A first operating mode of the circuit arrangement 1 is described below with reference to Fig. 3. In this mode, all phases 10, 20, 30 are operated in a transition mode in which the switching element Q contained in the power factor correction element 12, 22, 32 is periodically switched on and off. When the switching element Q is switched on, the connection node N is connected to ground, and an inductor current Id flowing through the inductor L increases continuously. After the switching element Q is switched off, the inductor L discharges the energy stored in it via the power diode D into the charging capacitor C, whereby the inductor current Id decreases continuously.

[0044] Transition mode means that a continuous transition occurs without a gap between the charging and discharging phases of the inductor L, i.e., between the phases with increasing inductor current Id and with decreasing inductor current Id. This is achieved, for example, by switching the switching element Q back on exactly when the current flowing through the inductor L has dropped almost to zero. Transition mode could also be achieved by switching the switching element back on earlier. However, such operation would be less efficient than waiting for the inductor to completely discharge.

[0045] To operate the master line 10 in transition mode, the control unit 100 outputs a switching signal S1 at the control output 110, which is, for example, at high level (e.g., a level of 3 V common for microcontrollers) for a predetermined duty cycle Ton and then drops back to low level (e.g., 0 V).

[0046] The switching signal S1 is converted by the DC-DC converter 11 to a level suitable for switching the switching element Q, for example, to a high level of 15 V, and fed to the power factor correction element 12. As a result, the switching element Q contained therein is switched on and off according to the switching signal S1.

[0047] The measuring device M contained in the power factor correction element detects the point in time at which the inductor current Id has decayed almost to zero with the switching element Q switched off and outputs the measurement signal M1 via the measurement output 16. The control unit 100 receives the measurement signal M1 via the trigger input 112 and, in response, sets the switching signal S1 back to the high level. This sequence is repeated periodically. After the inductor current Id has decayed almost to zero, an oscillation process occurs at the output of the switching element Q. This oscillation process depends on parasitic elements of the circuit, such as an output capacitance of the switching element Q implemented as a transistor and parasitic inductances of the lines. If the transistor remained switched off, the voltage drop across it would periodically oscillate between a minimum value, ideally zero or almost zero, and a maximum value.

[0048] To switch the switching element Q, it is preferable to wait until the voltage has dropped to zero or its minimum value. Switching at this point is referred to in technical terms as zero-voltage switching (ZVS). Zero-voltage switching is low-loss because the product of current and voltage becomes zero during switching.

[0049] Quasi-resonant switching is a special form of low-loss switching. The components L, D, and Q in Fig. 2 actually exhibit parasitic capacitances. The inductance L and the parasitic capacitances result in a resonance, which, after L is demagnetized, leads to a ringing of the switching node. In quasi-resonant switching, the instant at which the voltage across Q reaches a minimum is used to switch Q back on. If the condition Vout > 2xVin is met, the ringing of the switching node described above allows the voltage across Q to fall to zero. At these operating points, the ZVS is fully achieved.

[0050] The measuring device M is therefore preferably designed to delay the output of the measuring signal M1 to such an extent that the switching signal S1 output by the control unit 100 in response to the reception of the measuring signal M1 causes the switching element Q to be switched on without voltage.

[0051] A switching cycle T = Ton + Toff is thus determined from the specified on-time Ton and an off-time Toff, which is determined by the discharge time of the inductor L. This, in turn, is determined from an instantaneous value of the input voltage Vin and the essentially constant output voltage Vout. Approximately: Toff = Ton * Vin / (Vout - Vin)

[0052] The time periods are selected such that a resulting switching frequency fs is significantly higher than a mains frequency fn of the rectified mains voltage, for example fs = 10 kHz or more (period T = 100 ps or less) at a mains frequency of 50 Hz. Thus, one sine half-wave of the rectified mains voltage (duration 10 ms) requires 100 or more switching operations.

[0053] As can be seen from Fig. 3, in the present operating mode, the slave lines 20, 30 are operated in the same way as the master line 10. However, the signal profile of the switching signal S2 is shifted by a time shift AT2 relative to the switching signal S1, and the signal profile of the switching signal S3 is shifted by a time shift AT3. The time shifts are AT2 = 1 / 3*T and AT3 = 2 / 3*T. The same time shifts apply to the inductor current Id2, Id3 of the slave lines 20, 30 relative to the inductor current Id1 of the master line 10.

[0054] As described above, the off-time Toff, and thus the period T and the switching frequency fs, depends on the instantaneous value of the input voltage Vin and the output voltage Vout.

[0055] Fig. 4 shows an example of the dependence of the off-duty time Toff and the period T on time for a constant on-duty time Ton. Fig. 5 shows an example of the dependence of the switching frequency fs on time. The example is based on the following values:

[0056] • Mains voltage Vac = 230 Vac / 50 Hz

[0057] • Input power = 160 W

[0058] • Output voltage Vout = 400 Vdc

[0059] • Choke inductance L = 760 mH

[0060] • Duty cycle Ton = 4.6 ps. At an input voltage Vin of zero, the off-time Toff is also zero; at the peak value of the input voltage Vin (after 5 ms), it rises to approximately 20 ps. The period T therefore fluctuates between approximately 5 ps and 25 ps, and the switching frequency fs accordingly fluctuates between approximately 200 kHz and 40 kHz.

[0061] Since the period T of the switching signals S1, S2, and S3 is constantly changing, the time intervals AT2 and AT3 between them cannot be fixed, but must be adjusted dynamically. This is done automatically via a control system using the phase detectors 29 and 39.

[0062] Fig. 3 shows phase signals PH2, PH3 generated internally in the phase detectors 29, 39 prior to low-pass filtering. If the off-duty toff is increased during the transition of the input voltage Vin from zero to the peak, thereby increasing the period T, and if the time shift AT1, AT2 remains unchanged, the mean values ​​of the phase signals PH1, PH2 and thus the phase voltages Vph2, Vph3 obtained by low-pass filtering would decrease, which is detected by the control unit 100. In order to shift the switch-on times of the switching signals S2, S3 backward, the control unit 100 increases the switch-on duration Ton of the switching signals S2, S3 by a switch-on difference value ATon.

[0063] As shown in Fig. 6, this also delays the next re-switching on of the respective switching element S by a switch-off difference value AToff, for which approximately:

[0064] AToff = ATon * Vin / (Vout - Vin)

[0065] As a result, the time shifts AT2, AT3 of the switching signals S2, S3 are increased compared to the switching signal S1, whereby the deviations from the target sequence are reduced.

[0066] If the period T decreases during the transition from the peak to the zero crossing of Vin, the switch-on differential value ATon receives a negative sign, and the switch-on duration Ton is shortened accordingly. Fig. 7 shows a block diagram of a function block 190 for setting a changed switch-on duration ATon depending on a detected phase shift. The function block is preferably contained in the control unit 100 and, for example, is implemented by the firmware used when the control unit 100 is designed as a microprocessor.

[0067] In a comparison block 191, the phase voltage Vph (converted to a digital value) is compared with a reference voltage Vcomp. Depending on the comparison result, the switch-on differential value ATon is set in a setting block. If the switch-on differential value ATon reaches a specified maximum value, it is not further increased even if the control deviation Vph - Vcomp increases, but remains fixed at its maximum value.

[0068] To comply with the harmonic limits for the mains input current defined in standard EN61000-3-2, the maximum value for the duty cycle ATon must be significantly smaller than the duty cycle Ton. In the example described above with reference to Figures 3 and 4, the maximum value for ATon was set to 0.9% of Ton.

[0069] Even if the slave lines 20, 30 are in principle operated just as independently as the master line 10, the operation of the slave lines 20, 30 is dependent on the master line 10 in that their phase relationship to the master line 10 is set by the control described above.

[0070] A second operating mode of the circuit arrangement 1 is described below with reference to Fig. 8. Here, too, the master branch 10 is controlled by the control unit 100, as described above, so that it operates in transition mode. In contrast, the slave branches 20, 30 are controlled so that they operate in discontinuous mode.

[0071] In discontinuous mode, the switching element Q contained in the power factor correction element 22, 32 is also periodically switched on and off. Unlike in transition mode, however, the charging phase with increasing inductor current Id does not immediately follow the discharging phase with decreasing inductor current Id, but only after a time gap with a pause duration Tp.

[0072] This is achieved, for example, by making the duty cycle Ton of the slave strings 20, 30 smaller than the duty cycle Ton of the master string 10. Preferably, the duty cycle Ton of the slave strings 20, 30 is made 5 to 30% smaller than the duty cycle Ton of the master string 10. As can be seen from Fig. 8, the inductor current Id in the slave strings 20, 30 therefore only increases to a smaller peak value than in the master string 10. This results in a shorter discharge time for the inductor L.

[0073] On the other hand, the period T remains the same for all three phases 10, 20, and 30. Therefore, in the slave phases 20 and 30, the discharge period of the choke coil L is followed by a pause until the switching element Q is switched on again, during which the choke current Id remains at zero, except for minor oscillations.

[0074] In this operating mode, the times of reactivation do not result from the operation of the slave lines 20, 30 themselves, but are specified centrally by the control unit 100 depending on the timing of the master line 10 in such a way that they are shifted in time by T / 3 in each of the three lines 10, 20, 30.

[0075] The slave strings orient themselves towards the master string for the period T and, depending on the operating mode, are either also operated in transition mode or preferably in discontinuous mode, whereby the switch-on times Ton are shorter than in the master string. By avoiding real free-running operation of the slave strings, the phenomenon of self-synchronization and phase alignment of several neighboring free-running systems is prevented. Quasi-resonant, low-loss operation is achieved for the slave strings by selecting the shortening of the Ton times so that their restart times coincide with a voltage minimum at the switching element. Here, too, complete ZVS is achieved when Vout > 2xVin is met. As explained above in the description of the transition mode, an oscillation process occurs at the output of the switching element Q after the inductor current Id has decayed to almost zero. Fig.8 shows as an example the voltage Vq2 dropped across the switching element Q of the second phase 20.

[0076] Since the switch-on times of the switching elements Q of the three power factor correction elements 12, 22, 32 are fixedly specified by the control unit 100 in the discontinuous mode, a voltage-free switching of the slave strings 20, 30 is realized in this case by a suitable setting of the shortened switch-on times Ton.

[0077] Unlike in transition mode, where the switching element Q is turned on when the first minimum is reached, in discontinuous mode, as shown in Fig. 8 using the example of Vq2, the switching element Q waits until the second minimum is reached. Theoretically, it would also be possible to wait until the third or a later minimum is reached. However, this would further reduce the efficiency of the circuit.

[0078] The period of the oscillation at the switching element Q depends on the parasitic elements of the three power factor correction elements 12, 22, 32 and is therefore independent of the switching frequency fs currently in use. It can be determined, for example, by measurement. Depending on this, the duty cycles Ton of the slave phases 20, 30 can be adjusted by the control unit 100 depending on the instantaneous switching frequency fs such that the voltage drop Vq across the switching element Q reaches its second minimum one period after the switching element Q is switched on, resulting in a voltage-free switching of the switching element Q.

[0079] The resulting pause duration Tp is approximately between 10 and 30% of the period duration T.

[0080] This circuit diagram can be explained using a calculation example. As explained above, Ton and Toff denote the on and off times of the master phase. The inductor current is indicated in Figure 8 as Id1; it is clearly visible that there is no gap. During the time Ton, the inductor is magnetized and demagnetized during the time Toff. This is followed without a pause by the next magnetization. Looking at the inductor currents Id2 and Id3 in Figure 8, it is clearly visible that the magnetization time, which will be referred to as Ton_s from now on, is shorter. This also leads to a shorter demagnetization time, since the peak current, also clearly visible in the diagram in Figure 8, is lower. This creates a gap Tp in which the switching element is also switched off.The voltage curve Vq2 in Figure 8, which shows the voltage across the switching element of the slave line with the corresponding inductor current Id2, clearly shows that an oscillation occurs after the inductor has been completely demagnetized. The switching element Q must now be controlled in such a way that the switch-on time falls within a voltage minimum to enable low-loss switching.

[0081] The required duty cycle of the switching element Q of the slave line can be calculated as follows:

[0082] Where Vout is the supply voltage of the strings, i.e., the output voltage of the power factor correction element 22, 32, and the voltage Vin is the input voltage of the power factor correction element 22, 32. Tskip is the time period between two minima of the voltage Vq across the switching element Q and is thus approximately 1.5 times shorter than the time period Tp from Fig. 8. Tskip can be calculated from the Thomson oscillation equation (https: / / de.wikipedia.org / wiki / Thomsonsche_Schwingungsgleichung), where L is the transformer inductance L, and C is the sum of the capacitances at the switching node. The control unit 100 calculates the individual duty cycles Ton_s for the slave strings 20, 30 accordingly. Alternatively, the values ​​can of course also be specified in tabular form or in the form of a characteristic map, and the corresponding values ​​can be read out according to the boundary conditions.This has the advantage that the control unit 100 requires less computing power, and parasitic effects that are difficult to capture in formulas can be incorporated into the tables or characteristic maps. A correspondingly controlled switching element Q thus switches on at a minimum voltage, enabling quasi-resonant, low-loss switching.

[0083] The circuit arrangement described above and its various operating modes can achieve the following effects:

[0084] The modular design of three power lines and a common control unit allows for considerable flexibility, covering a wide power range. Implementing the control unit with a microcontroller and dedicated firmware increases flexibility compared to the previously used ASICs, which were previously only available for transition mode and could control a maximum of two power lines.

[0085] Splitting the power across three branches allows for the use of smaller components, resulting in weight and cost savings. The uniform phase shift between the three branches ensures that the resulting total current has the lowest possible ripple component.

[0086] When operating in transition mode, the phase shift control can also prevent self-synchronization of the strings that might otherwise occur due to coupling between the strings.

[0087] Since the switch-on times of the Q switching elements in discontinuous mode are fixed by the control unit, neither the measuring devices contained in the power factor correction elements nor the phase detectors are required in the slave lines. This simplifies the circuit design.

[0088] Furthermore, when operating in discontinuous mode, no external triggering of the slave strings is required. By eliminating the need for a retrigger circuit for each slave string, the circuit arrangement can be further simplified. The circuit arrangement is not limited to the example with three strings shown above. Instead, it can also contain just two strings: a master string and a slave string. Alternatively, it can also contain four or more strings. The phase shift ΔT / ΔT between the switching signals of the individual strings is then selected as an integer multiple of 1 Zn instead of an integer multiple of 1 / 3, where n is the total number of strings.

[0089] This makes the circuit arrangement scalable and easy to adapt to higher power levels. The even distribution of the switching signals also allows for low ripple current.

[0090] REFERENCE SYMBOL LIST

[0091] Circuit arrangement 1 EMC line filter 2

[0092] Bridge rectifier 3 master strings 10 slave strings 20, 30

[0093] DC-DC converter II, 21, 31 Power factor correction element 12, 22, 32 Control input 13, 23, 33 Power input 14, 24, 34 Power output 15, 25, 35 Measuring output 16, 26, 36

[0094] Phase detector 29, 39 Control unit 100 Function block 110, 120, 130 Control output III, 121, 131 Trigger input 112, 122, 132 ADC input 125, 135

[0095] Function block 190 Comparison block 191 Setting block 192

[0096] Charging capacitor C common charging capacitor Cg

[0097] Power diode D

[0098] Mains frequency fn

[0099] Switching frequency fs

[0100] Ground GND

[0101] Inductor current Id

[0102] Choke coil L

[0103] Measuring device M

[0104] Measuring signal M1, M2, M3

[0105] Connection node N common power input Pin common power output Pout

[0106] Switching element Q

[0107] Switching signal S1, S2, S3

[0108] Phase signal PH2, PH3

[0109] Period T

[0110] Off time Toff

[0111] Sound on time

[0112] Duty cycle of a slave line Ton_s

[0113] Pause duration Tp

[0114] Pause duration between two voltage minima Tskip

[0115] AC mains voltage Vac

[0116] Reference voltage Vcomp

[0117] Input voltage Vin

[0118] Output voltage Vout

[0119] Phase voltage Vph2, Vph3 voltage drop across the switching element Vq

[0120] Time difference AT2, AT3

[0121] Switch-on difference value ATon

[0122] Switch-off difference value Atoff

Claims

PATENT CLAIMS Circuit arrangement (1) for power factor correction, comprising: a control unit (100), a first branch (10) which is connected to a first control output (111) of the control unit (100), and at least one further branch (20, 30) which is connected to a further control output (121, 131) of the control unit (100), wherein each of the branches (10, 20, 30) contains a power factor correction element (12, 22, 32), each of the power factor correction elements (12, 22, 32) has a power input (14, 24, 34) and a power output (15, 25, 35), the power inputs (14, 24, 34) of the power factor correction elements (12, 22, 32) are connected to a common power input (pin), the power outputs (15, 25, 35) of the power factor correction elements (12, 22, 32) are connected to a common power output (Pout), the control unit (100) is configured to output switching signals (S1, S2, S3) to the strands (10, 20, 30) via the control outputs (111, 121, 131) in such a way that the first strand (10) is controlled as a master strand independently of the operation of the at least one further strand (20, 30) and the at least one further strand (20, 30) is controlled as a slave strand depending on the operation of the first strand (10), characterized in that the control unit (100) is configured to operate the master strand (10) in a transition mode and to operate the at least one slave strand (20, 30) either in a transition mode or in a discontinuous mode, and the duty cycle (Ton) of the at least one slave strand (20, 30) compared to the duty cycle (Ton) of the master line (10), wherein the control unit (100) is preferably configured toto set the duty cycle (Ton_s) of the at least one slave branch (20, 30) such that a voltage-free, quasi-resonant, low-loss switching of the switching element (Q) in the respective power factor correction element (22, 32), wherein the duty cycle (Ton_s) of the at least one slave branch (20, 30) is shorter than the duty cycle (Ton) of the master branch (10).

2. Circuit arrangement (1) according to claim 1, wherein the control unit (100) is formed as a microcontroller.

3. Circuit arrangement (1) according to claim 1 or 2, wherein each branch (10, 20, 30) further includes a DC-DC converter (11, 21, 31) for converting the level of the respective switching signal (S1, S2, S3) output by the control unit (100) to a level suitable for switching the respective power factor correction element (12, 22, 32).

4. Circuit arrangement (1) according to one of claims 1 to 3, wherein the power factor correction element (12, 22, 32) contains: a choke coil (L) and a power diode (D) connected in series between the power input (Pin) and the power output (Pout), and a switching element (Q) connected between a connection point (N) between the choke coil (L) and the power diode (D) and ground (GND).

5. Circuit arrangement (1) according to claim 4, wherein the power factor correction element (12, 22, 32) further contains a measuring device (M) for detecting a point in time at which a choke current (Id) flowing through the choke coil (L) has decayed almost to zero, and for outputting a measuring signal (M1, M2, M3), wherein the measuring device (M) is preferably designed to delay the output of the measuring signal (M1, M2, M3) to such an extent that a voltage-free switching of the switching element (Q) in the respective power factor correction element (12, 22, 32) takes place.

6. Circuit arrangement (1 ) according to claim 5, wherein the control unit (100) further includes a trigger input (112, 122, 132) for receiving the measurement signal (M1, M2, M3) of a strand (10, 20, 30) and the control unit (100) is configured to trigger the switching signal (S1, S2, S3) to the respective strand (10, 20, 30) in response to the received measurement signal (M1, M2, M3).

7. Circuit arrangement (1) according to one of claims 1 to 6, wherein the at least one slave branch (20, 30) further includes a phase detector (29, 39) for detecting a phase difference (AT2 / T, AT3 / T) between the switching signal (S1) output to the master branch (10) and the switching signal (S2, S3) output to the slave branch (20, 30) and for outputting a phase signal (Vph2, Vph3) corresponding to the phase difference.

8. Circuit arrangement (1) according to claim 7, wherein the control unit further includes a phase signal input (125, 135) for receiving the phase signal (Vph2, Vph3) of the slave branch (20, 30).

9. Circuit arrangement (1) according to one of claims 1 to 8, which further additionally contains one or more further strands, wherein each of the further strands contains a power factor correction element and is connected to a control output of the control unit assigned to it, the power inputs of the further power factor correction elements are connected to the common power input (Pin), the power outputs of the further power factor correction elements are connected to the common power output (Pout), and the control unit (100) is set up to control each of the further strands as a slave strand.

10. Circuit arrangement (1) according to one of claims 1 to 9, wherein the control unit (100) is configured to output the switching signals (S2, S3) of the slave strands (20, 30) in each case with a time shift relative to a time profile of the switching signal (S1) of the master strand (10) with a time shift (AT2, AT3) which is an integer multiple of the period duration (T) of the switching signal of the master strand (10) divided by the total number of strands. Circuit arrangement (1) according to one of claims 1 to 10, wherein the control unit (100) is configured to lengthen or shorten the duty cycle (Ton) of the at least one slave branch (20, 30) as a function of a detected phase shift (AT2 / T, AT3 / T) compared to the duty cycle (Ton) of the master branch. Circuit arrangement according to one of claims 1 to 11, characterized in that the period of the oscillation at the switching element (Q) depends on the parasitic elements of the power factor correction elements (12, 22, 32) and is thus independent of the switching frequency (fs) currently being used.Method for power factor correction using a circuit arrangement (1) according to one of claims 1 to 12, wherein the control unit (100) outputs the switching signals (S1, S2, S3) to the strands (10, 20, 30) in such a way that the first strand (10) is controlled as a master strand independently of the operation of the at least one further strand (20, 30) and the at least one further strand (20, 30) is controlled as a slave strand depending on the operation of the first strand (10).

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