Integrated electronic device and corresponding production method

Abstract

The invention relates to an integrated electronic device (1) comprising at least one component produced on a carrier structure (2) comprising a semiconductor substrate, and an interconnection track (8) that runs over the carrier structure from the component to a lateral face (9) of the device, the interconnection track comprising a layer of oxidizable material (12) bearing a continuous layer of conductive material (13), wherein the layer of oxidizable material is discontinuous. The invention also relates to a method for producing such a device.

Description

Integrated electronic device and corresponding manufacturing method

[0001] The present invention relates to the technical field of integrated circuits and in particular integrated circuits comprising one or more components connected to interconnection tracks. The invention finds an advantageous application in the field of integrated circuits which are made from group III-V semiconductor materials.

[0002] The invention relates in particular to an integrated electronic device as well as a method of manufacturing such a device. Technological background

[0003] In the field of integrated circuits, for example but not limited to integrated circuits operating at microwave frequencies, or MMIC (Monolithic Microwave Integrated Circuit, according to the usual English acronym), it is known to protect the components produced on the substrate by enclosing them in a polymer material.

[0004] The input and output signals emitted or received by these components pass through interconnection tracks which extend parallel to the substrate from the components to a side face of the integrated circuit (or edge), at the level of the component's cutting lines ("dicing street", according to the English term used by those skilled in the art). At this location, the interconnection tracks are therefore exposed to the external environment of the component and are likely to undergo oxidation due to humidity.

[0005] In particular, it has been observed that oxidation that originates at the component cutting line can migrate along the interconnection track, possibly to the component. This migration of oxidation is particularly favored by the electric field generated by the signal circulating on the track, and has been particularly observed on the interconnection tracks of transistor drains of the last amplification stages of MMIC components.

[0006] This oxidation leads to delamination of the interconnection track and, if it reaches the component, a modification of the semiconductor surface under the passivation layer at the interface with the interconnection track, thus generating electronic traps which are the cause of a drop in current density in the component. The performance of the component is strongly affected.

[0007] In order to overcome the above-mentioned drawback, a means is proposed to prevent the propagation of oxidation along the interconnection track to the active area of ​​the component.

[0008] According to one aspect of the invention, there is provided an integrated electronic device comprising at least one component produced on a carrier structure comprising a semiconductor substrate, and an interconnection track which extends on the carrier structure from the component to a lateral face of the device, the interconnection track comprising a layer of oxidizable material supporting a continuous layer of conductive material, in which the layer of oxidizable material is discontinuous.

[0009] An interconnection track in which the oxidizable part has a discontinuity advantageously makes it possible to stop oxidation appearing on the side face and which would spread towards the component.

[0010] According to one embodiment, the device comprises a blocking structure which is interposed between the carrier structure and a portion of the interconnection track, which extends transversely (to the interconnection track) from one edge to the other of the interconnection track and which has an upper face opposite the carrier structure, the layer of oxidizable material comprising a first portion which extends on the upper face and at least a second portion which extends upstream or downstream of the blocking structure along the interconnection track, the second portion not having continuity of material with the first portion.

[0011] The presence of a blocking structure interposed between the carrier structure and the interconnection track is a simple way to achieve discontinuity in the oxidizable layer of the interconnection track. In addition, this solution is compatible with conventional interconnection track manufacturing processes.

[0012] According to one embodiment, the second portion extends partly between the supporting structure and the first portion; in other words, the first portion extends above the second portion.

[0013] According to one embodiment, the blocking structure has a lower face in contact with the supporting structure, the lower face having a dimension along the interconnection track (i.e. taken in a plane orthogonal to the substrate and parallel to the direction of extension of the interconnection track) less than or equal to the dimension of the upper face along the interconnection track.

[0014] According to one embodiment, the blocking structure has a trapezoidal section with a plane which is parallel to the direction of extension of the interconnection track and orthogonal to the substrate.

[0015] According to one embodiment, the blocking structure comprises (or is made of) a dielectric material or a polymer.

[0016] According to one embodiment, the blocking structure has a thickness less than that of the layer of conductive material. Preferably, if the method for producing the layer of conductive material comprises producing a sub-layer of conductive material (or bonding layer), then the blocking structure has a thickness less than that of the sub-layer of conductive material.

[0017] According to one embodiment, the blocking structure is made at a distance greater than 200 micrometers from any component located along the interconnection track.

[0018] The component is made with group III-V materials. For example, the integrated circuit may have an active layer, comprising the component, and made by epitaxy of group III-V materials.

[0019] The component may be an active component, for example a high electron mobility transistor.

[0020] According to another aspect, there is provided a method for manufacturing an integrated electronic device comprising at least one component on a carrier structure which comprises a semiconductor substrate, the method comprising - a step of producing, on the carrier structure, a blocking structure which has an upper face opposite the carrier structure, - a step of producing an interconnection track which extends from the component to a lateral face of the device, comprising: - a sub-step of producing a layer of oxidizable material comprising a first portion which extends on the upper face, and at least a second portion which extends upstream or downstream of the blocking structure along the interconnection track, so that the first portion does not have material continuity with the second portion, - a sub-step of producing a continuous layer of conductive material on the layer of oxidizable material,so as to form an interconnection track comprising the layer of oxidizable material and the layer of conductive material.,

[0021] Of course, the various features, variants and embodiments of the invention may be combined with each other in various combinations to the extent that they are not incompatible or mutually exclusive. Brief description of the figures

[0022] In addition, various other characteristics of the invention emerge from the appended description given with reference to the drawings which illustrate non-limiting embodiments of the invention and where:

[0023] is a top view of a device according to one embodiment of the invention,

[0024] is a sectional view of the device of the,

[0025] illustrates a first step of a method of manufacturing a device according to the invention,

[0026] is a second step of a method of manufacturing a device according to the invention,

[0027] is a third step of a method of manufacturing a device according to the invention,

[0028] is a fourth step of a method of manufacturing a device according to the invention,

[0029] illustrates an alternative embodiment of the device according to the invention.

[0030] It should be noted that in these figures the structural and / or functional elements common to the different variants may have the same references. Detailed description

[0031] It goes without saying that integrated circuits can be oriented in different ways, in particular depending on the way in which they are integrated into electronic devices, the latter not always having a determined orientation (or reference orientation). Nevertheless, for the purpose of simplifying the disclosure, the reference orientation will be that which is conventionally used in reference works and in most patent documents, i.e. the carrier substrate will be considered to be at the bottom and the face of the substrate from which the various layers and components of the integrated circuit are made, conventionally called the "front face", will be considered to be the upper face of the substrate. Thus, relative terms such as "above", "below", "on", "under", "lateral", "lower" and "upper" must be interpreted in accordance with this reference orientation.This orientation coincides with the orientation of Figures 2 to 7 of the present application.

[0032] This is a schematic top view of an integrated electronic device 1, here a monolithic microwave integrated circuit (MMIC), which in this example is a high-power amplifier. The integrated electronic device 1 is for example made with group III-V semiconductor materials.

[0033] The integrated circuit 1 comprises a carrier structure 2 on which components and interconnection tracks are produced, and a protective layer, here made of dielectric material, produced on the carrier structure 2 so as to encompass the components and the interconnection tracks. In order to improve the intelligibility of the figures, the integrated circuit 1 is shown here without its protective layer.

[0034] The carrier structure 2 here comprises a carrier substrate, for example made of silicon carbide SiC, sapphire, silicon Si or gallium nitride GaN, on which there is a heterojunction formed by a first layer of a high bandgap material, for example gallium nitride GaN, and a second layer of a higher bandgap material, for example aluminum-gallium nitride AlGaN. A nucleation layer, or buffer layer, comprising for example gallium nitride, is present between the carrier substrate and the first layer and makes it possible to ensure the mesh adaptation for the growth of the heterojunction on the carrier substrate. For the purposes of simplification, these layers will not be shown in the figures.

[0035] On the supporting structure 2 are made components, here transistors, and in particular here high electron mobility transistors (HEMT, for "High Electron Mobility Transistors", according to the usual Anglo-Saxon acronym). These transistors belong here to two stages 3, 4 of radiofrequency power amplification.

[0036] The device 1 further comprises interconnection tracks which extend from lateral faces of the device 1 and which are electrically connected to the electrodes of the transistors of the two stages 3 and 4. For the purposes of the invention, the lateral faces of the device 1 are understood as the faces which are orthogonal to the front face of the substrate and correspond to the cutting lines of the device 1 prior to its individualization.

[0037] Here, a first interconnection track 6 extends from a first lateral face 7 of the device 1 towards the components so as to contact gate lines of the transistors of the two stages 3 and 4. The first interconnection track 6 forms, at the level of the first lateral face 7, an input electrode for the device 1.

[0038] A second interconnection track 8 extends from a second lateral face 9 of the device 1 towards the components so as to contact the drains of the transistors of the two stages 3 and 4. The second interconnection track 6 forms, at the level of the second lateral face 9, an output electrode for the device 1.

[0039] A third interconnection track connects the sources of the transistors of the two stages to ground and connects, for example, the different sources by an air-bridge architecture or a benzocycobutene bridge architecture, or BCB bridge. For example, the device 1 here is of the microstrip type and the ground plane is made at the rear face of the substrate (or lower face, opposite the front face). The bridges (air or BCB) are connected to the ground plane by through-hole vias.

[0040] Various passive components 5 make it possible in particular to carry out impedance adaptations on the interconnection tracks 6 and 8.

[0041] The interconnection tracks 6 and 8, respectively at the level of the lateral faces 7 and 9, are here exposed to the environment external to the device 1, in particular to humidity, and are therefore likely to oxidize. This risk is particularly significant for the second interconnection track 8 which here forms the output terminal of the high-power amplifier. The current density which circulates there is particularly high and the electromagnetic field generated promotes the migration of the oxidation along the second interconnection track 8 towards the second stage 4 of transistors.

[0042] The device 1 comprises, near the second lateral face 9, a blocking structure 11 which makes it possible to prevent the migration of oxidation along the second interconnection track 8. Preferably, the blocking structure 11 is located at a distance from the passive components 5 greater than 200 micrometers.

[0043] Here, the blocking structure 11 is interposed between the supporting structure 2 and the second interconnection track 8. It extends here transversely to the second interconnection track 8, from one edge to the other of the second interconnection track 8 and in particular here beyond the edges of the second interconnection track 8.

[0044] This blocking structure 11 is better visible in which is a sectional view of the electronic device 1 along section line II of the.

[0045] The blocking structure 11 has a first face 14, or lower face, which is in contact with the supporting structure 2, and a second face 15, or upper face, which is opposite the first face and the supporting structure 2. The dimension of the first face 14 along the interconnection track (i.e. taken parallel to the upper face of the supporting structure and in a plane parallel to the direction of extension of the interconnection track, here a plane parallel to the section plane II) is less than or equal to the dimension of the second face 15 along the interconnection track (i.e. taken in this same plane). The section of the supporting structure 2 (here again, in a plane parallel to the section plane II) is called “cap” (according to the usual denomination).

[0046] In particular here, the section of the supporting structure 2 in a plane parallel to the cutting plane II) is trapezoidal in shape. A first base of the trapezoid formed by this section belongs to the first face 14 and a second base of the trapezoid belongs to the second face 15. The length of the first base is less than the length of the second base and in this example, the trapezoid is an isosceles trapezoid.

[0047] The blocking structure 11 is made here from a dielectric material.

[0048] The second interconnection track 8 comprises at least two layers, including a layer of oxidizable material 12 and a layer of conductive material 13. The layer of oxidizable material 12 is here a support layer, or adhesion layer, which supports the layer of conductive material 13 and which allows better adhesion of the layer of conductive material 13 to the supporting structure 2.

[0049] Here, the layer of oxidizable material 12 is a layer of a titanium-based alloy, here an alloy of titanium and tungsten, and is produced directly on the supporting structure 2. The layer of conductive material 13 is here a layer of gold.

[0050] The thickness of the blocking structure 11 (distance between the first face 14 and the second face 15) is here greater than the thickness of the layer of oxidizable material 12 and much less than the thickness of the layer of conductive material 13. The blocking structure 11 has for example a thickness of between 60 nanometers and 80 nanometers, the thickness of the layer of oxidizable material 12 has for example a thickness of between 20 and 30 nanometers and the layer of conductive material 13 has for example a thickness equal to or greater than 1 micrometer (or even equal to or greater than 5 micrometers).

[0051] The layer of oxidizable material 12 is discontinuous; the layer of oxidizable material 12 here has three portions. A first portion 16 is located on the second face 15 of the blocking structure, a second portion 17 and a third portion 18 are located on the supporting structure 2, respectively upstream and downstream along the interconnection track (relative to the direction of propagation of the signal).

[0052] As indicated previously, the second face 15 has a dimension along the interconnection track (i.e. here in a plane parallel to the section plane II) greater than the dimension of the first face 14 along the interconnection track. Thus, the first portion 16 extends partly above the second portion 17 and partly above the third portion 18. In other words, the first portion 16 extends at a distance from the supporting structure 2 and a portion of the second portion 17 as well as a portion of the second portion 18 are interposed (without direct contact) between the first portion 16 and the substrate. More precisely, end portions of the second and third portions 17, 18 extend between the supporting structure 2 and end portions of the first portion 16.

[0053] Given the difference in thickness between the supporting structure 11 and the layer of oxidizable material 12, the first portion 16 is not continuous with the second and third portions 17 and 18 (which themselves are not mutually continuous because they are separated by the blocking structure 11).

[0054] On the other hand, the continuity of the layer of conductive material 13 is not affected by the presence of the blocking structure 11 since the thickness of the layer of conductive material 13 is greater than the thickness of the blocking structure 11.

[0055] The blocking structure 11 therefore advantageously makes it possible to break the continuity of the layer of oxidizable material 12 without breaking that of the layer of conductive material 13. The electrical connection is therefore ensured up to the components. Furthermore, the blocking structure 11 does not affect the mechanical integrity of the second interconnection track since the layer of conductive material 13 is well supported by the track of oxidizable material 12 over its entire length.

[0056] Figures 3 to 6 illustrate different steps of a method of manufacturing an integrated device according to the invention, for example the device illustrated in Figures 1 and 2.

[0057] During a first step in manufacturing a device according to the invention (), the blocking structure 11 is produced on the supporting structure 2, for example by depositing a layer of dielectric material on the supporting structure 11, in particular resin, then the blocking structure 11 is delimited in the resin layer by photolithography and dipping. The technique for producing the so-called “cap” section, in particular trapezoidal, of the blocking structure 11 will not be described in more detail here since it is conventional and known per se. It is notably used in metal deposition processes by removing layers (or “lift-off” processes, according to the usual English term).

[0058] A second step of the process involves the production of the interconnection tracks.

[0059] A first sub-step () of producing the interconnection tracks comprises the deposition of a layer of oxidizable material 12' by spraying onto the supporting structure 2 and onto the blocking structure 11.

[0060] A second sub-step () comprises a part of the production of the layer of conductive material 13, and comprises the deposition of a first sub-layer of conductive material 13', here gold, by sputtering on the layer of oxidizable material. A third sub-step () comprises another part of the production of the layer of conductive material 13 and comprises an electrolytic growth of a second sub-layer 13'' of the conductive material, here gold, on the layer of oxidizable material 12'. The production of the first sub-layer 13' by sputtering allows a homogeneous growth of the second sub-layer 13'' and thus improves the adhesion of the conductive material on the layer 12' of oxidizable material. In this example, the first sub-layer 13' has a thickness of 100 nanometers and the second sub-layer 13'' has a thickness of 6 micrometers.

[0061] In a fourth sub-step (not shown), the conductive tracks of device 1, in particular tracks 6 and 7, are delimited (or defined) in these three layers by photolithography and dipping.

[0062] The second interconnection track 8 is thus produced by conventional methods, but advantageously includes a discontinuity in the layer of oxidizable material 12 induced by the presence of the blocking structure 11.

[0063] The invention is not limited to the embodiments described previously in connection with Figures 1 and 2. In particular, although a trapezoidal section locking structure has been described, other shapes are conceivable, for example a T shape, or an inverted podium shape, as illustrated in the, in which the locking structure 11 comprises a first portion 19 in the shape of a rectangular parallelepiped in contact with the substrate and a second portion in the shape of a rectangular parallelepiped 20 which is produced on the first parallelepiped portion 19 and which has a dimension along the interconnection track greater than the dimension of the first parallelepiped portion 19 along the interconnection track.Such a profile is for example obtained from a two-layer resin of which each of the sub-layers has a different revelation speed (in this case, a higher revelation speed for the layer in contact with the supporting structure 2).

[0064] More generally, the invention is compatible with any blocking structure having a profile (i.e. a section in a plane parallel to the section plane II of the) in the form of a cap.

[0065] Furthermore, the invention finds a particularly advantageous application in the field of integrated circuits comprising group III-V semiconductors and in the field of microwave frequency monolithic integrated circuits. The invention is however not limited to its applications and is compatible with any integrated circuit comprising an interconnection track comprising two layers, one of which is liable to oxidize.

[0066] A blocking structure 11 produced at a distance from the second lateral face 9 (section line) of the integrated device 1 has been described here. The invention also covers embodiments in which the blocking structure 11 is flush with the second lateral face 9. Thus, the first portion 16 of the layer of oxidizable material extends to the second lateral face 9, and the layer of oxidizable material 12 does not have a third portion, but only a second portion which extends upstream of the blocking structure, i.e. between the components and the blocking structure 11.

[0067] Finally, the invention is not limited to embodiments which comprise only a single blocking structure, and covers embodiments comprising several blocking structures, for example as many blocking structures as there are interconnection tracks capable of oxidizing.

[0068] Various other modifications may be made to the invention within the scope of the appended claims.

Claims

Integrated electronic device comprising at least one component produced on a carrier structure (2) comprising a semiconductor substrate, and an interconnection track (8) which extends on the carrier structure from the component to a lateral face (9) of the device (1), the interconnection track (8) comprising a layer of oxidizable material (12) supporting a continuous layer of conductive material (13), characterized in that the layer of oxidizable material (12) is discontinuous. Device according to claim 1, comprising a blocking structure (11) which is interposed between the supporting structure (12) and a portion of the interconnection track (8), which extends transversely from one edge to the other of the interconnection track and which has an upper face (15) opposite the supporting structure (2), the layer of oxidizable material comprising a first portion (16) which extends on the upper face (15) and at least one second portion (17, 18) which extends upstream or downstream of the blocking structure (11) along the interconnection track, the second portion (17, 18) not having continuity of material with the first portion (16). Integrated electronic device according to claim 2, wherein the second portion (17, 18) extends partly between the supporting structure (2) and the first portion (16). Integrated electronic device according to claim 2 or 3, wherein the blocking structure (11) has a lower face (14) in contact with the supporting structure (2), the lower face (14) having a dimension along the interconnection track less than or equal to the dimension of the upper face (15) along the interconnection track. Electronic device according to any one of claims 2 to 4, wherein the blocking structure (11) has a trapezoidal section with a plane (II) which is parallel to the direction of extension of the interconnection track (8) and orthogonal to the substrate. An integrated electronic device according to any one of claims 2 to 5, wherein the blocking structure (11) comprises a dielectric material or a polymer. An integrated electronic device according to any one of claims 2 to 6, wherein the blocking structure (11) has a thickness less than that of the layer of conductive material (13). Integrated electronic device according to any one of claims 2 to 7, wherein the blocking structure (11) is made at a distance greater than 200 micrometers from any component (4, 5) located along the interconnection track (8). An integrated electronic device according to any one of claims 1 to 8, wherein the component and the substrate are made of group III-V materials. An integrated electronic device according to any one of claims 1 to 9, wherein the component is a high electron mobility transistor. A method of manufacturing an integrated electronic device (1) comprising at least one component on a carrier structure (2) which comprises a semiconductor substrate, the method comprising - a step of producing, on the carrier structure, a blocking structure (11) which has an upper face (15) opposite the carrier structure, - a step of producing an interconnection track (8) which extends from the component to a lateral face (9) of the device, comprising: - a sub-step of producing a layer of oxidizable material (12) comprising a first portion (16) which extends on the upper face (15), and at least one second portion (17, 18) which extends upstream or downstream of the blocking structure (11) along the interconnection track (8) so that the first portion (16) does not have continuity of material with the second portion (17,18) - a sub-step of producing a continuous layer of conductive material (13) on the layer of oxidizable material (12).,

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