Method for forming a layer of silicon carbide
Patent Information
- Application Number
- EP2023805643
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-27
- Filing Date
- 2023-10-25
- Publication Date
- 2025-09-03
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
The existing methods for forming silicon carbide layers on substrates for radio frequency applications are slow, expensive, and lack precise temperature control, leading to inefficiencies and potential loss of the SiC layer due to temperature fluctuations during the epitaxy process.
A method involving the vertical stacking of silicon substrates in an oven, where carbon gas is introduced to react with silicon, forming a silicon carbide layer and a carbon layer, with subsequent removal of the carbon layer using oxygen or plasma etching, allowing for simultaneous processing of multiple substrates and improved temperature control.
This method enables faster, less expensive, and more precise formation of silicon carbide layers on multiple substrates, enhancing the efficiency and quality of the process while avoiding the limitations of traditional epitaxy techniques.
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Figure 1.1
Abstract
Description
[0001] METHOD FOR FORMING A SILICON CARBIDE LAYER
[0002] FIELD OF THE INVENTION
[0003] The present invention relates to a method of manufacturing a semiconductor-on-insulator or piezoelectric-on-insulator substrate for radiofrequency applications.
[0004] STATE OF THE ART
[0005] Radio frequency (RF) devices, which process signals with frequencies between approximately 10 MHz and 300 GHz, find particular application in the field of telecommunications.
[0006] Such devices may be formed from semiconductor-on-insulator or piezoelectric-on-insulator substrates, successively comprising a base substrate, an electric charge trapping layer (called a "trap rich" layer in English), a dielectric layer disposed on the trapping layer and a semiconductor or piezoelectric active layer disposed on the dielectric layer. Active and / or passive components are formed in and / or on the active layer.
[0007] The charge trapping layer prevents the appearance of a conductive plane under the electrically insulating layer and the drop in resistivity of the base substrate. In addition, such a layer eliminates charge carriers in the substrate that can lead to the generation of harmonics that can interfere with the signals propagating in the radiofrequency device and degrade their quality.
[0008] The charge trapping layer can be made of silicon carbide (SiC). The formation of such a layer is typically carried out by epitaxy on the base substrate, in order to obtain the crystalline quality necessary for effective harmonic suppression in the RF component. This step is followed by chemical mechanical polishing (CMP) in order to obtain a uniform thickness and a sufficiently smooth surface of the silicon carbide layer.
[0009] Epitaxial deposition of a sufficiently thick layer of SiC is slow and therefore expensive. In addition, an epitaxial chamber accommodates a single substrate or a small number of substrates.
[0010] Furthermore, during an epitaxy process the base substrate is heated from its rear face. This technique does not allow precise control of the temperature of the front face. This can lead to the disappearance of the deposited silicon carbide layer if the front face temperature is too high. DISCLOSURE OF THE INVENTION
[0011] An aim of the invention is to design a method for manufacturing a layer of SiC on a silicon substrate, in particular to form a substrate for radiofrequency application, which is faster and less expensive than known methods.
[0012] To this end, the invention proposes a method for forming a respective layer of silicon carbide on a plurality of silicon substrates, said method successively comprising:
[0013] - placing a plurality of vertically superimposed silicon base substrates in an oven, a vertical space being provided between two adjacent base substrates,
[0014] - the introduction of a flow of carbonaceous gas into the furnace,
[0015] - raising to a temperature for forming a layer of silicon carbide to simultaneously form, by a reaction of the carbon gas with the silicon, a layer of silicon carbide on the surface of each base substrate and a layer of carbon on each layer of silicon carbide,
[0016] - the removal of each layer of carbon.
[0017] Preferably, the carbon gas is propane or acetylene.
[0018] Advantageously, the carbon gas is mixed with argon or a mixture of argon and hydrogen.
[0019] Advantageously, the formation temperature of the silicon carbide layer is between 750°C and 1100°C.
[0020] Typically, the removal temperature of the carbon layer is between 600°C and 950°C.
[0021] Preferably, the silicon substrate has an electrical resistivity greater than 500 Ohm.cm.
[0022] Advantageously, the thickness of the silicon carbide layer is between 2 and 5 nm.
[0023] Advantageously, the method further comprises, before the introduction of the carbon gas flow:
[0024] • heating the furnace to a decomposition temperature of a native silicon oxide,
[0025] • the removal of a layer of native silicon oxide from the base substrate by thermal decomposition of said oxide, and
[0026] • cooling the furnace to a temperature at which the propane flow is introduced. Preferably, the formation of the silicon carbide layer and the removal of the carbon layer are carried out in the same furnace.
[0027] In some embodiments, wherein the removal of the carbon layer is accomplished by introducing a stream of oxygen into the furnace and reacting the carbon layer with said stream of oxygen.
[0028] In other embodiments, the removal of the carbon layer is carried out by an oxygen plasma etching process.
[0029] The invention also relates to a method for manufacturing a semiconductor or piezoelectric substrate on insulator for radiofrequency applications, comprising the following steps:
[0030] • forming a layer of silicon carbide on a silicon substrate as described above to form a support substrate,
[0031] • the formation of a weakening zone by implantation of atomic species in a donor substrate made of a semiconductor or piezoelectric material,
[0032] • bonding said donor substrate to the front face of the support substrate, a dielectric layer being arranged between the silicon carbide layer and the donor substrate,
[0033] • detachment of the donor substrate along the weakening zone so as to transfer a layer of the semiconductor or piezoelectric material onto the support substrate.
[0034] BRIEF DESCRIPTION OF THE FIGURES
[0035] Other characteristics and advantages of the invention will emerge from the detailed description which follows, with reference to the appended drawings, in which:
[0036] Figures 1A and 1B are schematic views of a base substrate before a method according to the invention.
[0037] Figure 2 is a schematic view of a base substrate having a silicon carbide layer and a carbon layer.
[0038] Figure 3 is a schematic view of a base substrate having a silicon carbide charge trapping layer.
[0039] Figure 4 shows the thermal profile used for a process according to the invention.
[0040] Figures 5A to 5D illustrate the steps of manufacturing a semiconductor or piezoelectric on insulator substrate. Figure 6 illustrates an annealing furnace adapted for forming a silicon carbide layer on the base substrate and a carbon layer on the silicon carbide layer according to a preferred embodiment of the invention.
[0041] DETAILED DESCRIPTION OF EMBODIMENTS
[0042] Formation of the silicon carbide layer:
[0043] Figure 1A illustrates a base substrate 10 made of silicon intended for the manufacture of a semiconductor-on-insulator or piezoelectric-on-insulator type substrate. The electrical resistivity of such a base substrate is advantageously greater than 500 Ohm. cm. The base substrate has a rear face 110 and a front face 130. Typically, in its initial state, the base substrate has a layer of native silicon oxide 13 on its surface.
[0044] In order to prepare the front face for the subsequent steps, the native oxide layer is first removed. This step is typically carried out in a furnace at a temperature between 950°C and 1150°C, preferably close to 1100°C, under an inert atmosphere. At the end of this step, with reference to FIG. 1 B, the substrate has a front face 120 made of silicon.
[0045] A silicon carbide layer 20 is then formed on the front face 120 of the base substrate. The formation of the silicon carbide layer is carried out in a furnace which will be described later. Advantageously, the removal of the native oxide layer is carried out in the same furnace in order to avoid transfer steps resulting in a loss of time and energy for subsequent cooling and heating, and a need for additional labor.
[0046] The silicon carbide layer is formed in the gas phase, i.e. the carbon is present in the furnace in the form of a carbonaceous gas, for example propane (CsHs) or acetylene (C2H4) gas. The carbonaceous gas is mixed with a carrier gas, for example argon or a mixture of argon and hydrogen.
[0047] The substrate is heated in the furnace to a silicon carbide layer formation temperature. The carbon gas phase is transformed into silicon carbide by a reaction with the silicon on the surface of the substrate. The reaction is self-limiting, that is to say that when all the surface silicon of the front face of the base substrate is consumed, the carbonization reaction stops. No additional silicon source is provided. The final thickness of the silicon carbide layer 20 is between 2 and 5 nm. Simultaneously, with reference to FIG. 2, a carbon layer 30 is formed on the silicon carbide layer 20. At the end of this step, the substrate has a front face 320 made of carbon. The carbon layer is then removed, with reference to FIG. 3. Advantageously, this removal is carried out by supplying oxygen to the front face of the base substrate.
[0048] In some embodiments, the removal of the carbon layer is carried out by introducing a flow of oxygen into the furnace and a reaction of the carbon layer with said flow of oxygen. In this case, the removal of the oxygen layer is advantageously carried out in the same furnace as the deposition of the silicon carbide layer. This treatment is therefore carried out in situ and does not require any cooling step or transfer to another enclosure. Removal by a flow of oxygen in the same furnace makes it possible to obtain a roughness of the front face 220 that is sufficiently low for the subsequent steps to form a semiconductor or piezoelectric type substrate on insulator for radiofrequency applications.
[0049] In other embodiments, the removal of the carbon layer is carried out by an oxygen plasma etching process. This removal is effective, however it requires a step of transferring the substrate to another enclosure. In addition, the plasma treatment can degrade the roughness of the front face 220 of the base substrate, which requires subsequent treatment to improve the surface quality.
[0050] Figure 4 illustrates an example of a temperature profile for a process of forming a silicon carbide layer on a silicon substrate in an annealing furnace as a function of elapsed time. In this case, all steps from the removal of the native oxide layer to the removal of the carbon layer are carried out in the same furnace.
[0051] We can distinguish eight stages of the process:
[0052] The first step E1 begins at a time t0. The base substrate comprising a native oxide layer is at the introduction temperature in the furnace which is typically less than or equal to 500°C. The substrate is introduced into the furnace. The base substrate begins to be heated to a temperature To for removing the native oxide layer. This heating may, in an illustrative and non-limiting manner, comprise temperature increases of 5°C / min up to 900°C, then of 2°C / min up to 1000°C, and of 1°C / min up to 1100°C. At time t1, the native oxide removal temperature TO is reached.
[0053] The native oxide removal temperature To is between 1000°C and 1200°C, preferably close to 1100°C. This temperature is maintained during step E2 which typically lasts about 20 minutes until t2. The duration of this step E2 can vary depending on the thickness of the native oxide layer.
[0054] Cooling is then carried out during step E3 to a temperature T1 for injecting carbon gas into the furnace at time t3. For example, cooling can be carried out at a rate of 5°C / min and the gas injection temperature Ti is approximately 750°C.
[0055] After the injection of the carbon gas and the carrier gas, the substrate is heated in step E4 to a silicon carbide layer formation temperature TF. The silicon carbide layer formation temperature TF is advantageously between 750°C and 1100°C. The nucleation of the silicon carbide on the surface of the substrate begins during the temperature rise between t3 and t4 during step E4 and stops when the silicon on the surface of the base substrate has transformed into silicon carbide. The SiC formation reaction stops during the temperature rise, when all the silicon is consumed. Then, a carbon layer is formed linked to the high-temperature decomposition of the carbon gas. The temperature TF is maintained during step E5 during which the carbon gas is evacuated from the furnace under a flow of carrier gas for approximately 10 minutes.Subsequently, still at temperature TF, the silicon carbide layer is annealed, for example for a period of 2 hours up to t5.
[0056] Cooling E6 is then carried out to a temperature TR for removing the carbon layer. The temperature T is reached at time t6 and is between 600°C and 950°C. By way of illustration and not limitation, this temperature may be around 800°C. In the removal step E7, the removal temperature TR is maintained and oxygen O2 is injected into the furnace. For example, for an injection at 2 to 20 slm, the duration of removal of the carbon layer is approximately 5 min up to t7. The temperature is then lowered in a final step E8 to remove the substrate from the furnace.
[0057] Fabrication of a semiconductor or piezoelectric substrate on insulator:
[0058] The base substrate with the silicon carbide charge trapping layer can now be used for the fabrication of a semiconductor or piezoelectric on insulator substrate for radio frequency applications.
[0059] We will now describe the steps for producing such a substrate comprising a base substrate comprising a charge trapping layer produced according to a method as described above, a semiconductor layer on its surface, and an electrically insulating layer which is arranged at the interface between the charge trapping layer and the semiconductor surface layer.
[0060] With reference to Figure 5A, we start by providing a semiconductor or piezoelectric donor substrate 500 from which a semiconductor or piezoelectric layer will be transferred onto the base substrate and the charge trapping layer. An electrically insulating layer 40 is formed on the surface of the donor substrate 500. With reference to Figure 5B, as shown schematically by the arrows, an implantation of ionic species, such as hydrogen and / or helium, is carried out through the electrically insulating layer 40, so as to form a weakening zone 51 in the donor substrate 500. Said weakening zone 51 defines the semiconductor or piezoelectric layer 50 to be transferred.
[0061] With reference to FIG. 5C, the donor substrate 500 thus implanted is bonded to the charge trapping layer 20 on the base substrate 10 via the electrically insulating layer 40. The latter then becomes a buried oxide layer 40.
[0062] Alternatively, the electrically insulating layer 40 may be formed on the charge trapping layer on the base substrate, and the donor substrate 50 including the weakening zone 51 may be bonded to the base substrate 10 including the charge trapping layer 20 and the electrically insulating layer 40.
[0063] With reference to FIG. 5D, the donor substrate 500 is detached along the weakening zone 51, which leads to the transfer of the semiconductor or piezoelectric layer 50 onto the support substrate 100. The electrically insulating layer 40 is arranged between the charge trapping layer 20 and the semiconductor or piezoelectric layer 50. A finishing treatment of the transferred layer 50 can subsequently be carried out, so as to cure the defects linked to the implantation and to smooth the free surface of said layer 50. The semiconductor or piezoelectric on insulator type structure is now completed and can be used for the manufacture of components for radiofrequency applications.
[0064] Presentation of the oven:
[0065] In order to make a process for treating a plurality of substrates efficient and rapid, an annealing furnace is preferably used that can simultaneously treat a maximum number of substrates under identical conditions. Such a furnace is conventionally called a "batch anneal" furnace in the field of microelectronics.
[0066] Figure 6 illustrates a furnace adapted to receive a quantity of between 120 and 150 substrates in an annealing chamber. The substrates 10 are positioned horizontally in the furnace and are superimposed vertically in order to treat a maximum number of substrates in the same flow 73 of hot gas. A free space is maintained between each substrate 10 and the adjacent substrates 10 to optimize the gas flow and facilitate the formation of the silicon carbide layer.
[0067] Such a furnace uses a "top flow" type configuration, i.e. a gas flow is fed into the furnace from the top 71 and, after passing through the furnace, is discharged through an outlet 79 at the bottom of the furnace. Typically one gas flow brings the carrier gas, and a second gas flow brings a carbonaceous gas such as propane or acetylene. All the elements of the annealing chamber inside the furnace, i.e. the inner walls 75, the substrate holders for holding the substrates in a horizontal and vertically superimposed position, and the gas included in the annealing chamber are at the same temperature during use of the furnace, with the exception of the external elements such as the outer wall 76 and the ends of the gas inlet pipes.By the same temperature is meant that the temperature difference between the top end 74 of the furnace and the bottom end 78 of the furnace is minimal, typically a few degrees °C, for example less than 3 degrees for a temperature in the furnace between 800 and 1200°C.
[0068] The substrates are heated mainly by conduction from the furnace walls. The gas streams are injected at the same temperature as the temperature inside the furnace.
[0069] Such an oven allows a large number of substrates to be processed simultaneously thanks to the vertically stacked arrangement. In addition, such an oven allows the native oxide layer removal step, the silicon carbide layer deposition step and the carbon layer removal step to be carried out in the same chamber, which avoids the risk of contamination during a transfer between two different chambers. Transfer steps between different chambers adapted to the respective steps are avoided, thus avoiding cooling between steps, the need for labor for the transfer and thus a loss of time and efficiency.
Claims
CLAIMS 1. A method of forming a respective layer of silicon carbide (20) on a plurality of silicon substrates, said method successively comprising: o placing a plurality of base substrates (10) made of silicon superimposed vertically in a furnace, a vertical space being provided between two adjacent base substrates (10), o introducing a flow of a carbon gas into the furnace, o raising to a temperature (TF) for forming a layer of silicon carbide (20) to simultaneously form, by a reaction of the carbon gas with the silicon, a layer of silicon carbide (20) on the surface of each base substrate (10) and a layer of carbon (30) on each layer of silicon carbide (20), o removing each layer of carbon (30).
2. The method of claim 1, wherein the carbonaceous gas is propane or acetylene.
3. A method according to claim 1 or claim 2, wherein the carbonaceous gas is mixed with argon or a mixture of argon and hydrogen.
4. Method according to any one of claims 1 to 3, in which the temperature (TF) for forming the silicon carbide layer (30) is between 750°C and 1100°C.
5. Method according to any one of claims 1 to 4, in which the temperature (TR) for removing the carbon layer is between 600°C and 950°C.
6. A method according to any preceding claim, wherein the silicon substrate has an electrical resistivity greater than 500 Ohm.cm.
7. Method according to any one of the preceding claims, in which the thickness of the silicon carbide layer (20) is between 2 and 5 nm.
8. Method according to any one of the preceding claims, further comprising, before the introduction of the carbon gas flow: o heating the furnace to a temperature (To) for decomposition of a native silicon oxide, o removing a layer of native silicon oxide (13) from the base substrate (100) by thermal decomposition of said oxide, and o cooling the furnace to a temperature for introducing the propane flow (Tl).
9. Method according to one of the preceding claims, in which the formation of the silicon carbide layer (20) and the removal of the carbon layer (30) are carried out in the same furnace (70).
10. The method of claim 9, wherein the removal of the carbon layer (30) is achieved by introducing a flow of oxygen into the furnace and a reaction of the carbon layer with said flow of oxygen.
11. Method according to any one of claims 1 to 9, in which the removal of the carbon layer (30) is carried out by an oxygen plasma etching process.
12. A method of manufacturing a semiconductor or piezoelectric substrate on insulator for radiofrequency applications, comprising the following steps: o forming a silicon carbide layer (20) on a silicon substrate according to any one of the preceding claims to form a support substrate (100), o forming a weakening zone (51) by implanting atomic species in a donor substrate (500) made of a semiconductor or piezoelectric material, o bonding said donor substrate (500) to the front face of the support substrate (100), a dielectric layer (40) being arranged between the silicon carbide layer (20) and the donor substrate (500), o detaching the donor substrate (500) along the weakening zone (51) so as to transfer a layer (50) of the semiconductor or piezoelectric material onto the support substrate (100).