Piezoelectric-on-insulator (POI) substrate, and process for manufacturing a piezoelectric-on-insulator (POI) substrate
Patent Information
- Application Number
- EP2023794418
- Authority / Receiving Office
- EP · EP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-10-26
- Filing Date
- 2023-10-26
- Publication Date
- 2025-09-03
AI Technical Summary
The manufacturing process of piezoelectric substrates on insulators (POI) leads to the diffusion of metallic elements from the piezoelectric layer into the trapping layer, neutralizing electrical traps and degrading the electrical performance, particularly reducing the Q factor and radio frequency performance.
Incorporating a diffusion barrier layer, such as Tantalum Nitride or Silicon Carbon Nitride, between the piezoelectric layer and the trapping layer to prevent the diffusion of metallic elements, and optionally using a hydrogen diffusion barrier layer to limit hydrogen diffusion, thereby maintaining the trapping layer's high resistivity and improving the substrate's performance.
The use of diffusion barrier layers effectively reduces the neutralization of charge traps in the trapping layer, enhancing the electrical performance and lifespan of the POI substrate, leading to improved Q factor and radio frequency characteristics.
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Figure 1.1
Abstract
Description
Description Title of the invention: Piezoelectric-on-insulator (POI) substrate and method of manufacturing a piezoelectric-on-insulator (POI) substrate
[0001] , The invention relates to a piezoelectric on insulator (POI) substrate and a method of manufacturing such a piezoelectric on insulator (POI) substrate.
[0002] A piezoelectric on insulator (POI) substrate is used for acoustic wave devices, such as sensors, filters or others, because it allows to obtain good performances thanks to better values of quality Q and electromechanical coefficients k compared to other state-of-the-art substrates.
[0003] , Such a substrate comprises a thin layer of piezoelectric material on a dielectric layer, itself arranged on a support substrate. For certain applications, a trapping layer is placed between the support substrate and the dielectric layer. The trapping layer is typically a non-crystalline layer having structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, and / or pores. These structural defects form traps for charges likely to circulate in the material. The trapping layer thus has a high resistivity which results in reduced charge conduction inside the layer, and consequently a reduced current inside the trapping layer. The trapping layer makes it possible to reduce losses linked to parasitic conduction effects at the interface between the support substrate and the dielectric layer.In fact, the trapping layer serves to reduce the lifetime of the charges in this region.
[0004] . In the fabrication of such a piezoelectric-on-insulator (POI) substrate, a donor substrate is used in which a piezoelectric material substrate is bonded to a handling substrate. Then, the donor substrate undergoes a piezoelectric substrate thinning step to form a thinner piezoelectric layer before being bonded to the support substrate. Finally, the transfer of a thin piezoelectric layer to the support substrate is achieved mechanically or thermally at a fracture zone previously created in the piezoelectric layer of the donor substrate. A final heat treatment of the resulting POI substrate is required to repair the damage caused to the transferred piezoelectric layer during the fracturing step.
[0005] , However, this final annealing results in a diffusion of metallic elements from the piezoelectric layer to the trapping layer. When the metallic elements (Li, Fe, Cu, Ni) diffuse into the trapping layer, they will neutralize (occupy) electrical traps present in the trapping layer. This neutralization of the electrical traps of the trapping layer results in a degradation of the electrical performances of said trapping layer, in particular a reduction of the Q factor and the radiofrequency performances, and consequently also those of the POI substrate thus manufactured.
[0006] , An aim of the invention is thus to remedy the aforementioned drawbacks and in particular to design a piezoelectric on insulator (POI) substrate which has better characteristics for use in acoustic wave devices.
[0007] The subject of the invention is achieved by a piezoelectric on insulator (POI) substrate comprising a support substrate, in particular a silicon-based substrate, comprising a trapping layer on a free surface of the support substrate, in particular a layer based on polycrystalline or amorphous or porous silicon, a piezoelectric layer, in particular a layer of lithium tantalate (LiTaO) or lithium niobate (LiNbO) and an intermediate structure positioned in a sandwich between the piezoelectric layer and the trapping layer of the support substrate, in which the intermediate structure comprises at least one diffusion barrier layer of metallic elements, in particular lithium, based on tantalum nitride (TaN) or silicon carbon nitride (SiCN).
[0008] , The presence of the metallic element diffusion barrier structure between the piezoelectric layer and the trapping layer makes it possible to reduce the diffusion of metallic element from the piezoelectric layer to the trapping layer during the manufacturing process. Thus, the phenomenon of neutralization of the charge traps present in the trapping layer by metallic elements is reduced. The trapping layer in the final substrate (POI) therefore has a high resistivity which makes it possible to obtain a substrate (POI) with improved performances.
[0009] , According to a variant of the invention, the barrier layer may have a thickness tu greater than a predetermined thickness, said predetermined thickness being determined as a function of the thickness of the trapping layer in such a way that the dose of metallic element in the trapping layer is less than a threshold dose of metallic element causing the degradation of the trapping layer, in particular a threshold dose of metallic element less than 10 12 at / cm 2 , in particular less than 5*10 n at / cm 2 The threshold thickness of the barrier layer is determined based on the thickness of the trapping layer and the threshold dose of metallic element present in the trapping layer for which the trapping layer still has electrical characteristics that make it possible to obtain a POI substrate with improved performance.
[0010] , According to a variant of the invention, the barrier layer may have a thickness of between 5nm and 150nm, in particular between 10nm and 100nm, and the thickness of the trapping layer is between 50nm and 5pm. The barrier layer is a much thinner layer than the trapping layer.
[0011] , According to a variant of the invention, the intermediate structure may comprise at least one dielectric layer, in particular based on silicon dioxide or silicon nitride (SiN) or even silicon oxynitride (SiO x N y ), in contact with the at least one barrier layer. The dielectric layer allows good adhesion in the POI substrate between the piezoelectric material and the support substrate.
[0012] , According to a variant of the invention, the barrier layer can be positioned sandwiched between two dielectric layers.
[0013] , According to a variant of the invention, the intermediate structure may further comprise a second barrier layer. A second barrier layer makes it possible to obtain a substrate (POI) with improved electrical characteristics and therefore with better performance for SAW applications. Indeed, the second barrier layer may be a second diffusion barrier layer of the same metallic element as the first diffusion barrier layer from the piezoelectric layer to the trapping layer, or the second barrier layer may be a diffusion barrier layer of another metallic element than the first barrier layer in the composite substrate.
[0014] , According to a variant of the invention, the second barrier layer may be a hydrogen diffusion barrier layer, in particular based on Silicon Nitride (SiN) or Aluminum Nitride (AIN) or Silicon Oxynitride (SiO x N y). In a piezoelectric-on-insulator (POI) substrate, hydrogen diffusion to the piezoelectric layer and / or the trapping layer occurring during heat treatment steps of the manufacturing process of such a substrate also reduces the performance of the piezoelectric-on-insulator (POI) substrate. Thus, the presence of a hydrogen barrier layer makes it possible to reduce hydrogen diffusion inside the piezoelectric-on-insulator (POI) substrate during the manufacturing of the substrate (POI) and to obtain a POI substrate with better performance.
[0015] , According to a variant of the invention, the intermediate layer may comprise at least one layer with a hydrogen concentration of less than 10 20 at / cm 3 , especially less than 10 18 at / cm 3 . A layer with a hydrogen concentration less than 1O 20 at / cm 3corresponds to a hydrogen diffusion barrier layer. Thus, the POI substrate has improved performance thanks to the presence of such a layer in its structure.
[0016] , The subject of the invention is also achieved by a method for manufacturing a piezoelectric on insulator (POI) substrate described previously comprising the steps of providing a support substrate, in particular a silicon-based substrate, comprising a trapping layer, in particular a layer based on polycrystalline or amorphous or porous silicon, providing a substrate comprising a piezoelectric layer, in particular a layer based on Lithium Tantalate (LiTaO ,) or Lithium Niobate (LiNbCE), forming an intermediate structure on the substrate comprising a piezoelectric layer and / or on the support substrate, the formation of the intermediate structure comprising the formation of at least one barrier layer of metallic element, in particular Lithium, based on Tantalum Nitride (TaN) or Silicon Carbon Nitride (SiCN), and assembling the substrate comprising a piezoelectric layer with the support substrate.
[0017] , Thus, the step of forming an intermediate structure on the substrate comprising a piezoelectric layer and / or the support substrate in the method according to the invention makes it possible to form a metallic element diffusion barrier layer for reducing the diffusion of metallic element from the piezoelectric layer to the trapping layer during heat treatment steps of the process. With this method a substrate can be obtained which can effectively reduce the negative effect of diffusion of metallic elements to the support substrate, and in particular into the trapping layer of the support substrate.
[0018] , According to a variant of the invention, the step of forming the intermediate structure may further comprise the formation of a second barrier layer. The second barrier layer may be a barrier layer of metallic elements or a barrier layer of another element in the structure, in particular a non-metallic element. With this method a substrate may be obtained which makes it possible to reduce even more effectively the negative effect of the diffusion of elements towards the support substrate by reducing both the diffusion of metallic element coming from the piezoelectric layer but also the diffusion of other elements in the structure of the POI substrate.
[0019] , According to a variant of the invention, the step of forming the intermediate structure may further comprise a step of forming a layer with a hydrogen concentration of less than 10 20 at / cm 3 , especially less than 10 18 at / cm 3The formation of a layer with a reduced hydrogen concentration makes it possible to limit the diffusion of hydrogen into the structure during subsequent heat treatment, a treatment known to facilitate the diffusion of hydrogen towards the piezoelectric layer and / or the trapping layer.
[0020] , According to a variant of the invention, the step of forming the second barrier layer may comprise the formation of a layer based on Silicon Nitride (SiN) or Aluminum Nitride (AIN) or Silicon Oxynitride (SiO x N y ). A layer based on such a material makes it possible to create a hydrogen diffusion barrier towards the piezoelectric layer and / or the trapping layer.
[0021] , According to a variant of the invention, the method may further comprise a step of forming a dielectric layer on the support substrate and / or on the substrate comprising a piezoelectric layer before the assembly step, such that the bonding interface is an oxide-oxide bonding interface. The assembly interface of the support substrate with the substrate comprising a piezoelectric layer is made at the interface between two dielectric layers, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which is a type of bond known to be stable. Thus, the piezoelectric substrate on insulator obtained by the method according to the invention has a stable bond between the piezoelectric layer and the support substrate.
[0022] , According to a variant of the invention, the manufacturing method may further comprise a step of forming a dielectric layer of a first material on the support substrate and / or of a second material different from the first material on the substrate comprising a piezoelectric layer before the assembly step. For example, the first material is based on Silicon Nitride, in particular Si',N4. and the second material is based on Silicon Oxynitride (SiOxNy), especially SiON. Thus, the bonding interface is a Si',N - SiO bonding interface x Ny. Such an interface has advantages in terms of the acoustic impedance of the manufactured structure while being a stable assembly interface.
[0023] The invention and its advantages will be explained in more detail hereinafter by means of preferred embodiments and with particular reference to the following accompanying figures, in which the reference numbers identify features of the invention.
[0024] , [Figure 1] schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a first embodiment of the invention.
[0025] , [Figure 2a] schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a second embodiment of the invention.
[0026] , [Figure 2b] schematically represents a method of manufacturing a donor substrate and a donor substrate according to a first variant of the second embodiment of the invention.
[0027] , [Figure 2c] schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a second variant of the second embodiment of the invention.
[0028] , [Figure 3] schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a third embodiment of the invention.
[0029] . The invention will be described in more detail using advantageous embodiments in an exemplary manner and with reference to the drawings. The described embodiments are merely possible configurations and it should be borne in mind that individual features as described above may be provided independently of one another or may be omitted altogether when implementing the present invention.
[0030] , Figure 1 schematically illustrates a method of manufacturing a piezoelectric on insulator (POI) substrate according to the first embodiment of the invention.
[0031] , The method of manufacturing a piezoelectric on insulator (POI) substrate begins with step I) of providing a support substrate 100, in particular a bulk substrate. A bulk substrate is a substrate based on a single material typically with a thickness of between 200pm and 1mm.
[0032] , The support substrate 100 may be a substrate based on Silicon, Sapphire, Aluminum Nitride (AIN), Silicon Carbide (SiC) or Gallium Arsenide (GaAs). The support substrate 100 may be a crystalline or polycrystalline substrate.
[0033] , The support substrate 100 comprises a trapping layer 102 deposited on a free surface 104 of the support substrate by a deposition technique, for example by subatmospheric pressure chemical vapor deposition LPCVD or the plasma-assisted CVD chemical vapor deposition technique PCVD. The deposition temperature is between 200°C and 1100°C. The trapping layer 102 is a silicon-based layer, for example, based on polycrystalline silicon or amorphous silicon or porous silicon. The thickness t p of the trapping layer 102 is between 5nm and 5pm.
[0034] , The trapping layer 102 has structural defects such as dislocations, grain boundaries, amorphous areas, interstices, inclusions, and / or pores. These structural defects form traps for charges likely to flow in the material, for example at incomplete or dangling chemical bonds. The trapping layer 102 thus has a high resistivity which results in reduced charge conduction within the layer, and consequently a reduced current within the trapping layer.
[0035] , In step II) of the method according to the first embodiment, a substrate comprising a piezoelectric layer 106 is provided. This is preferably a thick layer of piezoelectric material 108 of a thickness ti, provided on a base substrate 110.
[0036] , The piezoelectric material 106 may be a lithium-rich piezoelectric material, for example, lithium tantalate (LiTaO,) or lithium niobate (LiNbCfi).
[0037] , The substrate comprising a piezoelectric layer 106 may have first undergone one or more steps of cleaning, brushing or polishing its free surface to remove particles or dust and thus obtain a cleaner and better quality free surface to subsequently carry out a successive layer deposition.
[0038] , According to the invention, a step III) of depositing an intermediate structure 120 on the free surface 102a, preferably directly on the free surface 102a, of the trapping layer 102 of the support substrate 100 is carried out.
[0039] , Step III) of depositing the intermediate structure 120 comprises the formation of at least one diffusion barrier layer of metallic elements 122. The barrier layer 122 may be a diffusion barrier layer of Lithium 122.
[0040] , The barrier layer 122 may, according to the invention, be a layer based on Tantalum Nitride (TaN) deposited by an ALD atomic layer deposition technique (in English: Atomic Layer Deposition) or by PE-ALD, a plasma-assisted atomic layer deposition. In this case, the ALD deposition temperature is between 25°C and 100°C.
[0041] , According to an alternative according to the invention, the barrier layer 122 may be a layer based on Silicon Carbon Nitride (SiCN) deposited by a plasma-enhanced chemical vapor deposition (PECVD) technique. In this case, the deposition temperature is of the order of 400°C.
[0042] , The barrier layer 122 has a thickness t E M greater than a predetermined thickness, said predetermined thickness being defined as a function of the thickness t p of the trapping layer 102 such that the dose of metallic element in the trapping layer 102 is less than a threshold dose of metallic element resulting in the degradation of the trapping layer 102.
[0043] , To calculate the threshold dose of metallic element, the person skilled in the art will know how to calculate the diffusion slope of the metallic element from its diffusion coefficient and thus adjust the thickness ÎEM of the barrier layer 122 in order to guarantee not to exceed an element dose threshold predetermined metallic in the trapping layer 102. This calculation also depends on the heat treatments applied to the structure during the manufacturing process and also on the thickness of the trapping layer 102.
[0044] , For example, for a layer of Lithium Tantalate (LiTaO3) or Lithium Niobate (LiNbCL) and for a trapping layer 102 having a thickness t p of Ipm, the threshold dose of Lithium in the trapping layer 102 must be less than 10 12 at / cm 2 . For a trapping layer 102 with a thickness t p of the order of 0.5pm, the threshold dose of Lithium will rather be of the order of 5.10 11 at / cm 2 .
[0045] , To obtain these values, the tEM thickness of the barrier layer 122 must be between 5nm and 150nm, in particular between 10nm and 100nm.
[0046] , During step 11a) a weakening zone 112 is formed in the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 so as to delimit the piezoelectric layer 114 to be transferred from the remainder 116 of the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106.
[0047] , This step 11a) of forming a weakening zone 112 is carried out by an implantation 118 of atomic or ionic species in the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106. The atomic or ionic implantation is carried out in such a way that the weakening zone 112 is located inside the piezoelectric layer 108 and separates a piezoelectric layer 116 from the remainder 114 of the piezoelectric layer 108. The atomic or ionic species are implanted at a determined depth L of the piezoelectric layer 108 which determines the thickness C of the piezoelectric layer 114 to be transferred. The thickness C is typically between 50nm and 1pm, in particular of the order of 600nm. The implantation dose of the atomic or ionic species is between 10 16 at / cm 2 and 10 17 at / cm 2 .
[0048] , The support substrate 100 obtained after step III), is then assembled to the donor substrate 110 obtained after step 11a) during the assembly step IV) to obtain a heterostructure 124 corresponding to the support substrate - donor substrate assembly. Here the assembly is done by molecular adhesion.
[0049] , The assembly of the substrate comprising a piezoelectric layer 106 on the support substrate 100 is made such that the barrier layer 122 of the intermediate structure 120 is positioned in a sandwich between the piezoelectric layer 114 of the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100. The contact interface 126 is located between the piezoelectric layer 114 and the barrier layer 122 of the support substrate 100.
[0050] , Then, a step V) of transferring the piezoelectric thin layer 114 is carried out. For this, a step of fracturing the donor substrate 124 by supplying thermal energy with a heat treatment between 100°C and 300°C in an atmosphere of Ar or N2, and / or mechanical at the level of the embrittlement zone 112 to obtain a POI substrate comprising a piezoelectric layer 114 with a thickness typically between 50nm and 1pm, in particular of the order of 600nm.
[0051] , A heat treatment of the piezoelectric-on-insulator (POI) substrate 122 obtained after step V) is carried out to repair the damage caused to the piezoelectric layer 114 transferred during the fracturing step. This heat treatment is carried out at a temperature between 400 and 600°C, in particular of the order of 500°C, in an atmosphere of Ar, O2 or N2.
[0052] , During these heat treatments when producing the POI substrate, diffusion of metallic elements may take place starting from the piezoelectric layer 114 towards the trapping layer 102.
[0053] , Due to the presence of the barrier layer 122, the diffusion of metallic element from the piezoelectric layer 114 to the trapping layer 102 is reduced, because the barrier layer 122 acts as a metallic element diffusion barrier layer. Thus, the passivation of the charge traps in the trapping layer 102 by metallic elements from the piezoelectric layer 114 is reduced, and the trapping layer 102 retains its power to reduce parasitic currents.
[0054] , In a variant of the method according to the first embodiment, the intermediate structure 120, here the metallic element diffusion barrier layer 122, is produced on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106, instead of being produced on the support substrate 100. In this case, the step of forming the barrier layer 122 is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface located between the barrier layer 122 of the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.
[0055] , In another variant of the method according to the first embodiment, the intermediate structure 120, here the metallic element diffusion barrier layer 122, can be provided on the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the barrier layer 122 is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface between two barrier layers. Assembling the substrate comprising a piezoelectric layer with the support substrate by assembling two barrier layers is advantageous for the assembly, because the assembly is made between two layers of the same material.
[0056] , In a variant of the method, instead of carrying out step 11a) of forming the weakening zone in the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106, after step III), step IV) of assembly is carried out directly between the substrate comprising a piezoelectric layer 106 and the support substrate 100. A thinning step IVa) (not illustrated) is then carried out to reduce the thickness of the substrate comprising a layer piezoelectric layer 106. This thinning step may be a step of grinding the substrate comprising a piezoelectric layer 106 to obtain a piezoelectric layer 114 of a thickness thinner than the piezoelectric layer 108.
[0057] , In addition, other treatments of the free surface 128 of the piezoelectric layer 114 may be performed to improve the quality of the free surface 128 of the piezoelectric layer 114.
[0058] , The piezoelectric on insulator (POI) substrate 130 illustrated in step V) of Figure 1 obtained with the support substrate 100, the trapping layer 102, the metallic element diffusion barrier layer 122 and the piezoelectric layer 114 corresponds to the substrate according to the invention according to the first embodiment also.
[0059] , Figure 2a schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a second embodiment of the invention.
[0060] . In this second embodiment, the only difference with the method according to the first embodiment is that the step III) of depositing the intermediate structure 120 additionally comprises a step Ilia) of forming a dielectric layer 132 on, in particular in direct contact with, the at least one barrier layer 122. Thus, the intermediate structure 120 comprises a metallic element diffusion barrier layer 122 and a dielectric layer 132.
[0061] , The other steps I) to V) are the same as in the first embodiment, except that in step IV) the assembly is made between the dielectric layer 132 and the substrate comprising a piezoelectric layer 106. All the features common with the first embodiment and its variant and using the same reference numbers as above will not be described again, but reference is made to their detailed description above.
[0062] , The dielectric layer 132 is for example a layer based on Silicon Oxide. But the dielectric layer 132 can also be a layer of Silicon Nitride (SisN), or a layer comprising a combination of Nitride and Silicon Oxide (SiO x N y ), or a superposition of a layer of Silicon Oxide and a combination of nitride and oxide (SiO x N y ) of Silicon or a superposition of a layer of Silicon oxide and a layer of Silicon nitride.
[0063] , The dielectric layer 132 is produced by a deposition technique such as CVD or LPCVD, assisted by plasma PECVD (in English: “Plasma Enhanced Chemical Vapor Deposition” or PVD physical vapor deposition or by oxidation thermal treatments. The PVD deposition comprises deposition temperatures between room temperature and 400°C, the PECVD technique comprises deposition temperatures between 150°C and 400°C. The LPCVD deposition comprises deposition temperatures between 600 and 700°C. The dielectric layer 132 is deposited on, in particular directly in contact with, the barrier layer 122.
[0064] . A heat treatment, also called densification treatment, can be carried out after the deposition of the dielectric layer 132 to degas the excess hydrogen formed during the deposition, Hydrogen that occupies the traps in the trapping layer 102. Additionally, or alternatively, a surface treatment may be performed to improve the quality of the surface of the deposited dielectric layer 132.
[0065] , The dielectric layer 132 is for example a layer based on silicon dioxide. But the dielectric layer 132 can also be a layer comprising a combination of nitride and silicon oxide (SiO x N y ), or a superposition of a layer of Silicon Oxide and a combination of Nitride and Silicon Oxide (SiO x N y ), or a layer of Silicon Nitride (SijN^, or a layer comprising a combination of Nitride and Silicon Oxide (SiO x N y ), or a superposition of a layer of Silicon Oxide and a layer of Silicon Nitride.
[0066] , Thus, during the assembly step V), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 134, by placing the dielectric layer 132 in direct contact with the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106. Thus, in this second embodiment, the assembly interface 136 is located between the piezoelectric layer 108 and the dielectric layer 132 of the support substrate 100.
[0067] , In a variant, the dielectric layer 132 may be a layer having a hydrogen concentration of less than 1O 20 at / cm 3 , especially less than 10 18 at / cm 3. After the step of deposition of the dielectric layer 132 carried out at a temperature typically between room temperature and 1000°C, depending on the deposition technique used, a densification annealing can be carried out to reduce the hydrogen concentration in this dielectric layer 132. For example, if the dielectric layer is produced by PVD deposition, the temperature is between room temperature and 400°C, for PECVD deposition, between 150°C and 400°C, LPCVD deposition between 600°C and 700°C, and for thermal oxidation, the temperature is between 800°C and 1000°C.
[0068] This annealing is an annealing in a hydrogen-poor atmosphere, i.e. less than 5 ppm, and exposes the dielectric layer 132 based on Silicon Oxide to a temperature higher than its deposition temperature. This may be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800°C, typically between 800°C and 1000°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodify the hydrogen from the dielectric layer 132, and possibly from the trapping layer 102. At the end of this densification annealing, the dielectric layer 132 has a hydrogen concentration lower than 10 20 at / cm 3 .
[0069] , In a variant, the dielectric layer 132 may be provided on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the dielectric layer 132 is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the dielectric layer 132 of the piezoelectric substrate 106 and the barrier structure 120 of the support substrate 100.
[0070] , In another variant, a dielectric layer may be provided on both substrates, the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the dielectric layer is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two dielectric layers. For example, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which allows a stable molecular force bond.
[0071] , In another variation, a dielectric layer of a first material may be provided on the substrate comprising a piezoelectric layer 106 and a dielectric layer of a second material may be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a Si;N4 layer while the dielectric layer provided on the support substrate 100 is a SiO layer x N y , in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two dielectric layers Si;N4 - SiO x N y which allows a stable connection.
[0072] , In a variant, the dielectric layer 132 and the barrier layer 122 of the intermediate structure 120 may be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the intermediate structure 120 is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the dielectric layer 132 of the intermediate structure 120 on the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.
[0073] , The piezoelectric on insulator (POI) substrate 138 illustrated in step V) of Figure 2a obtained with the support substrate 100, the trapping layer 102, the metallic element diffusion barrier layer 122, the dielectric layer 132 and the piezoelectric layer 114 corresponds to the substrate according to the invention according to the second embodiment also.
[0074] , In a variant, illustrated in Figure 2b, the step Ilia) of forming a dielectric layer 132' is carried out before the step III) of forming the at least one barrier layer 122'. The dielectric layer 132' and the barrier layer 122' are produced in the same way as the dielectric layer 132 and the barrier layer 122 described previously in Figure 2a. Thus, the intermediate structure 120' comprises the dielectric layer 132' and the metallic element diffusion barrier layer 122'.
[0075] , Thus, during the assembly step IV), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 140 by bringing the barrier layer 122' into contact with the piezoelectric substrate 106. Thus, in this variant, the assembly is carried out at the interface 142 between the piezoelectric layer 108 and the barrier layer 122' of the support substrate 100.
[0076] , In a variant, the barrier layer 122' may be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the barrier layer 122' is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the barrier layer 122' on the substrate comprising a piezoelectric layer 106 and the dielectric layer 132' of the support substrate 100.
[0077] , In another variant, the barrier layer 122' may be provided on the substrate comprising a piezoelectric layer 106 and on the support substrate 100. In this case, the step of forming the barrier layer 122' is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between the two barrier layers 120'.
[0078] , In another variant, the barrier layer 122' and the dielectric layer 132' of the intermediate structure 120' may be provided on the piezoelectric layer 108 of the substrate comprising a layer 106 instead of being provided on the support substrate 100. In this case, the step of forming the intermediate structure 120' is carried out before or after the step of forming the weakening zone 112 in the piezoelectric layer 108. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is carried out at the interface between the barrier layer 122' of the intermediate structure 120' on the substrate comprising a piezoelectric layer 106 and the trapping layer 102 of the support substrate 100.
[0079] , The piezoelectric on insulator (POI) substrate 144 illustrated in step V) of Figure 2b comprises in this order the support substrate 100, the trapping layer 102, the dielectric layer 132', the metallic element diffusion barrier layer 122' and the piezoelectric layer 114 according to this variant of the second embodiment of the invention.
[0080] , In a second variant of the second embodiment illustrated in Figure 2c, a step Illb) of forming a dielectric layer 146 is added compared to the embodiment illustrated in Figure 2b. During this step, the dielectric layer 146 is formed on the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106 after the step 11a) of forming the weakening zone 112 in the piezoelectric layer 108.
[0081] , The dielectric layer 146 is for example a layer based on Silicon Oxide. But the dielectric layer 146 can also be a layer of Silicon Nitride (SiO), or a layer comprising a combination of Nitride and Silicon Oxide (SiO x N y ), or a superposition of a layer of Silicon Oxide and a layer of Silicon Nitride or a combination of a layer of Silicon Oxide, a layer of Silicon Nitride and a layer of Silicon Oxynitride (SiO x N y ).
[0082] , The dielectric layer 146 is produced by a deposition technique such as chemical vapor deposition CVD or LPCVD, plasma-assisted PECVD or physical vapor deposition PVD or by oxidation heat treatment.
[0083] , A surface treatment can be carried out to improve the quality of the surface of the deposited dielectric layer 146. Thus, during the assembly step IV), the substrate comprising a piezoelectric layer 106 is assembled with the support substrate 100 to form the heterostructure 148 by bringing the barrier layer 122' into contact with the dielectric layer 146. Thus, in this variant, the assembly is carried out at the interface 150 between the dielectric layer 146 of the substrate comprising a piezoelectric layer 106 and the barrier layer 122' of the support substrate 100. Thus, the barrier layer 122' is sandwiched between the two dielectric layers 132' and 146.
[0084] , In the same way as in the variants of the method according to the first embodiment, the dielectric layer 146 can be provided on the support substrate 100 on the barrier layer 122' instead of being provided on the substrate comprising a piezoelectric layer 106. In this case, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is made at the interface between the dielectric layer 146 of the support substrate 100 and the piezoelectric layer 108 of the substrate comprising a piezoelectric layer 106.
[0085] , In the same way as in the other variants of the method according to the first embodiment, the dielectric layer can be provided on the piezoelectric substrate 106 and on the support substrate 100. The assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then made at the interface between two dielectric layers of the same material, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which allows a stable molecular force bond.
[0086] , In the same manner as in the other variants, a dielectric layer of a first material may be provided on the substrate comprising a piezoelectric layer 106 and a dielectric layer of a second material may be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a layer of Si;N4 while the dielectric layer provided on the support substrate 100 is a layer of SiO x N y> in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two dielectric layers Si;N4 - SiO x N y which allows a stable connection.
[0087] , In the same way as in the other variants of the second embodiment, one or more layers of the intermediate structure 120' may be provided on the piezoelectric substrate 106 instead of on the support substrate 100.
[0088] , The piezoelectric on insulator (POI) substrate 152 illustrated in step V) comprises the support substrate 100, the trapping layer 102, the dielectric layer 132', a metallic element diffusion barrier layer 122', the second dielectric layer 146 and the piezoelectric layer 114 corresponds to the substrate according to the invention according to this second variant of the second embodiment.
[0089] , Figure 3 schematically represents a method of manufacturing a piezoelectric on insulator (POI) substrate according to a third embodiment of the invention.
[0090] , In this third embodiment, step III) of forming the intermediate structure 120 of the method according to Figure 2a further comprises a step IIIc) of forming a second barrier layer 154 after step IIIa).
[0091] , All other steps I), II), Ila), III), Illa), IV) and V) are the same as in the second embodiment according to Figure 2a, except that in step IV) the assembly is between the second barrier layer 154 and the piezoelectric substrate 106. All features common to the first or second embodiment as well as their variants and using the same reference numbers as above will not be described again, but reference is made to their detailed description above.
[0092] The intermediate structure 120 thus comprises a first barrier layer 122 for diffusion of metallic element, a dielectric layer 132 and a second barrier layer 154, 156, 158, 160.
[0093] , This second barrier layer 154, 156, 158, 160 is deposited on the dielectric layer 132, which is deposited on the first barrier layer 122. Thus, the first barrier layer 122 and the second barrier layer 154, 156, 158, 160 are separated by the dielectric layer 132.
[0094] , During the assembly step IV), the second barrier layer 154, 156, 158, 160 is brought into contact at the interface 162 with the substrate comprising a piezoelectric layer 106 to form the donor substrate 164.
[0095] , The second barrier layer 154 may be a second metallic element diffusion barrier layer 156. In this case, the second barrier layer 156 is formed in the same manner as the first barrier layer 122. The second metallic element diffusion barrier layer 156 may have the same properties, such as thickness or material as the first barrier layer 122 or alternatively the first metallic element diffusion barrier layer 122 and the second barrier layer 156 may be different with different materials and / or a different thickness. For example, the first diffusion barrier layer 122 may be a Tantalum Nitride (TaN) layer and the second diffusion barrier layer 156 may be a Silicon Carbon Nitride (SiCN) layer, or vice versa. The second diffusion barrier layer 156 may also be Tantalum Oxide (Ta2Os) or Aluminum Oxide (AI2O3).
[0096] , According to a first variant, the second barrier layer 154 may be a hydrogen diffusion barrier layer 158 to limit the diffusion of hydrogen towards the piezoelectric substrate 106 and / or towards the trapping layer 102 of the support substrate 100. The hydrogen diffusion barrier layer 158 may be based on Silicon Nitride (SiN) or Silicon Oxynitride (SiO x N y ) or aluminum nitride (AIN). This second barrier layer 158 based on Silicon Nitride (SiN) or Silicon Oxynitride (SiO x N y) or aluminum nitride (AIN) is formed by a PECVD (Plasma Enhanced Chemical Vapor Deposition) or PVD (Physical Vapor Deposition) or ALD (Atomic Layer Deposition) deposition technique, with a thickness between 10nm and 100nm.
[0097] . Indeed, in a POI substrate, another source of degradation of the radiofrequency and electrical performances of the substrate is the diffusion of hydrogen towards the piezoelectric layer and / or towards the trapping layer during the manufacturing process of the POI substrate. The hydrogen can come from different sources, for example from the interface during assembly due to the hydrophilic nature of the layers at the interface, such as the silicon-based substrate 100, or from the dielectric layer which is rich in hydrogen due to its manufacturing process.
[0098] . During a heat treatment, such as during a deposition step or a fracturing step, carried out during the manufacturing process at temperatures of the order of 500°C, hydrogen, as the metallic element of the piezoelectric layer 114, can diffuse to the trapping layer 102 and neutralize the charge traps of the trapping layer 102. In addition, hydrogen can also diffuse into the piezoelectric layer / substrate, in which the presence of hydrogen can lower the Curie temperature which can locally cause the piezoelectric domain flip. This phenomenon of local ferroelectric domain flip affects the propagation of the acoustic waves of the ferroelectric material.
[0099] , According to a second variant, the hydrogen diffusion barrier layer 158 is a silicon oxide-based layer 160. In this second variant, the second barrier layer 160 has a hydrogen concentration of less than 1O 20 at / cm 3 , especially less than 10 18 at / cm 3 This can be achieved by deposition of silicon oxide by a plasma-assisted deposition technique such as PECVD, or such as chemical vapor deposition CVD or LPCVD, or physical vapor deposition PVD (in English: "Physical Vapor Deposition") or by oxidation thermal treatments. PVD deposition includes deposition temperatures between temperature ambient and 400°C, the PECVD technique includes deposition temperatures between 150°C and 400°C. LPCVD deposition includes deposition temperatures between 600 and 700°C. This deposition is carried out at a temperature typically between 600°C and 800°C. In this case, the dielectric layer 160 has a significant hydrogen concentration of more than 1O 20 at / cm 3 .
[0100] , To reduce the hydrogen concentration in this second barrier layer 160 based on silicon oxide, an annealing, called densification annealing, is applied. This annealing is an annealing in a hydrogen-poor atmosphere, i.e. less than 5 ppm, and exposes the layer 160 based on Silicon Oxide to a temperature higher than its deposition temperature. This may be a neutral or oxidizing atmosphere. Preferably, this temperature is higher than 800°C, typically between 800°C and 900°C. The annealing is continued for at least one hour, and preferably for several hours, in order to exodiffuse the hydrogen from the dielectric layer 160, and possibly from the trapping layer 102. At the end of this densification annealing, the dielectric layer 160 has a hydrogen concentration lower than 10 20 at / cm 3 .
[0101] , Such densification annealing can also lead to reducing the diffusivity of hydrogen, i.e. the capacity of this species to diffuse into the material constituting the dielectric layer 160, so that hydrogen, even in a concentration greater than 1O 20 at / cm 3 is less likely to diffuse towards the trapping layer 102. Thus, the trapping layer 102 also has a reduced hydrogen concentration, in particular lower 10 18 at / cm 3 .
[0102] , In a variant of this embodiment, one or more layer(s) of the intermediate structure 120, i.e., the dielectric layer 132, the barrier layer 122 and the second barrier layer 154, 156, 158, 160 may be provided on the piezoelectric substrate 106 instead of on the support substrate 100. In this variant, the order of deposition of the layers is carried out in such a way that the final POI substrate obtained after assembly and fracturing has the same sequence of layers, i.e., the same order of the deposited layers, as the POI substrate 166 obtained for the embodiment described previously.
[0103] , In another variant of this embodiment of the invention, a dielectric layer can be provided on both substrates, the substrate comprising a piezoelectric layer 106 and on the support substrate 100. The assembly interface of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is made at the interface between two dielectric layers, with oxide-oxide type bonds, in particular a Si-O-Si type bond, which is a type of bond known to be stable.
[0104] , In another variation of this embodiment of the invention, a dielectric layer of a first material may be provided on the substrate comprising a piezoelectric layer 106 and a dielectric layer of a second material may be provided on the support substrate 100, the first material being different from the second material. For example, the dielectric layer provided on the substrate comprising a piezoelectric layer 106 is a layer of Si;N4 while the layer dielectric provided on the support substrate 100 is a layer of SiO x N y , in particular SiON. Thus, the assembly of the support substrate 100 with the substrate comprising a piezoelectric layer 106 is then carried out at the interface between two dielectric layers Si;N4 - SiO x N y which allows a stable connection.
[0105] , The piezoelectric on insulator (POI) substrate 166 illustrated in step V) of Figure 3 produced by the manufacturing method according to the invention, comprises the support substrate 100, the trapping layer 102, the first barrier layer 122 for diffusion of metallic element, the dielectric layer 132, the second barrier layer 154 and the piezoelectric layer 114 and thus forms a POI substrate 166 according to the third embodiment.
[0106] , The embodiments described are merely possible configurations and it should be borne in mind that individual features of the different embodiments may be combined with each other or provided independently of each other.
Claims
Claims
1. A piezoelectric on insulator (POI) substrate comprising: - a support substrate (100), in particular a silicon-based substrate, comprising a trapping layer (102) on a free surface (104) of the support substrate (100), in particular a layer based on polycrystalline or amorphous or porous silicon - a piezoelectric layer (114), in particular a layer of Lithium Tantalate (LTO) or Lithium Niobate (LNO), - an intermediate structure (120, 120') positioned sandwiched between the piezoelectric layer (114) and the trapping layer (102) of the support substrate (100), in which the intermediate structure (120, 120') comprises at least one barrier layer (122, 122') for diffusion of a metallic element, in particular Lithium, based on Tantalum Nitride (TaN) or Silicon Carbon Nitride (SiCN).
2. The piezoelectric on insulator (POI) substrate according to claim 1, wherein the barrier layer (122, 122') has a thickness faw greater than a predetermined thickness, said predetermined thickness being determined as a function of the thickness of the trapping layer (102) such that the dose of metallic element, in particular the dose of Lithium, in the trapping layer (102) is less than a threshold dose of Lithium resulting in the degradation of the trapping layer (102), in particular a threshold dose of Lithium less than 10 12 at / cm 2 , especially less than 5.10 11 at / cm 2 .
3. The piezoelectric-on-insulator (POI) substrate according to claim 1 or 2, wherein the metal element diffusion barrier layer (122, 122') has a thickness εM of between 5nm and 150nm, in particular between 10nm and 100nm, and the thickness t pof the trapping layer (102) is between 50nm and 5pm.
4. The piezoelectric substrate on insulator (POI) according to one of the preceding claims, in which the intermediate structure (120) comprises at least one dielectric layer (132, 132'), in particular based on silicon dioxide or silicon nitride (SiN) or even silicon oxynitride (SiO x N y ), in contact with the at least one barrier layer (122, 122') for diffusion of metallic element.
5. The piezoelectric on insulator (POI) substrate according to one of the preceding claims, wherein the metallic element diffusion barrier layer (122') is sandwiched between two dielectric layers (132', 146).
6. The piezoelectric on insulator (POI) substrate according to one of the preceding claims, wherein the intermediate structure (120, 120') further comprises a second barrier layer (154, 156, 158, 160).
7. The piezoelectric on insulator (POI) substrate according to one of the preceding claims, wherein the intermediate structure (120, 120') comprises at least one layer (160) with a hydrogen concentration of less than 1O 20 at / cm 3 , especially less than 10 18 at / cm 3 .
8. The piezoelectric on insulator (POI) substrate according to claim 6 or claim 7 in combination with claim 6, wherein the second barrier layer (154, 158, 160) is a hydrogen diffusion barrier layer (156), in particular based on Silicon Nitride (SiN) or Silicon Oxynitride (SiO x N y ) or Aluminum Nitride (AIN).
9. A method of manufacturing a piezoelectric-on-insulator (POI) substrate (130, 138, 144, 152, 166) according to one of claims 1 to 8 comprising the steps of: - providing a support substrate (100), in particular a silicon-based substrate, comprising a trapping layer (102), in particular a layer based on polycrystalline or amorphous or porous silicon, - providing a substrate comprising a piezoelectric layer (106), in particular a piezoelectric layer (108) based on Lithium Tantalate (LTO) or Lithium Niobate (LNO), - forming an intermediate structure (120, 120') on the substrate comprising a piezoelectric layer (106) and / or on the support substrate (100), the formation of the intermediate structure (120, 120') comprising the formation of at least one diffusion barrier layer (122, 122') of a metallic element, in particular Lithium, based on Tantalum Nitride (TaN) or Silicon Carbon Nitride (SiCN), and - assembling the substrate comprising a piezoelectric layer (106) with the support substrate (100).
10. The method of manufacturing a piezoelectric-on-insulator (POI) substrate (152, 166) according to claim 9, wherein the step of forming the intermediate structure (120, 120') further comprises forming a second barrier layer (154, 156, 158, 160).
11. The method of manufacturing a piezoelectric-on-insulator (POI) substrate (152, 166) according to one of claims 9 or 10, wherein the step of forming the intermediate structure (120, 120') further comprises a step of forming a layer (160) with a hydrogen concentration of less than 10 20 at / cm 3 , especially less than 10 18 at / cm 3 .
12. The method of manufacturing a piezoelectric-on-insulator (POI) substrate (152, 166) according to claim 10 or claim 11 in combination with claim 10, wherein the step of forming the second barrier layer (154) comprises formation of a layer (158) based on Silicon Nitride (SiN) or Silicon Oxynitride (SiO x N y ) or Aluminum Nitride (AIN).
13. The method of manufacturing a piezoelectric-on-insulator (POI) substrate (130, 138, 144, 152, 166) according to one of claims 9 to 12, further comprising a step of forming a dielectric layer (132, 146) on the support substrate (100) and / or on the substrate comprising a piezoelectric layer (106) before the assembly step, such that the bonding interface is an oxide-oxide bonding interface.
14. The method of manufacturing a piezoelectric-on-insulator (POI) substrate (130, 138, 144, 152, 160) according to one of claims 9 to 12, further comprising a step of forming a dielectric layer (132, 146) of a first material on the support substrate (100) and / or of a second material different from the first material on the substrate comprising a piezoelectric layer (106) before the assembly step.
15. The method of manufacturing a piezoelectric on insulator (POI) substrate (130, 138, 144, 152, 160) according to claim 14, wherein the first material is based on Silicon Nitride, in particular SisN4, and the second material is based on Silicon Oxynitride (SiO x N y ), in particular SiON.