Memory cell and operation of the memory cell

Abstract

The invention relates to a memory cell which has a layer (101) for collecting charge carries at a surface of the layer (101), an electrically insulating layer (102) on the surface provided for collecting charge carriers, a low-doped, semiconducting layer (103) on the electrically insulating layer (102), a dielectric layer (106) on the low-doped, semiconductor layer (103), an electrical contact (107) which is used as a gate terminal and is located on the dielectric layer (106), an electrical contact used as a source terminal (105a), and an electrical contact used as a drain terminal (105b), wherein the dielectric layer (106) is located between the source terminal (105a) and the drain terminal (105b). The invention relates to a method for operating a memory cell of this type. The memory cell can be operated at cryogenic temperatures and can store more than two different states.

Description

[0001] Memory cell and operation of the memory cell

[0002] The invention relates to a memory cell and a method for operating the memory cell.

[0003] A conventional DRAM (Dynamic Random Access Memory) cell consists of a transistor and a capacitor (1T1C). The transistor can be a field-effect transistor. A field-effect transistor has three terminals called the source, gate, and drain. By applying a voltage to the gate terminal, an electric current can be controlled, flowing from the source terminal to the drain terminal.

[0004] Information can be stored by the capacitor. To electrically charge the capacitor for storing information, a voltage can be applied to the gate terminal. An electric current then flows through the transistor, from the source terminal to the drain terminal. This current charges the capacitor. The charged state of the capacitor can be considered a "1" state. The uncharged state of the capacitor can be considered a "0" state. Information can therefore be stored digitally using a DRAM memory cell.

[0005] The transistor, which serves as a switch, can also read the charge state of the capacitor and thus the information stored in the DRAM memory cell. The 1T1 C-DRAM has a disadvantage for high-density integration due to the large capacitor area.

[0006] SOI transistors are known from the prior art. A distinction is made between FD-SOI transistors and PD-SOI transistors. PD-SOI transistors have a relatively thick SOI layer, which can be at least 50 nm thick. FD-SOI transistors have a thin SOI layer, which can be thinner than 40 nm. FD-SOI transistors with a very thin SOI layer have a so-called "ground plain" beneath an electrically insulating layer. Such a transistor cannot store information and is therefore not a memory cell.

[0007] The object of the invention is to further develop a memory cell.

[0008] The object of the invention is achieved by a memory cell having the features of the first claim. The subordinate claim relates to a method for operating the memory cell. The dependent claims relate to advantageous embodiments.

[0009] To solve the problem, a memory cell with a layer is used to collect charge carriers on a surface of the layer. The collected charge carriers can be electrons or defect electrons. Defect electrons are also called holes. A layer is a flat mass of a substance that can be located above, below, or between something else. The length and / or width of the layer can be greater than the thickness of the layer. Collecting charge carriers such as electrons on a surface means that by applying a voltage to a designated electrical connection of the memory cell, charge carriers such as electrons can be collected on a surface of the layer.If charge carriers have been collected on a surface, then there is a surface area of ​​the layer with a higher concentration of charge carriers—for example, with a higher electron concentration—compared to adjacent areas. This surface area is then electrically charged, i.e., negatively charged in the case of electrons. An adjacent surface area can then be charged inversely, for example, positively charged due to an increased concentration of defect electrons. Collection generally occurs by applying an electric field to the layer. The layer for collecting charge carriers is generally made of a semiconductor, particularly a lightly doped semiconductor.A semiconductor is a solid with an electrical conductivity that lies between the electrical conductivity of electrical conductors and the electrical conductivity of electrical insulators, i.e., non-conductors. The electrical conductivity of a semiconductor can be less than 10. 4 S / cm and greater than 10 -8 S / cm. The electrical conductivity of a semiconductor increases with increasing temperature.

[0010] An electrically insulating layer may be present on the surface provided for collecting charge carriers. An electrically insulating layer consists of an electrically non-conductive material. The electrical conductivity of the electrically non-conductive material may be less than 10 -8S / cm. Generally, there is no intermediate layer between the electrically insulating layer and the layer for collecting charge carriers. Hafnium oxide, zirconium oxide, or aluminum oxide can form the electrically insulating material. A lightly doped, semiconducting layer can be present on the electrically insulating layer. The lightly doped, semiconducting layer can act like a channel in a transistor. The lightly doped, semiconducting layer is then formed from a semiconductor, which is doped. To dope the semiconductor, impurity atoms are introduced into the semiconductor. In the case of doping, the amount of impurity atoms is very small compared to the amount of semiconductor. The proportion of impurity atoms in the semiconductor after doping can be between 0.1 and 100 ppm, where ppm means "parts per million." The impurity atoms form defects in the semiconductor and change the electrical conductivity of the semiconductor.

[0011] A dielectric layer can be located on top of the lightly doped, semiconducting layer. "On" means that there is essentially no intermediate layer between the two layers. The dielectric layer is made of a dielectric material. This can be a dielectric material used for a gate oxide in a MOSFET. The dielectric material has a high electrical resistivity and therefore can hardly or not at all conduct electrical charge. The dielectric layer can be made of Al2O3, HfO2, ZrO2, or SiA4, for example.

[0012] An electrical contact serving as a gate terminal can be located on the dielectric layer. The dielectric layer can be located between a source terminal and a drain terminal of the memory cell. The source terminal and drain terminal each form an electrical contact of the memory cell. By applying a voltage to the gate terminal or to the gate, a current flow from the source terminal to the drain terminal can be regulated. An electrical contact consists of an electrically conductive material. The electrical conductivity of an electrical contact can be more than 10 4 S / cm. The electrically conductive material generally exhibits an overlap between the valence band and the conduction band.

[0013] Such a memory cell can be particularly small. Technology nodes of 10 nm and smaller are possible. Unlike the DRAM memory cell described above, no capacitor is required in addition to a transistor. The threshold voltage can be tuned very well when charge carriers are collected. This very good tunability can be achieved particularly when the electrically insulating layer is very thin. It is possible to store not only two states, "0" and "1," with such a memory cell, but also other states. In this sense, information can be stored in analog form, not just digitally. Such a memory cell can operate at very low, cryogenic temperatures. Such a memory cell can be part of a quantum computer, for example, a quantum computer that operates at temperatures close to 0 Kelvin, i.e., close to absolute zero.The storage cell can be operated at temperatures of less than 77 Kelvin or 77 K, for example at temperatures of a few 100 mK or at temperatures of 3 K to 8 K.

[0014] The source terminal can be separated from the dielectric layer by a highly doped semiconductor. The drain terminal can be separated from the dielectric layer by a highly doped semiconductor. The highly doped semiconductor can form a layer that is a single intermediate layer between the source terminal and the dielectric layer, or a single intermediate layer between the drain terminal and the dielectric layer. In this case, there is only the highly doped semiconductor between the source terminal and the dielectric layer, or between the drain terminal and the dielectric layer. This avoids a disadvantageous Schottky contact that makes it difficult to read information. However, the memory cell can also have a Schottky contact with a very small Schottky barrier, making it relatively easy to dispense with the separating highly doped semiconductor.

[0015] A low-doped semiconducting layer or a low-doped semiconductor is doped at least one order of magnitude or at least two orders of magnitude less than a highly doped semiconducting layer or a highly doped semiconductor.

[0016] Silicon or germanium are particularly suitable semiconductors for memory cells. Group IV or Group III-V semiconductor alloys are also particularly suitable. Examples of suitable semiconductor alloys are silicon carbide (SiC) or germanium-tin (GeSn).

[0017] The source terminal and / or drain terminal can be located directly on the electrically insulating layer. In this case, there is no intermediate layer between the electrically insulating layer and the source terminal and / or drain terminal. However, it is also possible for the source terminal to be separated from the electrically insulating layer by a highly doped semiconductor. The drain terminal can also be separated from the electrically insulating layer by a highly doped semiconductor. The highly doped semiconductor can be a single intermediate layer between the electrically insulating layer and the source terminal or drain terminal.

[0018] The dielectric layer can be thinner than 50 nm or thinner than 30 nm. The dielectric layer can be a maximum of 20 nm or a maximum of 15 nm thick. The dielectric layer can be at least 1 nm or at least 5 nm thick. A particularly thin dielectric layer can further improve some of the aforementioned properties of the memory cell.

[0019] The layer for collecting charge carriers can be the substrate of the memory cell. Substrate refers to a self-supporting layer onto which the other layers of the memory cell are applied. The substrate can be thicker than any other layer of the memory cell.

[0020] The layer for collecting charge carriers can be formed from a low-doped semiconductor.

[0021] The electrically insulating layer can be made of silicon dioxide, Sial^L, or high-k dielectrics such as HfC^, AI2O3, ZrO2, LU2O3, LaLuCh, GdScCh, LaScC.

[0022] Low-doped silicon can be used as a low-doped semiconductor.

[0023] The gate, source, and / or drain terminals may be formed of metal. The gate, source, and / or drain terminals may be formed of silicide or metallic materials such as Cu, Ni, Ti, Al, Pt, Cr, W, or TiN. The gate, source, and / or drain terminals may be formed of highly doped semiconductors.

[0024] A low-doped semiconducting layer can have a doping of not more than 1e17 cm 3 A highly doped semiconducting layer can have a doping of at least 1e18 cm -3 or at least 1e19 cm -3 A low-doped, semiconducting layer can thus be doped at least three orders of magnitude lower than a highly doped, semiconducting layer.

[0025] The memory cell can be configured so that information can be stored in the memory cell and / or information can be read out from the memory cell by applying an electrical voltage to the drain terminal, wherein the magnitude of the electrical voltage for reading out is lower than the magnitude of the electrical voltage for storing information. The magnitude refers to the distance from zero of the number for the voltage specified in volts on the number line. While information is being read out, a voltage applied to the gate terminal can be changed, for example linearly increased or linearly decreased. There is therefore a limit value. The memory state of the memory cell can be changed if the magnitude of the applied voltage is above the limit value.If a voltage is applied that is below the threshold value, the memory state of the memory cell is not changed. However, such a voltage can be used to read the memory state and thus the stored information.

[0026] The memory cell can be configured so that information can be stored in the memory cell by applying an electrical voltage to the drain terminal in the form of electrical pulses, and the stored information depends on the number of pulses. With each pulse, charge carriers are collected on the surface for collection. The number or quantity of collected charge carriers can therefore depend on the number of pulses. The memory cell can thus behave like a biological synapse. The memory cell can therefore be part of an artificial neural network.

[0027] For example, a pulse can be at least 10 ns or at least 50 ns long. For example, a pulse can be at least no longer than 100 ms or no longer than 10 ms long. The time interval between two pulses can be at least 10 ns or at least 50 ns. The time interval between two pulses can be no more than 10 s or no more than 5 s.

[0028] The memory cell can be configured so that information can be stored in the memory cell by applying a voltage to both the source terminal and the drain terminal simultaneously. This can be done in the form of one or more pulses.

[0029] The invention also relates to a method for operating the memory cell. Information is stored in the memory cell and / or information is read from the memory cell by applying an electrical voltage to the drain terminal. The magnitude of the electrical voltage for reading is lower than the magnitude of the electrical voltage for storing information. During the reading of information, a voltage applied to the gate terminal is changed.

[0030] Information in the memory cell can be erased by applying a voltage to the drain terminal whose polarity is the opposite of the polarity of the voltage used to store the information. The voltage required for erasing can be greater than the voltage required for writing, given the same pulse length. Given the same voltage, the pulse length for erasing can be greater than the pulse length for writing.

[0031] Information can be stored in the memory cell by applying an electrical voltage in the form of several electrical pulses to the drain terminal.

[0032] Information stored in a memory cell can depend on the number of pulses. In this sense, information can be stored analogously.

[0033] The memory cell can be operated at a cryogenic temperature of below -200°C or below -250°C. The lower the temperature, the better the charge carriers accumulated by storing information can be retained without the need to re-store stored information at regular intervals. It is therefore preferable for the memory cell to be operated at very low temperatures, such as near absolute zero.

[0034] The voltage applied to the drain terminal for storing and reading information can be negative if the highly doped semiconducting layer is p-doped. The voltage applied to the drain terminal for storing and reading information can be positive if the highly doped semiconducting layer is n-doped.

[0035] The invention is explained in more detail below with reference to figures. The figures show examples of possible embodiments of the invention. They show:

[0036] Figure 1: Section through a first memory cell;

[0037] Figure 2: Current-voltage curve of the memory cell;

[0038] Figure 3: Write pulse and read pulse; Figure 4: Current-voltage curves of the memory cell due to write pulses;

[0039] Figure 5: Section through the first memory cell after a write pulse;

[0040] Figure 6: Current-voltage curves of the memory cell due to erase pulses;

[0041] Figure 7: States of the memory cell due to a large number of write pulses;

[0042] Figure 8: Section through a second memory cell and corresponding electron microscope image;

[0043] Figure 9: Section through a third memory cell.

[0044] Figure 1 shows a section through a first memory cell. A substrate 101 of the memory cell is a layer for collecting charge carriers at a surface of the layer. An electrically insulating layer 102 is applied on top of layer 101. The electrically insulating layer 102 can be formed from silicon dioxide. The electrically insulating layer 102 can be very thin. The thickness of the electrically insulating layer 102 can be less than 40 nm or less than 20 nm. The electrically insulating layer 102 can be realized by "buried oxide," also known as "BOX" or "buried oxide." A layer 103 made of a low-doped semiconductor is applied on top of the electrically insulating layer 102. The low-doped, semiconducting layer 103 can be formed from low-doped silicon.The thickness of the lightly doped, semiconducting layer 103 can be less than 40 nm or less than 20 nm. A particularly thin, lightly doped, semiconducting layer 103 is preferable. Furthermore, a layer 104a or 104b, formed from a highly doped semiconductor, is applied to the top side of the electrically insulating layer 102, adjacent to both sides of the lightly doped, semiconducting layer 103. The lightly doped, semiconducting layer 103 separates one highly doped, semiconducting layer 104a from the other highly doped, semiconducting layer 104b. The highly doped, semiconducting layer 104a can, as shown in Figure 1, advantageously be thinner than the lightly doped, semiconducting layer 103. In the case of silicon, the impurity atoms boron, indium, aluminum, or gallium are considered for doping if p-type doping is to be achieved.In the case of silicon, the foreign atoms phosphorus, arsenic, or antimony can be considered for doping if n-doping is to be achieved. This also applies when germanium is used instead of silicon. On each highly doped, semiconducting layer 104a there is an electrical contact 105a or 105b. The two contacts can be made of NiSi2. One highly doped, semiconducting layer 104a is continued in an L-shape such that it separates one electrical contact 105a from the lightly doped, semiconducting layer 103. The other highly doped, semiconducting layer 104b is continued in an L-shape such that it separates the other electrical contact 105b from the lightly doped, semiconducting layer 103. A dielectric layer 106 is applied to the low-doped, semiconducting layer 103, which - as shown - can also be located on the ends of the highly doped, semiconducting layers 104a and 104b.The dielectric layer may be made of HfO2. An electrical contact 107 is applied to the dielectric layer 106. The electrical contact 107 may be made of TiN.

[0045] The electrical conductivity of the highly doped, semiconducting layers 104a and 104b is greater than the electrical conductivity of the low-doped, semiconducting layer 103 due to the higher doping.

[0046] Electrical contact 105a can serve as a source terminal. Electrical contact 105b can serve as a drain terminal. Electrical contact 107 can serve as a gate terminal. The doped layers can be p-doped.

[0047] A pulse with a negative voltage V Dof -0.3 V and a time duration of 1 ms was applied to the drain terminal 105b. No voltage was applied to the gate terminal 107 or the source terminal 105a. Following this pulse, with a delay of one second, the electric current from the source terminal 105a to the drain terminal 105b was changed depending on a time-varying voltage V applied to the gate terminal 107. DR of -0.30 volts was measured. A voltage of -0.30 V was also applied to the drain terminal 105b. No voltage was applied to the source terminal 105a. This experiment was performed with a pulse with a negative voltage V D = -1.75 V and a time length of 1 ms.

[0048] Figure 2 shows the measured current curves from the source terminal 105a to the drain terminal 105b as a function of the time-varying voltage VG applied to the gate terminal 107. On the one hand, the current-voltage curve is shown for the case where a pulse V D = -0.30 V has been applied and on the other hand a pulse V D = -1.75 V. This is a pulse voltage.

[0049] During the measurement, the voltage VG applied to the gate terminal 107 was varied linearly over time from -1.0 V to +1.0 V. From a voltage VG applied to the gate terminal 107 of -1.0 V to a voltage VG applied to the gate terminal 107 of approximately +0.14 V, the current l fell D out of 10 -4 A on 10 -14A, according to the initially arcuate curve shown in Figure 2. A voltage VG of more than 0.14 V applied to the gate terminal 107 has the measured currents l D no longer changed. The behavior of the transistor, or the electric current flowing from the source terminal to the drain terminal, therefore depended on the previous voltage pulses V D = -0.3 V and V D = -1 ,75 V does not decrease.

[0050] Figure 3 illustrates the application of a write pulse and subsequent readout of the memory cell. A pulse with a negative voltage V Dw = -2.0 V and a time duration of 1 ms was applied to the drain terminal 105b. No voltage was applied to the gate terminal 107 and the source terminal 105a during writing. The magnitude of the write pulse exceeded a limit value VT determined by tests. The limit value VWT determined by tests was between -1.75 V and -2.0 V. Following this write pulse, the current curve from the source terminal 105a to the drain terminal 105b was measured with a delay of one second as a function of a voltage VG applied to the gate terminal 107. A voltage V DR = -0.30 V is applied to the drain terminal 105b. The voltage V D R was therefore below the limit value VWT. No voltage was applied to the source terminal 105b. This experiment was repeated with further write pulses at different voltages, namely V DW = -2.25 V, V DW = -2.50 V and V Dw = -2.75 V. However, a voltage for collecting charge carriers and for storage can also be applied to the source terminal 105b, which in the example mentioned also lies between -1.75 V and -2.0 V.

[0051] Figure 4 shows the measured current waveforms of the current from the source terminal 105a to the drain terminal 105b. The comparison of the measured current waveforms with the current waveform already shown in Figure 2 for the case V D = -0.30 V shows that the application of pulsed voltages V DW = -2.00 V, V DW = -2.25 V, V D w = -2.50 V and VDW = -2.75 V changes the current flow from the source terminal 105a to the drain terminal 105b. This change is for the case V DW = -2.00 V by an added AV, which shows the change in the threshold voltage between the current waveform in Figure 2 for the case V D = -0.30 V and the current curve after application of V DW= -2.00 V. The current l D reached the current of 10 -14 A only when a voltage VG of approximately 0.33 V is applied to the gate terminal 107. Figure 4 further illustrates that the current waveform after application of write pulses V DW also depends on the magnitude of the voltage. The larger the magnitude of the voltage V DW was, the greater was AV and the voltage VG that was needed so that the current l D the current of 10 -14 A. This means that the memory cell can store several different states. In this sense, the memory cell enables multi-state logic and, in this sense, analog storage of information.

[0052] Figure 5 illustrates the technical background for the case where a write pulse V DWis applied and no voltage is applied to the source terminal 105a and no voltage to the gate terminal 107 when the magnitude of the write pulse V DW the amount of the limit value V WT Such a write pulse V DW Charge carriers are generated, with the result that electrons accumulate at the top side of substrate 101 beneath the lightly doped, semiconducting layer 103. For this reason, the top side of substrate 101 includes a surface or surface area for collecting charge carriers. This surface area is important for storing information because it changes the behavior of the memory cell's transistor.

[0053] Below the drain terminal 105b, electron holes also accumulate at the top of the substrate 101. Therefore, there is a second surface area where charge carriers accumulate. This second area is not important for storing information, since it does not, or at least practically does not, influence the behavior of the transistor.

[0054] If the temperature of the memory cell is close to absolute zero, this prevents the electrons from recombinating with the holes in a timely manner. The information is then stored virtually permanently. It is therefore advantageous to operate the memory cell at very low temperatures. At very low temperatures, the substrate is frozen and behaves like an electrical insulator or at least like an electrical resistor. The region near 102 has a so-called "floating-body effect." This means that this region is not connected to a conductive layer and can therefore accumulate charges.

[0055] The information stored in this way can be erased by an erase pulse VDE, which differs from the write pulse V DW by polarity. If a write pulse V DW= -x [V] is applied, the information stored thereby can in principle be erased again by an erase pulse VDE = (x+y) [V], where x>0 and y > 0. The erase pulse causes a recombination of the previously collected charge carriers. Erasing can therefore be achieved by first reading the state of the memory cell and then achieving a recombination of collected charge carriers with a pulse of appropriate length and / or magnitude with appropriate polarity. The magnitude of the pulse refers to the electrical voltage in volts. Erasing is illustrated in Figure 6. A 1 ms long write pulse with a voltage V DW -2.75 V was applied to the drain terminal 105b. The dashed line shows the resulting current-voltage curve relative to the current-voltage curve with V D= -0.3 V, which was measured before a write pulse. Later, a 1 ms erase pulse VDE was applied to the drain terminal 105b. Three such experiments were conducted with three different erase pulses: VDE = 2.0 V, VDE = 2.2 V, and VDE = 3.0 V. Figure 6 shows that complete erasure was only achieved with a voltage of VDE = 3.0 V.

[0056] Figure 7 shows the effect on a current l D from the source terminal 105a to the drain terminal 105b at a predetermined gate voltage VG when write pulses V DW = -2.5 V with a length of 100 ns with a time interval of 100 ns to the drain terminal 105b. Figure 7 shows the electrical current l D depending on the number of pulses. In addition, Figure 7 shows the voltage curve V Dat the drain terminal 105b over time t. The temperature of the memory cell was 5.5 K. Figure 7 shows that the current l D increases with the number of pulses, following an arc-shaped pattern. The memory cell thus behaved like a biological synapse.

[0057] Figure 8 shows a cross-sectional view of a second memory cell. This differs from the memory cell shown in Figure 1 in the absence of an intermediate layer between the electrically insulating layer 102 and the electrical contacts 105a and 105b. A section of such a physically manufactured memory cell, taken with an electron microscope, is also shown.

[0058] Figure 9 shows a cross-sectional view of a third memory cell, which may comprise an SOI, also known as a "silicon-on-insulator." An electrically insulating layer 101b is located on a substrate 101a. A layer 101 for collecting charge carriers is located on the electrically insulating layer 101b. The substrate 101a may be made of silicon. The electrically insulating layer 101b may be buried oxide, i.e., a "BOX." The layer 101 for collecting charge carriers may be the uppermost silicon layer of the SOI component. Figure 9 shows a described state. Thus, charge carriers are collected in the layer 101 for collecting charge carriers, which is indicated by the and "+" signs. The advantage of this structure is that it increases the operating temperature, since 101 has a floating-body effect even at room temperature. In principle, it can operate as a memory at room temperature.

[0059] In one embodiment, the source terminal is located directly or indirectly on the electrically insulating layer. In one embodiment, the drain terminal is located directly or indirectly on the electrically insulating layer. If a terminal is located indirectly on a layer, there are in particular one or more intermediate layers between the terminal and the layer. In one embodiment, the layer for collecting charge carriers is not located directly on a gate terminal.

[0060] In one embodiment, the charge carrier collection layer and / or the substrate of the memory cell is electrically insulated from the ground. In one embodiment, the memory cell comprises an electrically insulating layer on the backside of the charge carrier collection layer and / or the substrate. The backside is typically the side facing away from the electrically insulating layer on the surface provided for charge carrier collection. This makes it possible to store the stored charges in the charge carrier collection layer or in the substrate at room temperature for a significantly longer time, for example, several days. This is useful, for example, in "neuromorphic hardware," such as technical systems based on neural systems and / or analog memories. "Neuromorphic hardware" requires residence times of more than one hour, which is possible even at room temperature thanks to this design.The device, for example, with a thin buried oxide layer, can also be used as an image sensor. Exposure to light creates holes and / or electrons in the substrate, which also changes the switching voltage and / or current of the transistor. The combination of optics and memory can further expand the device's applications.

[0061] A further aspect of the invention is a light and / or image sensor, in particular with a layer for collecting charge carriers on a surface of the layer, in particular with an electrically insulating layer on the surface provided for collecting charge carriers, in particular with a lightly doped, semiconducting layer on the electrically insulating layer, in particular with a dielectric layer on the lightly doped, semiconducting layer, in particular with an electrical contact serving as a gate terminal on the dielectric layer, in particular with an electrical contact serving as a source terminal, in particular with an electrical contact serving as a drain terminal, wherein the dielectric layer is located in particular between the source terminal and the drain terminal. All features, advantages, and configurations of the above-mentioned memory cell also apply to the image sensor and vice versa.

Claims

Claims 1. A memory cell comprising a layer (101) for collecting charge carriers on a surface of the layer (101), an electrically insulating layer (102) on the surface provided for collecting charge carriers, a lightly doped, semiconducting layer (103) on the electrically insulating layer (102), a dielectric layer (106) on the lightly doped, semiconducting layer (103), an electrical contact (107) serving as a gate terminal on the dielectric layer (106), an electrical contact serving as a source terminal (105a), and an electrical contact serving as a drain terminal (105b), the dielectric layer (106) being located between the source terminal (105a) and the drain terminal (105b).

2. Memory cell according to the preceding claim, characterized in that the source terminal (105a) is separated from the dielectric layer (106) by a highly doped semiconductor (104a) and / or the drain terminal (105b) is separated from the dielectric layer (106) by a highly doped semiconductor (104b).

3. Memory cell according to one of the preceding claims, characterized in that the source terminal (105a) is separated from the electrically insulating layer (102) by a highly doped semiconductor (104a) and / or the drain terminal (105b) is separated from the electrically insulating layer (102) by a highly doped semiconductor (104b).

4. Memory cell according to one of the preceding claims, characterized in that the dielectric layer (106) is at most 20 nm or at most 15 nm thick or at most 10 nm.

5. Memory cell according to one of the preceding claims, characterized in that the layer (101) for collecting charge carriers is the substrate of the memory cell.

6. Memory cell according to one of the preceding claims, characterized in that the layer (101) for collecting charge carriers is formed from a low-doped semiconductor and / or that the electrically insulating layer is made of silicon dioxide, silicon nitride, hafnium oxide, Zirconium oxide or aluminum oxide is formed and / or that low-doped silicon is used as the low-doped semiconductor and / or that the gate, source and / or drain terminal (105b) are formed from silicide or Al, Cu, Cr, W, TiN.

7. Memory cell according to one of the preceding claims, characterized in that the memory cell is configured such that information can be stored in the memory cell and / or information can be read out from the memory cell by applying an electrical voltage to the drain terminal (105b), wherein the amount of the electrical voltage for reading out is lower than the amount of the electrical voltage for storing information.

8. Memory cell according to one of the preceding claims, characterized in that a low-doped, semiconducting layer has a doping of at most 1e17 cm -3 and / or that a highly doped semiconducting layer has a doping of at least 1e18 cm -3 has.

9. Memory cell according to one of the preceding claims, characterized in that the memory cell is arranged so that information can be stored in the memory cell by applying an electrical voltage to the drain terminal (105b) in the form of electrical pulses, and the stored information depends on the number of pulses.

10. A method for operating a memory cell according to one of the preceding claims, characterized in that information is stored in the memory cell and / or information is read out from the memory cell by applying an electrical voltage to the drain terminal (105b), the amount of the electrical voltage for reading out being lower than the amount of the electrical voltage for storing information.

11. Method according to the preceding claim, characterized in that information in the memory cell is erased by applying a voltage to the drain terminal (105b) whose polarity is reversed to the polarity of the voltage for storing information.

12. Method according to one of the two preceding claims, characterized in that information is stored in the memory cell by applying an electrical voltage in the form of several electrical pulses to the drain terminal (105b).

13. Method according to the preceding claim, characterized in that information stored in the memory cell depends on the number of pulses.

14. Method according to one of the preceding method claims, characterized in that the memory cell is operated at a temperature of less than 200 K or less than 10 K.

15. Method according to one of the preceding method claims, characterized in that the voltage applied to the drain terminal (105b) for storing information and for reading out information is negative if the highly doped, semiconducting layer (104) and (101) is p-doped and that the voltage applied to the drain terminal (105b) for storing information and for reading out information is positive if the highly doped, semiconducting layer (104) and (101) is n-doped.

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