Readout circuit for infrared detector

Abstract

The invention relates to a readout circuit for an infrared detector, comprising: a pixel array circuit, each pixel comprising a capacitance, referred to as an integration capacitance; a memory unit having a memory location for each pixel of the array circuit. The readout circuit is configured to acquire an image from the infrared detector for a duration, referred to as the frame time, by iteratively implementing the following steps: an integration step in which the integration capacitances are charged with photoelectrons from the infrared detector for a duration, referred to as the elementary integration time, the elementary integration time being configured such that the respective charges of the integration capacitances remain lower than a maximum allowable charge; a storage step in which, for each pixel, the amount of charge of the respective integration capacitance at the end of the elementary integration time is added to a value stored in the memory location corresponding to the pixel; a step of resetting the integration capacitance to the initial state; and, at the end of the frame time, by transmitting image data comprising the values stored in the memory locations of the memory unit.

Description

DESCRIPTION Title of the invention: Reading circuit for infrared detector

[0001] The invention relates to the field of infrared detectors and in particular a reading circuit for an infrared detector, an image acquisition device comprising an infrared detector and a reading circuit according to the invention.

[0002] Generally, in the field of infrared imaging, an image acquisition device comprises an optical focusing system, which will combine an observed scene with an infrared detector, and thus project an image of the scene onto the detector. An example of an image acquisition device 10 is partially represented in FIG. 1.

[0003] Infrared detection is performed by an infrared detector 12 which is typically a quantum or photonic detector. The infrared detector 12 comprises a semiconductor material sensitive to the radiation λ to be detected. The detection principle is based on the photoelectric effect within the semiconductor material, which therefore performs a transducer function by converting a photonic flux into a current. The semiconductor material may be a small gap semiconductor material such as indium antimonide InSb or mercury-cadmium telluride HgCdTe 12b, associated with a substrate 12a made of cadmium-zinc telluride CdZnTe. The semiconductor material may also be a meta-material such as a type 2 superlattice, or a multi-quantum well material. The detector 12 is structured as a matrix of pixels, each pixel forming a photosensor which is intended to detect an element of the image. The size of the pixel is of the order of a few micrometers.Typically, it is between 5 and 30 pm on each side. The plane formed by the pixel matrix is ​​generally called the focal plane. To enable the generation of signals by the detector 12 and their processing, it is necessary to associate a reading circuit 16 with it. The reading circuit 16 also comprises a matrix circuit. Each pixel of the detector 12 is then connected to a respective pixel of the reading circuit 16 by a connection matrix 14. Such a connection matrix 14 can be made of indium beads and obtained by a hybridization process. The reading circuit 16 can be made using CMOS (Complementary Metal Oxide Semiconductor) technology. During operation of the image acquisition device, each pixel of the detector 12. absorbs the incident photons and releases a proportional quantity of electrons which will be processed by the reading circuit 16.

[0004] Figure 2 gives a simplified electrical representation of the imaging device 10. Electrically, a pixel of the detector 12 has a photodiode 120 function. The corresponding pixel 160 of the reading circuit 16 makes it possible to bias the photodiode 120 to allow the generation of photoelectrons. It also ensures the accumulation of charges from the photodiode 120. The reading circuit 16 uses these accumulated charges to determine a light value of the element of the image detected by the corresponding pixel of the detector 12. The duration of accumulation of the charges in the reading circuit is called the integration time. The pixel 160 of the reading circuit 16 notably comprises an OINT capacitor, called the integration capacitor, which makes it possible to convert the quantity of charges into voltage. The pixel 160 comprises other components allowing it to perform sample-and-hold functions and reset the integration capacitor.The charge integration phase is followed by a phase of reading the information stored in the pixel 160 of the reading circuit 16.

[0005] The matrix circuit of the reading circuit 16 comprises a plurality of rows and columns, for example 512 rows and 640 columns of pixels. The reading phase is then made possible by an addressing system using multiplexers 162, 166 making it possible to address the pixels, row by row and column by column. Generally, the processing of the pixels is carried out by groups of pixels processed in parallel. Thus, for example, pixels belonging to the same row can be processed in parallel. For this purpose, each column of the matrix circuit of the reading circuit 16 comprises a row multiplexer 162 configured to select a pixel from the column. During the addressing operation, at least some of the row multiplexers 162 operate in parallel to select a respective pixel from the same row. All the pixels of the same row can be processed in parallel.Alternatively, some of the pixels in the same row are processed in parallel. A column multiplexer 166 then makes it possible to select the column(s) of the matrix circuit 160 concerned by this parallel processing. The signal from each pixel is then amplified by an amplifier circuit 164. In particular, there is one amplifier circuit 164 per column. The signal from pixel 160 can then be made available at output 168 of the reading circuit 16. Generally, the level. of pixel 160 is converted into digital data by an analog / digital converter. The analog / digital converter is located in particular at the end of the column, or at output 168 or outside the reading circuit 16. In infrared imaging applications, the digital data is in particular coded on 14 bits.

[0006] At the scale of the reading circuit 16, at the end of the integration time, the information stored in the pixels, namely the charge level or the voltage of the integration capacitor, is transmitted to output 168 for a reconstruction of the image detected by the detector 12. In particular, in the acquisition of a video, the images are successively acquired periodically. The period between two successive images is in particular the frame time.

[0007] In optimal operation, the noise in the signal is mainly due to background radiation. Infrared detectors are then referred to as BLIP detectors (for “Background Limited Infrared Photodetector”). The dominant noise is then linked to shot noise, which is intrinsic to the quantum nature of light. This is Poisson noise, meaning that it increases with the root of the signal. The signal-to-noise ratio is therefore proportional to the root of the signal.

[0008] In the case of an infrared image acquisition device, to increase the signal received by the detector 12, it is possible to adjust the optical parameters, for example the spectral band, the transmission, the aperture, the pixel pitch, the quantum efficiency. Once these electro-optical conditions are fixed, the only way to increase the signal is to increase the integration time. The signal-to-noise ratio is at best proportional to the root of the integration time. The longer the integration time, the better the signal-to-noise ratio. In an ideal video system, the integration time is limited by the chosen video rate, namely the frame time. Thus, imaging at 100 Hz allows a maximum integration time of 10 ms. It is then necessary to ensure that the maximum storable charge associated with the integration capacity of a pixel is sufficient to accumulate the signal during the integration time.However, the achievable integration capacity is limited by the pixel surface.

[0009] For some wavelengths λ, the photon flux is too large for the integration capacity CINT - It is not large enough to integrate all the electrons generated by the photons during the frame time. This is particularly the case for radiation in the atmospheric transmission band, known as long wavelength or band 3. This radiation typically has a spectral band ranging from 8 to 14 pm. This leads to a reduction in the integration time and therefore to a degradation of the signal-to-noise ratio and thus the sensitivity of the image acquisition device.

[0010] Patent application publication WO2015 / 016991 and patent publication EP2687020 describe a solution consisting of allowing full charges of the integration capacitor during the integration time. The integration capacitor is discharged each time. A count of the number of charge cycles is carried out, allowing the quantity of charges received during the integration time to be counted. This solution overcomes the constraint linked to the maximum charge storable by the integration capacitor. However, it requires that an analog-digital conversion, namely counting, be carried out in the pixel. To maintain a limited pixel size, very advanced and expensive technologies, for example CMOS, are required, which degrade the industrial profitability of infrared imaging devices. In addition, the power consumption per pixel is higher than that of a conventional readout circuit.This is particularly penalizing in constrained environments, such as an infrared image detection application in a cryogenic environment.

[0011] A simple and relatively low-consumption solution is therefore sought to overcome the maximum acceptable load by an integration capacity during the integration time.

[0012] To this end, the invention provides a reading circuit for an infrared detector, comprising: i. a pixel matrix circuit, each pixel comprising a capacitance, called an integration capacitance; ii. a memory unit having a memory location for each pixel of the matrix circuit; and said reading circuit being configured to acquire an image from the infrared detector for a duration, called frame time, by iteratively implementing the following steps: i. an integration step in which the integration capacitors are charged with photoelectrons from the infrared detector for a duration, called elementary integration time, said elementary integration time being configured so that the respective charges of the integration capacitors remain lower than a maximum admissible charge; ii. a storage step in which, for each pixel, the quantity of charge of the respective integration capacitor at the end of the elementary integration time is added to a value stored in the memory location corresponding to the pixel; iii.a step of resetting the integration capacity; and, at the end of the frame time, transmitting image data comprising the values ​​stored in the memory locations of the memory unit. For a number N of iterations, the total integration time is equal to N times the elementary integration time.

[0013] In the reading circuit according to the invention, the quantity of electrical charge stored by the integration capacitor over the elementary integration time remains lower than the maximum admissible charge. Thus, unlike the prior art, there are no full charge cycles during the elementary integration time. However, over a frame time, a high signal value can be obtained because the charges obtained during several successive elementary integrations are added together. The invention therefore makes it possible to improve the signal-to-noise ratio, without modifying the circuit of a pixel of a conventional reading circuit. Unlike the prior art, the pixel is notably devoid of analog / digital conversion means within it. Thus, the pixel circuit is simplified and consumes less than the previously mentioned prior art, while allowing an improved signal-to-noise ratio.

[0014] According to one embodiment, the reading circuit comprises: i. at least one analog / digital converter configured to, in the storage step, convert the charge quantity of the integration capacitor into a digital value; and ii. at least one adder configured to, in the storage step, add said digital value to the value stored in the memory location corresponding to the pixel.

[0015] According to one embodiment, the analog / digital converter and / or the adder are shared by a set of pixels of the matrix circuit.

[0016] According to one embodiment, the reading circuit is configured such that, at the first execution of the integration and storage steps in frame time, the initial value stored in the memory locations of the memory unit is zero.

[0017] According to one embodiment, the reading circuit is configured to, before the steps implemented iteratively, implement the following steps: i. an integration step in which the integration capacitors are charged with photoelectrons from the infrared detector during the elementary integration time; ii. a storage step in which, for each pixel, the charge quantity of the respective integration capacitor at the end of the elementary integration time is stored in the memory location corresponding to the pixel; iii. a step of resetting the integration capacitor to the initial state.

[0018] According to one embodiment, the reading circuit is configured to, in the frame time, shift the values ​​stored in the memory locations as a function of a displacement of an image formed on the infrared detector.

[0019] The invention also relates to an infrared image acquisition device intended to acquire at least one image of a scene, comprising: i. an infrared detector forming a matrix detector having a plurality of pixels, said infrared detector being configured to receive the at least one image of said scene; ii. a reading circuit according to the invention, configured to process signals received from the infrared detector representative of the at least one image.

[0020] According to one embodiment, the infrared image acquisition device further comprises a scanning device configured to scan the scene in a direction, such that the image of the scene moves on the infrared detector during the frame time; said reading circuit being configured to shift the values ​​stored in the memory locations as a function of the movement of the image on the detector.

[0021] The invention also relates to a cryostat comprising an infrared image acquisition device according to the invention.

[0022] The invention further relates to a method for acquiring images using a device comprising an infrared detector and a reading circuit which comprises a pixel matrix circuit, each pixel comprising a capacitance, called an integration capacitance; and a memory unit having a memory location for each pixel of the matrix circuit, said method comprising for a duration, called a frame time, the iterative implementation of the following steps: i. an integration step in which the integration capacitances are charged with photoelectrons from the infrared detector for a duration, called an elementary integration time, said elementary integration time being configured so that the respective charges of the integration capacitances remain below a maximum admissible charge; ii.a storage step in which, for each pixel, the charge quantity of the respective integration capacitance at the end of the elementary integration time is added to a value stored in the memory location corresponding to the pixel; and iii. a step of resetting the integration capacitance; said method further comprising, at the end of the frame time, a transmission of image data comprising the values ​​stored in the memory locations of the memory unit.

[0023] Other characteristics and advantages of the present invention will appear more clearly on reading the description which follows in relation to the following appended figures: [Fig. 1]: Figure 1, already described, shows an image acquisition device according to the prior art; [Fig. 2]: Figure 2 shows a simplified electrical diagram of the image acquisition device illustrated in Figure 1; [Fig. 3]: Figure 3 shows an example of a reading circuit according to the invention; [Fig. 4]: Figure 4 is a block diagram illustrating an example of a method according to the invention; [Fig. 5]: Figure 5 is a timing diagram illustrating the example process; [Fig. 6]: Figure 6 shows another example of a reading circuit according to the invention. Figure 3 illustrates an example of an infrared image acquisition device 20 according to the invention, in which only a reading circuit 26 is shown. The reading circuit 26 is associated with an infrared detector known per se, the pixels of which produce photoelectrons under the effect of infrared radiation. By having a photodiode type operation, each pixel of the detector supplies a current to a respective pixel of a matrix circuit 262 of the reading circuit 26. The pixel of the matrix circuit 262 may comprise a P-MOS or N-MOS type transistor for biasing the photodiode.

[0024] The matrix circuit 262 forms a matrix of pixels. The pixels are arranged in columns and rows, in particular across the entire matrix circuit 262. The matrix circuit 262 may be produced using CMOS technology. The pixel includes an integration capacitor that will accumulate the electrical charges produced by the corresponding pixel of the detector. In particular, in a manner known per se, each pixel includes other components such as a sampling-blocking and resetting device for the integration capacitor. A first addressing system 263, such as a multiplexer, makes it possible in particular to access a pixel of the matrix circuit 262.

[0025] The reading circuit 26 further comprises a memory unit 264 which has a memory location for each pixel of the matrix circuit 262. The memory unit 264 is for example a dynamic memory, such as a DRAM (Dynamic Random Access Memory) or static memory, such as SRAM (Static Random Access Memory). A second addressing system 265 makes it possible in particular to access a memory location of the memory unit 264. In particular, the memory unit 264 forms a monolithic unit within the reading circuit 26. Thus, unlike the prior art, the memory locations are not inside the pixel, but in a single separate unit. This removes a constraint on the size of the pixel.

[0026] The readout circuit 26 may include an analog-to-digital converter 268 that converts a charge quantity Q Ai accumulated in the integration capacity during the elementary integration time into a representative numerical value Ai.

[0027] The reading circuit 26 comprises in particular an adder 266 which receives as input the value Ai representative of the charge accumulated in the integration capacitor during an elementary integration time, and adds it with the current value An already stored in the memory unit 264. The value An corresponds to a value representative of a quantity of charge obtained at the end of a previous elementary integration time. The result of this addition operation is stored in the memory unit 264.

[0028] The reading circuit 26 forms in particular an integrated electronic circuit. Its elements are in particular assembled on the same electronic chip.

[0029] At the end of a frame time, the last value A stored in the memory location is transmitted to the output of the reading circuit 26.

[0030] Figure 4 illustrates the steps implemented by the reading circuit 26 during an acquisition of an image for a duration, called frame time. In a step 310, the integration capacitors of the pixels are charged with photoelectrons from the respective pixels of the infrared detector. The accumulation of charges is carried out for a duration, called elementary integration time. The elementary integration time is chosen so that the respective charges of the integration capacitors remain lower than a maximum charge admissible by the integration capacitors. Thus, unlike the prior art, a complete charge of the integration capacitor is not permitted. Then, during a step of storage 320, the charge reached by the integration capacity at the end of the integration step 310 is added to the value stored in the memory location corresponding to the pixel. The integration capacity is then reset to the initial state to be available for the next elementary integration time.

[0031] These steps 310, 320 are repeated during the frame duration. At the end of the frame time, image data comprising the values ​​stored in the memory locations of the memory unit 264 are made available at the output of the reading circuit 26.

[0032] Thus, during an image acquisition during the frame time, the reading circuit 26 locally accumulates in the memory unit 26 intermediate images, called “thumbnails”, which are added together to form the image transmitted as output by the reading circuit 26 at the end of the frame time. In particular, each thumbnail is formed at the end of an elementary integration time. It is added together with a thumbnail already stored in the memory location and replaces this old thumbnail in the memory unit 264.

[0033] In particular, at the start of the frame time, at the first execution of the integration 310 and storage 320 steps, the initial value stored in the memory locations is zero. So that at the end of the first integration 310 and storage 320 steps, the value stored in the memory location corresponding to the pixel is the amount of charge of the integration capacity obtained at the end of the first elementary integration step. This initiation of the image acquisition can be implemented differently. For example, during the first storage step in the frame time, the addition operation is inhibited. The value stored in the memory location corresponding to the pixel is then the amount of charge of the integration capacity obtained at the end of the first integration step.

[0034] Figure 5 shows a timing diagram illustrating this succession of elementary integration times in the reading circuit 26. In the following description, we will focus on one pixel, knowing that it applies to all the pixels of the matrix circuit 262. The first line represents an INT signal for activating the integration 310, the second a SH-RAZ signal for activating the resetting of the charge of the integration capacitor to the initial state, the third a CONV signal for activating the analog / digital conversion, the fourth an ACC-TDI signal for activating the storage of the value in the memory unit 264, the fifth an INT2 signal for acquiring the image A, B, the sixth line a LECT signal for transmitting the image A, B to the output of the reading circuit 26.

[0035] An image A is acquired during the duration of Frame Tr. For this purpose, a succession of imagettes A1, A2, A3, A4, A5 are detected one after the other and progressively added to each other. In particular, in a first elementary integration time Tji, a first charge QAI is accumulated in the integration capacitor during an integration step 310. The integration capacitor of the pixel is progressively charged by the photoelectrons coming from the corresponding pixel of the detector. In particular, during a step 312, the voltage of the integration capacitor is read to determine the quantity of charges received during the elementary integration time T i1 ;and the integration capacitance is reset to the initial state to allow a successive integration 310 of another image A2. In a step 320a, the quantity of charge QAI accumulated in the integration capacitance can be converted into a representative digital value A1. Then, in a step 320b, the quantity of charge of the integration capacitance, in particular the representative digital value A1, at the end of the elementary integration time, is added to a value stored in the memory unit 264 at the memory location corresponding to the pixel of the matrix circuit 262.

[0036] During the first storage step 320 of the frame time Tr, the value initially stored in the memory location is preferably zero.

[0037] Alternatively, during the first storage step 320 of the frame time Tr, the addition operation is disabled and the digital value A1 is stored directly in the memory location of the memory unit 264.

[0038] Then the following numerical values ​​A2, A3, A4, A5 are obtained and progressively added and stored in the memory location corresponding to the pixel. At the end of the last elementary integration time T i5 for image A, the last value stored in the memory location is transmitted to the output of the reading circuit 26. This last value is the image data A for the total integration time T int in the frame time Tr. This total integration time Tint is defined by the relation: [Math] T int = N x T i

[0039] Where N is the number of successive elementary integration times Tj in the frame time Tr.

[0040] Similarly, other B, C images are acquired and transmitted. As shown, some steps may occur at least partially in parallel when possible, in order to save processing time.

[0041] In particular, each memory location is preferably greater than or equal to 19 bits in order to allow an accumulation of N=2 5 =32 thumbnails. The signal-to-noise ratio of image A is then improved by a factor of N compared to a single thumbnail.

[0042] Figure 6 illustrates an example of an embodiment of the reading circuit 36. The reading circuit 36 ​​is similar to that illustrated in Figure 3, except for the addressing system 365 of the memory unit 264. In this reading circuit 36, the addressing of the memory locations may undergo an offset D, for example a row and / or column offset. Such an offset D is a function of a displacement of an image formed on the detector. Such a reading circuit 36 ​​is particularly advantageous for an image acquisition device comprising a scanning device, in particular an opto-mechanical scanning unit, as disclosed for example in published patent applications FR2830339 or FR3112229.

[0043] The offset D is notably applied during the storage step 320. The offset D may be less than or equal to 10% of the number of lines or columns. For example, if the scanning direction extends along the columns of the matrix detector, each line of the scene will be seen by several lines of the matrix detector. The offset D corresponds to the scanning. The acquisition of the image A on several pixels makes it possible to reduce the fixed spatial noise. Such spatial noise is inherent to infrared technologies and corresponds to a dispersion and / or a response shift between the pixels. Typically, this spatial noise can be reduced by the use of a pixel uniformity correction table (or NUC for “Non Uniformity Correction”). However, there still remains a residual fixed spatial noise which is generally decorrelated from pixel to pixel. The exemplary reading circuit 36 ​​according to this embodiment makes it possible to process the image obtained by scanning in a simplified manner compared to the prior art. The acquisition of a point of the scene by M different pixels makes it possible to reduce the residual spatial noise by a factor M.

[0044] The operation of the read circuit 26, 36 has been explained in relation to a pixel. In the schematic representations of Figures 3 and 6, a single analog / digital converter 268 and a single adder 266 are shown. However, in a manner known per se, the processing of the pixels can be carried out in parallel for a group of pixels. The read circuit 26, 36 can thus comprise a plurality of analog / digital converters 268 and a plurality of adders 264. In particular, the processing of the pixels can be carried out row by row. The read circuit 26, 36 can comprise one analog / digital converter 268 per column, or analog / digital converters 268 each shared by a respective set of columns. In the latter case, a multiplexer can be used to assign one analog / digital converter 268 to several columns.Similarly, the read circuit 26, 36 may comprise one adder 266 per analog / digital converter 268, or adders 266 each shared by a respective set of analog / digital converters 268. In the latter case, a multiplexer may be used to assign one adder 266 to several analog / digital converters 268.

[0045] The reading circuit 26,36 makes it possible to detect an image in a simple manner with an improved signal-to-noise ratio and reduced consumption compared to the prior art. An image acquisition device comprising the reading circuit 26,36 is particularly advantageous for use in a cryostat. Indeed, infrared detectors operate at cryogenic temperature, in particular at 70k or 80K, and even below 70K for components sensitive to long wavelengths between 8 and 14pm. The cryostat is typically cooled by a cryogenic cooling device, generally based on a Stirling cycle or by pressure wave. The electrothermal efficiency of such a cooling device is generally low.

[0046] For example, a cryostat includes a conventional infrared image acquisition device, which operates at a temperature of approximately 70 K. The The reading circuit consumes approximately 50 mW. The cooling device consumes 5 W at an external ambient temperature of 20°C, and twice as much at an ambient temperature of 70°C. An equivalent cryostat having a detector using a reading circuit adapted to reduce noise as in the prior art consumes approximately 1 W. This corresponds to a consumption of the cooling device of the order of 100 W. Such consumption for cooling makes this device difficult to use in the majority of cryostats, unlike the reading circuit 26,36 which has a lower power consumption.

Claims

CLAIMS 1. A reading circuit (26, 36) for an infrared detector, comprising: i. a pixel matrix circuit (262), each pixel comprising a capacitance, called an integration capacitance; ii. a memory unit (264) having a memory location for each pixel of the matrix circuit (262); and said reading circuit (26, 36) being configured to acquire an image (A, B) from the infrared detector for a duration, called a frame time (Tr), by iteratively implementing the following steps, for each pixel: i. an integration step (310) in which the respective integration capacitance is charged with photoelectrons from the infrared detector for a duration, called an elementary integration time (Tj), said elementary integration time (Tj) being configured such that the charge of the integration capacitance remains below a maximum admissible charge; ii. a step (320a), in which the charge quantity (QA i) accumulated in the integration capacitance at the end of the elementary integration time (Tj) is converted into a representative digital value (Ai); iii. a step (320b), in which the digital value (Ai) representative of the charge quantity (QAI) of the integration capacitance, at the end of the elementary integration time (Ti), is added to a value stored in the memory unit (264) at the memory location corresponding to the pixel of the matrix circuit (262); iv. a step of resetting the integration capacitance to the initial state to allow a successive integration (310) of another digital value; digital values ​​(A1, A2, A3, A4, A5) being obtained and progressively added and stored in said memory location corresponding to the pixel; and, at the end of the frame time (Tr), transmitting image data (A, B) comprising the values ​​stored in the memory locations of the memory unit (264); the circuit being further configured to, in the frame time (Tr), shift the values ​​stored in the memory locations according to a displacement of an image formed on the infrared detector.

2. Reading circuit (26,36) according to claim 1, comprising: i. at least one analog / digital converter (268) configured to, in the storage step (320), convert the charge quantity of the integration capacitor into a digital value; and ii. at least one adder (266) configured to, in the storage step (320), add said digital value to the value stored in the memory location corresponding to the pixel.

3. Reading circuit (26,36) according to the preceding claim, in which the analog / digital converter (268) and / or the adder (266) are shared by a set of pixels of the matrix circuit (262).

4. Reading circuit (26,36) according to any one of the preceding claims, configured so that, at the first execution of the steps of integration (310) and storage (320) in the frame time (Tr), the initial value stored in the memory locations of the memory unit (264) is zero.

5. Read circuit (26, 36) according to one of claims 1 to 3, configured to, before the steps implemented iteratively, implement the following steps: i. an integration step (310) in which the integration capacitors are charged with photoelectrons from the infrared detector during the elementary integration time (Tj); ii. a storage step (320) in which, for each pixel, the charge quantity of the respective integration capacitor at the end of the elementary integration time (Ti) is stored in the memory location corresponding to the pixel; iii. a step of resetting the integration capacity to the initial state.

6. Infrared image acquisition device (20) intended to acquire at least one image of a scene, comprising: i. an infrared detector forming a matrix detector having a plurality of pixels, said infrared detector being configured to receive the at least one image of said scene; ii. a reading circuit (26, 36) according to any one of the preceding claims, configured to process signals received from the infrared detector representative of the at least one image.

7. Infrared image acquisition device (20) according to the preceding claim, further comprising a scanning device configured to scan the scene in a direction, so that the image of the scene moves on the infrared detector during the frame time (Tr), said reading circuit (36) being configured to shift the values ​​stored in the memory locations as a function of the movement of the image on the detector.

8. Cryostat comprising an infrared image acquisition device (20) according to claim 6 or 7.

9. A method for acquiring images using a device (20) comprising an infrared detector and a reading circuit (26, 36) which comprises a pixel matrix circuit (262), each pixel comprising a capacitance, called an integration capacitance; and a memory unit (264) having a memory location for each pixel of the matrix circuit (262), said method comprising for a duration, called a frame time (Tr), iteratively implementing the following steps, for each pixel: i. an integration step (310) in which the respective integration capacitance is charged with photoelectrons from the infrared detector for a duration, called an elementary integration time (Tj), said elementary integration time (Tj) being configured so that the charge of the integration capacitance remains lower than a maximum admissible charge; ii. a step (320a), in which the amount of charge (Q Aj) accumulated in the integration capacity at the end of the elementary integration time (Tj) is converted into a representative digital value (Ai) iii. a step (320b), in which the digital value (Ai) representative of the charge quantity (QAI) of the integration capacity, at the end of the elementary integration time (Ti), is added to a value stored in the memory unit (264) at the memory location corresponding to the pixel of the matrix circuit (262); and iv.a step of resetting the integration capacity to the initial state to allow a successive integration (310) of another digital value; digital values ​​(A1, A2, A3, A4, A5) being obtained and progressively added and stored in said memory location corresponding to the pixel; said method further comprising, at the end of the frame time (Tr), a transmission of image data (A, B) comprising the values ​​stored in the memory locations of the memory unit (264); and in the frame time (Tr), a shift of the values ​​stored in the memory locations as a function of a displacement of an image formed on the infrared detector.

Images