System and method for mapping of spiking neural networks on neuromorphic processor

Abstract

A method for mapping a spiking neural network design onto a configurable neuromorphic processor, the method comprising: defining a resource model describing the neuromorphic processor, defining a network definition file describing the spiking neural network design, wherein the further method comprises: dividing the neurons of the network definition file into one or more partitions, each partition comprising a portion of the neurons from one of the layers; selecting one of the partitions; selecting an available one of the planes of the resource model, wherein a number of neurons of the plane is equal to or greater than a number of neurons in the selected partition; and mapping the neurons of the selected partition to the neurons of the selected plane of the resource model, wherein a neuron of the selected partition is mapped to a neuron of the selected plane if the neuron of the selected plane has available interconnections matching the interconnections to the neuron of the selected partition.

Description

System and method for Mapping of Spiking Neural Networks on Neuromorphic processorTECHNICAL FIELD

[0001] The presented disclosure is in the field of spiking neural networks, in particular the hardware implementation of spiking neural networks on hardware accelerators like neuromorphic chips, in particular the hardware implementation is performed by a mapping algorithm.BACKGROUND

[0002] The concept of mapping refers to configuring a hardware accelerator, such as a neuromorphic chip, to perform network inference tasks efficiently and reliably. Network inference involves using a trained neural network model to make predictions or classifications based on input data. However, executing neural network inference on specialized hardware like neuromorphic chips requires careful configuration to ensure optimal performance and accuracy.

[0003] The mapping process involves addressing various challenges that arise when deploying neural network inference on hardware accelerators.

[0004] The hardware accelerator may have limitations in terms of memory, computational resources, and power consumption. Mapping may involve optimizing the neural network model to fit within these constraints while maintaining performance. Efficient data movement between different components of the hardware accelerator is crucial for minimizing latency and maximizing throughput. Mapping may thus also involve designing data flow patterns that minimize data movement overhead. Mapping may furthermore involve selecting or designing algorithms that are suitable for execution on the hardware accelerator architecture. This may involve algorithmic optimizations to exploit the parallelism or specialized features of the hardware. Different neural network architectures may have different requirements and characteristics when deployed on hardware accelerators. Mapping may thus also involve selecting or designing network topologies that are well-suited for efficient execution on the target hardware.

[0005] Overall, the goal of the mapping process is to enable reliable and efficient execution of neural network inference on hardware accelerators, taking into account the constraints and characteristics of the underlying hardware architecture.

[0006] The concept of mapping can thus be defined as the process of configuring the hardware accelerator (e.g. implemented as a neuromorphic chip) to run network inference. The mapping process aims to solve certain problems that will be encountered when a neural network inference needs to run on the hardware such that reliable inference can be achieved.

[0007] However, certain problems need to be solved when performing mapping.

[0008] For example, neurons connected to other neurons via synapses in a neural network should be connected in the hardware such that the neurons can send spikes to each other. Under certain special conditions, hardware should be configured such that spike traffic from off chip to the neuromorphic hardware array should not be hindered. Users of mapping may have desirable preferences to use hardware accelerated functions such as encoders, decoders, et cetera. Furthermore, users of mapping may have configured their neural networks such that neurons and synapses have specific properties that can be mapped to only certain types of hardware neurons and synapses. Finally, the mapping may require optimization for dynamic power consumption, latency between neurons on the chip.

[0009] Inside the hardware, the components are restricted to a certain number and they are inter-connected in a specific way. This is termed as the chip’s architecture. Such architectures, generally, can have restrictions while configuring them to run the network. These restrictions may arise out of the connectivity of the components, as well as due to run time requirements of the hardware. Moreover, users of the hardware will require to further tune the hardware configuration based on the requirement of the neural network model. Thus, the problems that this process solves are heavily specific to the target architecture.SUMMARY OF INVENTION

[0010] In order to solve the above, the inventors of the present invention realized that the mapping process requires complete representation of the hardware architecture in software, as well as a way to represent neural networks in a generic way. In addition, the process must consist of an algorithm that must have at least the following requirements. Namely, the algorithm should be able to map sparsely connected networks as well as fully connected networks in a short amount of time. Also, the algorithm should identify any hardware constraints, if any, and aim to find a mapping solution for the network by avoiding these constraints. Finally, the algorithm should be able to identify if there are any conflicts resulting out of the hardware constraints which should result in the mapping not being possible.

[0011] The invention comprises a computer-implemented mapping system and computer- implemented mapping method for more efficiently configuring a hardware accelerator (neuromorphic chip) or for generating a configuration file to be used for configuring a hardware accelerator. The mapping system and method generates the configuration for the hardware accelerator based on a definition of a neural network to be implemented in the hardware accelerator, providing an improved configuration of the hardware accelerator which enables the hardware accelerator to run the desired neural network inference more efficiently.

[0012] In order to solve the aforementioned problems, the subj ect-matter of the present claims is proposed. Below certain aspects of the invention will be described.

[0013] In a first aspect of the present invention, a method for mapping a spiking neural network design onto a configurable neuromorphic processor is disclosed. The method may comprise at least one of the following steps: defining a resource model describing the neuromorphic processor, wherein the resource model defines one or more planes, each plane comprising a plurality of presynapses, synapses and spiking neurons arranged in a sub-network, wherein each presynapse is adapted to receive one or more inputs and each neuron has an output, and each synapse connects one of the presynapses to one of the neurons, and wherein the resource model defines a plurality of interconnections for connecting an output of one of the neurons of one of the planes to one or more of the presynapses of one of the planes; defining a network definition file describing the spiking neural network design, wherein the network definition file defines a plurality of neurons interconnected by a plurality of synapses, wherein the neurons are arranged in layers, each neuron in one of the layers being connected to one or more neurons in the same or another one of the layers.

[0014] The method may further comprise at least one of the following steps: dividing the neurons of the network definition file into one or more partitions, each partition comprising a portion of the neurons from one of the layers; selecting one of the partitions; selecting an available one of the planes of the resource model, wherein a number of neurons of the plane is equal to or greater than a number of neurons in the selected partition; and mapping the neurons of the selected partition to the neurons of the selected plane of the resource model, wherein a neuron of the selected partition is mapped to a neuron of the selected plane if the neuron of the selected plane has available interconnections matching the interconnections to the neuron of the selected partition.

[0015] In an embodiment of the first aspect, selecting an available one of the planes further comprises selecting a plane for which a number of inputs to the neurons of the plane is equal to or greater than a number of inputs to the neurons of the selected partition.

[0016] In an embodiment of the first aspect, selecting an available one of the planes further comprises selecting a plane for which a number of external inputs to the neurons of the plane is equal to or greater than a number of external inputs to the neurons of the selected partition, for which a number of recurrent inputs to the neurons of the plane is equal to or greater than a number of recurrent inputs to the neurons of the selected partition.

[0017] In an embodiment of the first aspect, mapping the neurons of the selected partition comprises allocating one of the neurons of the selected plane to one of the neurons of the selected partition, and allocating an interconnection to the allocated neuron of the selected plane if the neuron of the selected partition has a corresponding interconnection.

[0018] In an embodiment of the first aspect, if an interconnection to the allocated neuron of the selected plane corresponding to an interconnection to the neuron of the selected partition cannot be found or has already been allocated, allocating a different neuron of the selected plane to the neuron of the selected partition.

[0019] In an embodiment of the first aspect, allocating an interconnection to the allocated neuron of the selected plane comprises allocating an external input to the allocated neuron of the selected plane if the neuron of the selected partition has an external input, and allocating a recurrent input to the allocated neuron of the selected plane if the neuron of the selected partition has a recurrent input.

[0020] In an embodiment of the first aspect, allocating an interconnection to the allocated neuron of the selected plane comprises allocating a connection via an interconnect to the allocated neuron if the neuron of the selected partition has an input from a neuron in a different partition.

[0021] In an embodiment of the first aspect, allocating an interconnection to the allocated neuron of the selected plane comprises removing a synapse input to the allocated neuron of the selected plane if the neuron of the selected partition does not have a corresponding synapse input.

[0022] In an embodiment of the first aspect, the method further comprises defining a set of mapping constraints which describe potentially conflicting interconnections in the resource model.

[0023] In an embodiment of the first aspect, the set of mapping constraints comprises an indication of quantity and types of interconnections to neurons in a partition of the network definition file.

[0024] In an embodiment of the first aspect, the set of mapping constraints comprises an indication of quantity of interconnections between neurons of different partitions of the network definition file.

[0025] In an embodiment of the first aspect, indicating one of the planes of the resource model as unavailable if the neurons of the selected partition are successfully mapped to the neurons of the selected plane.

[0026] In an embodiment of the first aspect, selecting another plane of the resource model if the neurons of the selected partition are not successfully mapped to the neurons of the previously selected plane.

[0027] In an embodiment of the first aspect, the method further comprises merging a partition of the network definition file with another partition of the network definition file if the number of partitions exceeds a number of planes in the resource model.

[0028] In a second aspect of the present invention, a system for mapping a spiking neural network design onto a configurable neuromorphic processor is disclosed. The system may comprise at least one of the following: a first memory for storing a resource model describing the neuromorphic processor, wherein the resource model defines one or more planes, each plane comprising a plurality of presynapses, synapses and spiking neurons arranged in a subnetwork, wherein each presynapse is adapted to receive one or more inputs and each neuron has an output, and each synapse connects one of the presynapses to one of the neurons, and wherein the resource model defines a plurality of interconnections for connecting an output of one of the neurons of one of the planes to one or more of the presynapses of one of the planes; a second memory for storing a network definition file describing the spiking neural network design, wherein the network definition file defines a plurality of neurons interconnected by a plurality of synapses, wherein the neurons are arranged in layers, each neuron in one of the layers being connected to one or more neurons in another one of the layers.

[0029] Furthermore, the system may comprise a processor configured to perform at least one of the following steps: divide the neurons of the network definition file into one or more partitions, each partition comprising a portion of the neurons from one of the layers; select one of the partitions; select an available one of the planes of the resource model, wherein a number of neurons of the plane is equal to or greater than a number of neurons in the selected partition;and map the neurons of the selected partition to the neurons of the selected plane of the resource model, wherein a neuron of the selected partition is mapped to a neuron of the selected plane if the neuron of the selected plane has available interconnections matching the interconnections to the neuron of the selected partition.BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Embodiments will now be described, by way of example only, with reference to the accompanying drawings in which corresponding reference symbols indicate corresponding parts, and in which:

[0031] FIG. 1 schematically shows the overall flow of the mapper compiling an exemplary network to an exemplary processor;

[0032] FIG. 2 schematically shows the flow of the operations in the mapper;

[0033] FIG. 3 schematically shows the software for representing the hardware architecture in a generic way;

[0034] FIG. 4 schematically shows the high-level algorithm of the (for example greedy) mapping algorithm.DESCRIPTION OF EMBODIMENTS

[0035] Hereinafter, certain embodiments will be described in further detail. It should be appreciated, however, that these embodiments should not be construed as limiting the scope of protection for the present disclosure.

[0036] In this section, a system and method for mapping neural-network-based applications to a domain specific Al accelerator are described, wherein the mapping is easily adaptable to different neuromorphic chip architectures and is capable of mapping different types of neural networks to the given chip architectures.

[0037] FIG. 1 schematically shows the overall flow 10 of the mapper compiling an exemplary network 1 to an exemplary processor 5. The target processor, which is Al hardware, may be an Al hardware accelerator chip. In particular, the processor may be a spiking neural network processor. For example, the Al hardware accelerator chip may be an Al hardware accelerator chip as produced by Innatera Nanosystems BV, such as the Spiking Neural Processor T1.

[0038] In this example, a neural network is defined in a software development kit (SDK) and the mapper in the SDK generates a hardware configuration of the neural network that can be used as input to configure a spiking neural network processor or a simulator that uses thisconfiguration to run network inference. For example, the SDK may be the Talamo Software Development Kit produced by Innatera Nanosystems BV.

[0039] The SDK 2 takes as input a network definition 1. The network definition 1 comprises a graph of the spiking neural network one wants to implement in the target processor 5. The network definition 1 may further comprise extra information about the neurons and the synapses making up the spiking neural network. The network definition 1 may comprise a description of the overall structure of the SNN, including the number of neurons, their connectivity, and the types of connections between them (e.g., feedforward, recurrent). Furthermore, the network definition 1 may comprise a description of the neuron models used in the SNN, including their dynamics, spiking behaviour, and parameters such as membrane potential threshold, refractory period, and synaptic weights. Different types of neurons (e.g., integrate-and-fire, leaky integrate-and-fire) may have different computational requirements and hardware implementations. The network definition 1 may further comprise a specification of the synaptic dynamics and plasticity mechanisms used in the network, including parameters such as synaptic weights, time constants, and learning rules (e.g., spike-timing-dependent plasticity). This information guides the implementation of synaptic connections and plasticity mechanisms in the hardware. Furthermore, the network definition 1 may optionally comprise a description of the input stimuli or sensory data that the network will process, including their format, encoding scheme, and temporal characteristics. This helps determine how sensory information is presented to the network and how it influences neuronal activity. The network definition 1 may further comprise a specification of the desired operational mode of the network, such as inference, learning, or a combination of both. Different modes may require different computational resources and memory configurations in the hardware.

[0040] The SDK 2 may optionally be provided with a definition of the performance metrics or objectives that the mapping process should optimize for, such as accuracy, throughput, energy efficiency, or latency. This helps guide the mapping algorithm in selecting the most appropriate hardware configurations and optimization strategies. These performance metrics or objectives can be spiking neural network or target processor 5 specific.

[0041] Furthermore, the SDK 2 may be provided with information about the hardware constraints and characteristics of the target neuromorphic processor, such as available memory, processing elements, interconnectivity, and power consumption.

[0042] The SDK 2 comprises a mapper 2A which performs the mapping of the spiking neural network on to the target processor. This mapping can be performed either offline or online.

[0043] The SDK 2 outputs a set of instructions 3 to deploy the spiking neural network on the target processor 5. This set of instructions 3 can for example be a binary file used to configure the target processor 5. Optionally, the set of instructions 3 can be used to configure a hardware aware simulator that simulates the target hardware.

[0044] The configuration of the target processor can be performed in an exemplary manner by setting the synaptic weights that connect the present neurons standard to zero, and the set of instructions provides an instruction to set a synaptic weight for a synaptic element connecting two neurons to a particular non-zero value if a connection between these two neurons is determined to be required by the mapper.

[0045] FIG. 2 schematically shows the flow 20 of the operations in the mapper.

[0046] The mapper plays the role of enablement of co-alignment between software and hardware, as well as translation of the SNN onto the hardware. The flow of operations in the mapper is described in this embodiment. The present invention proposes two important components of the mapping system: (1) hardware architecture representation in software, and (2) the (for example greedy) mapping algorithm.

[0047] A configuration file 21, also sometimes referred to as a ‘arch config’ file can describe important parameters about the specified hardware architecture. The information may be represented in the form of some essential properties of the hardware such as number of neurons, number of synapses, number of segments, etc. This input can be configured by users and desired architecture properties can be input to the configuration file 21.

[0048] Next, the hardware resource model 23 is initialised and elaborated using the architecture configuration file as a one-time operation, by configuring 22 the hardware resource model. A hardware resource model is a representation of the computational and / or memory resources available on the target hardware platform. This model provides detailed information about the characteristics and capabilities of the hardware architecture, which is essential for optimizing the mapping process. For example, as shown multiple segments or cores 23D may be present in the target hardware, each having presynapses 23A (for example arranged in a column), a synaptic elements 23B (for example arranged in a synaptic matrix) and neurons 23 C (for example arranged in a row).

[0049] The hardware resource model typically includes several key components. First of all, a description of the computational elements available on the neuromorphic processor may be present, such as processing cores, neuromorphic synapses, and specialized accelerators. This may include details about the types of operations supported by each computational unit, theircomputational throughput, and any limitations or constraints on their usage. Secondly, a specification of the memory hierarchy of the hardware platform, including on-chip memory (e.g., registers, caches) and off-chip memory (e.g., DRAM) may be available. This includes details about memory sizes, access latencies, and bandwidth limitations, which influence data movement and storage during neural network execution. Thirdly, a description of the interconnection network or fabric that connects different computational units and memory elements within the hardware platform may be available. This includes details about communication bandwidth, latency, and routing algorithms, which affect data exchange and synchronization between processing elements. Fourthly, information about power consumption and energy efficiency characteristics of the hardware platform may be available, including power budgets, thermal constraints, and / or energy consumption profiles for different operations. This may be important for optimizing the mapping to minimize energy consumption and maintain thermal stability. Fifthly, a specification of the programming model and interface for interacting with the hardware platform may be available, including APIs, libraries, and development tools. This includes details about how neural network models are represented, compiled, and executed on the hardware, as well as any constraints imposed by the programming environment.

[0050] In particular, the hardware resource model may comprise information about the neurons and synapses making up the spiking neural network, or any other neurosynaptic core, present in the target processor.

[0051] Thus, the hardware resource model may comprise a description of the types of neurons supported by the neurosynaptic core, such as integrate-and-fire neurons, leaky integrate-and- fire neurons, or more complex neuron models. Furthermore, it may comprise a specification of the parameters associated with each neuron type, including membrane potential threshold, reset voltage, refractory period, and spike dynamics. Information about the total number of neurons supported by the core and any limitations on the number of neurons that can be active simultaneously may also be present. Furthermore, the hardware resource model may comprise details about how neuron dynamics are implemented in hardware, such as the integration of input currents, calculation of membrane potentials, and generation of spikes.

[0052] With respect to the synapses of the spiking neural network, the hardware resource model may detail a description of the types of synapses supported by the neurosynaptic core, including static synapses, dynamic synapses, and plastic synapses with various learning rules. Furthermore, a specification of the parameters associated with each synapse type, such assynaptic weights, time constants for synaptic dynamics, and plasticity parameters may be given. Information about the total number of synapses supported by the core and any limitations on the number of synapses that can be active simultaneously can be given. Finally, for example details about how synapses are connected between neurons, including the architecture of the synaptic matrix or connectivity fabric may be detailed by the hardware resource model.

[0053] Specifics as to the available memory for the spiking neural network may also be given by the hardware resource model. For example, a description of the memory resources dedicated to storing neuron state variables, such as membrane potentials and spike timings, for each neuron in the core. Another example may be the specification of the memory resources dedicated to storing synaptic weights and other synaptic parameters, including the size and organization of the synaptic weight matrix. Also, memory access characteristics such as information about memory access latencies, bandwidth, and access patterns for reading and writing neuron and synapse state information may be given.

[0054] The hardware resource model may also detail how interconnects and communication is arranged on the target hardware. For example, with respect to neuron-synapse connectivity, details about the interconnection network or routing fabric used to connect neurons and synapses within the core, including communication bandwidth and latency, may be given. Finally, also inter-core communication information about communication interfaces for exchanging spike events or synaptic updates between multiple neurosynaptic cores in a multicore system may be detailed.

[0055] The hardware resource model may also detail certain power and energy characteristics. For example, a description of the power consumption profile associated with neuron and synapse operations, including idle power, dynamic power, and any power-saving mechanisms may be given. Also, metrics related to the energy efficiency of neuron and synapse operations, such as energy per spike or energy per synaptic update may be given.

[0056] The mapping algorithm 26 takes as further input the neural network graph that needs to be implemented into the hardware which the hardware resource model 23 corresponds to. The network definition 24 can be used to obtain network partitions and / or network layers 25.

[0057] The user sets the network definition (for example a network graph) in order to solve a particular problem. Such a network graph can be layer-based, wherein the layers can be defined by the user. These layers can be divided into partitions (sub-networks). The partitions have to be mapped to the planes of the hardware chip. This mapping generally comes at a cost, for example power consumption, area usage on the chip, et cetera.

[0058] After the hardware resource model 23 has been initialised and configured 22 on the basis of the configuration file 21, the mapping algorithm 26 iterates through various layers or partitions 25 of the given neural network graph 24 and uses the hardware resource model 23 to query 27 for available hardware resources and the validity of connectivity between the resources.

[0059] The mapping algorithm 26 in this process consumes certain resources to “map” the network layers or partitions onto some portions of the hardware architecture only if the selected resources can satisfy the requirements of the network graph partition. In that case, the resource model is updated 28 based on the selection. If it cannot satisfy the requirements, the mapping algorithm 26 continues to search for other hardware resources until the requirements can be satisfied and the network graph partition can successfully maintain its structure using the selected hardware resources.

[0060] The mapping algorithm 28 finishes once the mapping algorithm finds an appropriate hardware configuration that can maintain the structure of the given neural network graph and can execute the inference of the network.

[0061] The hardware resource model is the target hardware’s architecture representation in the mapper software. This hardware representation in the mapper software is important for scalability and maintainability of the software and can be adaptable to diverse hardware architectures. It also represents modularity, such that feature additions of the hardware can be added to the hardware representation without modifying the mapping algorithm. The hardware architecture can be understood as a set of hardware resources and the connectivity between the resources.

[0062] FIG. 3 schematically shows the software for representing the hardware architecture in a generic way. The main objective of this software component is to represent the hardware architecture such that different architectures can be explored by the user. This means that the software can create different types of resource models given any architecture, albeit with some restrictions.

[0063] First, basic assumptions considered in an exemplary resource model are discussed below.

[0064] In the exemplary neuromorphic architecture, a fundamental commonality (1) could be that a neuron is connected to another neuron via a synapse that resides on a “presynapse” which is essentially a wire connection. This wire connection, i.e. presynapse, can hold multiple synapses which subsequently connect to neurons as destination. Another fundamentalcommonality (2) could be that neuron-to-neuron connections are via specific presynapses. The correct presynapse needs to be chosen in order to make it possible to connect one particular neuron to another particular neuron, within the hardware architecture’s constraints. This property assumes pre-determined information from the hardware architects about the target hardware’s architecture. Another assumption (3) could be that every neuron, synapse and presynapse is assumed to belong to a particular “segment” or core that houses these local resources. Any neuron that requires communication with another neuron in another segment requires to go through an “interconnect” which behaves like a bus connecting two segments. This interconnect must lie external to a segment. As another option, one takes the output of a neuron of a first segment and maps this output to a particular presynapse of a second segment, and one programs this presynapse to connect to the second neuron also present in the second segment, via a particular synapse. One thus maps the output Another assumption (4) could be that a neuromorphic array of the neuromorphic architecture may hold one or more segments. Another important underlying commonality (5) could be the notion of “planes”. A set of synapses and neurons and presynapses could lie in certain “planes” or i.e. sections that are confined to a specific “segment”. A "plane" can be defined as a specific layer or subset of neurons within the network. SNNs often consisting of multiple layers of neurons, with connections (synapses) between them. Each layer can be thought of as a plane of neurons, with connections between planes representing synaptic connections. Each layer of neurons in the SNN can occupy a specific position within the network's architecture. The position of a plane can be defined by its depth within the network, with input layers typically at the bottom and output layers at the top. Within each layer, neurons are typically arranged in a two-dimensional grid or array. This arrangement can define the plane of neurons within that layer. Each layer of neurons within an SNN may serve a specific functional role, such as processing input, extracting features, or generating output. The boundaries of a plane can be defined by its specific functional role within the network. Another assumption (6) might be that input channels receiving spikes from the external world can make use of multiple presynapses to connect to other neurons. The number of presynapses for a single input channel can be predetermined information from the hardware architects. Another assumption (7) might be that there might always be presynapses originating from neurons to route spikes to other neurons. These presynapses may be classified into two exemplary types: “interconnect” and “loopback”. The loopback presynapses 37A are assumed to route spikes to other neurons resided in thesame segment as the origin neuron. The interconnect presynapses 37B are assumed to route spikes to other neurons resided in other segments external to the segment of the origin neuron.

[0065] Using one or more of the above assumptions, the resource model can be initialised. The resource model is populated along with the assumptions, using the architecture configuration file.

[0066] In the present embodiment, hardware resource model 30 comprises a segment array container 31, which is a container comprising an array of segments. The segment array container 31 can represent the entirety of the target hardware for which the resource model is made, it is an abstraction of the target hardware. In other words, the segment array container 31 comprises one or multiple segment containers 32 (satisfying assumption 4 given above). The segment array container 31 may comprise further information including the number of segments, the hardware chip name and a list of segments present in the hardware.

[0067] The segment container 32 is a container comprising an array of segment plane containers 33. A segment plane container 33 represents a “plane” lying within a segment (satisfying assumption 5 given above). The number of planes in a segment is configured via the architecture configuration. A segment container 32 may comprise further information 32A including the segment identification, the number of segment planes, the number of neurons, the number of presynapses, the number of synapses, the number of presynapses per plane, the segment coordinate and / or the number of neurons per plane.

[0068] The segment plane container 33 may comprise further information 33A including the segment plane identification, and the neurons, presynapses and synapses comprised within the plane the segment plane container 33 represents (the latter three are represented by neuron container 34, presynapse container 35 and synapse container 36 respectively).

[0069] A neuron container 34 can comprise information 34A on the neuron identification, the position of the neuron, i.e. where the neuron is placed, source synapses 37C connected to the neuron, loopback presynapses 37A connected to the neuron, interconnect presynapses 37B connected to the neuron, the threshold of the neuron, the capacitance of the neuron, the neuron switch configuration, the refractory period of the neuron, and / or the associated segment identification. The neuron identification can be a parameter that assigns a unique identifier to each neuron in the network. It allows for the identification and tracking of individual neurons within the network. The position of the neuron may specify the spatial coordinates or location of the neuron within the network. It can include information about the neuron's position relative to other neurons or within a specific segment or core. The source synapses 37C connected tothe neuron may be the synaptic connections originating from other neurons and targeting the neuron in question. These synapses transmit signals (spikes) from presynaptic neurons to the postsynaptic neuron. Loopback presynapses 37A connected to the neuron are connections that project from the neuron itself back onto itself. These connections can contribute to recurrent or feedback dynamics within the network. Interconnect presynapses 37B connected to the neuron may refer to connections from neurons in other segments or cores that target the neuron. These connections allow for communication between different parts of the network. The threshold is a parameter that determines the level of membrane potential a neuron must reach for it to generate an action potential (spike). When the membrane potential surpasses this threshold, the neuron fires. Capacitance refers to the ability of the neuron's membrane to store electrical charge. It influences how the membrane potential of the neuron changes in response to synaptic inputs and determines the neuron's response dynamics. The neuron switch configuration may describe whether the neuron is currently active or inactive. In some cases, neurons may be dynamically switched on or off based on network activity or specific conditions. The refractory period of the neuron is a period of time after a neuron fires an action potential during which it is temporarily unable to generate another action potential. It prevents neurons from firing too rapidly and regulates the timing of spikes. Finally, the associated segment identification may specify the segment or core to which the neuron belongs (i.e., the segment identification of the segment container 32).

[0070] A neuron can thus have a set of emerging loopback presynapses 37A as well as a set of interconnect presynapses 37B (satisfying assumption 7 and assumption 3 respectively). The specific number of loopback and interconnect presynapses 37A, 37B for a neuron is configured via the architecture configuration.

[0071] A presynapse container 35 can comprise information 35 A on multiple destination synapses 38B (satisfying assumption 1) related to the presynapse the presynapse container 35 represents. The number of synapses that the presynapse container 35 can hold can be configured using information from the input architecture configuration. A presynapse should have a source neuron 38A and at least one destination synapse 39B (the latter being connected to a particular neuron), as it acts as the “wire” connecting paths between the neurons (satisfying assumption 2). The number of neurons that it connects to can be configured using information from the architecture configuration.

[0072] The presynapse container 35 can comprise information 35 A such as for example a presynapse identification, the position of the presynapse (i.e., where the presynapse is placed),the destination synapses 38B connected to the presynapse, the source neuron 38A connected to the presynapse and the associated segment identification. Presynapse identification may assign a unique identifier to each presynapse within the network. It allows for the identification and tracking of individual presynapses and their properties. Similar to the position of neurons, the position of the presynapse may specify the spatial coordinates or location of the presynapse within the network. It can include information about the presynapse's position relative to other elements, such as neurons or segments. The destination synapses 38B connected to the presynapse can be the synapses originating from the presynapse and targeting specific postsynaptic neurons. These synapses transmit signals (spikes) from the presynaptic neuron to the postsynaptic neuron. The source neuron 38A connected to the presynapse may specify the neuron from which the presynapse receives input. It identifies the source of signals that the presynapse transmits to the postsynaptic neuron. The associated segment identification, similar to the associated segment identification for neurons, may specify the segment or core to which the presynapse belongs.

[0073] A synapse has a source presynapse 39A as described earlier and a destination neuron 39B since a spike goes directly from a synapse to a neuron. The corresponding synapse container 36 thus also may comprise information 36A on these structures. The synapse container may comprise information 36A for example on the row identification and the column identification of the synapse matrix in which the represented synapse is comprised (or more general, information on a location of the synapse within the hardware), the position of the synapse (i.e., where the synapse is placed), the weight of the synapse, the source presynapce connected to the synapse, the destination neuron 39B connected to the synapse, and / or the associated segment identification. The row identification and column identification may specify the location of the synapse within the hardware, often referring to its position within a synapse matrix. The row identification indicates the row in which the synapse is located, while the column identification indicates the column. This information helps in addressing and accessing the synapse within the network architecture. The position of the synapse, similar to the position of neurons and presynapses, may specify the spatial coordinates or location of the synapse within the network. It can include information about the synapse's position relative to other elements, such as neurons or presynapses. The weight of the synapse may represent the strength or efficacy of the connection between the presynaptic neuron and the postsynaptic neuron. It determines the influence of presynaptic activity on the postsynaptic neuron's membrane potential and is crucial for synaptic plasticity and learning within the network. Thesource presynapse 39A connected to the synapse specifies the presynapse from which the synapse receives input. It identifies the source of signals transmitted by the synapse to the postsynaptic neuron. The destination neuron 39B connected to the synapse may specify the postsynaptic neuron targeted by the synapse. It identifies the neuron that receives signals transmitted by the synapse originating from the presynaptic neuron. The associated segment identification, similar to neurons and presynapses, may specify the segment or core to which the synapse belongs.

[0074] The interconnect as one can see from this example need not be modelled separately since it is quite straightforward and a simple one-to-one connection using wires (presynapses) between neurons.

[0075] The inherent assumption 6 can be internally embedded in the legal connectivity check between resources which is part of the “queryResourceModel” API module, the API module 3 IB being for example present in the segment array container 31. This hardware assumption is called “multicasting”. The query API module queries the resource model, for a given partition, layer, or for the entire network for example that is fed as an argument to the query, and it is checked whether the argument can be mapped onto the resource mode and returns the components of the resource model that can be used to map the given argument onto. These components can be for example neurons, synapses, presynapses, planes, segments and / or the entire chip. It is assumed that input spikes arriving from the external world can be copied onto a set of presynapses that will transport these spikes to a range of synapses. The “updateResourceModel” is an API module that reserves the resources that have been claimed by the mapping algorithm as consumed. It is a module that interacts between the mapping algorithm and the resource model. Its functionality is to receive the information of resources that should be reserved and the module reserves those resources. The “buildResourceModel” API module can also be comprised in the segment array container 31 and can be used to build the resource model, by creating a hardware graph based on the hardware constraints, number of components (neurons, synapses, presynapses, planes, segments, et cetera). Another function could be “revertResourceModel”, which is an API module that can revert the resource model back to a previous state if a particular mapping try was unsuccessful.

[0076] FIG. 4 schematically shows the high-level algorithm of the (for example greedy) mapping algorithm.

[0077] Prior to the algorithm, it assumes that the resource model is initialised with the architecture configuration and that the neural network is parsed appropriately into a formalgraph representation. Parsing a neural network into a formal graph representation involves representing the network's components (neurons, synapses, etc.) as nodes and the connections between them as edges in a graph. An exemplary method is given below.

[0078] As a first step, the components of the neural network such as neurons, synapses, presynapses, postsynapses, segments, and any other relevant elements should be identified which should be represented in the graph. Next, a node should be created for each component identified in step 1. Assign a unique identifier to each node to distinguish them from one another. The nodes can be for example neurons A, B, et cetera. Next the edges need to be defined, by determining the connections between the network components and representing them as edges in the graph. For example, if neuron A is connected to neuron B via a synapse, create an edge between the nodes representing neurons A and B. Optionally, one can assign attributes to the edges to represent properties such as the weight of synapses, the type of connection, or any other relevant information. Using a graph data structure or a graph representation library (such as for example NetworkX in Python), one construct the graph based on the nodes and edges defined in the previous steps.

[0079] An exemplary graph is shown in the embodiment, with layers 0-1 indicated with reference numeral 119 and layers 1-2 indicated with reference numeral 120.

[0080] As an optional pre-cursor step before the mapping algorithm 100 is used, for a given neural network, the mapper 100 might use a “network analyzer” which essentially parses different properties of the neural network graph and checks against the connectivity properties of the hardware architecture. If there is any property of the network graph which is not compatible with the properties of the hardware architecture, the user cannot go any further and the mapping process declares the network as incompatible to run network inference on the hardware.

[0081] The mapping algorithm 100 starts with forming graph partitions in step 101. If requested by the user to partition according to network layers, the algorithm creates partitions by layers. The next step 102 is sorting the partitions. Sorting partitions implies finding the order in which the partitions will be selected for mapping onto the hardware configuration. In step 103, a particular partition P is taken to map onto the hardware. In step 104, the partition is split into fragments. Thus, for a given partition P, firstly the algorithm breaks them down into fragments. Each fragment consists of one neuron with all their incoming edges (also known as synapses). An exemplary fragment (indicated by a dashed triangle) is shown with reference numeral 121.

[0082] For each fragment, the mapping algorithm may find the source nodes of these edges. If the source nodes are already successfully mapped, the algorithm finds valid paths such that the aforementioned incoming edges are mapped to appropriate synapses. As long as the valid path is not found, the loop iterates by requesting different components from the hardware resource model. If the source nodes are already successfully mapped and no valid paths are found to connect to the neuron, the loop exits and goes back to find a partition that does not have any mapped source nodes.

[0083] As an example, in step 105 legal components to place are found. One can perform Boolean constraint checking 105 A with a history 106 of visited nodes or components. The algorithm stores a history 106 of visited resources such that the algorithm does not search for resources which have already been traversed and checked for valid connectivity. In step 107, it is checked whether there are not enough legal components so that placement can occur. If the answer is no, one goes back to finding legal components to place, if the answer is yes, one the mapping algorithm accumulates components for every fragment in step 108. Resource model is built and updated in step 110A based on the accumulated components for every fragment of the partition from step 108, based on the architecture configuration 109 and / or based on calibration data 110.

[0084] The role of “calibration data” may arise from a need to preserve the accuracy of the neural network inference on the hardware. If the neural network runs with faulty or nonfunctioning resources, the inference accuracy could reduce drastically. Thus, it might be important in certain cases for the mapper to receive information about resources that should not be considered during the mapping process. The resource model could for example already reserve these resources that should not be considered as used and prevents the algorithm from using them and adding them to the mapping configuration. In this way for example, those nonfunctioning resources are not used to run the network inference.

[0085] Thus, the hardware resources are accumulated per fragment in step 108 to gather all resources for the entire partition. Next, the algorithm queries these accumulated resources to the resource model 111 in step 112 for checking if these requested resources can be mapped by preserving the graph partition structure.

[0086] Thus, a query is made whether the mapping has been completed successfully. If the answer is yes, one updates the resource model in step 112A and one moves to the next partition in step 112B. Updating the resource model can be done using the updateResource API module and the mapping configuration is populated accordingly.

[0087] Once the partition mapping is thus successful, it moves on to the subsequent partition in step 112B in the given sorted order. If all partitions were able to be mapped successfully in step 112D, it generates a mapping configuration 114 and exits. The generated mapping configuration 114 can be used to generate a mapped JSON file which can be used to set the configure the hardware such that it corresponds to the found mapping by the mapping algorithm 100.

[0088] The mapping model 113 is a abstracted model of the mapping outputted by the mapping algorithm of the network definition onto the hardware resource model.

[0089] If the loop unsuccessfully attempts to map a partition for a particular amount of attempts (for example 100-1000 attempts, preferably 100-500 attempts, more preferably 100- 200 attempts) in step 116 by going back to the first partition 117 in step 102 (for example by trying in a different order to map the partitions, or performing a new partitioning of the neural network), the algorithm exits in step 118 and declares that the neural network cannot be mapped to the hardware. The algorithm analyses the result of querying the resource model and concludes if the request for those resources to map the partition was successful.

[0090] Note that features of any of the embodiments disclosed herein may be combined in an appropriate manner.

Claims

CLAIMS1. A method for mapping a spiking neural network design onto a configurable neuromorphic processor, the method comprising: defining a resource model describing the neuromorphic processor, wherein the resource model defines one or more planes, each plane comprising a plurality of presynapses, synapses and spiking neurons arranged in a sub-network, wherein each presynapse is adapted to receive one or more inputs and each neuron has an output, and each synapse connects one of the presynapses to one of the neurons, and wherein the resource model defines a plurality of interconnections for connecting an output of one of the neurons of one of the planes to one or more of the presynapses of one of the planes; defining a network definition file describing the spiking neural network design, wherein the network definition file defines a plurality of neurons interconnected by a plurality of synapses, wherein the neurons are arranged in layers, each neuron in one of the layers being connected to one or more neurons in the same or another one of the layers; wherein the further method comprises: dividing the neurons of the network definition file into one or more partitions, each partition comprising a portion of the neurons from one of the layers; selecting one of the partitions; selecting an available one of the planes of the resource model, wherein a number of neurons of the plane is equal to or greater than a number of neurons in the selected partition; and mapping the neurons of the selected partition to the neurons of the selected plane of the resource model, wherein a neuron of the selected partition is mapped to a neuron of the selected plane if the neuron of the selected plane has available interconnections matching the interconnections to the neuron of the selected partition.

2. The method of claim 1, wherein selecting an available one of the planes further comprises selecting a plane for which a number of inputs to the neurons of the plane is equal to or greater than a number of inputs to the neurons of the selected partition.

3. The method of claim 2, wherein selecting an available one of the planes further comprises selecting a plane for which a number of external inputs to the neurons of the plane is equal to or greater than a number of external inputs to the neurons of the selected partition, for which a number of recurrent inputs to the neurons of the plane is equal to or greater than a number of recurrent inputs to the neurons of the selected partition..

4. The method of any one of the preceding claims, wherein mapping the neurons of the selected partition comprises allocating one of the neurons of the selected plane to one of the neurons of the selected partition, and allocating an interconnection to the allocated neuron of the selected plane if the neuron of the selected partition has a corresponding interconnection.

5. The method of claim 4, wherein, if an interconnection to the allocated neuron of the selected plane corresponding to an interconnection to the neuron of the selected partition cannot be found or has already been allocated, allocating a different neuron of the selected plane to the neuron of the selected partition.

6. The method of claim 4 or 5, wherein allocating an interconnection to the allocated neuron of the selected plane comprises allocating an external input to the allocated neuron of the selected plane if the neuron of the selected partition has an external input, and allocating a recurrent input to the allocated neuron of the selected plane if the neuron of the selected partition has a recurrent input.

7. The method of any one of claims 4-6, wherein allocating an interconnection to the allocated neuron of the selected plane comprises allocating a connection via an interconnect to the allocated neuron if the neuron of the selected partition has an input from a neuron in a different partition.

8. The method of any one of claims 4-7, wherein allocating an interconnection to the allocated neuron of the selected plane comprises removing a synapse input to the allocated neuron of the selected plane if the neuron of the selected partition does not have a corresponding synapse input.

9. The method of any one of the preceding claims, further comprising defining a set of mapping constraints which describe potentially conflicting interconnections in the resource model.

10. The method of claim 9, wherein the set of mapping constraints comprises an indication of quantity and types of interconnections to neurons in a partition of the network definition file.

11. The method of claim 9 or 10, wherein the set of mapping constraints comprises an indication of quantity of interconnections between neurons of different partitions of the network definition file.

12. The method of any one of the preceding claims, indicating one of the planes of the resource model as unavailable if the neurons of the selected partition are successfully mapped to the neurons of the selected plane.

13. The method of any one of the preceding claims, selecting another plane of the resource model if the neurons of the selected partition are not successfully mapped to the neurons of the previously selected plane.

14. The method of any one of the preceding claims, further comprising merging a partition of the network definition file with another partition of the network definition file if the number of partitions exceeds a number of planes in the resource model.

15. A system for mapping a spiking neural network design onto a configurable neuromorphic processor, the system comprising: a first memory for storing a resource model describing the neuromorphic processor, wherein the resource model defines one or more planes, each plane comprising a plurality of presynapses, synapses and spiking neurons arranged in a sub-network, wherein each presynapse is adapted to receive one or more inputs and each neuron has an output, and each synapse connects one of the presynapses to one of the neurons, and wherein the resource model defines a plurality of interconnections for connecting an output of one of the neurons of one of the planes to one or more of the presynapses of one of the planes; a second memory for storing a network definition file describing the spiking neural network design, wherein the network definition file defines a plurality of neurons interconnected by a plurality of synapses, wherein the neurons are arranged in layers, each neuron in one of the layers being connected to one or more neurons in another one of the layers; and a processor configured to: divide the neurons of the network definition file into one or more partitions, each partition comprising a portion of the neurons from one of the layers; select one of the partitions; select an available one of the planes of the resource model, wherein a number of neurons of the plane is equal to or greater than a number of neurons in the selected partition; and map the neurons of the selected partition to the neurons of the selected plane of the resource model, wherein a neuron of the selected partition is mapped to a neuron of the selected plane if the neuron of the selected plane has available interconnections matching the interconnections to the neuron of the selected partition.

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