Electric switching arrangement for generating current-controlled electric signals

Abstract

The invention relates to an electric switching arrangement for generating current-controlled electric signals for functional intracorporeal stimulation in the manner of a controlled cascode current mirror, comprising a first, second, third and fourth transistor each having allocated source, drain and gate terminals, of which the second and the fourth transistor are connected as an output cascode such that the source terminal of the fourth transistor is connected to the drain terminal of the second transistor and the drain terminal of the fourth transistor is connected to an output contact which can be allocated to the electric switching arrangement, at which output contact a voltage potential allocated to the current-controlled electric signal can be tapped. The invention is characterised in that the gate terminal of the fourth transistor is connected in a switchable manner to at least one constantly specifiable voltage potential.

Description

[0001] Electrical circuit arrangement for generating current-controlled electrical signals

[0002] Technical area

[0003] The invention relates to an electrical circuit arrangement for generating current-controlled electrical signals for functional intracorporeal stimulation in the manner of a regulated cascode current mirror, comprising a first, second, third and fourth transistor, each with associated source, drain and gate terminals, of which the gate terminals of the first and second transistors are connected to each other to form a current mirror, of which the third and first transistors are connected as an input cascode, in which the drain terminal of the third transistor is connected to the gate terminal of the first and second transistors, its source terminal is connected to the drain terminal of the first transistor and its gate terminal is connected to an output of an operational amplifier with at least two inputs,of which one input of the operational amplifier is connected to the drain terminal of the second transistor, and the other input of the operational amplifier is connected to the source terminal of the third transistor and the drain terminal of the first transistor, which are at the same potential. The second and fourth transistors are connected as an output cascode such that the source terminal of the fourth transistor is connected to the drain terminal of the second transistor, and the drain terminal of the fourth transistor is connected to an output contact associated with the electrical circuit arrangement, at which a voltage potential associated with the current-controlled electrical signals can be tapped. State of the art,

[0004] Functional electrical stimulation or neural stimulation (FES / FNS) is a technique for treating various types of neurological disorders by stimulating nerves with electrical charge. Applications range from pacemakers and retinal implants to peripheral nerve stimulators.

[0005] A known medical implant, which is the subject of EP 3204 105 B1 and serves for the location-selective detection of neuronal electrical signals propagating along at least one nerve fiber, as well as for the selective electrical stimulation of at least one nerve fiber, uses an electrode arrangement designed as a wound cuff for electrical signal transmission between the nerve fiber and the implant. The electrode arrangement has a plurality of electrode contacts that come into direct contact with the epineurium of the nerve fiber bundle, preferably the vagus nerve. Each individual electrode contact must be electrically polarized or activated in a coordinated manner based on a medical-therapeutic or analytical objective.For this purpose, the electrode contacts are each electrically connected to at least one stimulation channel, each of which can be tapped off at a separate output contact of an electrical circuit arrangement arranged on the implant side.

[0006] There are basically three ways to create a stimulation channel and the associated polarization of individual electrode contacts: voltage-based, charge-based, or current-based stimulation. These are physically related, but describe different approaches to charge delivery, i.e., controlled by a voltage source, by a capacitive discharge, or by a current source. However, the principle of charge delivery generated by a current source, i.e., "current-controlled stimulation," or CCS for short, will be pursued below.

[0007] It is therefore important to control the electrical charge applied locally to the epineurium via the electrode contacts, since the metal electrode contact-electrolyte interface at the epineurium is characterized by a maximum permissible charge that can be transferred from the respective electrode contact into the biological tissue.

[0008] For example, with current-controlled stimulation, the pulse width t_w and the stimulus current amplitude l_stim can be controlled independently of impedance fluctuations. Furthermore, charge and current are directly related to each other, through Q = l_stim * t_w, when rectangular stimulation is applied. However, with current-controlled stimulation, it is important to consider that high voltages are required to achieve a certain current level at high load impedances, necessitating high-voltage-resistant CMOS processes for the development of application-specific integrated circuits (ASICs).

[0009] The current source for each of the stimulation channels is a current mirror, which represents a controllable current source with the highest possible output resistance.

[0010] In an article by O. Charion and W. Redman-White, “Ultra high-compliance CMOS current mirrors for low voltage charge pumps and references,” Sept. 2004, pp. 227-230, possible architectures for such current mirrors are presented. In addition to a series of current mirrors differing in complexity, Figure 1 shows a known regulated cascode current mirror disclosed in the article, comprising a first, second, third and fourth transistor (T1, T2, T3, T4) each with associated source, drain and gate terminals, of which the gate terminal of the first and second transistor (T1, T2) is connected to each other and to an input potential (Vj) assigned to the cascode current mirror to form a current mirror. n), and of which the third and first transistors (T3, T1 ) are connected as an input cascode. For this purpose, the drain terminal of the third transistor (T3) is connected to the input potential (Vj n), whose source terminal is connected to the drain terminal of the first transistor (T1) and whose gate terminal is connected to an output (A) of an operational amplifier (OPA). The operational amplifier OPA has two inputs, one of which is connected (+) to the drain terminal of the second transistor (T2) and the other input (-) of the operational amplifier (OPA) is connected to the source terminal of the third transistor (T3) and the drain terminal of the first transistor (T1), which are at the same potential (Va). Furthermore, the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2), whose gate terminal is connected to the input potential (Vin), and whose drain terminal is connected to an output contact (out) that can be assigned to the electrical circuit arrangement and to which a voltage potential (V ou t) can be tapped.

[0011] Description of the invention

[0012] The invention is based on the object of developing an electrical circuit arrangement for generating current-controlled electrical signals for functional intracorporeal stimulation in the manner of a regulated cascode current mirror in such a way that the quality of the stimulation channel tapped at at least one output contact in the form of current-controlled electrical signals is to be improved compared to known circuit topologies. Furthermore, the circuit structure, particularly with regard to the scalability of the number and combinability of stimulation channels, is to be as compact as possible, i.e., small in size, yet diverse in terms of various switchable connection options between the stimulation channels and the output contacts connected to the electrode contacts.

[0013] The solution to the problem underlying the invention is defined in claim 1. Features that advantageously further develop the inventive concept are the subject of the dependent claims and the further description with reference to the drawings.

[0014] An electrical circuit arrangement according to the invention for generating current-controlled electrical signals for functional intracorporeal stimulation in the manner of a regulated cascode current mirror according to the features of the preamble of claim 1 is characterized in that the gate terminal of the fourth transistor is switchably connected to at least one constant, predeterminable voltage potential. In contrast to the known circuit concept explained at the outset, in which the gate voltage of the fourth transistor is co-regulated by the gate voltage of the first and second transistors (see Figure 1), the fourth transistor according to the invention is biased with a constant electrical voltage, which preferably originates from an external supply voltage source.

[0015] Basically, the higher the output resistance of a current source, the better the current source. According to the solution, the fourth transistor is not regulated, which makes the circuit topology comparable to that of an input-controlled current mirror, but with a significantly increased output resistance, since the output resistance increases by the intrinsic gain of the fourth transistor. The output resistance at the drain terminal of the fourth transistor that can be achieved with the circuit topology according to the solution is therefore significantly higher than in the known case of the regulated fourth transistor, see Figure 1, whose gate terminal is connected to the gate terminals of the first and second transistors and thus pushes the electrical potential at the drain terminal of the second transistor so low that the second transistor changes its operating range, i.e.from the saturation region to the linear region, in which a transistor has a significantly lower output resistance than in the saturation region.

[0016] A further advantage of the circuit topology according to the solution relates to improved robustness against possible drain voltage fluctuations. This is because, on the one hand, the first and second transistors are operated in strong inversion instead of in the linear range. On the other hand, the fourth transistor, whose gate voltage is now constant and detached from the control loop, acts as a buffer. As a result, unwanted voltage fluctuations, particularly at the drain terminal of the fourth transistor, which is directly connected to the electrode contacts, cannot have a direct impact on the current amplitudes. Furthermore, the fourth transistor serves as a static switch and thus has a switching function. During operation, the supply voltage, e.g. 1.8 V, is applied to the gate terminal of the fourth transistor. Depending on the switch position, the control or supply voltage of 0 V or 1.8 V is applied to the fourth transistor.

[0017] If particularly high stimulation currents need to be generated, e.g., up to 2 mA or more, a maximum gate-source voltage is advantageous. Even in the smallest designs for the fourth transistor, preferably with the smallest width / length dimensions (W / L = 1-3 pm / 500 nm - 1.3 pm), the maximum gate-source voltage can open the fourth transistor wide.

[0018] In order to protect the electrical circuit arrangement as a whole against high external voltages, a high-voltage protection transistor connected in series with the source-drain path of the fourth transistor is preferably arranged between the output contact and the latter. This enables all other transistors, i.e. the first, second, third and fourth transistors, to be designed as low-voltage transistors that can be controlled with electrical voltages up to a maximum of ±1.8 V, whereas the high-voltage transistor according to the invention can be operated with electrical control voltages up to a maximum of ±20 V, but preferably with ±18 V. Low-voltage transistors can be dimensioned smaller than high-voltage transistors, thus opening up the possibility of further miniaturization of the entire electrical circuit arrangement.

[0019] In addition to the first electrical circuit arrangement explained above, a second circuit arrangement is provided that is inverted to the first circuit arrangement and capable of generating current-controlled electrical signals that are inverted relative to the current-controlled electrical signals of the first electrical circuit arrangement. The second circuit arrangement, similar to the first, also has a fourth transistor that is connected to the output contact of the first circuit arrangement.

[0020] Due to the inverted circuit design of both circuit arrangements, one serves as a current source for the realization of positive stimulation channels, and the other as a current sink for the realization of negative stimulation channels. For this purpose, both circuit arrangements have the same design, but are implemented with inverted transistor types (n-MOS; p-MOS).

[0021] Preferably, the current mirror formed by the first and second transistors of the electrical circuit arrangement designed according to the solution is constructed as an n-bit digital-analog converter, preferably a 5-bit digital-analog converter, and has 2 n -1 second transistors. The drain terminals of the 2 n -1 second transistors each connected to the source terminal of one of 2 n -1 fourth transistors, the drain terminals of which are each connected to an output contact of the electrical circuit arrangement.

[0022] In a further preferred embodiment, the drain terminals of the 2 n -1 second transistors are also connected or connectable to each other, so that those bits that are activated are always led via correspondingly connected then terminals.

[0023] In a further preferred embodiment, it is possible to connect a stimulation channel to different or multiple output contacts and the electrode contacts connected to them, which, for example, directly contact the vagus nerve. This is achieved by a circuit matrix to which, on the one hand, the drain terminal of at least a fourth transistor of the electrical circuit arrangement and, on the other hand, a number m output contacts are connected. Both to protect against harmful overvoltages and to achieve a desired reduction in component size, additional high-voltage transistors are provided between each of the m output contacts and the respective fourth transistors that are part of the circuit matrix.

[0024] Brief description of the invention

[0025] The invention is described below without limiting the general inventive concept by means of exemplary embodiments with reference to the drawings. In the drawings: Fig. 1 Circuit topology of a known

[0026] current mirror arrangement,

[0027] Fig. 2 electrical circuit arrangement designed according to the solution,

[0028] Fig. 3 Representation of an extended circuit arrangement and

[0029] Fig. 4 schematically shown circuit matrix.

[0030] Ways of implementing the invention, industrial applicability

[0031] For an explanation of the known current mirror circuit arrangement shown in Figure 1, reference is made to the above description. The circuit arrangement can be found in the article by O. Charlon et al. mentioned above, illustrated in Figure 9 therein.

[0032] The electrical circuit arrangement according to the solution shown in Figure 2 also has the already explained first, second, third and fourth transistors T1, T2, T3 and T4, of which the series-connected first and third transistors T1 and T3 are connected as a regulated input cascode and the first and second transistors T1, T2 are connected as current mirrors. For this purpose, the gate terminals of the first and second transistors T1, T2 are connected both to one another and to the input potential Vin, which is applied to the input contact (in) of the circuit arrangement. In addition, the fourth transistor T4 is added as an output cascode, whose source-drain path is connected in series with the source-drain path of the second transistor T2. The fourth transistor T4 is supplied with a constant supply voltage VDD and serves as a switch.The supply voltage VDD is typically 1.8 V, which is switchably applied to the gate terminal of the fourth transistor T4.

[0033] The base current l is supplied via a reference current source. re f is provided, which is scaled by means of the circuit arrangement according to the solution and can be tapped as stimulation current at the output out of the circuit arrangement. Similar to the circuit concept shown in Figure 1, the third transistor T3 is connected to an output A of an operational amplifier OPA, whose output voltage Vc regulates the third transistor T3, which operates in saturation. The operational amplifier OPA has two inputs, the positive input of which is connected to the voltage potential Vb, which is present between the second and fourth transistors T2 and T4 connected in series. The negative input of the operational amplifier OPA is connected to the voltage potential V awhich is connected between the first and third transistors T1, T3 connected in series.

[0034] By controlling the third transistor T3 by means of the operational amplifier OPA, two control paths R1, R2 can be distinguished within the circuit arrangement: A first control path R1 corresponds to a negative feedback of the source voltage V applied to the third transistor T3 a via the negative input of the operational amplifier OPA, and a second control path R2 provides positive feedback via the third, first, and second transistors T3, T1, and T2 via the positive input "+" of the operational amplifier OPA. This very concept of a controlled input cascode leads to improved mirroring accuracy of the output current l tapped at the output. ou t.

[0035] Due to the additional amplification caused by the operational amplifier OPA, the output resistance Rou t at the output contact out significantly increased. For the output resistance R ou t applies: Rout = A ■ Rds2 ■ g m 4 ■ Rds4 with A: amplification factor of the operational amplifier OPA, Rds2 = small signal resistance between drain and source terminal of the second transistor, g m 4 = small signal transconductance of T4 and Rds4 = small signal resistance between drain and source terminal of the fourth transistor.

[0036] Furthermore, the third transistor T3 can be made small and in particular smaller than the fourth transistor T4, whereby the requirements for the operational amplifier OPA for controlling the third transistor T3 are far lower than in the case of the known circuit concept with a regulated output stage, ie with a regulated fourth transistor T4, see circuit arrangement in Figure 1.

[0037] A further development of the electrical circuit arrangement shown in Figure 2 is an optional additional monitoring circuit component CM, also referred to as a compliance monitor and shown in dashed lines in Figure 2. The monitoring circuit component CM is used to detect abnormal operating states of the electrical circuit arrangement, which are characterized by irregular voltage potentials that can develop at certain nodes of the circuit arrangement. If, for example, the voltage potential Vout tapped at the output out of the circuit arrangement falls to a minimum potential prevailing within the circuit arrangement, an irregular state has occurred, resulting in a potential crossing within the circuit arrangement, which must be detected.

[0038] The monitoring circuit component CM shown in Figure 2 is a comparator K with two comparator inputs Ke1, Ke2 and one comparator output Ka. The comparator input Ke1 is connected to the gate terminals of the first and second transistors (T1, T2), and thus to the input contact (in) of the circuit arrangement to which the input potential Vin is applied. The comparator input Ke2, on the other hand, is connected to the potential Vc present at the output (A) of the operational amplifier (OPA).

[0039] In a preferred application of the circuit arrangement, which serves to generate current-controlled electrical signals for functional intracorporeal stimulation, the voltage potentials within the circuit arrangement are selected such that the input potential Vin in normal operation is always lower than the voltage potential Vc amplified by the operational amplifier OPA. Furthermore, during normal operation, all potentials at the circuit nodes of the circuit arrangement ideally remain constant at their operating point. However, if potential shifts at the operating points deviate from the normal state and are greater than an initial potential difference of Vc-Vin, preferably 140 mV, the circuit arrangement no longer functions reliably and correctly. In the case of Vin = Vc, a voltage identity or voltage crossing exists, which represents a very suitable detection feature.The moment at which the voltage crossing occurs can be defined by the circuit design, depending on how large the initial potential difference between Vin and Vc is chosen.

[0040] Depending on the potential difference between the input potential Vin and the potential Vc present at the output of the operational amplifier OPA, the comparator K generates a signal S which serves as a warning signal as soon as a critical operating condition occurs, as explained above.

[0041] The warning signal S can be used as a criterion for terminating the operation of the circuit or as a control variable to adjust the supply voltage VDD to the required output voltage Vout within the scope of power management. The supply voltage VDD of the circuit should always be slightly higher than the output potential Vout available at the output. However, the two voltage potentials VDD and Vout should not be selected too differently in order to minimize any power loss occurring in the circuit. For this reason, so-called "compliance monitoring" is advantageous.

[0042] Figure 3 shows an advantageous extended circuit arrangement, comprising a first circuit arrangement I and a second circuit arrangement II, which are formed in a mirror image inverted to each other and are connected to each other only via the respective fourth transistor T4 with at least one output contact out.

[0043] It is assumed that the first circuit arrangement I is designed as a current sink for the generation of negative stimulation channels and the second circuit arrangement II as a current source for the generation of positive stimulation channels. Both circuit arrangements I and II are mirror images but each with inverted transistor types, i.e. either n-MOS transistors (T1, T2, T3, T4) in the case of the first circuit arrangement I, or p-MOS transistors (T1* T2* T3*, T4*) in the case of the second circuit arrangement II. The first circuit arrangement I is operated in a lower voltage domain, i.e. between the voltage potentials vivo and vlvi, compared to the second circuit arrangement II, which is operated between the voltage potentials vhvo and vhvi.

[0044] Since the fourth transistors T4 and T4* respectively serve as switches, both circuit arrangements can supply at least one output contact out with positive or negative stimulation signals, preferably in a time-coordinated manner. For this purpose, the fourth transistors T4 and T4* respectively are controlled or switched by static switching signals enbit_x.

[0045] The first and second transistors T1 and T1*, respectively, and T2 and T2*, respectively, connected as current mirrors IDAC,N, IDAC,P, each represent a stimulation channel and are implemented as a 5-bit digital-to-analog converter (DAC). In this case, the first transistor T1 and T1*, respectively, is connected to 2 5 -1 second transistors T2 or

[0046] T2* connected

[0047] For high-voltage protection, a high-voltage transistor THV or THV* is connected between the fourth transistor T4 or T4* and the output contact out to protect the circuit from external overvoltages. This makes it possible to implement all remaining transistors as low-voltage transistors, which can be dimensioned significantly smaller than high-voltage transistors, thus allowing the entire circuit to be further miniaturized. The high-voltage transistors THV or THV* are also switched with static switching signals enE_x, with enbit_x and enE_x being independent of each other. The switching signal Enbit_x determines the current amplitude at the output out, and the switching signal enE_x selects the electrode that is connected to the output out.

[0048] In a preferred optional embodiment of the circuit arrangements I and II, the respective first transistor T1 or T1 * is connected via a dynamic switch S en connected to the second transistors T2 and T2*, respectively. When the switch S is closed, en A source-drain current of 20 pA flows through the respective second transistor T2 or T2*. Furthermore, a further second transistor T2hc or T2hc* is provided, which can be switched on as required via a switch She. When the switch She is closed, a source-drain current of 30 pA flows through the respective second transistor T2hc or T2hc*, so that when the switches S are closed simultaneously, en and She, a total current of 50 pA can be tapped at the drain terminals of both second transistors T2 / T2hc and T2* / Thc2*. By combining all current paths within the 5-bit current mirror IDAC,P and IDAC,N, stimulation currents of up to (2 5-1 )-50 pm = 1 ,55 mA can be tapped at the output out.

[0049] A further option that expands the functionality of the circuit arrangement is the additional highly dynamic switches Shs, which can realize faster or shorter switching times, thus achieving steeper rising edges of the stimulation current. If the switches Shs and She are closed simultaneously, the switches Shs ensure that at least any slowing of the current rise times caused by the many transistors (T2 + T2hc, or T2* + T2hc*) is compensated.

[0050] For the sake of completeness, it should be noted at this point that the monitoring circuit component CM explained in conjunction with Figure 2 can be added to the circuit arrangements I and II for monitoring purposes.

[0051] In order to be able to switch the stimulation current, which can be tapped at the output out, to several or different output contacts and ultimately electrode contacts, each together or separately, the circuit arrangement provides a circuit matrix sw_matrix, which is shown schematically and in more detail in Figure 4.

[0052] Figure 4 illustrates a circuit matrix sw_matrix, which connects a number k=8 stimulation channels with a number m of output contacts out, at each of which stimulation currents can be tapped, which are applied directly to an organic structure, e.g. to the vagus nerve, by means of electrode contacts.

[0053] To represent and implement a stimulation channel, a circuit arrangement is required as illustrated in Figure 3 and is composed of circuit arrangements I and II.

[0054] Figure 4 illustrates a circuit matrix that can electrically connect m = 12 output contacts out with k = 8 stimulation channels. For each individual stimulation channel k per first and second circuit arrangement I and II, k first and third transistors T1, T3 and k- (2 n -1 ) second transistors T2, with n=5, since 5 bit, are required. In Figure 4, the schematic representation of the individual stimulation channels k of circuit arrangement II has been omitted due to the otherwise identical structure as in circuit arrangement I. For a switchable connection of k=8 stimulation channels to the m=12 output contacts, the k (2 n -1 ) second transistors T2 are connected to the m=12 output contacts out, ie it requires mk (2 n-1 ) fourth transistors T4, each of which establishes a switchable connection to the m=12 output contacts. The drain connections of all fourth transistors T4 are each connected in an orderly manner to an electrical lead, which is connected to one of the m=12 output contacts. In order to ensure the high-voltage protection against external overvoltages explained at the beginning, a high-voltage transistor THV is arranged along each individual electrical lead, i.e. only m = 12 high-voltage transistors THV are required per circuit arrangement I or II to protect all other transistors from overvoltages. The latter, in contrast to the high-voltage transistors THV, can be dimensioned much smaller, so that the entire circuit arrangement can be miniaturized.

[0055] List of reference symbols

[0056] T1, T2, T3, T4 first, second, third and fourth transistor

[0057] T1*, T2* T3* T4* first, second, third and fourth transistor in input contact out output contact

[0058] OPA operational amplifier

[0059] VDD supply voltage

[0060] V in Input potential m Number of output contacts k Number of stimulation channels n Bit-DAC

[0061] The further second transistor

[0062] THV high-voltage transistor

[0063] She Switch

[0064] Sen switch

[0065] A Output of the operational amplifier

[0066] CM monitoring circuit component

[0067] K Comparator

[0068] Ke1 comparator input

[0069] Ke2 comparator input

[0070] Ka comparator output

[0071] S Signal

Claims

Patent claims 1. An electrical circuit arrangement for generating current-controlled electrical signals for functional intracorporeal stimulation in the manner of a regulated cascode current mirror, comprising a first, second, third, and fourth transistor (T1, T2, T3, T4) each having associated source, drain, and gate terminals, of which the gate terminals of the first and second transistors (T1, T2) are connected to one another to form a current mirror, of which the third and first transistors (T3, T1) are connected as an input cascode, in which the drain terminal of the third transistor (T3) is connected to the gate terminal of the first and second transistors (T1, T2), the source terminal of the third transistor is connected to the drain terminal of the first transistor (T1), and the gate terminal of the third transistor is connected to an output (A) of an operational amplifier (OPA) having at least two inputs,of which one input (+) of the operational amplifier (OPA) is connected to the drain terminal of the second transistor (T2) and the other input (-) of the operational amplifier (OPV) is connected to the source terminal of the third transistor, which are at the same potential (Va), and the drain terminal of the first transistor (T1), and of which the second and fourth transistors (T2, T4) are connected as an output cascode in such a way that the source terminal of the fourth transistor (T4) is connected to the drain terminal of the second transistor (T2) and the drain terminal of the fourth transistor (T4) is connected to an output contact (out) which can be assigned to the electrical circuit arrangement and to which a voltage potential (V, ou t), characterized in that the gate terminal of the fourth transistor (T4) is switchably connected to at least one constantly predeterminable voltage potential.

2. Electrical circuit arrangement according to claim 1, characterized in that the voltage potential which can be constantly preset at the gate terminal of the fourth transistor (T4) is supplied by an external supply voltage source (VDD) or corresponds to a voltage potential (VSS) applied to the source terminal of the first and second transistors (T1, T2).

3. Electrical circuit arrangement according to claim 1 or 2, characterized in that a high-voltage protection transistor (THV) connected in series with the source-drain path of the fourth transistor (T4) is arranged between the output contact (out) and the fourth transistor (T4), and in that the fourth transistor (T4) is designed as a low-voltage transistor relative to the high-voltage protection transistor (THV).

4. Electrical circuit arrangement according to claim 3, characterized in that the low-voltage transistor (T4) is designed for drain voltages up to a maximum of ± 2 V and the high-voltage transistor (THV) is designed for drain voltages up to a maximum of ± 18 V.

5. Electrical circuit arrangement according to claim 4, characterized in that the first, second and third transistors are each designed as low-voltage transistors.

6. Electrical circuit arrangement according to one of claims 1 to 5, characterized in that the current mirror formed by the first and second transistor (T1, T2) is constructed as an n-bit digital-to-analog converter and 2 n -1 second transistors (T2) that the drain terminals of the 2 n -1 second transistors (T2) each connected to the source terminal of one of 2 n -1 fourth transistors (T4) are connected, whose Drain terminals are each connectable or connected to an output contact (out) of the electrical circuit arrangement.

7. Electrical circuit arrangement according to one of claims 1 to 6, characterized in that the output contact (out) is connected to a drain terminal of a further fourth transistor (T4*), which is part of a further electrical circuit arrangement (n) identical to the first electrical circuit arrangement (i) according to one of claims 1 to 6, and in that the further electrical circuit arrangement (n) is capable of generating current-controlled electrical signals which are inverted with respect to the current-controlled electrical signals of the first electrical circuit arrangement (i).

8. Electrical circuit system with a plurality k of stimulation channels, each with current-controlled electrical signals for functional intracorporeal stimulation, with k electrical circuit arrangements according to one of claims 1 to 7, characterized in that the drain terminals of the respective fourth transistors (T4) are connected via a circuit matrix to a number m of output contacts (out).

9. Electrical circuit system according to 8, characterized in that in the circuit matrix the number m output contacts (out) are each connected via a high-voltage transistor (THV) to the drain terminals of the respective fourth transistors (T4).

10. Electrical circuit arrangement according to one of claims 1 to 9, characterized in that a monitoring circuit component is provided which, in the event of an unauthorized operating state of the electrical Circuit arrangement generates a signal by exclusively tapping internal circuit potentials of the electrical circuit arrangement.

11. Electrical circuit arrangement according to claim 10, characterized in that the monitoring circuit component is designed in the form of a comparator, with two comparator inputs and one comparator output at which the signal can be tapped, and that at one of the two comparator inputs a potential applied to the gate terminals of the first and second transistors (T1, T2) is applied and at the other of the two comparator inputs the potential applied to the output (A) of the operational amplifier (OPA) is applied.

12. Electrical circuit arrangement according to one of claims 1 to 11, characterized in that the gate terminals of the first and second transistors (T1, T2) are connected both to each other and to an input potential (Vj n ) which is connected to the electrical circuit arrangement.

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