Vertical cavity surface emitting laser and method for producing same

Abstract

The invention relates to a vertical cavity surface emitting laser (VCSEL) comprising: a first reflector which is connected to a first semiconductor substrate; a second reflector; and an active region having a quantum well structure for emitting light, which active region is located in series between the first reflector and the second reflector, wherein the first reflector is located in series between the first semiconductor substrate and the active region, wherein the surface of the outer face of the first semiconductor substrate, which surface is remote from the first reflector, has an orientation mark that is designed so as to clearly define the position of the vertical cavity surface emitting laser in a plane in parallel with the outer face of the first semiconductor substrate. The invention also relates to a method for producing a vertical cavity surface emitting laser according to the invention.

Description

[0001] Vertical cavity surface emission laser and method for its manufacture

[0002] Description

[0003] Field of the invention

[0004] The invention relates to a vertical cavity surface emission laser having a first reflector, a second reflector and an active region with a quantum well structure for emitting light, which is arranged in series between the first and the second reflector, and to a method for producing such a vertical cavity surface emission laser.

[0005] Background of the invention

[0006] Vertical cavity surface-emitting lasers (VCSELs), also known as surface-emitting semiconductor lasers, are a type of semiconductor laser diode whose laser beam is emitted perpendicular to the top or bottom of the device. A VCSEL typically comprises two distributed Bragg reflectors (DBRs) arranged parallel to the wafer surface and an active region located between the Bragg reflectors, containing one or more quantum wells for generating the laser light. The Bragg reflectors typically comprise layers with alternating high and low refractive indices.

[0007] To manufacture VCSELs, the Bragg reflectors and the active region arranged between them can be manufactured separately and then connected to each other by wafer bonding (fusion bonding). Document US Pat. No. 6,542,531 B2 describes such a method for manufacturing a VCSEL. In a first step, the active region with quantum wells and a tunnel junction is grown on a semiconductor substrate and then structured by etching. Separate from the active region, two Bragg reflectors are manufactured by epitaxially growing the different layers on another semiconductor substrate and are each connected to one side of the active region by wafer bonding. Finally, the substrate of the upper DBR is removed by etching, and electrical contacts are applied to the component.

[0008] The production of a modern VCSEL requires complex process steps. Matching different materials for the reflectors and the active region, for example, requires multiple patterning steps before, during, and after wafer bonding. One challenge in VCSEL production is that precise alignment of the layers and their patterning during the manufacturing steps are crucial for the correct functioning of the VCSEL.

[0009] To ensure this, markings are often applied during the manufacturing process to verify correct alignment. Various techniques for marking and alignment control have become established in the state of the art. In one variant, in which the active region with quantum wells and tunnel junction layer and the two Bragg reflectors are manufactured separately and connected by wafer bonding, the marking is applied by structuring the tunnel junction layer. To ensure that the marking remains visible in the assembled VCSEL, one of the Bragg mirrors in the area of ​​the marking must be removed, which requires an additional processing step.

[0010] In an alternative variant, where the marking is also located in the tunnel junction layer, the marking is detected through the component using infrared radiation. While this variant does not require any material to be removed to detect the marking, the wavelength of infrared radiation limits the accuracy of detecting the marking, making this variant unsuitable for many applications due to its low resolution.

[0011] In other variants, the markings are transferred from a first marking to one of the new layers after several layers have been created. This variant also eliminates the additional process step of subsequent material removal. However, transferring the markings requires additional effort. A further disadvantage of these variants is that inaccuracies can occur with each transfer of a marking, which may be exacerbated with multiple transfers. Therefore, these variants are also not suitable for many applications due to the insufficient alignment accuracy.

[0012] Problem underlying the invention

[0013] The invention is based on the object of improving known manufacturing processes for VCSELs in such a way that a precise alignment of the resulting component is ensured in a simple manner when carrying out the individual process steps.

[0014] Inventive solution

[0015] In the absence of any contrary indications, any reference to one (including by indefinite and definite articles), two, or any other number of objects shall be understood as not excluding the presence of further such objects. The reference signs in all claims have no limiting effect but are intended merely to improve their readability.

[0016] The terms "before," "after," "between," and "on" used below can refer to a relative position of a layer with respect to other layers. A layer that is "on top of" or "connected to" another layer can be in direct contact with the other layer or have one or more intervening layers. A layer "between" layers can be in direct contact with the layers or have one or more intervening layers.

[0017] The stated object is achieved by a vertical cavity surface emission laser having the features of claim 1. The vertical cavity surface emission laser according to the invention comprises a first reflector which is connected to a first semiconductor substrate, a second reflector, and an active region with a quantum well structure for emitting light, which is arranged in series between the first reflector and the second reflector, wherein the first reflector is arranged in series between the first semiconductor substrate and the active region, wherein the surface of the outer side of the first semiconductor substrate facing away from the first reflector has an alignment mark which is designed such that it clearly defines the position of the vertical cavity surface emission laser in a plane parallel to the outer side of the first semiconductor substrate.

[0018] Furthermore, the stated object is achieved by a method for producing a vertical cavity surface emission laser with the features of claim 6. The method according to the invention for producing a vertical cavity surface emission laser with a first semiconductor substrate, a first reflector, a second reflector and an active region with a quantum well structure for generating light, which active region is arranged in series between the first reflector and the second reflector, comprises the steps: a) providing the first semiconductor substrate on which the first reflector is produced; b) providing a second semiconductor substrate on which the second reflector is produced; c) providing a third semiconductor substrate and epitaxially growing the active region with the quantum well structure on the third semiconductor substrate; d) connecting the first reflector to the active region;e) removing the third semiconductor substrate; f) connecting the second reflector to the active region; and g) removing the second semiconductor substrate; wherein, before carrying out step f), an alignment mark is produced on the surface of the outer side of the first semiconductor substrate facing away from the first reflector, said alignment mark being designed such that it unambiguously defines the position of the vertical cavity surface emission laser in a plane parallel to the outer side of the first semiconductor substrate.

[0019] The VCSEL according to the invention and the method for its production have the advantage that, due to the alignment marking on the outside of the semiconductor substrate, which is not altered during the production process, precise alignment of all steps of the production process is possible. A further advantage over the prior art, in which markings are applied in the active region, is that the active region does not need to be altered in the method according to the invention. This enables a significantly more flexible design of the active region and its simpler production compared to the prior art. Preferred embodiments of the invention

[0020] Advantageous training and further developments, which can be used individually or in combination with one another, are the subject of the dependent claims and the following description.

[0021] The VCSEL according to the invention comprises two reflectors. The first reflector and the second reflector are part of an optical resonator, by means of which the light generated in the quantum well structure is amplified before it leaves the VCSEL. Preferably, the first reflector and the second reflector are multilayer reflectors, each constructed from several layers of different materials. Particularly preferably, the first reflector and the second reflector are designed as Bragg reflectors (distributed Bragg reflectors, DBR), also referred to as Bragg mirrors. Bragg reflectors are typically formed from several layer pairs consisting of a material system that generally consists of two materials with different refractive indices and can be easily adapted to the other parts of the VCSEL.Preferred material systems for DBRs are undoped layers of aluminum arsenide (AlAs) and gallium arsenide (GaAs), of aluminum gallium arsenide (AlGaAs) and AlAs, or of AlGaAs and GaAs. The different refractive indices of the individual layers of a pair can be achieved by changing the aluminum content in the layers.

[0022] To produce the VCSEL according to the invention, process steps a) and b) can comprise both the provision of prefabricated reflectors on semiconductor substrates and the production of reflectors on semiconductor substrates. The reflectors can be produced in various ways. Corresponding methods are known in the prior art. Preferably, the reflectors are produced on a semiconductor substrate, in particular a wafer to which they are firmly bonded. Preferably, the first semiconductor substrate and / or the second semiconductor substrate is a GaAs wafer.

[0023] The active region, which is arranged between the two reflectors in the finished state of the VCSEL, comprises at least one quantum well structure for emitting light. Corresponding structures are known in the prior art, for example as so-called heterostructures. According to the invention, the active region is produced by epitaxial growth on a third semiconductor substrate. The material of the third semiconductor substrate is preferably indium phosphide (InP). The third semiconductor substrate is preferably a wafer, in particular an InP wafer. Further layers with the lattice constant of InP can advantageously be grown on the InP wafer, for example, an InP buffer layer, InGaAsP bonding layers, InAlAs intermediate layers, or InAlGaAs / InP quantum wells.

[0024] In one embodiment, the vertical-cavity surface-emitting laser further comprises a tunnel junction region arranged in series between the first reflector and the second reflector. The tunnel junction region is also referred to as a "tunnel junction."

[0025] Preferably, the tunnel junction region comprises two highly doped semiconductor layers of different conductivity (e.g., n++-doped and p++-doped). Preferably, the tunnel junction region comprises n++-doped indium gallium aluminum arsenide (InGaAIAs) and p++-doped InGaAIAs.

[0026] In one embodiment, a buffer region, which can also be grown epitaxially, is arranged between the quantum well structure and the tunnel junction region. The buffer region is preferably formed from an undoped semiconductor material, in particular from undoped InP.

[0027] To produce this embodiment, a tunnel junction region is preferably further formed in series before or after the quantum well structure in the active region by epitaxial growth in step c). If a buffer region is provided, this is also preferably formed by epitaxial growth in step c).

[0028] The VCSEL according to the invention can also comprise multiple layers of quantum wells, multiple layers of tunnel junction regions, and / or multiple layers of buffer regions. To produce such designs, preferably in step c) of the manufacturing process, multiple quantum well structures for generating light, multiple tunnel junction regions, and / or multiple buffer regions are epitaxially grown in series.

[0029] In a preferred embodiment, the active region comprises several quantum well structures for generating light and several tunnel junction regions arranged alternately in series between the first reflector and the second reflector. Such an arrangement has the advantage that a significantly higher laser light output can be achieved despite a compact design.

[0030] To produce this embodiment, preferably in step c) of the manufacturing process, several quantum well structures for generating light and several tunnel junction regions are epitaxially grown alternately in series. This has the advantage that the active region can be manufactured simply and efficiently. A further advantage is that, by growing all layers sequentially on the substrate, inaccuracies regarding the conformity of structures at the transitions from one layer to another, which can occur in some known manufacturing processes, are avoided.

[0031] This design is made possible by the fact that the alignment feature is applied to the outside of the first semiconductor substrate. In state-of-the-art devices, in which the markers in the active region are produced by patterning a layer, an arrangement of multiple active centers is not possible with sufficient precision. The reasons for this are that (i) patterning steps that create a topography within the VCSEL region require the quantum well structure to grow over the topography, which would drastically degrade its quality, and (ii) patterning steps that locally alter the conductivity would impair the patterned profile due to the high temperatures required during subsequent overgrowth, which would lead to large errors in the alignment accuracy.

[0032] In one embodiment, the vertical cavity surface emitting laser further comprises a first current distribution layer and a first contact, as well as a second current distribution layer and a second contact for exciting the VCSEL with electrical current. The types, shapes, and positions of the current distribution layers and contacts can be selected according to the respective requirements of the VCSEL, for example, with regard to its intended use.

[0033] In one embodiment, the vertical cavity surface emitting laser comprises a first current distribution layer and a first contact, wherein the first contact is in electrical communication with the first current distribution layer and the first current distribution layer is arranged between the first reflector and the active region, and a second current distribution layer and a second contact, wherein the second contact is in electrical communication with the second current distribution layer and the second current distribution layer is arranged between the second reflector and the active region.

[0034] In this embodiment, the first current distribution layer and the second current distribution layer are preferably etch stop layers. Etch stop layers are typically applied at specific locations during the layer-by-layer fabrication of a VCSEL in order to limit the effect of the etching to specific layers during the subsequent fabrication process, in which structuring is performed by etching. The use of etch stop layers as current distribution layers has the advantage that no additional effort is required for the production of the current distribution.

[0035] To produce an embodiment with current distribution layers, the first current distribution layer and the second current distribution layer are preferably grown epitaxially at the corresponding location in step c). Preferably, in step c), a current distribution layer is grown epitaxially before the growth of a quantum well structure and / or a tunnel junction region and after the growth of all quantum well structures and / or tunnel junction regions.

[0036] To manufacture a VCSEL according to the invention, three separate components are connected to each other: the first reflector to the active region and the second reflector to the active region. The respective connections according to steps d) and f) of the method according to the invention are preferably made by wafer bonding (fusion bonding).

[0037] The surfaces to be joined can be pretreated as needed prior to joining. In one embodiment, one or both surfaces to be joined are cleaned. In another embodiment, the surface of the first reflector is structured prior to step d), in particular by nanoimprinting, lithography, etching, local diffusion, and / or local defect generation.

[0038] Since the active region was grown on the third semiconductor substrate, the substrate must be removed before the active region can be connected to the second reflector. Removal is preferably performed by etching. For this purpose, an etch stop layer is advantageously applied as a first layer between the third semiconductor substrate and the active region.

[0039] After connecting the second reflector to the active region, the second semiconductor substrate is removed in step g) of the method according to the invention. Removal is preferably carried out by etching. In one variant, an etch stop layer is applied between the second semiconductor substrate and the second reflector. In another variant, the material of the second semiconductor substrate is selectively removable, so that no etch stop layer is required.

[0040] According to the invention, the surface of the outer side of the first semiconductor substrate facing away from the first reflector has an alignment mark. The alignment mark is produced before performing step f). The alignment mark can have any shape suitable for unambiguously defining the position of the vertical cavity surface emission laser in a plane parallel to the outer side of the first semiconductor substrate. A unique definition in a plane is achieved, for example, when two identifiable parts of the mark have different spatial coordinates in the plane.

[0041] The alignment mark can be a single mark with at least two identifiable parts or consist of multiple components. In one embodiment, the alignment mark comprises two separate partial marks applied at different locations on the surface of the outer side of the first semiconductor substrate facing away from the first reflector. Particularly preferably, the two partial marks are applied at locations on the surface that are as far apart as possible, in particular on opposite sides of the surface. In the case of a circular cross-section of the surface, the two partial marks are preferably applied at the outer points of a line through the center of the circle.

[0042] The alignment mark may also contain more than two identifiable parts, in particular partial marks, for example three, four or five.

[0043] The size of the alignment mark or its components is preferably selected so that they can be detected with sufficient precision using the available detection equipment and techniques. The alignment mark can be precisely produced, for example, by etching or laser engraving.

[0044] The alignment mark can be created at any time in the manufacturing process as long as the mark is not required for a subsequent process step.

[0045] For example, the alignment mark may already be present on the first semiconductor substrate on which the first reflector is produced during the provision according to step a). Preferably, the alignment mark is already produced after step a) by being incorporated into the provided first semiconductor substrate.

[0046] The process steps of the manufacturing process according to the invention do not necessarily have to be performed in the specified order, unless a mandatory sequence arises from logic. For example, steps a) to c) of the manufacturing process can be performed in any order or even simultaneously.

[0047] Brief description of the drawings

[0048] Further advantageous embodiments are described in more detail below with reference to several exemplary embodiments shown in the drawings, to which the invention is not limited, however.

[0049] It shows schematically:

[0050] Figure 1 shows a first embodiment of a VCSEL according to the invention;

[0051] Figure 2 shows a second embodiment of a VCSEL according to the invention.

[0052] Detailed description of embodiments of the invention

[0053] In the following description of preferred embodiments of the present invention, identical reference numerals designate identical or comparable components. Where multiple identical components are used, generally only one is provided with a reference numeral. Fig. 1 schematically shows a first embodiment of a VCSEL according to the invention. The VCSEL shown in Fig. 1 can be manufactured using the method described below.

[0054] A DBR, consisting of alternating layers of GaAs and AlGaAs, is epitaxially grown on a GaAs wafer as the first semiconductor substrate 1. The surface of the first semiconductor substrate 1 facing away from the DBR is provided with an alignment mark 9 comprising two partial marks located on opposite sides of the surface (indicated by the two arrows in Fig. 1). The alignment mark 9 can be produced, for example, by etching or laser engraving. The alignment mark 9 enables precise alignment for all subsequent process steps.

[0055] On another GaAs wafer serving as the second semiconductor substrate, an etch stop layer 7 made of AlGaAs is first epitaxially grown, followed by a DBR as the second reflector 3 with alternating layers of GaAs and AlGaAs. As an alternative to GaAs, Ge, for example, can be used as the material for the second semiconductor substrate. Since Ge can be selectively removed later in the process, no etch stop layer is required between the DBR and the substrate when Ge is used as the substrate material. The use of Ge has the further advantage of enabling defect-free mirror growth, which results in improved bonding quality.

[0056] The following layers are epitaxially grown on an InP wafer as the third semiconductor substrate in the specified order: an etch stop layer 7 made of InGaAsP, an InP layer as buffer layer 8, an active region 4 with quantum wells 5, another InP layer as buffer layer 8, a tunnel junction layer (6), another InP layer as buffer layer 8 and another etch stop layer 7.

[0057] The third semiconductor substrate, including the layers grown on it, is placed on the DBR of the first semiconductor substrate and connected to it by wafer bonding. The connected component has the GaAs layer of the first semiconductor substrate 1 on one side and the InP layer of the third semiconductor substrate on the other side. The latter is then removed by etching down to the etch stop layer 7. The surface exposed by etching is cleaned and then structured, for example, by photolithography followed by etching. If multiple quantum films are to be produced, it is advisable to implant or diffuse a different material instead of etching in order to electrically define the tunnel junction regions.

[0058] After structuring is complete, the surface is cleaned again. The DBR applied to the second semiconductor substrate is then placed onto the cleaned, structured surface and bonded by wafer bonding. In the final step, the second semiconductor substrate is removed. Thanks to the alignment mark 9 on the underside of the VCSEL, it can be precisely positioned in subsequent process steps.

[0059] Fig. 2 schematically shows a second embodiment of a VCSEL according to the invention. This differs from the first embodiment described above with reference to Fig. 1 only in that the active region 4 has a plurality of sequentially arranged quantum well structures 5 and tunnel junction regions 6. The VCSEL shown in Fig. 2 can be manufactured using the same method as described above with reference to the first embodiment. During the manufacture of the active region 4, the plurality of quantum well structures 5 for generating light and the plurality of tunnel junction regions 6 are grown epitaxially alternately in series.

[0060] The features disclosed in the above description, the claims and the drawings may be important both individually and in any combination for the realization of the invention in its various embodiments.

[0061] List of reference symbols

[0062] 1 first semiconductor substrate

[0063] 2 first reflector

[0064] 3 second reflector

[0065] 4 active area

[0066] 5 Quantum well structure

[0067] 6 Tunnel transition area

[0068] 7 Etch stop layer

[0069] 8 Buffer layer

[0070] 9 Alignment mark

Claims

Claims 1. Vertical cavity surface emitting laser (VCSEL) comprising: a first reflector (2) connected to a first semiconductor substrate (1), a second reflector (3), and an active region (4) having a quantum well structure (5) for emitting light, which active region is arranged in series between the first reflector (2) and the second reflector (3), wherein the first reflector (2) is arranged in series between the first semiconductor substrate (1) and the active region (4), characterized in that the surface of the outer side of the first semiconductor substrate (1) facing away from the first reflector (2) has an alignment mark (9) which is designed such that it clearly defines the position of the vertical cavity surface emitting laser in a plane parallel to the outer side of the first semiconductor substrate (1).

2. Vertical cavity surface emitting laser according to claim 1, characterized in that the vertical cavity surface emitting laser further comprises a tunnel junction region (6) arranged in series between the first reflector (2) and the second reflector (3).

3. Vertical cavity surface emission laser according to claim 1 or 2, characterized in that the active region (4) comprises a plurality of quantum well structures (5) for generating light and a plurality of tunnel junction regions (6) which are arranged alternately in series between the first reflector (2) and the second reflector (3).

4. Vertical cavity surface emitting laser according to one of claims 1 to 3, characterized in that the vertical cavity surface emitting laser further comprises: a first current distribution layer and a first contact, wherein the first contact is in electrical connection with the first current distribution layer and the first current distribution layer is arranged between the first reflector (2) and the active region (4), and a second current distribution layer and a second contact, wherein the second contact is in electrical connection with the second current distribution layer and the second current distribution layer is arranged between the second reflector (3) and the active region (4).

5. Vertical cavity surface emitting laser according to claim 4, characterized in that the first current distribution layer and the second current distribution layer are etching stop layers (7).

6. A method for producing a vertical cavity surface emission laser with a first semiconductor substrate (1), a first reflector (2), a second reflector (3), and an active region (4) with a quantum well structure (5) for generating light, which is arranged in series between the first reflector (2) and the second reflector (3), the method comprising the steps of: a) providing the first semiconductor substrate (1) on which the first reflector (2) is produced; b) providing a second semiconductor substrate on which the second reflector (3) is produced; c) providing a third semiconductor substrate and epitaxially growing the active region (4) with the quantum well structure (5) on the third semiconductor substrate; d) connecting the first reflector (2) to the active region (4); e) removing the third semiconductor substrate; f) connecting the second reflector (3) to the active region (4);and g) removing the second semiconductor substrate; characterized in that, before carrying out step f), an alignment mark (9) is produced on the surface of the outer side of the first semiconductor substrate (1) facing away from the first reflector (2), which alignment mark is designed such that it unambiguously defines the position of the vertical cavity surface emission laser in a plane parallel to the outer side of the first semiconductor substrate (1).

7. The method according to claim 6, characterized in that in step c) a tunnel junction region (6) is further produced in series before or after the quantum well structure (5) in the active region (4) by epitaxial growth.

8. The method according to claim 6 or 7, characterized in that in step c) a plurality of quantum well structures (5) for generating light and a plurality of tunnel junction regions (6) are grown epitaxially alternately in series.

9. Method according to one of claims 6 to 8, characterized in that in step c) before the growth of a quantum well structure (5) and / or a tunnel junction region (6) and after the growth of all quantum well structures (5) and / or tunnel junction regions (6), a current distribution layer is grown epitaxially.

10. Method according to claim 9, characterized in that the current distribution layers are designed as etching stop layers (7).

11. Method according to one of claims 6 to 10, characterized in that before step d) the surface of the first reflector (2) is structured, in particular by nanoimprinting, lithography, etching, local diffusion and / or local defect generation.

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