Method for operating a half-bridge, driver circuit, and power converter comprising the driver circuit

Abstract

The invention relates to a method for actuating a half-bridge (100) comprising a first semiconductor switch (110) and a second semiconductor switch (120) which are connected together in series between a first bridge connection (101) and a second bridge connection (102) using a driver circuit (1) which is connected to the semiconductor switches (110, 120). The method has the step of: varying a gate source voltage UGS at a deactivated semiconductor switch of the two semiconductor switches (110, 120) by changing the gate potential UG at a gate driver connection (15, 25) of the driver circuit (1), said gate driver connection being connected to the deactivated semiconductor switch (110, 120), wherein the variation of the gate source voltage UGS at the deactivated semiconductor switch (110, 120) counteracts a voltage peak (221) which is produced by a switching process of the respective other semiconductor switch (120, 110) of the half-bridge (100) and which occurs on the basis of the switching process of the respective other semiconductor switch (120, 110). The invention additionally relates to a driver circuit (1) which is designed to carry out the method step and to a power converter comprising such a driver circuit (1).

Description

[0001] METHOD FOR OPERATING A HALF-BRIDGE, DRIVER CIRCUIT AND CURRENT CONVERTER WITH THE DRIVER CIRCUIT

[0002] Technical field of the invention

[0003] The invention relates to a method for operating a half-bridge with two semiconductor switches arranged in series, in particular—but not exclusively—semiconductor switches based on silicon carbide (SiC). The invention further relates to a driver circuit designed for the method for operating the half-bridge, as well as to a current transformer having at least one such driver circuit.

[0004] State of the art

[0005] Semiconductor switches based on silicon carbide (SiC) offer several advantages over conventional silicon-based semiconductor switches. Specifically, they enable operation at higher temperatures, higher (blocking) voltages, and higher switching frequencies. SiC-based semiconductor switches generally exhibit lower switching losses and lower contact resistance, which is why the heat dissipated during operation of these components is typically lower than with conventional Si-based semiconductor switches. Due to these advantages, SiC-based semiconductor switches, such as SiC-based metal oxide field-effect transistors (SiC MOSFETs) or SiC-based insulated-gate bipolar transistors (SiC IGBTs), are increasingly being used in various areas of power electronics. In addition to these advantages, however, there are also some disadvantages that must be considered when using them.In particular, SiC-based semiconductor switches have a narrower tolerance range with regard to their permissible gate-source voltage compared to conventional semiconductor switches. Specifically, they are susceptible to operation at negative gate-source voltages that lie outside the permissible tolerance range. Furthermore, when operating a half-bridge consisting of two SiC semiconductor switches, the switching process of one semiconductor switch results in greater crosstalk with the gate-source voltage of the other, i.e., complementary, semiconductor switch due to their faster switching behavior. The voltage peaks resulting from crosstalk, which increase in intensity at higher switching frequencies, can damage the SiC semiconductor switches. During operation, these voltage peaks can even lead to undesirable behavior, such as unwanted switching on of a semiconductor switch, thereby destroying it.For safe operation of the SiC semiconductor switches within the half-bridge, it is therefore desirable to reduce the severity of the voltage peaks and / or to prevent the voltage peaks from exceeding the permissible tolerance range of the gate-source voltage.

[0006] In principle, this behavior also occurs in conventional semiconductor switches as a result of the charge reversal of parasitic gate-drain capacitances of the respective semiconductor switches (see also Miller effect). It will be explained in more detail later using Figs. 1a - 1c. However, the impact of the voltage peaks resulting from crosstalk is significantly greater in SiC-based semiconductor switches due to their narrow tolerance range of the permissible gate-source voltage.

[0007] The documents US11184003B2 and US11108388B1 disclose a method and a driver circuit for a silicon carbide power device, which suppress a voltage spike caused by a change in a gate-source voltage and crosstalk. The silicon carbide power device is controlled by a driver and includes a gate-source voltage and a source voltage. The source voltage decreases in accordance with an increase in the gate-source voltage, or the source voltage increases in accordance with a decrease in the gate-source voltage. However, the known method is complex and expensive to implement. Therefore, an alternative method and an alternative driver circuit for the gentle operation of a half-bridge, in particular a half-bridge with SiC-based semiconductor switches, are desirable, which avoids or at least reduces the aforementioned disadvantages.

[0008] The article ZHANG, Z. [et al.]; “Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration”; IEEE Transactions on Power Electronics, vol. 29, no. 4, April 2014, pp. 1986–1997; discloses two gate-assist circuits for actively suppressing crosstalk between two semiconductor switches in a half-bridge based on the intrinsic properties of SiC power devices. One of the two gate-assist circuits uses an auxiliary transistor in series with a capacitor, while the other gate-assist circuit includes two auxiliary transistors with a diode. The document DE 10 2021 213 295 A1 discloses a method for controlling a first and a second switching element of a half-bridge in a power converter. The method comprises the step of setting a first variation of a first current profile by means of a first gate driver at the first control contact for closing the first switching element.The method further comprises the step of setting a second variation of a second current waveform by means of a second gate driver at the second control contact during the closing of the first switching element.

[0009] Object of the invention

[0010] The invention is based on the object of providing a method for the gentle operation of a half-bridge comprising two series-connected semiconductor switches, in particular SiC-based semiconductor switches, which reduces the risk of exceeding a permissible tolerance range of the gate-source voltage due to voltage peaks occurring during operation. It is also an object of the invention to provide a driver circuit suitable for implementing the method and a current transformer comprising such a driver circuit.

[0011] Solution

[0012] The object of demonstrating an optimized method for operating a half-bridge is achieved according to the invention with the features of independent claim 1. The object of demonstrating a driver circuit suitable for the method is achieved according to the invention with the features of independent claim 10. The object of demonstrating a suitable current transformer with such a driver circuit is achieved according to the invention with the features of independent claim 17. Advantageous embodiments of the method are recited in claims 2 to 9. Advantageous embodiments of the driver circuit are recited in claims 11 to 16.

[0013] Description of the invention

[0014] The method according to the invention aims at controlling a half-bridge comprising a first semiconductor switch and a second semiconductor switch. The two semiconductor switches are arranged between a first bridge terminal and a second bridge terminal and are connected in series there. The half-bridge, in particular its semiconductor switches, are controlled via a driver circuit connected to the semiconductor switches. The method comprises the following steps:

[0015] Varying a gate-source voltage UGS at a switched-off one of the two semiconductor switches by changing a gate potential UG at a gate driver terminal of the driver circuit which is connected to the switched-off semiconductor switch, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch counteracts a voltage peak which is generated by a switching operation of the other semiconductor switch of the half-bridge and which occurs as a function of the switching operation of the other semiconductor switch.

[0016] The fact that the variation of the gate-source voltage UGS at the switched-off semiconductor switch counteracts a voltage peak means, according to the invention, that in the event of an upward (i.e. towards more positive values) voltage peak in the gate-source voltage, the gate potential is reduced. Correspondingly, in the event of a downward voltage peak in the gate-source voltage UGS, the gate potential is increased. The fact that the variation of the gate-source voltage at the switched-off semiconductor switch occurs as a function of the switching operation of the other semiconductor switch means that it does not have to occur continuously, but can only occur temporarily and, in particular, in close temporal proximity to the switching operation of the other semiconductor switch. It can also mean that an extent of the variation of the gate potential UG at the gate driver terminal depends on a frequency of the switching operation of the semiconductor switch.

[0017] A driver circuit according to the invention is designed to operate a half-bridge, wherein the half-bridge has a first semiconductor switch and a second semiconductor switch that are connected in series between a first bridge terminal and a second bridge terminal. The driver circuit comprises: a first drive circuit with a first gate driver terminal for connection to a gate terminal of the first semiconductor switch and a first source driver terminal for connection to a source terminal of the first semiconductor switch, a second drive circuit with a second gate driver terminal for connection to the gate terminal of the second semiconductor switch and a second source driver terminal for connection to a source terminal of the second semiconductor switch, and a control unit for operating the first drive circuit and the second drive circuit.The driver circuit is characterized in that it is designed and configured to operate the half-bridge according to the method according to the invention.

[0018] The fact that the driver circuit is configured to operate the half-bridge according to the method according to the invention includes, in particular, that the first control circuit is designed, when the first semiconductor switch is switched off, to vary a gate-source voltage UGS at the first gate driver terminal by changing a gate potential UG applied thereto. Furthermore, it includes that the second control circuit is designed, when the second semiconductor switch is switched off, to vary a gate-source voltage UGS at the second gate driver terminal by changing a gate potential UG applied thereto. The driver circuit can, but does not necessarily have to, be present as a separate component relative to the half-bridge. Rather, it is also possible for the driver circuit with its control circuits and the half-bridge with its semiconductor switches to be arranged on a common circuit board and connected to one another there via conductor tracks.In this case, the respective endpoints of the corresponding traces can be regarded as gate driver terminals, source driver terminals, gate terminals and source terminals.

[0019] The invention utilizes the effect that, by varying the gate potential at the switched-off, i.e., switched-off, semiconductor switch, the risk is reduced, and possibly even prevented, of the voltage peak generated in the gate-source voltage of the switched-off semiconductor switch by the switching operation of the other semiconductor switch exceeding a permissible tolerance range of the semiconductor switch. Specifically, the risk is reduced, and possibly even prevented, of an upwardly directed voltage peak exceeding an upper tolerance limit and thus leading to an undesired switching-on of the switched-off semiconductor switch. According to the invention, this is achieved by lowering, in particular temporarily lowering, the gate potential of the switched-off semiconductor switch when an upwardly directed voltage peak is expected.In this way, both a starting point and an end point of the voltage peak—in a sense, the voltage peak as a whole—are lowered, and exceeding the upper tolerance limit is prevented, or at least reduced. Furthermore, the risk of a downward-directed voltage peak in the gate-source voltage of the switched-off semiconductor switch falling below a lower tolerance limit, in particular repeatedly falling below it and thereby permanently damaging the semiconductor switch, can be reduced, or even prevented. According to the invention, this is achieved by raising the gate potential of the switched-off semiconductor switch when a downward-directed voltage peak is expected, in particular temporarily raising it, i.e., varying it toward more positive values.Thus, both the starting point and the end point of the voltage peak—the voltage peak as a whole, in a sense—are raised, and a fall below the lower tolerance limit is prevented, or at least reduced. A driver circuit designed for this process does not necessarily require additional components and thus increased component complexity compared to a conventional driver circuit. The changes required for the driver circuit are usually limited to corresponding software modifications in the existing control unit of the driver circuit. Additional hardware—and the associated costs—are usually not required, or only to a limited extent, if at all.

[0020] Advantageous embodiments of the invention are specified in the following description and the subclaims, the features of which can be used individually and in any combination with one another.

[0021] In one embodiment of the method, the variation of the gate-source voltage UGS at the switched-off semiconductor switch can be triggered in time by the switching operation of the other semiconductor switch. In particular, it can have a time offset Δt relative to the switching operation of the complementary semiconductor switch. The time offset Δt can assume positive as well as negative values. Furthermore, it is possible for the time offset to be 0 and for the variation of the gate potential to occur virtually simultaneously with the switching operation. The respective time offset depends on how long the control unit requires for the desired variation of the gate potential. The time offset Δt can be determined once before commissioning of the driver circuit and the half-bridge and then specified by the control unit.For example, a starting point of the variation in the gate-source voltage and a time of a signal for triggering the switching process at the other semiconductor switch can be used as reference points for the time offset Δt. Instead of the time at which the triggering of the switching process is signaled at the other semiconductor switch, the time at which the switching process of the other semiconductor switch actually occurs can also be selected, i.e. the time at which the maximum rate of change of an absolute value of a drain-source voltage occurs at the other semiconductor switch, ie | d / dt UDS | = max.

[0022] In one embodiment of the method, the variation of the gate-source voltage UGS at the switched-off semiconductor switch can comprise an increase in the gate potential UG at the corresponding gate driver terminal when the other semiconductor switch is switched off. Specifically, switching off the other semiconductor switch results in a downward voltage peak in the gate-source voltage UGS of the semiconductor switch that is already switched off, i.e. the semiconductor switch that is not currently performing a switching operation. By increasing the gate potential UG at the switched-off semiconductor switch, the downward voltage peak is shifted towards more positive values. This prevents, or at least reduces, the voltage peak from falling below a lower tolerance limit assigned to the switched-off semiconductor switch.In a further embodiment of the method, the variation of the gate-source voltage UGS at the switched-off semiconductor switch can comprise a reduction in the gate potential UG at the corresponding gate driver terminal when the other semiconductor switch is switched on. Switching on the other semiconductor switch results in an upward voltage peak in the gate-source voltage UGS of the switched-off semiconductor switch, i.e., the semiconductor switch that is not currently performing a switching operation. By reducing the gate potential UG at the switched-off semiconductor switch, the voltage peak is shifted toward more negative values, and exceeding an upper tolerance limit assigned to the switched-off semiconductor switch is prevented or reduced.

[0023] In one embodiment of the method, the gate-source voltage UGS at the switched-off semiconductor switch can be varied by temporarily connecting a capacitor with a preset voltage, dependent on the switching operation of the other semiconductor switch, to the corresponding gate driver terminal in the respective control circuit associated with the switched-off semiconductor switch—and via this to the gate terminal of the switched-off semiconductor switch. In this case, the gate potential is varied by a charge exchange between the precharged capacitor and a parasitic gate-source capacitance of the switched-off semiconductor switch.After the voltage peak occurs, the capacitor can be disconnected from the gate driver terminal again and connected to a voltage source within the drive circuit, allowing it to be precharged again for a subsequent voltage peak. For this purpose, the first drive circuit of the driver circuit can comprise a capacitor having a first contact that can be connected via a switch—optionally also via two switches—either to a first pole of a voltage source or to the first gate driver terminal of the first drive circuit. A second contact of the capacitor of the first drive circuit can be connected to a second pole of the voltage source of the first drive circuit.Alternatively or additionally, it is also possible for the second drive circuit to comprise a capacitor having a first contact that can be connected via a switch—possibly also via two switches—either to a first pole of a voltage source or to the second gate driver terminal of the second drive circuit. A second contact of the capacitor of the second drive circuit can be connected to a second pole of the voltage source of the second drive circuit.

[0024] In a further embodiment of the method, the gate-source voltage UGS at the switched-off semiconductor switch within the driver circuit—and thus also the gate potential UG within the driver circuit—can be varied by setting a potential using a voltage divider. For this purpose, the first control circuit, or alternatively or cumulatively also the second control circuit, can each have a voltage divider. The voltage divider can each have a bridge branch. Alternatively, however, it is also possible for the voltage divider / each of the voltage dividers to have several bridge branches. Each of the bridge branches can each comprise an upper series circuit of an upper switch and an upper resistor, as well as a lower series circuit of a lower switch and a lower resistor.The upper series circuits of each bridge branch of a, in particular the same, control circuit can each be connected to one another via a center tap assigned to the bridge branch. The lower series circuits of each bridge branch of a, in particular the same, control circuit can also be connected to one another via the center tap assigned to the bridge branch. Furthermore, the center tap of each bridge branch of a, in particular the same, control circuit can each be connected to the gate driver terminal of the control circuit assigned to it. The gate driver terminal of each control circuit can in turn be connected to the gate terminal of the semiconductor switch assigned to it. In this way, the gate terminal of each semiconductor switch is each connected to the center tap or taps of the control circuit assigned to it.

[0025] In the voltage divider, which has one or more bridge arms, each with an upper series circuit of an upper switch and an upper resistor, and a lower series circuit of a lower switch and a lower resistor, a first number of upper series circuits is always equal to a second number of lower series circuits. Finally, a bridge arm always has an upper series circuit as well as a lower series circuit. Alternatively to this embodiment, the voltage divider can also be designed such that the first number of upper series circuits is not equal to the second number of lower series circuits.In a further embodiment of the driver circuit, the first drive circuit and / or the second drive circuit can each have a voltage divider, wherein the voltage divider comprises a first number of upper series circuits, each with an upper switch and an upper resistor, and a second number of lower series circuits, different from the first number, each with a lower switch and a lower resistor. Within one, in particular the same, drive circuit, each of the upper series circuits is connected to each of the lower series circuits via a common center tap. The common center tap is connected to the gate driver terminal of the corresponding drive circuit. The gate driver terminal is in turn connected to the gate terminal of the semiconductor switch assigned to the respective drive circuit.

[0026] In one embodiment of the method that uses the voltage divider with the first number of upper series circuits and the different second number of lower series circuits, the gate-source voltage UGS at the switched-off semiconductor switch is varied within the control circuit of the switched-off semiconductor switch by adjusting a potential using the voltage divider designed in this way. In each of the control circuits that have the voltage divider designed in this way, the common center tap of the voltage divider is connected to the gate driver terminal of the corresponding control circuit. The gate driver terminal of each of the control circuits is in turn connected to the gate terminal of its respective assigned semiconductor switch. Therefore, this also applies to the control circuit assigned to the respective switched-off semiconductor switch.Therefore, the potential prevailing at the common center tap of the voltage divider and the associated gate driver terminal of the control circuit associated with the switched-off semiconductor switch can be transferred to the gate terminal of the switched-off semiconductor switch.

[0027] In one variant of the method, the potential can be adjusted using the voltage divider by at least one or more upper switches and one or more lower switches of the voltage divider being closed simultaneously. This variant of the method can be used for any of the voltage dividers shown. Its use is therefore independent of whether the first number of upper series circuits in the voltage divider is the same as or different from the second number of lower series circuits. In this way, a predefined potential can be statically provided at the center tap of the voltage divider and transferred to the gate driver terminal of the associated control circuit. The potential can be transferred continuously for a predetermined period of time by keeping the corresponding switches continuously closed for the predetermined period of time.Alternatively, it can also be clocked, with the corresponding switches being closed and opened alternately in synchronization for the specified period of time—i.e., clocked synchronously. This variant can be used particularly when the voltage divider has multiple bridge arms or when each of the voltage dividers has multiple bridge arms.

[0028] In an alternative embodiment of the method, the potential can also be adjusted using the voltage divider by either having one or more upper switches, but none of the lower switches, closed simultaneously in the voltage divider in question, or by having one or more lower switches, but none of the upper switches, closed simultaneously in the voltage divider in question. The alternative variant of the method can also be used for each of the voltage dividers shown, regardless of whether the first number of upper series circuits in the voltage divider is equal to or different from the second number of lower series circuits.In this variant, the center tap can jump back and forth between several potentials, for example between two, whereby the gate-source capacitance of the switched-off semiconductor switch can be charged or discharged in short time pulses.

[0029] Within the scope of the invention, the first control circuit can be structurally identical or substantially identical to the second control circuit. Alternatively, however, the first control circuit can also have a design that differs from the design of the second control circuit. Specifically, for example, one of the control circuits can have a voltage divider and the other of the control circuits can have a capacitor for changing the gate potential.

[0030] In one embodiment of the driver circuit, the first control circuit can have a maximum of one voltage source or a maximum of two voltage sources. Alternatively or additionally, it is also possible for the second control circuit to have a maximum of one voltage source or a maximum of two voltage sources. A voltage source within the scope of the invention is understood to be a component or circuit whose supplied voltage does not change or changes only insignificantly, even under load. An insignificant change here is, in particular, a voltage change that does not exceed a maximum of 30% of the nominal value of the voltage source.

[0031] A current transformer according to the invention comprises one or more half-bridges and one or more driver circuits according to the invention. The driver circuit(s) is / are designed to control a respective half-bridge of the one or more half-bridges assigned to it according to the method according to the invention. The advantages already explained in connection with the method also apply to the current transformer.

[0032] Short description of the characters

[0033] The invention is illustrated below with the aid of figures, of which

[0034] Fig. 1a shows a half-bridge with two semiconductor switches, which is controlled by a conventional driver circuit;

[0035] Fig. 1b diagrams for explaining a voltage peak in the gate-source voltage of a semiconductor switch, which is generated when the other semiconductor switch is turned on with the conventional driver circuit;

[0036] Fig. 1c diagrams for explaining a voltage peak in the gate-source voltage of a semiconductor switch, which is generated when the other semiconductor switch is turned off with the conventional driver circuit;

[0037] Fig. 2 shows a first embodiment of a driver circuit according to the invention for reducing / preventing damage to a half-bridge by a voltage peak in the gate-source voltage of a semiconductor switch;

[0038] Fig. 3 diagrams to explain an operation of the driver circuit from Fig. 2 (using the example: switching off the other semiconductor switch);

[0039] Fig. 4 shows a second embodiment of a driver circuit according to the invention for reducing / preventing damage to a half-bridge caused by a voltage peak in the gate-source voltage of a semiconductor switch; Fig. 5a shows diagrams for explaining the operation of the driver circuit from Fig. 4 (using the example of switching on the other semiconductor switch);

[0040] Fig. 5b diagrams to explain an operation of the driver circuit from Fig. 4 (using the example of switching off the other semiconductor switch);

[0041] Fig. 6 shows a third embodiment of a driver circuit according to the invention for reducing / preventing damage to a half-bridge by a voltage peak in the gate-source voltage of a semiconductor switch;

[0042] Fig. 7 diagrams to explain an operation of the driver circuit from Fig. 6 (using the example of switching off the other semiconductor switch);

[0043] Fig. 8 shows a fourth embodiment of a driver circuit according to the invention for reducing / preventing damage to a half-bridge by a voltage peak in the gate-source voltage of a semiconductor switch;

[0044] Character description

[0045] Fig. 1a shows a conventional driver circuit 80 for controlling a half-bridge 100 with a first semiconductor switch 110 and a second semiconductor switch 120, which are arranged between bridge terminals 101, 102 of the half-bridge 100 and are connected in series there via a bridge tap 103. Each of the semiconductor switches 110, 120 is controlled by a control circuit 60, 70 of the driver circuit 80 assigned to it and is alternately switched on and off via this. For this purpose, each of the control circuits 60, 70 has a voltage generator 61, 71, the first contact of which is connected via a resistor 62, 72 and a gate driver terminal 65, 75 of the control circuit 60, 70 to a gate terminal 115, 125 of the corresponding semiconductor switch 110, 120. The second contact of the

[0046] Each voltage generator 61, 71 is connected via a source driver terminal 66, 76 to a source terminal 116, 126 of the corresponding semiconductor switch 110, 120. The drive circuits 60, 70 are controlled by a control unit 50 of the driver circuit 80 and are designed to alternately switch the semiconductor switches 110, 120 assigned to them on and off by generating a corresponding gate-source voltage UGS. The semiconductor switches 110, 120 are shown as MOSFETs by way of example. For example, each can be a silicon carbide (SiC) MOSFET. Alternatively, however, it is also possible for the semiconductor switches to be designed as IGBTs, for example, as SiC IGBTs. The semiconductor switches 110, 120 have parasitic capacitances.Specifically, they have so-called gate-drain capacitances 111, 121 between their gate terminals 115, 125 and their drain terminals, and so-called gate-source capacitances 112, 122 between their gate terminals 115, 125 and their source terminals, each shown in dashed lines in Fig. 1a. The half-bridge 100 also has an antiparallel oriented freewheeling diode 113, 123 for each of the two semiconductor switches 110, 120. The freewheeling diode 113, 123 can be either an intrinsic diode of the corresponding semiconductor switch 110, 120 (e.g., in the case of a MOSFET as a semiconductor switch) or a separate freewheeling diode connected antiparallel to the corresponding semiconductor switch (e.g., in the case of an IGBT as a semiconductor switch).

[0047] The following explains the emergence of a voltage peak 221 in the gate-source voltage of one of the semiconductor switches - here, by way of example, the second semiconductor switch 120 - when the other of the semiconductor switches - here, the first semiconductor switch 110 - is switched on. For this purpose, Fig. 1b shows several diagrams 91, 92, 93, 94 that characterize the time profiles of different voltages of the semiconductor switches 110, 120. Specifically, diagram 91 shows a time profile 210 of the gate-source voltage UGS and diagram 92 shows a time profile 215 of the drain-source voltage of the first semiconductor switch 110. The diagrams 93, 94 are assigned to the second semiconductor switch 120. Specifically, diagram 93 represents a time profile 220 of the gate-source voltage UGS and diagram 94 represents a time profile 225 of the drain-source voltage UDS of the second (here switched off) semiconductor switch 120. The time profiles can, for example,when using the driver circuit 80 in conjunction with the half-bridge 100 when the first semiconductor switch 110 is switched on, when the second semiconductor switch 120 is switched off.

[0048] At time t0, the voltage generator 61 of the first control circuit 60 generates a sudden voltage increase in order to switch on the first semiconductor switch 110 while the second semiconductor switch 120 is switched off. As a result, the gate-source capacitance 112 of the corresponding semiconductor switch 110 is charged via the resistor 62, which charging is reflected in the time profile 210 in the gate-source voltage of the first semiconductor switch 110—here, an exponentially decaying voltage increase. Upon reaching a threshold value for the gate-source voltage UGS, an almost sudden switch-on of the corresponding semiconductor switch 110 is initiated. Accordingly, the drain-source voltage UDS assigned to the semiconductor switch 110 drops to a low value that corresponds to a forward voltage of the switch.The sudden drop in the voltage drop UDS across the load terminals of the first semiconductor switch leads to a sudden increase in the voltage drop of the second semiconductor switch 120. Specifically, at the second (switched-off) semiconductor switch 120, the voltage drop between its drain terminal and its source terminal suddenly increases to twice the value, namely from half the voltage applied between the bridge terminals 101, 102 (when the two semiconductor switches 110, 120 are open) to almost the entire voltage applied between the bridge terminals 101, 102 (when the second semiconductor switch 120 is open and the first semiconductor switch 110 is closed). The high temporal rates of change of the voltage drops between the load terminals of the semiconductor switches 110, 120 result in strong charge reversals at the corresponding gate-drain capacitances 111, 121 of the semiconductor switches 110, 120.Specifically, the corresponding charging current must be provided by the control circuit 70 of the second semiconductor switch 120 at the gate-drain capacitance 121 of the second semiconductor switch 120, despite its permanently switched-off state during this period. However, because the charging current of the control circuit 70 between the voltage generator 71 and the gate terminal 125 of the second semiconductor switch 120 is limited by the resistor 72 and cannot assume arbitrarily high values, this subsequently leads to an upwardly directed (i.e., toward positive values) voltage peak 221 in the time profile 220 of the gate-source voltage UGS of the second semiconductor switch 120 (see diagram 93). If it exceeds an upper tolerance limit 222, the voltage peak 221 can even lead to an undesired switching-on of the second semiconductor switch 120 and thus to a short circuit of the half-bridge 100 and possiblylead to the destruction of both semiconductor switches 110, 120.

[0049] In Fig. 1c, time profiles 210, 215, 220, 225 of characteristic voltages are shown in several diagrams 91, 92, 93, 94 for the case in which the first semiconductor switch 110 is turned off while the second semiconductor switch 120 is turned off. Diagram 91 shows the time profile 210 of the gate-source voltage UGS and diagram 92 shows the corresponding time profile 215 for the voltage drop UDS across the load terminals (i.e. drain and source) of the first semiconductor switch 110. Diagram 93 shows the time profile 220 of the gate-source voltage UGS and diagram 94 shows the time profile 225 of the voltage drop UDS between the load terminals drain and source for the second semiconductor switch 120.

[0050] Similar to the case in Fig. 1 b, the voltage change between the load terminals of the first semiconductor switch 110 during its turn-off process generates an opposite voltage change between the terminals of the second semiconductor switch 120. Specifically, when the first semiconductor switch 110 is turned off, the voltage drop between the drain and source of the second semiconductor switch is abruptly halved, i.e. from almost a full voltage applied between the bridge terminals 101, 102 (when the first semiconductor switch 110 is turned on) to almost half the voltage applied between the bridge terminals 101, 102 (when the first semiconductor switch 110 and the second semiconductor switch 120 are turned off) (cf. diagram 94). This abrupt change in the voltage drop between the drain and source terminals of the second semiconductor switch 120 also has here, similar to the diagram shown in Fig.1 b, charge reversal processes at the gate-drain capacitance 121 of the second semiconductor switch 120 result. Since these cannot occur arbitrarily quickly, but rather its current is limited by the resistor 72, this leads to a voltage peak 221 directed downwards (i.e. towards negative values). If this voltage peak 221 falls below a lower tolerance limit 223, in particular if it falls below it repeatedly during normal operation of the half-bridge 100, this can lead to permanent damage to the corresponding semiconductor switch 120. The behavior of the bridge switches 110, 120 was explained in Figs. 1 b and 1 c for the exemplary case in which the first semiconductor switch 110 was switched on or off, while the second semiconductor switch 120 is switched off or remains switched off.However, this behavior can also be applied to the case where the second semiconductor switch 120 is switched on or off while the first semiconductor switch 110 is switched off or remains switched off. In this case, the aforementioned voltage peaks 221 occur at the first semiconductor switch 110.

[0051] Fig. 2 shows a first embodiment of a driver circuit 1 according to the invention in conjunction with a half-bridge 100 operated by the driver circuit 1. In contrast to the conventional driver circuit 80 from Fig. 1a, the driver circuit 1 is designed to reduce / prevent damage to the half-bridge 100 caused by a voltage peak 221 in the gate-source voltage UGS of one of the semiconductor switches 110, 120. The semiconductor switches 110, 120 of the half-bridge 100 can in particular be SiC MOSFETs or SiC IGBTs. The half-bridge 100 essentially corresponds in its structure to the half-bridge 100 also shown in Fig. 1a. Therefore, reference is made here to the description in Fig. 1a, and only the driver circuit 1 is explained in more detail below.

[0052] The driver circuit 1 includes two drive circuits 10, 20, each associated with one of the semiconductor switches 110, 120. They each have a gate driver terminal 15, 25 and a source driver terminal 16, 26. In each drive circuit 10, 20, the gate driver terminal 15, 25 is connected to the gate terminal 115, 125, and the source driver terminal 16, 26 is connected to the source terminal 116, 126 of the associated semiconductor switch 110, 120. Each of the drive circuits 10, 20 has two voltage sources 11, 12, 21, 22, which are connected in series via a center point 13, 23. Each of the voltage sources 11, 12, 21, 22 has a respective voltage Un, U21, U12, U22 assigned to it. The center point 13, 23 serves as the reference potential GND10, GND20 for the respective control circuit 10, 20 and is connected to the corresponding source driver terminal 16, 26 for each of the control circuits 10, 20.The control circuits 10, 20 each further comprise a voltage divider in the form of a bridge arm. The bridge arm comprises an upper series circuit of an upper switch S10.1, S20.1 and an upper resistor R10.1, R20.1, as well as a lower series circuit of a lower switch S10.2, S20.2 and a lower resistor R10.2, R20.2. The upper and lower series circuits of the same bridge arm are each connected in series via a center tap 14, 24. Within the same control circuit 10, 20, each bridge arm is connected at one end to a positive (+) pole of the first voltage source 11, 21 and at the other end to a negative (-) pole of the second voltage source 12, 22. The center tap 14, 24 is each connected to the gate driver terminal 15, 25 of the corresponding control circuit 10, 20.In the driver circuit 1, the center tap 14, 24 serves not only to switch the semiconductor switch 110, 120 assigned to it on and off, but also to change a gate potential UG at the gate terminal 15, 25 of the respective semiconductor switch 110, 120 when it is in the off, i.e., open, state. For this purpose, the driver circuit 1 has a control unit 5 for controlling the drive circuits 10, 20, in particular for controlling their upper and lower switches S10.1, S10.2, S20.1, S20.2. In combination with the control unit 5, the driver circuit 1 is particularly designed to change a gate potential UG of the first semiconductor switch 110 depending on a switching operation at the second semiconductor switch 120 when the first semiconductor switch 120 is in a off, i.e., open, state.With the aid of the control unit 5, the driver circuit 1 is additionally designed to change a gate potential UG of the second semiconductor switch 120 as a function of a switching operation at the first semiconductor switch 110 when the second semiconductor switch 120 is in a switched-off, i.e., open, state.

[0053] In Fig. 3, the operation of the driver circuit 1 from Fig. 2 is explained using diagrams 304, 305, 306. The explanation is given by way of example for the case of the first semiconductor switch 110 being switched off while the second semiconductor switch 120 is switched off, i.e., in the switched-off state.

[0054] The starting point is a first semiconductor switch 110 that is switched on and a second semiconductor switch 120 that is switched off. At the initial time t=0, the upper switch S10.1 in the first control circuit 10 is closed and the lower switch S10.2 is open. In the second control circuit 20, the upper switch S20.1 is in its open state and the lower switch S20.2 is in its closed state. Diagram 304 shows a time profile 210 of the gate-source voltage UGS at the first semiconductor switch 110. At time t0, the switch-off process of the first semiconductor switch 110 is initiated. For this purpose, a negative gate-source voltage UGS is built up at the gate driver terminal 115 relative to the source driver terminal 116 by closing the lower switch S10.2 and opening the upper switch S10.1 shortly beforehand, possibly also simultaneously at t0.A charge stored in the gate-source capacitance 112 discharges via the lower resistor R10.2 of the first control circuit 10, resulting in an exponentially decaying time characteristic 210. When a threshold value for the gate-source voltage is undershot (here after a time period Δt after the switching process is triggered), the first semiconductor switch 110 is opened, and the resistance between its drain and source terminals becomes high-impedance. The switching process now generates a voltage peak 221 in the gate-source voltage of the switched-off or switched-off second semiconductor switch 120. To ensure that the voltage peak 221 does not fall below the lower tolerance limit 223, the gate potential UG of the second semiconductor switch 120 is raised relative to its source potential. The increase is achieved by briefly opening the lower switch S20.2 in the second control unit 20 and the upper switch S20.1 is briefly closed. This is illustrated in diagram 305 using the time profiles assigned to switches S10.1, S10.2, S20.1, S20.2. By raising the gate potential UG, the voltage peak 221 is shifted upwards, which is symbolized by an upward-pointing arrow in diagram 306, which illustrates a time profile of the gate-source voltage UGS at the second semiconductor switch 120.

[0055] Instead of a single pulsed increase of the gate potential UG of the second semiconductor switch 120 in the off state, a multiple pulsed increase can also occur. In this case, the upper switch S20.1 of the second control circuit 20 would have several short turn-on pulses. This can prevent, in a clocked manner, a drop below the tolerance limit 223 at the second semiconductor switch 120, which would otherwise occur conventionally.

[0056] The operation explained above can also be applied to the case in which the second semiconductor switch 120 within the half-bridge 100 is switched off when the first semiconductor switch 110 is switched off, i.e., switched off. Then, the time characteristic 210 shown in diagram 304 reflects the gate-source voltage UGS at the second semiconductor switch 120, while the time characteristic 220 shown in diagram 306 reflects the gate-source voltage UGS at the switched-off first semiconductor switch 110. The time courses of the upper and lower switches S10.1, S10.2, S20.1, S20.2 assigned to the control units 10, 20 are to be exchanged between the control units 10, 20, ie the currently displayed time course for S10.1 then describes the time course of the switch S20.1, the currently displayed time course for S10.2 then describes the time course of the switch S20.2, the currently displayed time course for S20.1 then describes the time course of the switch S10.1 , and the currently displayed time course for S20.2 then describes the time course of the switch S10.2.

[0057] In Fig. 4 a second embodiment of a driver circuit according to the invention is

[0058] 1 for reducing / preventing damage to a half-bridge 100 caused by a voltage peak 221 in the gate-source voltage of a semiconductor switch 110, 120. The driver circuit 1 corresponds in many respects to the first embodiment already shown in Fig. 2, which is why reference is made to the figure description of Fig. 2 for the identical points. Therefore, only the differences from the first embodiment according to Fig. 2 are described below.

[0059] The second embodiment of the driver circuit 1 also includes two control circuits 10, 20, each of which is designed to control one of the semiconductor switches 110, 120. In contrast to the first embodiment according to Fig. 2, however, each of the control circuits 10, 20 includes a voltage divider, each with

[0060] 2 half-bridges. Each of the half-bridges has an upper series circuit consisting of an upper switch S10.1, S10.3, S20.1, S20.3 and an upper resistor R10.1, R10.3, R20.1, R20.3, as well as a lower series circuit consisting of a lower switch S10.2, S10.4, S20.2, S20.4 and a lower resistor R10.2, R10.4, R20.2, R20.4. The upper series circuits and the lower series circuits of each, in particular of the same half-bridge, are each connected in series via a center tap 14, 24. Each of the center taps 14, 24 is connected to the gate driver terminal 15, 25 of its associated control circuit 10, 20. The source driver terminal 16, 26 of each drive circuit 10, 20 is connected to the center point 13, 23 of its corresponding drive circuit 10, 20.The center point 13, 23, via which the two voltage sources Un, U12 of a control circuit 10, 20 are connected in series, serves as the reference potential GND10, GND20 within the control circuit 10, 20.

[0061] The control unit 5 is designed to set a potential UG at the gate driver terminal 15, 25 within each drive circuit 10, 20 and, via this, a gate-source voltage UGS between the gate driver terminal 15, 25 and the source driver terminal 16, 26 by actuating one or more switches S10.1 - S10.4, S20.1 - S20.4. In this case, it is possible for each of the control circuits 10, 20 to simultaneously close or keep closed one or more upper switches S10.1, S10.3, S20.1, S20.3, but none of the lower switches S10.2, S10.4, S20.2, S20.4, as well as to simultaneously close or keep closed one or more lower switches S10.2, S10.4, S20.2, S20.4, but none of the upper switches S10.1, S10.3, S20.1, S20.3. Furthermore, however, it is also possible to simultaneously close or keep closed one or more upper switches (S10.1, S10.3, S20.1, S20.3), as well as one or more lower switches (S10.2, S10.4, S20.2, S20.4) of the voltage divider simultaneously or to keep it closed. In particular, with the latter variant, it is possible to specifically specify several discretely adjustable potential levels at the gate driver terminal 15, 25. Although Fig. 4 shows an exemplary voltage divider with only two half-bridges for each of the control circuits, it is also possible within the scope of the invention for the voltage divider to comprise more than two half-bridges, for example, three or four half-bridges.

[0062] In Figs. 5a and 5b, an operation of the driver circuit 1 from Fig. 4 is explained in more detail. While Fig. 5a shows an example of switching on the first semiconductor switch 110 with the second semiconductor switch 120 off, Fig. 5b shows an example of switching off the first semiconductor switch 110 with the second semiconductor switch 120 off. The diagrams 504-505 show in detail: a time profile 210 of a gate-source voltage UGS of the first semiconductor switch 110 (diagram 504), a time profile 220 of a gate-source voltage UGS of the second semiconductor switch 120 together with upper tolerance limits 222 and lower tolerance limits 223 assigned to the second semiconductor switch 120 (diagram 506), as well as time profiles that represent the switching states of the upper and lower switches S10.1 - S10.4, S20.1 - S20.4 within the control circuits 10, 20 (diagram 505).

[0063] The starting point of Fig. 5a is an open first semiconductor switch 110 and an open second semiconductor switch 120. Therefore, in the first control circuit 10, the upper switches S10.1, S10.3 are open, while the lower switches S10.2, S10.4 are closed. In the second control circuit 20, the upper switches S20.1, S20.3 are open, while a lower switch S20.2 is closed and another lower switch S20.4 is open. At time t0, a closing of the first semiconductor switch 110 is initiated. This is done by the first control circuit 10, specifically by closing the upper switches S10.1, S10.3 there, the lower switches S10.2, S10.4 having been opened shortly beforehand - possibly even at the same time as the upper switches.The control unit 5 now knows that, due to the switching operation (here, the switching on) of the first semiconductor switch 110, an upward voltage peak 221 is to be expected in the gate-source voltage UGS of the second semiconductor switch 120. The upward voltage peak 221 is now counteracted by a lower switch S20.4 of the second control circuit 20 being temporarily closed for an average duration Δt* of the voltage peak 221. This results in a reduction in the gate potential UG at the gate driver terminal 25 of the second control circuit 20 and, consequently, a downward shift of the upward voltage peak 221. This is symbolized in diagram 506 by a downward-pointing arrow. After the time period Δt* has elapsed, the lower switch S20.3 of the second control circuit 20 is opened again.

[0064] In contrast to Fig. 5a, the starting point of Fig. 5b is now a closed first semiconductor switch 110 and an open second semiconductor switch 120. Accordingly, in the first control circuit 10, the upper switches S10.1, S10.3 are closed, while the lower switches S10.2, S10.4 are open. In the second control circuit 20, the upper switches S20.1, S20.3 are open, while a lower switch S20.2 is closed and another lower switch S20.4 is open. At time t0, an opening of the first semiconductor switch 110 is now initiated. This takes place in the first control circuit 10, in particular by closing the lower switches S10.2, S10.4, the upper switches S10.1, S10.3 having been opened shortly beforehand, possibly also at the same time at t0. The subsequently resulting downward voltage peak 221 in the gate-source voltage UGS of the second semiconductor switch 120 is counteracted here by an upper switch S20.3 of the second control circuit 20 is closed for an average duration Δt* of the voltage peak 221. This results in an increase in the gate potential UG at the gate driver terminal 25 of the second control circuit 20. By increasing the gate potential UG at the gate driver terminal 25, the downward-directed voltage peak 221 is shifted upward, which is symbolized in diagram 506 by an upward-directed arrow. After the time period Δt* has elapsed, the upper switch S20.3 is opened again.

[0065] In Fig. 5b, exceeding an upper tolerance limit 221 by an upwardly directed voltage peak 221 is already reduced or prevented by the fact that the off state of the respective semiconductor switch - here: the second semiconductor switch 120 - is maintained by a negative gate-source potential UGS < 0. Therefore, if an upwardly directed voltage peak 221 occurs, a reduction in the corresponding gate potential UG may not be necessary. However, the reduction may become necessary if i) the off state of the respective semiconductor switch is not maintained with a negative gate-source voltage UGS < 0 V, but for example with a gate-source voltage of UGS = 0 V and / or ii) a ratio of the height of the voltage peak 221 and a distance of the tolerance limit 222, 223 exceeds a threshold value.It may be advantageous, when the semiconductor switches 110, 120 are switched off, to keep a base level of the gate potential UG slightly negative if an upward voltage peak is expected, and, on the other hand, to keep it slightly positive if a downward voltage peak is expected. Setting corresponding base levels for the gate potential UG at the respective gate driver output 15, 25 can also be achieved by actuating the corresponding switches S10.1 - S10.4, S20.1 - S20.4.

[0066] Fig. 6 shows a third embodiment of a driver circuit 1 according to the invention for gentle operation, together with a half-bridge 100 controlled by the driver circuit 1. In the following, only the different aspects from the embodiments of Figs. 2 and 4 are explained, while reference is made to the previous description for similar aspects. In the third embodiment of the driver circuit 1, too, each of the drive circuits 10, 20 has a series connection of two voltage sources 11, 12 and 21, 22, respectively. The two voltage sources of one, in particular of the same, drive circuit 10, 20 are each connected in series via a center point 13, 23 operating as a reference potential GNDw, GND20. The center point 13, 23 is in each case connected to the source driver terminal 16, 26 of the drive circuit 10, 20 assigned to it.A positive (+) pole of the first voltage source 11, 21 and a negative (-) pole of the second voltage source 12, 22 serve as supply voltage for an amplifier 17, 27, and possibly also for an inverting amplifier 18, 28 (not explicitly shown in Fig. 6). The amplifier 17, 27 is connected on the input side to the control unit 5 of the driver circuit 1 via a first control input 19.1. An output of the amplifier 17, 27 is connected via a resistor R10.5, R20.5 to the gate driver terminal 15, 25 of the respective control circuit 10, 20. The negative (-) pole of the second voltage source 12, 22 is connected either via a capacitor C10, C20 and a fifth switch S10.5 to the center point 13, 23 or via the capacitor C10, C20 and a sixth switch S10.6, S20.6 to the gate driver terminal 15, 25. Within their respective control circuits 10, 20, are the fifth switch S10.5, S20.5 and the sixth switch S10.6, S20.6 are each connected by one of their contacts to the capacitor C10, C20 of the control circuit 10, 20. The switches S10.5, S20.5, S10.6, S20.6 are controlled in each of the control circuits 10, 20 via a second control input 19.2, 29.2 connected to the control unit 5. Due to the inverting amplifier 18, 28, the switching states of the fifth switch S10.5, S20.5 are inverse to those of the sixth switch S10.6, S20.6, i.e., when the fifth switch S10.5, S20.5 is closed, the sixth switch S10.6, S20.6 is open, and vice versa.

[0067] In Fig. 7, an operation of the third embodiment of the driver circuit 1 from Fig. 6 is explained in more detail using various diagrams 704-706, exemplarily for the case of the first semiconductor switch 110 being switched off when the second semiconductor switch 120 is switched off. The diagrams show a time profile 210 for a gate-source voltage UGS of the first semiconductor switch 120 (diagram 704) and a time profile 220 of a gate-source voltage UGS of the switched-off second semiconductor switch 120 (diagram 706). Diagram 705 shows corresponding time profiles for the control inputs 19.1, 19.2, 29.1, 29.2 and the switching states of the fifth and sixth switches S10.5, S10.6, S20.5, S20.6 of the respective control circuits 10, 20.

[0068] The starting point at t = 0 is a closed first semiconductor switch 110 and an open second semiconductor switch 120. In the first control circuit 10, the first control input 19.1 and the second control input 19.2 each have a "high" signal. The fifth switch 10.5 is in a closed ("on") state and the sixth switch is in its open ("on") state. In the second control circuit 20, the first control input 19.1 has a "low" signal and the second control input 29.2 has a "high" signal. Consequently, the fifth switch S20.5 is in its closed ("on") state and the sixth switch S20.6 is in its open ("off") state.

[0069] At time t0, the control unit 5 sends a signal to turn off the first semiconductor switch 110 by changing the first control input 19.1 from the "high" signal to a "low" signal. In response, the amplifier 17 provides a potential at its output that corresponds to the negative (-) pole of the second voltage source 12. As a result, the charge stored in the gate-source capacitance 112 can discharge via the gate driver terminal 15 and the resistor R10.5, which is why the time characteristic 210 of the gate-source voltage UGS of the first semiconductor switch 110 decays exponentially from t0. To counteract an immediately occurring downward voltage peak 221 in the gate-source voltage UGS of the second semiconductor switch 120, a gate potential UG of the second semiconductor switch 120 is raised in its off state. For this purpose, the second control input 29 is switched on at t0.2 of the second control circuit 20 is set by the control unit 5 from the present "high" signal to a "low" signal for a predefined period of time Δt*. Thus, in the second control circuit 20, the fifth switch S20.5 is opened and the sixth switch S20.6 is closed for the predefined period of time Δt*. The capacitor C20 of the second control circuit 20, previously charged to the potential difference between the reference potential GND20 and the negative (-) pole of the second voltage source 22, is thereby temporarily connected to the gate driver output 25, whereby the gate potential UG at the gate terminal of the second semiconductor switch 120—and thus also the voltage peak 221—is kept within its permissible tolerance limits 222.

[0070] REPLACEMENT SHEET (RULE 26) 223 - is raised. The increase in voltage peak 221 is symbolized in diagram 706 by an upward-pointing arrow.

[0071] Fig. 8 shows a fourth embodiment of a driver circuit 1 according to the invention for gentle operation of a half-bridge 100, together with the half-bridge 100 controlled by the driver circuit 1. The driver circuit 1 of Fig. 8 is similar in many features to the driver circuits 1 shown in Fig. 2 and Fig. 4, respectively. Therefore, only the different aspects from the embodiments of Fig. 2 and Fig. 4 are explained below, while reference is made to the previous descriptions for similar aspects.

[0072] In the fourth embodiment of the driver circuit 1 in Fig. 8, the first control circuit 10 and the second control circuit 20 each comprise a voltage divider. The voltage divider has a first number (in Fig. 8: exemplary = 1) of upper series circuits, each with an upper switch S10.1, S20.1 and an upper resistor R10.1, R20.1. In addition, the voltage divider has a second number (in Fig. 8 exemplary = 2) of lower series circuits, each with a lower switch S10.2, S10.4, S20.2, S20.4 and a lower resistor R10.2, R10.4, R20.2, R20.4. In contrast to the embodiments in Fig. 2 and Fig. 4, however, in the fourth embodiment of the driver circuit 1 the first number of upper series circuits is different from the second number of lower series circuits.Within the same control circuit 10, 20, each of the upper series circuits is connected at one end to a common center tap 14, 24 of the voltage divider. Each of the lower series circuits is also connected at one end to the common center tap 14, 24 within its associated control circuit 10, 20. The common center tap 14, 24 is in turn connected to the gate driver terminal 15, 25 of the respective control circuit.

[0073] The upper series circuits of the same drive circuit 10, 20 are each connected at their other end to the positive pole of the first voltage source 11, 21 of the respective drive circuit. In contrast, the lower series circuits of the same drive circuit are each connected at their other end to the negative pole of the second voltage source 12, 22 of the respective drive circuit. The two voltage sources 11, 12, 21, 22 of one and the same drive circuit 10, 20 are each connected in series to one another, i.e. for each of the drive circuits 10, 20, the negative pole of its first voltage source 11, 21 is connected to the positive pole of its second voltage source 12, 22. Analogous to the driver circuits of Fig. 2 and Fig. 4, the fourth embodiment of the driver circuit 1 according to Fig.8, in combination with the control unit 5, is designed to change a gate potential UG of the first semiconductor switch 110 as a function of a switching operation at the second semiconductor switch 120 when the first semiconductor switch 120 is in a switched-off, i.e., open, state. With the aid of the control unit 5, the driver circuit 1 is additionally designed to change a gate potential UG of the second semiconductor switch 120 as a function of a switching operation at the first semiconductor switch 110 when the second semiconductor switch 120 is in a switched-off, i.e., open, state.

[0074] By making the first number of upper series circuits unequal to the second number of lower series circuits, a greater degree of freedom and finer adjustment of the potentials at the respective gate driver terminal 15, 25 can be provided individually only for charging the respective gate-source capacitance 112, 122 or only for discharging the respective gate-source capacitance 112, 122. This results in a cost advantage compared to the embodiment of the driver circuit 1 shown in Fig. 4.

[0075] Fig. 8 shows, by way of example, the case in which the first number of upper series circuits is 1 and the second number of lower series circuits is 2. The voltage dividers in both of the control circuits 10, 20 each have the same first number and the same second number. However, other combinations of a first number of upper series circuits—e.g., 2, 3, or more than 3 upper series circuits—and a second number of lower series circuits—e.g., 1, 3, or more than 3 lower series circuits—are also possible within the scope of the invention. It is also possible within the scope of the invention for the first number of upper series circuits and the second number of lower series circuits to be designed differently for the different control circuits 10, 20. List of reference symbols

Claims

Patent claims 1. A method for controlling a half-bridge (100) comprising a first semiconductor switch (110) and a second semiconductor switch (120) which are connected in series between a first bridge terminal (101) and a second bridge terminal (102), with a driver circuit (1) connected to the semiconductor switches (110, 120), comprising the steps: Varying a gate-source voltage UGS at a switched-off one of the two semiconductor switches (110, 120) by changing a gate potential UG at a gate driver terminal (15, 25) of the driver circuit (1) which is connected to the switched-off semiconductor switch (110, 120), wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) counteracts a voltage peak (221) which is generated by a switching operation of the respective other semiconductor switch (120, 110) of the half-bridge (100) and takes place as a function of the switching operation of the respective other semiconductor switch (120, 110).

2. The method according to claim 1, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) is triggered in time by the switching operation of the respective other semiconductor switch (120, 110), and in particular has a time offset Δt to the switching operation of the respective other semiconductor switch (120, 110).

3. The method according to claim 1 or 2, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) is effected by temporarily connecting a capacitor (Cw, C20) with a preset voltage to the corresponding gate driver terminal (15, 25) in the respective drive circuit (10, 20) associated with the switched-off semiconductor switch (110, 120).

4. Method according to one of claims 1 to 3, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) within the control circuit (10, 20) of the switched-off semiconductor switch (110, 120) is carried out by setting a potential with the aid of a voltage divider, wherein the voltage divider comprises a first number of upper series circuits, each with an upper switch (S10.1, S20.1) and an upper resistor (R10.1, R20.1) and a second number of lower series circuits, different from the first number, each having a lower switch (S10.2, S10.4, S20.2, S20.4) and a lower resistor (R10.2, R10.4, R20.2, R20.4), wherein each of the upper series circuits is connected to each of the lower series circuits via a common center tap (14, 24) which is connected to the gate terminal (115, 125) of the switched-off semiconductor switch (110, 120).

5. Method according to one of claims 1 to 3, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) within the driver circuit (1) is carried out by setting a potential with the aid of a voltage divider having one or more bridge branches, each comprising an upper series circuit of an upper switch (S10.1, S10.3, S20.1, S20.3) and an upper resistor (R10.1, R10.3, R20.1, R20.3) and a lower series circuit of a lower switch (S10.2, S10.4, S20.2, S20.4) and a lower resistor (R10.2, R10.4, R20.2, R20.4), wherein the upper series circuit and the lower series circuit of each bridge branch of a control circuit (10, 20) are each connected via a center tap (14, 24) are connected to each other, which is connected to the gate terminal (115, 125) of the switched-off semiconductor switch (110, 120).

6. The method according to claim 4 or 5, wherein the setting of the potential with the aid of the voltage divider is carried out in that at least one or more upper switches (S10.1, S10.3, S20.1, S20.3) and one or more lower switches (S10.2, S10.4, S20.2, S20.4) of the voltage divider are closed simultaneously.

7. The method according to claim 4 or 5, wherein the setting of the potential with the aid of the voltage divider is carried out in that either one or more upper switches (S10.1, S10.3, S20.1, S20.3), but none of the lower switches (S10.2, S10.4, S20.2, S20.4) is / are closed at the same time, or one or more lower switches (S10.2, S10.4, S20.2, S20.4), but none of the upper switches (S10.1, S10.3, S20.1, S20.3) is / are closed at the same time.

8. Method according to one of the preceding claims, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) causes an increase of the gate potential UG at the corresponding gate Driver terminal (15, 25) when the other semiconductor switch (120, 110) is switched off.

9. The method according to any one of the preceding claims, wherein the variation of the gate-source voltage UGS at the switched-off semiconductor switch (110, 120) comprises a lowering of the gate potential UG at the corresponding gate driver terminal (15, 25) when the respective other semiconductor switch is switched on.

10. Driver circuit (1) for operating a half-bridge (100), wherein the half-bridge (100) has a first semiconductor switch (110) and a second semiconductor switch (120) which are connected in series between a first bridge terminal (101) and a second bridge terminal (102), comprising: a first drive circuit (10) with a first gate driver terminal (15) for connection to the gate terminal (115) of the first semiconductor switch (110) and a first source driver terminal (16, 26) for connection to a source terminal (116) of the first semiconductor switch (110), a second drive circuit (20) with a second gate driver terminal (25) for connection to the gate terminal (125) of the second semiconductor switch (120) and a second source driver terminal (26) for connection to a source terminal (126) of the second semiconductor switch (120),and a control unit (5) for operating the first drive circuit (10) and the second drive circuit (20), characterized in that the driver circuit (1) is designed and arranged to operate the half-bridge (100) according to the method according to one of the preceding claims.

11. Driver circuit (1) according to claim 10, characterized in that the first control circuit (10) and / or the second control circuit (20) each have a voltage divider, wherein the voltage divider has a first number of upper series circuits, each with an upper switch (S10.1, S20.1) and an upper resistor (R10.1, R20.1) and a second number of lower series circuits, different from the first number, each with a lower switch (S10.2, S10.4, S20.2, S20.4) and a lower resistor (R10.2, R10.4, R20.2, R20.4) wherein each of the upper series circuits is connected to each of the lower series circuits via a common center tap (14, 24), and wherein the common center tap (14, 24) is connected to the gate driver terminal (115, 125) of the corresponding drive circuit (10, 20).

12. Driver circuit (1) according to claim 10, characterized in that the first The first control circuit (10) and / or the second control circuit (20) each comprises a voltage divider with a bridge branch which has an upper A series circuit of an upper switch (S10.1, S10.3) and an upper resistor (R10.1, R10.3) and a lower series circuit of a lower switch (S10.2, S10.4) and a lower resistor (R10.2, R10.4), wherein the upper series circuit and the lower series circuit of the bridge branch are connected to one another via a center tap (14, 24), and wherein the center tap (14, 24) is in each case connected to the gate driver terminal (115, 125) of the corresponding drive circuit (10, 20).

13. Driver circuit (1) according to claim 12, characterized in that the voltage divider of the first drive circuit (10) and / or the voltage divider of the second drive circuit (20) each has a plurality of bridge branches, wherein each of the bridge branches comprises an upper series circuit of an upper switch (S10.1, S10.3) and an upper resistor (R10.1, R10.3) and a lower series circuit of a lower switch (S10.2, S10.4) and a lower resistor (R10.2, R10.4), wherein the upper series circuit and the lower series circuit of each bridge branch of a drive circuit (10, 20) are connected to one another via a center tap (14, 24) assigned to the respective bridge branch, and wherein each of the center taps (14, 24) is connected to the gate driver terminal (15, 25) of the drive circuit (10, 20) assigned to it. is.

14. Driver circuit (1) according to one of claims 10 to 13, characterized in that the first control circuit (10) comprises a capacitor (C10) having a first contact which can be connected via at least one switch (S10.5, S10.6) either to a first pole of a voltage source (12) or to the first gate driver terminal (15) of the first control circuit (10) and / or wherein the second control circuit (20) comprises a capacitor (C20) having a first contact which can be connected via at least a switch (S20.5, S20.6) can be connected either to a first pole of a voltage source (22) or to the second gate driver terminal (25) of the second drive circuit (20).

15. Driver circuit (1) according to claim 14, characterized in that a second contact of the capacitor (C10) of the first drive circuit (10) is connected to a second pole of the voltage source (12) of the first drive circuit (10), and / or wherein a second contact of the capacitor (C20) of the second drive circuit (20) is connected to a second pole of the voltage source (22) of the second drive circuit (20).

16. Driver circuit (1) according to one of claims 10 to 15, whose first control circuit (10) has a maximum of two voltage sources (11, 12) and / or whose second control circuit (20) has a maximum of two voltage sources (21, 22).

17. Current transformer with one or more half-bridges (100), characterized in that the current transformer comprises a driver circuit (1) or several driver circuits (1) according to one of claims 10 to 16 for controlling the one or more half-bridges (100).

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