Spy pocket neuron circuit system and Spy pocket neuron circuit

Abstract

A spiking neuron circuit system 100 includes: a charging circuit 10 that, when an input voltage is applied, starts charging of a capacitor 12 by an output current I of a field effect transistor 11; a pulse generation circuit 20 that generates and outputs a pulse signal when a charging voltage of the capacitor 12 reaches a first threshold value; and a control circuit 50 that controls the output current I of the field effect transistor 11 by controlling a bulk voltage and / or a gate voltage of the field effect transistor 11.

Description

[Technical Field]

[0001] This disclosure relates to a spiking neuron circuit system, and more particularly to a spiking neuron circuit system having a delay between the application of an input voltage and the output of a pulse signal. This disclosure also relates to a spiking neuron circuit usable in such a spiking neuron circuit system. [Background technology]

[0002] A spiking neuron circuit has been proposed that more faithfully mimics the firing signals of biological nerve cells. In a spiking neuron circuit, the waveform of the output signal is a spike-shaped pulse. International Publication No. 2020 / 175290 describes a spiking neuron circuit in which there is a predetermined waiting time between the application of an input voltage and the output of a spike-shaped pulse signal.

[0003] In the spiking neuron circuit described in International Publication No. 2020 / 175290, a capacitor is charged by the input voltage, and when the charging voltage of the capacitor reaches a predetermined value, a pulse signal is output. Furthermore, International Publication No. 2020 / 175290 describes how the pulse signal output by the spiking neuron circuit can be used to control the timing of the power supply circuit, thereby enabling extremely low power consumption control of the power supply circuit. [Overview of the project] [Problems that the invention aims to solve]

[0004] When a spiking neuron circuit is implemented on an integrated circuit, the characteristics of each element within the circuit will differ from the design values ​​due to the influence of the manufacturing process, element placement, and operating temperature. Therefore, the waiting time from when an input voltage is applied to the spiking neuron circuit until a pulse signal is output may also differ between the design value and the actual value.

[0005] Such discrepancies between design values ​​and actual values ​​can lead to technical challenges. For example, when using pulse signals output by a spiking neuron circuit to control the timing of a power supply circuit, as described in International Publication No. 2020 / 175290, a significant difference between the design value and the actual value of the waiting time may impair the control of the power supply circuit.

[0006] This is not the only issue that can arise. For example, when modulating the time interval between pulses in the pulse train output by a spiking neuron circuit according to the information being transmitted, the actual value of that time interval may differ from the designed value, which can lead to the information being received incorrectly by the receiver.

[0007] This disclosure aims to solve the above-mentioned problems and to provide a spiking neuron circuit system that can precisely control the waiting time from when an input voltage is applied until a pulse signal is output. [Means for solving the problem]

[0008] To solve the above problems, the spiking neuron circuit system according to this disclosure includes: a charging circuit that starts charging a capacitive component by the output current of a field-effect transistor when an input voltage is applied; a pulse generation circuit that generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value; and a control circuit that controls the output current of the field-effect transistor by controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor.

[0009] The control circuit may include a control voltage generation circuit that generates a control voltage for controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor.

[0010] The control circuit may further include a selection signal generation circuit that generates a selection signal for the control voltage generation circuit. The selection signal generation circuit may have a storage circuit that stores information for generating the selection signal.

[0011] The control circuit may discretely control either or both of the bulk voltage and / or gate voltage of the field-effect transistor.

[0012] The control voltage generation circuit includes a plurality of diodes connected in forward series between a first power line and a second power line, and may generate the control voltage from any of the voltages generated at each node between the diodes.

[0013] The control voltage generation circuit may include a capacitor, and the charging voltage of the capacitor may be used to generate the control voltage.

[0014] The spiking neuron circuit system may further include a reference signal circuit that outputs a reference signal after a predetermined time has elapsed since the input voltage was applied, and the control circuit may compensate for the waiting time from the application of the input voltage to the output of the pulse signal based on the time difference between the timing at which the reference signal is output and the timing at which the pulse signal is output.

[0015] The variation in temperature change over the predetermined time may be smaller than the variation in temperature change over the waiting time.

[0016] The charging circuit may be mounted on a semiconductor substrate. The spiking neuron circuit system may include a resistor and a capacitor, which are composed of discrete elements externally attached to the semiconductor substrate, and may further include a time constant circuit for charging the capacitor at a predetermined time constant, and the reference signal circuit may output the reference signal when the charging voltage of the capacitor reaches a second predetermined value.

[0017] The spiking neuron circuit system may further include a switch for controlling power supply to the resistor and the capacitor, and the switch may allow power supply to the resistor and the capacitor only when compensating for the waiting time.

[0018] The control circuit may stepwise switch the voltage supplied to either or both of the bulk terminal or the gate terminal of the field effect transistor until the time difference between the timing when the reference signal is output and the timing when the pulse signal is output becomes not more than a third predetermined value.

[0019] The control circuit may further include a control voltage generation circuit that generates a control voltage for controlling either or both of the bulk voltage or the gate voltage of the field effect transistor, and a selection signal generation circuit that generates a selection signal for the control voltage generation circuit to generate the control voltage. When the time difference between the timing when the reference signal is output and the timing when the pulse signal is output becomes not more than the third predetermined value, the compensation of the waiting time may be terminated. The selection signal generation circuit may have a storage circuit that stores information for generating the selection signal, and the information for generating the selection signal at the end of the compensation of the waiting time may be stored in the storage circuit.

[0020] The capacitive component of the charging circuit may include the parasitic capacitance of a transistor.

[0021] The control circuit may control the output current of the field effect transistor by controlling the bulk voltage.

[0022] The field effect transistor may be of N-channel type, and when the power supply voltage of the spiking neuron circuit system is VDD, the control circuit may control the bulk voltage within the range from -VDD to 0.4VDD.

[0023] The field effect transistor may be a P-channel type, and when the power supply voltage of the spiking neuron circuit system is VDD, the control circuit may control the bulk voltage in the range of 0.6VDD to 2VDD.

[0024] The control circuit may control the output current of the field effect transistor by controlling the gate voltage.

[0025] When the power supply voltage of the spiking neuron circuit system is VDD, the control circuit may control the gate voltage in the range of 0 to VDD.

[0026] The pulse generation circuit may have a positive feedback loop and a negative feedback loop.

[0027] The positive feedback loop may steepen the rising edge of the pulse signal, and the negative feedback loop may steepen the falling edge of the pulse signal.

[0028] The pulse generation circuit may include a plurality of cascaded inverters. Each of the plurality of inverters may include a P-channel field effect transistor and an N-channel field effect transistor that are complementarily turned on, and the ratio of the channel widths of the P-channel field effect transistor and the N-channel field effect transistor may be different between adjacent inverters.

[0029] The spiking neuron circuit system may further include a timing control circuit that outputs a standby signal, and a plurality of output control circuits provided corresponding to at least one of the pulse generation circuits, which output an output signal whose state transitions at a timing corresponding to the pulse signal output from the corresponding pulse generation circuit, and hold the state of the output signal during the standby period indicated by the standby signal when the standby signal is input.

[0030] The spiking neuron circuit system may include a switching element connected to the capacitive component. A pulse signal train may be output from the pulse generation circuit by repeatedly charging the capacitive component by the charging circuit and discharging the capacitive component by the switching element. The control circuit may control the pulse interval of the pulse signal train output from the pulse generation circuit.

[0031] The control circuit may control the pulse interval of the pulse signal train based on the information to be transmitted.

[0032] The information to be transmitted may be a time-varying input signal.

[0033] The spiking neuron circuit according to this disclosure comprises a charging circuit that starts charging a capacitive component with the output current of a field-effect transistor when an input voltage is applied, a plurality of inverters connected between an input node connected to the capacitive component and an output node that outputs a pulse signal, and a switching element provided between the input node and a first reference voltage, with a control terminal connected to the output node, and does not have a feedback loop that returns from the connection point between the inverters in the plurality of inverters to the input node.

[0034] The first stage inverter among the plurality of inverters may include a first switching element provided between the first reference voltage and an intermediate output node, and a second switching element provided between the intermediate output node and a second reference voltage. A first diode may be forward-connected between the first reference voltage and the first switching element, and a second diode may be forward-connected between the second switching element and the second reference voltage.

[0035] The comparator further includes one input terminal connected to the input node, the other input terminal connected to a predetermined intermediate potential between the first reference voltage and the second reference voltage, and an output terminal connected to the input terminal of the first stage inverter among the plurality of inverters. The spiking neuron circuit according to claim 27.

[0036] The charging circuit may include a plurality of capacitors, and a voltage determined according to the ratio of the capacitances of the plurality of capacitors may be applied to the gate terminal of the field-effect transistor. [Effects of the Invention]

[0037] The spiking neuron circuit system described herein allows for highly accurate control of the waiting time from the application of an input voltage to the output of a pulse signal. [Brief explanation of the drawing]

[0038] [Figure 1] This is a diagram showing the configuration of the spiking neuron circuit system according to Embodiment 1. [Figure 2] This diagram shows the internal configuration of the first-stage inverter of the pulse generation circuit according to Embodiment 1. [Figure 3] This diagram shows the internal configuration of the control circuit according to Embodiment 1. [Figure 4] This diagram shows the internal configuration of the startup circuit according to Embodiment 1. [Figure 5] This diagram shows the internal configuration of the input generation circuit according to Embodiment 1. [Figure 6] This diagram shows the internal configuration of the reset generation circuit according to Embodiment 1. [Figure 7] This diagram shows the internal configuration of the matching determination circuit according to Embodiment 1. [Figure 8] This diagram shows the internal configuration of the length / shortness determination circuit according to Embodiment 1. [Figure 9] This diagram shows the internal configuration of the selection signal generation circuit according to Embodiment 1. [Figure 10] This diagram shows the internal configuration of the control voltage generation circuit according to Embodiment 1. [Figure 11] This is a timing chart illustrating an example of normal operation of the spiking neuron circuit system according to Embodiment 1. [Figure 12] This is a flowchart illustrating the operation of the control circuit during the latency compensation operation of the spiking neuron circuit according to Embodiment 1. [Figure 13] This is a timing chart illustrating an example of the latency compensation operation of the spiking neuron circuit system according to Embodiment 1. [Figure 14] This figure shows the configuration of the spiking neuron circuit system according to Embodiment 2. [Figure 15] This diagram shows the internal configuration of the selection signal generation circuit according to Embodiment 2. [Figure 16] This diagram shows the internal configuration of the control voltage generation circuit according to Embodiment 2. [Figure 17] This is a timing chart illustrating an example of the latency compensation operation of the spiking neuron circuit system according to Embodiment 2. [Figure 18] This figure shows the configuration of the spiking neuron circuit system according to Embodiment 3. [Figure 19] This diagram shows the internal configuration of the control voltage generation circuit according to Embodiment 3. [Figure 20] This figure shows the configuration of the spiking neuron circuit system according to Embodiment 4. [Figure 21] This diagram shows the internal configuration of the control voltage generation circuit according to Embodiment 4. [Figure 22] This diagram shows the configuration of the charging circuit according to the first modified form of Embodiment 5. [Figure 23] This diagram shows the configuration of the charging circuit according to the second modified form of Embodiment 5. [Figure 24] This diagram shows the configuration of the charging circuit according to the third modified form of Embodiment 5. [Figure 25]This diagram shows the configuration of the charging circuit according to the fourth modified form of Embodiment 5. [Figure 26] This figure shows the configuration of the pulse generation circuit according to the first modified form of Embodiment 6. [Figure 27] This figure shows the configuration of a pulse generation circuit according to the second modified form of Embodiment 6. [Figure 28] This figure shows the configuration of the pulse generation circuit according to Embodiment 7. [Figure 29] This figure shows the configuration of the spiking neuron circuit system according to Embodiment 8. [Figure 30] This diagram shows the internal configuration of the control circuit according to Embodiment 8. [Figure 31] This figure shows the correspondence between the input and output of the selection signal generation circuit according to Embodiment 8. [Figure 32] This diagram shows the internal configuration of the control voltage generation circuit according to Embodiment 8. [Figure 33] This figure shows an example of the configuration of a control voltage generation circuit according to Embodiment 9. [Figure 34A] This figure shows the first and second stage inverters that constitute the pulse generation circuit according to Embodiment 10. [Figure 34B] This figure shows the first and second stage inverters that constitute the pulse generation circuit according to Embodiment 10. [Figure 35] This figure shows an example of the configuration of a spiking neuron circuit system according to Embodiment 11. [Figure 36] This figure shows an example of the internal configuration of the output control circuit according to Embodiment 11. [Figure 37] This is a timing chart showing an example of the operation of the spiking neuron circuit system according to Embodiment 11. [Figure 38] This figure shows an example of the configuration of a boost circuit controlled by the spiking neuron circuit system according to Embodiment 11. [Figure 39] This is a waveform diagram of the current flowing through an inductor. [Figure 40]This figure shows an example of the configuration of a charging circuit according to Embodiment 12. [Modes for carrying out the invention]

[0039] The embodiments of this disclosure will be described in detail below with reference to the drawings. Other embodiments may also be included in the claims and be implementable by those skilled in the art.

[0040] [Embodiment 1] (Spiking neuron circuit system 100) Figure 1 shows the configuration of a spiking neuron circuit system 100 according to Embodiment 1 of the present disclosure. The spiking neuron circuit system 100 comprises a charging circuit 10, a pulse generation circuit 20, a CR time constant circuit 30, a reference signal circuit 40, and a control circuit 50.

[0041] In Figure 1, a spiking neuron circuit is formed by a charging circuit 10 and a pulse generation circuit 20. The spiking neuron circuit outputs a spike-shaped pulse signal Vpls to the output terminal Tout after a predetermined waiting time has elapsed since an input voltage was applied to the input terminal Tin. However, in this disclosure, the shape of the pulse signal is not limited to a spike shape, and may be a rectangular pulse, for example. The spiking neuron circuit is mounted on a semiconductor substrate of an integrated circuit.

[0042] As mentioned earlier, the characteristics of each element mounted on the semiconductor substrate of an integrated circuit are affected by the manufacturing process, element placement, and operating temperature, and therefore differ from the design values. Consequently, the latency of a spiking neuron circuit may also differ between the design value and the actual value.

[0043] The CR time constant circuit 30, the reference signal circuit 40, and the control circuit 50 are circuits that control the latency of the spiking neuron circuit and compensate so that the actual latency matches the design value. These circuits are also mounted on the semiconductor substrate. However, only the resistor R and capacitor C of the CR time constant circuit 30 are composed of discrete elements and are mounted externally to the semiconductor substrate. In Figure 1, the region 32 enclosed by the dashed line represents the region mounted externally to the semiconductor substrate.

[0044] The spiking neuron circuit system 100 has two operating modes: normal operation and time-compensated operation. During normal operation of the spiking neuron circuit system 100, only the spiking neuron circuit and a portion of the control circuit 50, which are composed of the charging circuit 10 and the pulse generation circuit 20, are operational. At this time, a 1V DC voltage is applied to the input terminal Tin via an OR gate 60 from an external power supply (not shown).

[0045] On the other hand, during the latency compensation operation of the spiking neuron circuit system 100, in addition to the charging circuit 10 and pulse generation circuit 20, the CR time constant circuit 30, reference signal circuit 40, and control circuit 50 also operate. At this time, no power is supplied from an external power source (not shown), and a compensation input voltage Vin_bit=1V is applied to the input terminal Tin from the control circuit 50 via the OR gate 60.

[0046] (Charging circuit 10) When an input voltage is applied to the input terminal Tin of the spiking neuron circuit system 100 via the OR gate 60 from an external power supply (not shown) or a control circuit 50, the charging circuit 10 begins charging the capacitive component of its field-effect transistor using the output current I. The input voltage is a 1V DC voltage applied via the OR gate 60 from an external power supply (not shown) during normal operation, and a compensation input voltage Vin_bit applied via the OR gate 60 from the control circuit 50 during delay compensation operation.

[0047] The charging circuit 10 includes a transistor 11, which is an N-channel MOSFET, and a capacitor 12 as a capacitive component. The drain terminal of transistor 11 is connected to input node N0 of the charging circuit 10, and input node N0 is connected to input terminal Tin of the spiking neuron circuit system 100. The source terminal of transistor 11 is connected to one terminal of capacitor 12 and to input node N1 of the pulse generation circuit 20, which will be described later. In this embodiment 1, capacitor 12 is a capacitor mounted on a semiconductor substrate. The other terminal of capacitor 12 is grounded to ground GND on the semiconductor substrate.

[0048] Furthermore, the gate and source terminals of transistor 11 are short-circuited. Therefore, the gate-source voltage of transistor 11 is 0V, and ideally, no output current I should flow. However, in real MOSFETs, even when the gate-source voltage is 0V, a small leakage current called subthreshold current flows. When an input voltage is applied to the input terminal Tin of the charging circuit 10 from an external power supply (not shown) or a control circuit 50 via the OR gate 60, the charging circuit 10 starts charging the capacitor 12 with the subthreshold current of transistor 11.

[0049] In this disclosure, the term "capacitive component" does not refer only to capacitors mounted on a semiconductor substrate. For example, the parasitic capacitance of a MOSFET other than transistor 11 may be used as the capacitive component, or the capacitance of wiring mounted on the semiconductor substrate may be used. In other words, the term "capacitive component" in this disclosure is a concept that includes capacitors mounted on a semiconductor substrate, the parasitic capacitance of MOSFETs, and the capacitance of wiring, etc.

[0050] (Pulse generation circuit 20) The pulse generation circuit 20 generates and outputs a pulse signal Vpls when the charging voltage of the capacitor 12 of the charging circuit 10 reaches a first predetermined value. In detail, the pulse generation circuit 20 comprises four multi-stage connected inverters 21 to 24, diodes 25 and 26, and a transistor 27 which is an N-channel MOSFET.

[0051] The four inverters 21 to 24, connected in a multi-stage configuration, function as a delay circuit that delays the signal input to the first-stage inverter 21 for a certain period of time before outputting it from the last-stage inverter 24. For example, when 0V is input to the first-stage inverter 21, 0V is output from the last-stage inverter 24 after a certain delay. Also, as the voltage input to the first-stage inverter 21 increases and reaches a first predetermined value, which is the threshold at which the output of the inverter 21 switches, the output of the first-stage inverter 21 changes from 1V to 0V. At this time, 1V is output from the last-stage inverter 24 after a certain delay. Note that the number of inverters connected in a multi-stage configuration is not limited to four; any even number is acceptable. With a configuration that increases the number of inverters, the gain increases, making it easier to make the rising edge of the pulse signal steeper and reducing the energy generated by the pulse signal itself. This makes it possible to perform control using a control circuit with pulse signals with extremely low power consumption.

[0052] Furthermore, unlike the pulse generation circuit described in the aforementioned International Publication No. 2020 / 175290, there is no feedback loop that returns from the connection points between the four inverters 21 to 24 back to the input node N1. Therefore, the wiring area of ​​such a feedback loop is reduced, allowing for a smaller circuit. Moreover, it is possible to prevent such a feedback loop from picking up electromagnetic induction noise and causing adverse effects on the circuit operation due to such noise. In other words, the waiting time from when the input voltage is applied until the pulse signal is output can be set with high precision, enabling highly accurate control.

[0053] The input of the first-stage inverter 21 is connected to the input node N1 of the pulse generation circuit 20. The output of the last-stage inverter 24 is connected to the output node N2 of the pulse generation circuit 20. Output node N2 is connected to the output terminal Tout of the spiking neuron circuit system 100.

[0054] Furthermore, the gate terminal of transistor 27 is connected to output node N2. The drain terminal of transistor 27 is connected to input node N1, and the source terminal of transistor 27 is grounded to GND.

[0055] When the voltage at input node N1 rises from 0V to a first predetermined value, after a certain time delay by inverters 21 to 24, the voltage at output node N2 becomes 1V. When the voltage at output node N2 becomes 1V, transistor 27, which is an N-channel MOSFET, turns on, and its drain-source conducts, causing the voltage at input node N1 to become 0V. When the voltage at input node N1 becomes 0V, after a certain time delay by inverters 21 to 24, the voltage at output node N2 returns to 0V.

[0056] In the pulse generation circuit 20, the path from output node N2, transistor 27, input node N1, and inverters 21 and 24 back to output node N2 constitutes a delayed feedback loop that returns the voltage at output node N2 to 0V after a certain delay when it reaches 1V.

[0057] Figure 2 shows the internal configuration of the first-stage inverter 21 of the pulse generation circuit 20. The inverter 21 consists of an N-channel MOSFET transistor 21a and a P-channel MOSFET transistor 21b. The gate terminals of transistors 21a and 21b are both connected to the input node N1, and the drain terminals of transistors 21a and 21b are connected to the intermediate output node N10. The intermediate output node N10 is connected to the input of the subsequent inverter 22.

[0058] The source terminal of transistor 21a is connected to ground GND, which is a first reference voltage, via a forward-connected diode 25. The source terminal of transistor 21b is connected to the power line VDD, which is a second reference voltage, via a forward-connected diode 26. In this embodiment 1, the voltage of the power line VDD is 1V.

[0059] Diodes 25 and 26 are provided to suppress shoot-through current when transistors 21a and 21b transition from on to off or off to on. Specifically, the potential difference between the source terminals of transistors 21a and 21b is made smaller than the potential difference between ground GND and the power line VDD, thereby suppressing the shoot-through current that flows during the transition of transistors 21a and 21b and reducing power consumption.

[0060] Diodes 25 and 26 may be implemented by forming a PN junction on a semiconductor substrate, or they may be implemented by shorting the gate-drain terminals of a different MOSFET than transistors 21a and 21b, i.e., by a diode-connected MOSFET.

[0061] (CR time constant circuit 30) Returning to Figure 1, the CR time constant circuit 30 charges the capacitor C attached to the semiconductor substrate with a predetermined time constant CR when a compensation input voltage Vin_bit=1V is applied to the input terminal Tin via the OR gate 60 from the control circuit 50 (described later) during the waiting time compensation operation of the spiking neuron circuit system 100.

[0062] In detail, the CR time constant circuit 30 includes a resistor R and a capacitor C attached externally to the semiconductor substrate, and an AND gate 31 mounted on the semiconductor substrate. One end of the resistor R is connected to the output terminal of the AND gate 31. The other end of the resistor R is connected to one end of the capacitor C and to the input node N3 of the reference signal circuit 40, which will be described later.

[0063] The other end of capacitor C is grounded to GND. One input terminal of AND gate 31 is connected to input node N0 of the charging circuit 10. A switch control signal Vsw_bit, which takes a value of either 1V or 0V, is input to the other input terminal of AND gate 31 from the control circuit 50.

[0064] The resistor R is composed of individual components with high precision and excellent temperature characteristics, such as chip resistors and metal film resistors. The capacitor C is also composed of individual components with high precision and excellent temperature characteristics, such as ceramic capacitors and film capacitors. Therefore, the time constant CR of the CR time constant circuit 30 is more precise than the time constant determined by the components mounted on the semiconductor substrate.

[0065] Furthermore, the variation in the time constant CR, determined by the resistor R and capacitor C attached externally to the semiconductor substrate, with respect to temperature changes is smaller than the variation in the time constant with respect to temperature changes determined by the elements mounted on the semiconductor substrate.

[0066] The AND gate 31 functions as a switch that controls the power supply to the resistor R and capacitor C. Specifically, during the latency compensation operation of the spiking neuron circuit system 100, when a compensation input voltage Vin_bit = 1V is applied to the input terminal Tin via the OR gate 60, and the switch control signal Vsw_bit = 1V, the output of the AND gate 31 becomes 1V, allowing power to be supplied to the resistor R and capacitor C. This causes current to flow through the resistor R and charges the capacitor C.

[0067] On the other hand, during normal operation of the spiking neuron circuit system 100, even if a DC voltage is applied to the input terminal Tin from an external power supply (not shown) via the OR gate 60, if the switch control signal Vsw_bit = 0V, the output of the AND gate 31 becomes 0V, and the power supply to the resistor R and capacitor C is cut off. As a result, no current flows through the resistor R, and the capacitor C is not charged.

[0068] (Reference signal circuit 40) The reference signal circuit 40 outputs a reference signal Vref when, during the latency compensation operation of the spiking neuron circuit system 100, the switch control signal Vsw_bit = 1V is applied to the input terminal Tin, and a predetermined time has elapsed since the compensation input voltage Vin_bit = 1V was applied, and the charging voltage of the capacitor C of the CR time constant circuit 30, i.e., the voltage at the input node N3, reaches a second predetermined value.

[0069] Here, the reference signal circuit 40 according to this embodiment 1 has the same configuration as the pulse generation circuit 20 described above. Therefore, the first predetermined value of the pulse generation circuit 20 and the second predetermined value of the reference signal circuit 40 are equal. When the charging voltage of the capacitor C of the CR time constant circuit 30 reaches the second predetermined value which is equal to the first predetermined value, the reference signal circuit 40 generates and outputs a pulse signal as a reference signal Vref.

[0070] In detail, the reference signal circuit 40 comprises four multi-stage connected inverters 41 to 44, diodes 45 and 46, and a transistor 47 which is an N-channel MOSFET. The input of the first-stage inverter 41 is connected to the input node N3 of the reference signal circuit 40. The output of the last-stage inverter 44 is connected to the output node N4 of the reference signal circuit 40. The reference signal Vref output from output node N4 is input to the control circuit 50.

[0071] Additionally, the gate terminal of transistor 47 is connected to output node N4. The drain terminal of transistor 47 is connected to input node N3, and the source terminal of transistor 47 is grounded to GND.

[0072] (Control circuit 50) During the latency compensation operation of the spiking neuron circuit system 100, the control circuit 50 controls the output current I of transistor 11 by controlling the bulk voltage Vb of transistor 11 included in the charging circuit 10.

[0073] In detail, the control circuit 50 compensates for the waiting time based on the time difference between a predetermined time from when the compensation input voltage Vin_bit=1V is applied to the input terminal Tin until the reference signal Vref is output by the reference signal circuit 40, and the waiting time from when the compensation input voltage Vin_bit=1V is applied to the input terminal Tin until the pulse signal Vpls is output by the pulse generation circuit 20.

[0074] More specifically, the control circuit 50 increases the output current I of transistor 11 by controlling the bulk voltage Vb of transistor 11 in the charging circuit 10 to rise if the waiting time until the pulse signal Vpls is output is longer than the predetermined time until the reference signal Vref is output. If the output current I of transistor 11 increases, the time until the charging voltage of capacitor 12 reaches a first predetermined value is shortened, and the time until the operation of pulse generation circuit 20 is started is also shortened. As a result, the waiting time from when the compensation input voltage Vin_bit=1V is applied to the input terminal Tin until the pulse signal Vpls is output to the output terminal Tout is shortened.

[0075] On the other hand, if the waiting time until the pulse signal Vpls is output is shorter than the predetermined time until the reference signal Vref is output, the control circuit 50 reduces the output current I of the transistor 11 by controlling the bulk voltage Vb of the transistor 11 included in the charging circuit 10 to decrease. If the output current I of the transistor 11 decreases, the time until the charging voltage of the capacitor 12 reaches the first predetermined value increases, and the time until the operation of the pulse generation circuit 20 also increases. As a result, the waiting time from when the compensation input voltage Vin_bit=1V is applied to the input terminal Tin until the pulse signal Vpls is output to the output terminal Tout increases.

[0076] As mentioned earlier, the transistor 11 and capacitor 12 of the charging circuit 10 are mounted on a semiconductor substrate, so the characteristics of these elements are susceptible to the effects of the manufacturing process, element placement, and operating temperature. Therefore, the waiting time until the pulse signal Vpls defined by the charging circuit 10 is output may differ between the design value and the actual value. In contrast, the resistor R and capacitor C of the CR time constant circuit 30 are composed of high-precision discrete elements externally mounted on the semiconductor substrate. Therefore, the accuracy of the predetermined time until the reference signal Vref defined by the CR time constant circuit 30 is output is higher than the accuracy of the waiting time until the pulse signal Vpls defined by the charging circuit 10 is output.

[0077] The control circuit 50 compensates for the waiting time between the application of the compensation input voltage Vin_bit=1V and the output of the pulse signal Vpls by controlling the bulk voltage Vb of the transistor 11 included in the charging circuit 10, thereby calibrating the timing of the output of the reference signal Vref to coincide with the timing of the output of the pulse signal Vpls.

[0078] Figure 3 shows the internal configuration of the control circuit 50. The control circuit 50 includes a startup circuit 51, an input generation circuit 52, a reset generation circuit 53, a match determination circuit 54, a long / short determination circuit 55, a selection signal generation circuit 56, and a control voltage generation circuit 57.

[0079] (Startup circuit 51) The startup circuit 51 activates the control circuit 50 when predetermined conditions are met, initiating the waiting time compensation operation of the spiking neuron circuit system 100. In this embodiment 1, the startup circuit 51 activates the control circuit 50 every hour after power is supplied to the spiking neuron circuit system 100, initiating the compensation operation.

[0080] However, the timing for initiating the compensation operation is not limited to this. The compensation operation may be initiated every few minutes, every few days, or, for example, when the spiking neuron circuit system 100 is powered on, when a significant environmental change is detected, etc.

[0081] Figure 4 shows the internal configuration of the startup circuit 51. The startup circuit 51 includes a timer circuit 51a. The timer circuit 51a outputs a pulse-shaped start signal Vin_pls every hour.

[0082] (Input generation circuit 52) Returning to Figure 3, when the input generation circuit 52 receives the start signal Vin_pls from the startup circuit 51, it generates and outputs a compensation input voltage Vin_bit=1V multiple times. The input generation circuit 52 also outputs a switch control signal Vsw_bit=1V.

[0083] As mentioned above, the compensation input voltage Vin_bit is the voltage applied to the input terminal Tin during the latency compensation operation of the spiking neuron circuit system 100. The reference signal circuit 40 outputs a reference signal Vref after a predetermined time has elapsed since the compensation input voltage Vin_bit was applied to the input terminal Tin. The pulse generation circuit 20 outputs a pulse signal Vpls after a predetermined waiting time has elapsed since the compensation input voltage Vin_bit was applied to the input terminal Tin.

[0084] As described later, the control circuit 50 steps-by-step switches the bulk voltage Vb of the transistor 11 included in the charging circuit 10 until the timing of the output of the reference signal Vref coincides with the timing of the output of the pulse signal Vpls. The compensation input voltage Vin_bit is output again each time the bulk voltage Vb is switched. The switch control signal Vsw_bit becomes 1V at the start of the delay compensation operation and continues to be output until the timing of the output of the reference signal Vref coincides with the timing of the output of the pulse signal Vpls and the compensation operation is completed.

[0085] Figure 5 shows the internal configuration of the input generation circuit 52. The input generation circuit 52 includes an SR latch 52a, a delay circuit 52b, an AND gate 52c, an OR gate 52d, and an SR latch 52e.

[0086] The S terminal of SR latch 52a receives the start signal Vin_pls from the activation circuit 51. The R terminal of SR latch 52a receives the match detection signal Syn_bit from the match detection circuit 54, which will be described later. The Q terminal of SR latch 52a outputs the switch control signal Vsw_bit. The switch control signal Vsw_bit is also input to one of the input terminals of AND gate 52c.

[0087] The delay circuit 52b receives a reset signal, Reset, from the reset generation circuit 54, which will be described later. The reset signal, Reset, is a pulsed signal that is output once each time the matching judgment operation, described later, is completed. When the reset signal Reset=1V is input to the delay circuit 52b, it outputs a pulsed signal after 1 microsecond. The output terminal of the delay circuit 52b is connected to the other input terminal of the AND gate 52c.

[0088] The output terminal of the AND gate 52c is connected to one input terminal of the OR gate 52d. The other input terminal of the OR gate 52d is input to the start signal Vin_pls. The output terminal of the OR gate 52d is connected to the S terminal of the SR latch 52e. The R terminal of the SR latch 52e is input to the reset signal Reset. The Q terminal of the SR latch 52e outputs the compensation input voltage Vin_bit.

[0089] (Reset generation circuit 53) Returning to Figure 3, the reset generation circuit 53 generates and outputs a reset signal Reset=1V after 1 microsecond has elapsed since both the reference signal Vref output from the reference signal circuit 40 and the pulse signal Vpls output from the pulse generation circuit 20 were output. The reset signal Reset is a signal that returns the compensation input signal Vin_bit, the extended reference signal Vref_bit, and the extended pulse signal Vpls_bit, which will be described next, back to 0V.

[0090] When the reset signal Reset=1V is output, the compensation input signal Vin_bit returns to 0V. The reset signal Reset is repeatedly output each time the bulk voltage Vb of the transistor 11 in the charging circuit 10 is switched, until the timing of the output of the reference signal Vref coincides with the timing of the output of the pulse signal Vpls.

[0091] Figure 6 shows the internal configuration of the reset generation circuit 53. The reset generation circuit 53 includes an SR latch 53a, an SR latch 53b, an AND gate 53c, and a delay circuit 53d.

[0092] The S terminal of SR latch 53a receives the reference signal Vref from the reference signal circuit 40. The R terminal of SR latch 53a receives the reset signal Reset again. The Q terminal of SR latch 53a outputs an extended reference signal Vref_bit, which starts outputting at the same timing as the reference signal Vref. The extended reference signal Vref_bit is also input to one of the input terminals of AND gate 53c. The extended reference signal Vref_bit returns to 0V when the reset signal Reset=1V is output.

[0093] The pulse signal Vpls from the pulse generation circuit 20 is input to the S terminal of the SR latch 53b. The reset signal Reset is re-input to the R terminal of the SR latch 53b. An extended pulse signal Vpls_bit is output from the Q terminal of the SR latch 53b, with the output starting at the same timing as the pulse signal Vpls. The extended pulse signal Vpls_bit is also input to the other input terminal of the AND gate 53c. The extended pulse signal Vpls_bit returns to 0V when the reset signal Reset=1V is output.

[0094] The output terminal of the AND gate 53c outputs a Fin_bit signal indicating whether both the reference signal Vref and the pulse signal Vpls have been output, and this signal is input to the delay circuit 53d. The delay circuit 53d outputs a reset signal Reset=1V after 1 microsecond has elapsed since the Fin_bit signal=1V was input.

[0095] Furthermore, because the delay time of the delay circuit 53d is 1 microsecond, the pulse widths of the extended reference signal Vref_bit and the extended pulse signal Vpls_bit will be 1 microsecond or longer. However, the pulse widths of the extended reference signal Vref_bit and the extended pulse signal Vpls_bit determined by the delay time of the delay circuit 53d are not limited to 1 microsecond. These pulse widths, i.e., the delay time of the delay circuit 53d, only need to be longer than the time from when the reference signal Vref and pulse signal Vpls, as well as the extended reference signal Vref_bit and the extended pulse signal Vpls_bit, are input to the short / short determination circuit 55 (described later) until the values ​​of the output Short_bit and Long_bit are determined.

[0096] (Concordance judgment circuit 54) Returning to Figure 3, the matching determination circuit 54 determines whether the timing at which the reference signal Vref is output from the reference signal circuit 40 and the timing at which the pulse signal Vpls is output from the pulse generation circuit 20 coincide when the input voltage Vin_bit=1V for compensation is output from the input generation circuit 52.

[0097] In detail, if the time difference between the timing at which the reference signal Vref is output and the timing at which the pulse signal Vpls is output is less than or equal to a third predetermined value of 1 millisecond, the match determination circuit 54 determines that the timings of the outputs of both signals are synchronized and outputs a match signal Syn_bit=1V and a match non-match signal ~Syn_bit=0V. On the other hand, if the time difference between the timing at which the reference signal Vref is output and the timing at which the pulse signal Vpls is output is greater than 1 millisecond, the match determination circuit 54 determines that the timings of the outputs of both signals are not synchronized and outputs a match signal Syn_bit=0V and a match non-match signal ~Syn_bit=1V.

[0098] Figure 7 shows the internal configuration of the match determination circuit 54. The match determination circuit 54 includes a holding circuit 54a, a holding circuit 54b, an AND gate 54c, and an SR latch 54d.

[0099] When the reference signal Vref is input to the reference signal circuit 40, the holding circuit 54a outputs a signal called Vref_1ms, which is the input reference signal Vref stretched into a pulse with a width of 1 millisecond. The output terminal of the holding circuit 54a is connected to one of the input terminals of the AND gate 54c.

[0100] When the pulse signal Vpls is input to the pulse generation circuit 20, the holding circuit 54b outputs a signal called Vpls_1ms, which is the input pulse signal Vpls stretched into a pulse with a width of 1 millisecond. The output terminal of the holding circuit 54b is connected to the other input terminal of the AND gate 54c.

[0101] The pulse widths output by the holding circuits 54a and 54b are set to be equal to the third predetermined value described above. That is, in this embodiment 1, since the third predetermined value is 1 millisecond, the pulse widths output by the holding circuits 54a and 54b are also set to 1 millisecond. However, the third predetermined value is not limited to 1 millisecond and can be set to any time.

[0102] The output terminal of the AND gate 54c is connected to the S terminal of the SR latch 54d. The R terminal of the SR latch 54d receives the Reset signal. The Q terminal of the SR latch 54d outputs the Syn_bit signal (match successful). The ~Q terminal of the SR latch 54d outputs the ~Syn_bit signal (no match).

[0103] (Length / shortness judgment circuit 55) Returning to Figure 3, the length determination circuit 55 determines whether the waiting time from when the input generation circuit 52 outputs the compensation input voltage Vin_bit=1V until the pulse generation circuit 20 outputs the pulse signal Vpls is longer or shorter than a predetermined time until the reference signal Vref is output by the reference signal circuit 40.

[0104] In detail, if the waiting time until the pulse signal Vpls is output is longer than a predetermined time until the reference signal Vref is output, the long / short determination circuit 55 outputs Short_bit=0V and Long_bit=1V.

[0105] On the other hand, if the waiting time until the pulse signal Vpls is output is shorter than the predetermined time until the reference signal Vref is output, the short / long determination circuit 55 outputs Short_bit=1V and Long_bit=0V.

[0106] Figure 8 shows the internal configuration of the length / short determination circuit 55. The length / short determination circuit 55 includes AND gate 55a, AND gate 55b, SR latch 55c, SR latch 55d, AND gate 55e, and AND gate 55f.

[0107] One input terminal of the AND gate 55a receives the reference signal Vref from the reference signal circuit 40. The other input terminal of the AND gate 55a receives the extended pulse signal Vpls_bit from the reset generation circuit 54. The output terminal of the AND gate 55a is connected to the S terminal of the SR latch 55c.

[0108] One input terminal of the AND gate 55b receives a pulse signal Vpls from the pulse generation circuit 20. The other input terminal of the AND gate 55b receives an extended reference signal Vref_bit from the reset generation circuit 54. The output terminal of the AND gate 55b is connected to the S terminal of the SR latch 55d.

[0109] The R terminal of the SR latch 55c is input to the Reset signal. The Q terminal of the SR latch 55c is connected to one input terminal of the AND gate 55e. The other input terminal of the AND gate 55e is input to the Syn_bit signal from the match determination circuit 53. The Short_bit signal is output from the output of the AND gate 55e.

[0110] A reset signal, Reset, is input to the R terminal of the SR latch 55d. The output terminal Q of the SR latch 55d is connected to one input terminal of the AND gate 55f. A non-match signal, ~Syn_bit, is input to the other input terminal of the AND gate 55f from the match determination circuit 53. A Long_bit signal is output from the output of the AND gate 55f.

[0111] (Selection signal generation circuit 56) Returning to Figure 3, the selection signal generation circuit 56 generates and outputs Vsw-2 from five selection signals Vsw+2 based on the Short_bit signal and Long_bit signal output from the short / long determination circuit. These five selection signals Vsw+2 to Vsw-2 are signals in which only one of them is 1V and all the others are 0V, based on the Short_bit signal and Long_bit signal. As will be described later, the bulk voltage Vb of the transistor 11 included in the charging circuit 10 is controlled in five stages based on which of these five selection signals is 1V.

[0112] Figure 9 shows the internal configuration of the selection signal generation circuit 56. The selection signal generation circuit 56 includes eight AND gates 56a to 56h, four SR latches 56i to 56l, and five EXOR gates 56m to 56q.

[0113] The two input terminals of AND gate 56a receive the selection signal Vsw+2 and the Short_bit signal. The output terminal of AND gate 56a is connected to the S terminal of SR latch 56i. The two input terminals of AND gate 56b receive the Long_bit signal and the selection signal Vsw+1. The output terminal of AND gate 56b is connected to the R terminal of SR latch 56i.

[0114] Similarly, the two input terminals of AND gate 56c receive the selection signal Vsw+1 and the Short_bit signal. The output terminal of AND gate 56c is connected to the S terminal of SR latch 56j. The two input terminals of AND gate 56d receive the Long_bit signal and the selection signal Vsw0. The output terminal of AND gate 56d is connected to the R terminal of SR latch 56j.

[0115] Similarly, the two input terminals of the AND gate 56e receive the selection signal Vsw0 and the Short_bit signal. The output terminal of the AND gate 56e is connected to the S terminal of the SR latch 56k. The two input terminals of the AND gate 56f receive the Long_bit signal and the selection signal Vsw-1. The output terminal of the AND gate 56f is connected to the R terminal of the SR latch 56k.

[0116] Similarly, the two input terminals of AND gate 56g receive the selection signal Vsw-1 and the Short_bit signal. The output terminal of AND gate 56g is connected to the S terminal of SR latch 56l. The two input terminals of AND gate 56h receive the Long_bit signal and the selection signal Vsw-2. The output terminal of AND gate 56h is connected to the R terminal of SR latch 56l.

[0117] Additionally, the power line VDD and the Q terminal of the SR latch 56i are connected to the two input terminals of the EXOR gate 56m. The EXOR gate 56m outputs a selection signal Vsw+2.

[0118] Similarly, the two input terminals of the EXOR gate 56n are connected to the Q terminals of the SR latch 56i and the SR latch 56j. The EXOR gate 56n outputs a selection signal Vsw+1.

[0119] Similarly, the two input terminals of the EXOR gate 56o are connected to the Q terminals of the SR latch 56j and the SR latch 56k. The EXOR gate 56o outputs the selection signal Vsw0.

[0120] Similarly, the two input terminals of the EXOR gate 56p are connected to the Q terminals of the SR latch 56k and the SR latch 56l. The EXOR gate 56p outputs the selection signal Vsw-1.

[0121] Similarly, the two input terminals of the EXOR gate 56q are connected to the Q terminal and ground (GND) of the SR latch 56l. The EXOR gate 56q outputs a selection signal Vsw-2.

[0122] (Control voltage generation circuit 57) Returning to Figure 3, the control voltage generation circuit 57 generates and outputs a bulk control voltage Vctr_b based on Vsw-2 from the selection signal Vsw+2 output from the selection signal generation circuit 56. This bulk control voltage Vctr_b is applied to the bulk terminal of the transistor 11 included in the charging circuit 10.

[0123] Figure 10 shows the internal configuration of the control voltage generation circuit 57. The control voltage generation circuit 57 includes 12 diodes 57a to 57l and 5 switches 57m to 57q.

[0124] Diodes 57a to 57l are connected in forward series between a first power line L1 connected to the power line VDD and a second power line L2 connected to the power line -VDD. Therefore, a voltage of δ = 2VDD / 12 is applied across each diode. In this embodiment 1, the voltage of the power line VDD is 1V, so δ = 2 / 12 ≈ 0.17V. Note that diodes 57a to 57l may be mounted by forming a PN junction on a semiconductor substrate, or they may be mounted by diode-connected MOSFETs.

[0125] Switch 57m turns on when the selection signal Vsw+2=1V. Switch 57n turns on when the selection signal Vsw+1=1V. Switch 57o turns on when the selection signal Vsw0=1V. Switch 57p turns on when the selection signal Vsw-1=1V. Switch 57q turns on when the selection signal Vsw-2=1V.

[0126] When the selection signal Vsw+2=1V and all other selection signals are 0V, the bulk control voltage Vctr_b=2δ=0.34V is output.

[0127] When the selection signal Vsw+1=1V and all other selection signals are 0V, the bulk control voltage Vctr_b=δ=0.17V is output.

[0128] When the selection signal Vsw0 = 1V and all other selection signals are 0V, the bulk control voltage Vctr_b = 0V is output.

[0129] When the selection signal Vsw-1 = 1V and all other selection signals are 0V, the bulk control voltage Vctr_b = -δ = -0.17V is output.

[0130] When the selection signal Vsw-2 = 1V and all other selection signals are 0V, the bulk control voltage Vctr_b = -2δ = -0.34V is output.

[0131] (Operation of the spiking neuron circuit system 100) Next, the operation of the spiking neuron circuit system 100 according to this embodiment 1 will be described. First, the normal operation of the spiking neuron circuit system 100 will be described, and then the latency compensation operation of the spiking neuron circuit system 100, which is the main focus of this disclosure, will be described.

[0132] (normal operation) The normal operation of the spiking neuron circuit system 100 according to this embodiment 1 will now be described. During the normal operation of the spiking neuron circuit system 100 shown in Figure 1, the compensation input voltage Vin_bit = 0V and the switch control signal Vsw_bit = 0V. Also, in the initial state, the capacitor 12 of the charging circuit 10 is not charged, and its charging voltage is 0V.

[0133] Since the charging voltage of capacitor 12 is 0V, the voltage at input node N1 of pulse generation circuit 20 is also 0V, and the output of the first-stage inverter 21 is 1V. Therefore, the output of the second-stage inverter 22 is 0V, the output of the third-stage inverter 23 is 1V, the output of the last-stage inverter 24 is 0V, and the voltage at output node N2 is 0V. Since output node N2 is connected to output terminal Tout, the voltage at output terminal Tout is also 0V.

[0134] In this initial state, let's consider the case where a 1V DC voltage is applied to the input terminal Tin from an external power source (not shown) via the OR gate 60. First, since the compensation input voltage Vin_bit = 0V, no power is supplied from the control circuit 50 via the input terminal Tin. Also, since the switch control signal Vsw_bit = 0V, the DC power supplied from the external power source (not shown) via the OR gate 60 is not supplied to the CR time constant circuit 30, but only to the charging circuit 10.

[0135] Figure 11 is a timing chart illustrating an example of the normal operation of the spiking neuron circuit system 100. First, at time t0, a 1V DC voltage is applied to the input terminal Tin via an OR gate 60 from an external power supply (not shown), causing the voltage at the input terminal Tin to become 1V.

[0136] At this time, the transistor 11 of the charging circuit 10 outputs an output current I, which is the subthreshold current. This output current I charges the capacitor 12, and its charging voltage increases. Since the charging voltage of the capacitor 12 is equal to the voltage at the input node N1 of the pulse generation circuit 20, the voltage at the input node N1 also increases.

[0137] At time t1, when the voltage at input node N1 reaches a first predetermined value Vth1, which is the threshold at which the output of the first-stage inverter 21 switches, the output of the first-stage inverter 21 changes from 1V to 0V. Due to this change, the output of the second-stage inverter 22 changes from 0V to 1V, the output of the third-stage inverter 23 changes from 1V to 0V, and the output of the last-stage inverter 24 changes from 0V to 1V. As a result, after a certain time delay from when the voltage at input node N1 reaches the first predetermined value Vth1, the voltage at output node N2 rises sharply from 0V to 1V. Since output node N2 is connected to output terminal Tout, the voltage at output terminal Tout also rises sharply from 0V to 1V.

[0138] At time t2, when the voltage at output node N2 becomes 1V, transistor 27 of pulse generation circuit 20 turns on, and at time t3, the voltage at input node N1 becomes 0V. As a result, the charge stored in capacitor 12 of charging circuit 10 flows from input node N1 through the drain-source of transistor 27 to ground GND, and capacitor 12 is discharged.

[0139] At time 3, when the voltage at input node N1 becomes 0V, the output of the first-stage inverter 21 of the pulse generation circuit 20 changes from 0V to 1V. Due to this change, the output of the second-stage inverter 22 changes from 1V to 0V, the output of the third-stage inverter 23 changes from 0V to 1V, and the output of the last-stage inverter 24 changes from 1V to 0V. As a result, after a certain time delay following the voltage at input node N1 becoming 0V, the voltage at output node N2 drops sharply from 1V to 0V. Since output node N2 is connected to output terminal Tout, at time t4, the voltage at output terminal Tout also drops sharply to 0V.

[0140] From this point onward, the same operation as from time t0 to t4 is repeated as long as the voltage at input terminal Tin remains at 1V. In the timing chart of Figure 11, the time defined by T=t2-t0 corresponds to a predetermined waiting time in the spiking neuron circuit system 100.

[0141] As described above, during normal operation of the spiking neuron circuit system 100 according to this embodiment 1, when a DC voltage of 1V is applied to the input terminal Tin from an external power supply (not shown) via an OR gate 60, a pulse signal Vpls is output from the output terminal Tout after a predetermined waiting time T has elapsed. The pulse width of the pulse signal Vpls corresponds to the delay time formed by the four inverters 21 to 24.

[0142] (Compensation for waiting time) Next, the latency compensation operation of the spiking neuron circuit system 100 according to this embodiment 1 will be described. Figure 12 is a flowchart illustrating the operation of the control circuit 50 during the latency compensation operation of the spiking neuron circuit system 100. Figure 13 is a timing chart illustrating an example of the latency compensation operation of the spiking neuron circuit system 100. Please also refer to Figures 1 to 10 in the following explanation.

[0143] In the initial state of the latency compensation operation of the spiking neuron circuit system 100 in Figure 1, both capacitor 12 of the charging circuit 10 and capacitor C of the CR time constant circuit 30 are uncharged, and their charging voltages are 0V. Also, in the initial state of the control circuit 50 in Figure 3, the match signal Syn_bit=0 and the non-match signal ~Syn_bit=1V, and the Reset signal=0V. In addition, the switch control signal Vsw_bit=0V, the compensation input voltage Vin_bit=0, and the bulk control voltage Vctr_b=0V.

[0144] In step S101 of Figure 12, the startup circuit 51 outputs a pulsed start signal Vin_pls=1V, which is input to the input generation circuit 52. As mentioned above, the start signal Vin_pls is a signal to start the control circuit 50 and begin the waiting time compensation operation, and in this embodiment 1, it is output every hour. In the timing chart of Figure 13, the pulsed start signal Vin_pls=1V is output at time t0.

[0145] In step S102, the input generation circuit 52 outputs a switch control signal Vsw_bit=1V.

[0146] In detail, in the input generation circuit 52 of Figure 5, the start signal Vin_pls = 1V and the match signal Syn_bit = 0V, so the switch control signal Vsw_bit = 1V is output from the Q terminal of the SR latch 52a.

[0147] In step S103, the input generation circuit 52 outputs a compensation input voltage Vin_bit = 1V.

[0148] In detail, in the input generation circuit 52 of Figure 5, the start signal Vin_pls=1V is input to the S terminal of the SR latch 52e via the OR gate 52d, and since the reset signal Reset=0V, the compensation input voltage Vin_bit=1V is output from the Q terminal of the SR latch 52e.

[0149] In the timing chart of Figure 13, the pulsed start signal Vin_pls=1V is output almost simultaneously with the switch control signal Vsw_bit=1V and the compensation input voltage Vin_bit=1V.

[0150] As shown in Figure 1, the compensation input voltage Vin_bit = 1V is applied to the input terminal Tin via the OR gate 60. Also, since the switch control signal Vsw_bit = 1V, the DC power supplied from the input terminal Tin is supplied to both the charging circuit 10 and the CR time constant circuit 30.

[0151] At this time, the charging circuit 10 and the pulse generation circuit 20 operate in the same manner as during normal operation as described above. That is, during the delay compensation operation, instead of an external power supply (not shown), the control circuit 50 applies a compensation input voltage Vin_bit = 1V to the input terminal Tin. As a result, the charging voltage of the capacitor 12 of the charging circuit 10 increases, and when the voltage at the input node N1 of the pulse generation circuit 20 reaches a first predetermined value, the operation of the pulse generation circuit 20 begins and a pulse signal Vpls is output from the output node N2. This pulse signal Vpls is input to the control circuit 50. In the timing chart of Figure 13, the pulse signal Vpls is output at time t2.

[0152] Furthermore, the CR time constant circuit 30 and the reference signal circuit 40 operate in much the same way as the charging circuit 10 and the pulse generation circuit 20. That is, as the charging voltage of capacitor C in the CR time constant circuit 30 increases and the voltage at input node N3 of the reference signal circuit 40 reaches a second predetermined value, the operation of the reference signal circuit 40 begins and a reference signal Vref is output from output node N4. This reference signal Vref is also input to the control circuit 50. In the timing chart of Figure 13, the reference signal Vref is output at time t1.

[0153] In step S104, the reset generation circuit 53 outputs a reset signal Reset=1V.

[0154] In detail, the reset generation circuit 53 in Figure 6 outputs a reset signal Reset=1V 1 microsecond after both the reference signal Vref and the pulse signal Vpls have been output. The reset generation circuit 53 also outputs an extended reference signal Vref_bit, which starts outputting at the same timing as the reference signal Vref, and an extended pulse signal Vpls_bit, which starts outputting at the same timing as the pulse signal Vpls.

[0155] In the timing chart of Figure 13, after the reference signal Vref is output at time t1, and after 1 microsecond has elapsed since the pulse signal Vpls was output at time t2, the Reset signal = 1V is output at time t3. When the reset signal Reset=1V rises, the extended reference signal Vref_bit, the extended pulse signal Vpls_bit, and the compensation input voltage Vin_bit fall.

[0156] In step S105, the matching determination circuit 54 determines whether the timing at which the reference signal Vref is output matches the timing at which the pulse signal Vpls is output.

[0157] In detail, the matching detection circuit 54 in Figure 7 determines that the timing of the outputs of the two signals coincides when the time difference between the timing of the output of the reference signal Vref and the timing of the output of the pulse signal Vpls is less than a third predetermined value of 1 millisecond, and outputs a matching signal Syn_bit=1V and a non-matching signal ~Syn_bit=0V. In other words, the matching detection circuit 54 determines that the timing of the outputs of the two signals coincides when Vref_1ms, which is the reference signal Vref extended into a pulse with a width of 1 millisecond, and Vpls_1ms, which is the pulse signal Vpls extended into a pulse with a width of 1 millisecond, overlap on the time axis, and outputs a matching signal Syn_bit=1V and a non-matching signal ~Syn_bit=0V.

[0158] In the timing chart of Figure 13, Vref_1ms based on the reference signal Vref at time t1 and Vpls_1ms based on the pulse signal Vpls at time t2 do not overlap on the time axis, and the timing of their outputs does not coincide. Therefore, the match determination circuit 54 outputs a match signal Syn_bit=0 and a match non-match signal Syn_bit=1.

[0159] In step S106, the length determination circuit 55 determines whether the waiting time from when the compensation input voltage Vin_bit=1V is output until the pulse signal Vpls is output is longer or shorter than a predetermined time until the reference signal Vref is output.

[0160] In detail, the long / short determination circuit 55 in Figure 8 outputs a Long_bit signal of 1V and a Short_bit signal of 0V if the waiting time from when the compensation input voltage Vin_bit=1V is output until the pulse signal Vpls is output is longer than a predetermined time until the reference signal Vref is output.

[0161] On the other hand, the long / short determination circuit 55 outputs a Long_bit signal of 0V and a Short_bit signal of 1V if the waiting time from when the compensation input voltage Vin_bit=1V is output until the pulse signal Vpls is output is shorter than a predetermined time until the reference signal Vref is output.

[0162] In the timing chart of Figure 13, the waiting time t2-t0 from when the compensation input voltage Vin_bit is output until the pulse signal Vpls is output is longer than the predetermined time t1-t0 until the reference signal Vref is output. Therefore, the long / short determination circuit 55 outputs a Long_bit signal of 1V and a Short_bit signal of 0V.

[0163] In this case, in steps S107 to S108 described below, control is performed to increase the bulk voltage Vb of the transistor 11 of the charging circuit 10. As mentioned earlier, the transistor 11 of the charging circuit 10 is an N-channel type MOSFET. Therefore, as the bulk voltage Vb of the transistor 11 increases, the output current I of the transistor 11 increases, and the time it takes for the charging voltage of the capacitor 12 to reach the first predetermined value is shortened. As a result, the waiting time until the pulse signal Vpls is output is shortened.

[0164] In step S107, the selection signal generation circuit 56 generates and outputs Vsw-2 from the selection signal Vsw+2 based on the Long_bit signal, the Short_bit signal, and the current state of the selection signal.

[0165] In detail, in the initial state of the selection signal generation circuit 56 in Figure 9, the Q terminal of SR latch 56i is 1V, the Q terminal of SR latch 56j is 1V, the Q terminal of SR latch 56k is 0V, and the Q terminal of SR latch 56l is 0V. Therefore, the initial output of the selection signal generation circuit 56 is Vsw+2=0V, Vsw+1=0V, Vsw0=1V, Vsw-1=0V, and Vsw-2=0V. As a result, in the initial state, only the central switch 57o among the five switches 57m to 57q is turned on, and the bulk control voltage Vctr_b=0V is output. That is, in the initial state, the voltage applied to the bulk terminal of transistor 11 is 0V.

[0166] In this initial state, when the selection signal generation circuit 56 receives a Long_bit signal of 1V and a Short_bit signal of 0V, the selection signal generation circuit 56 outputs selection signals Vsw+2=0V, Vsw+1=1V, Vsw0=0V, Vsw-1=0V, and Vsw-2=0V. In the timing chart of Figure 13, the selection signal Vsw0 switches from 1V to 0V, and the selection signal Vsw+1 switches from 0V to 1V. As a result, of the five switches 57m to 57q, only switch 57n, one step above the center, turns on.

[0167] In step S108, the control voltage generation circuit 57 generates and outputs a bulk control voltage Vctr_b based on the selection signal Vsw+2 to Vsw-2.

[0168] In detail, in the control voltage generation circuit 57 in Figure 10, when the selection signal Vsw+1=1V and all other selection signals are 0V, the bulk control voltage Vctr_b is output as 0V+δ=0.17V. In the timing chart in Figure 13, the bulk control voltage Vctr_b changes from 0V to 0.17V.

[0169] The bulk control voltage Vctr_b is applied to the bulk terminal of transistor 11 in the charging circuit 10. This raises the bulk voltage Vb of transistor 11 from 0V to 0.17V, increasing the output current I of transistor 11 and shortening the time it takes for the charging voltage of capacitor 12 to reach a first predetermined value. As a result, the waiting time from when the input voltage is applied until the pulse signal Vpls is output is shortened.

[0170] From this point onward, the operations from steps S103 to S108 described above are repeated until the timing of the output of the reference signal Vref coincides with the timing of the output of the pulse signal Vpls, and step S105 = YES is reached.

[0171] Specifically, in the timing chart of Figure 13, the timing at which the reference signal Vref is output at time t4 and the timing at which the pulse signal Vpls is output at time t5 do not yet coincide. Therefore, in step S107, the selection signal generation circuit 56 generates and outputs the selection signals Vsw+2=1V, Vsw+1=0, Vsw0=0V, Vsw-1=0V, and Vsw-2=0V. At this time, the control voltage generation circuit 57 outputs 0V+2δ=0.34V as the bulk control voltage Vctr_b.

[0172] Next, in the timing chart of Figure 13, the timing at which the reference signal Vref is output at time t7 coincides with the timing at which the pulse signal Vpls is output at time t8, so step S105 = YES. At this time, the match determination circuit 54 outputs a match success signal Syn_bit = 1V and a match failure signal Syn_bit = 0V.

[0173] In step S109, the input generation circuit 52 outputs a switch control signal Vsw_bit=0V. This causes the output of the AND gate 31 of the CR time constant circuit 30 to become 0V, and the power supply to the resistor R and capacitor C is cut off. With this, the operation of the flowchart in Figure 12 is completed, and the latency compensation operation of the spiking neuron circuit system 100 is completed. In other words, the so-called calibration operation is completed.

[0174] Furthermore, if the match determination circuit 54 outputs a match signal Syn_bit=1V and a non-match signal ~Syn_bit=0V just before the completion of the above-mentioned waiting time compensation operation, the output of the long / short determination circuit 55 in Figure 8 will be Long_bit signal=0V and Short_bit signal=0V. At this time, the outputs of each AND gate 56a to 56l of the selection signal generation circuit 56 in Figure 9 will all be 0V, and each SR latch 56m to 56q will maintain the output state Q that was achieved when a match was achieved. This output state is maintained even during normal operation after the waiting time compensation operation is completed.

[0175] In other words, each SR latch 56m to 56q stores information as its internal state Q for generating the selection signal Vsw+2 to Vsw-2 when a match is achieved, even after the waiting time compensation operation is complete. Therefore, the control voltage generation circuit 57 in Figure 10 can continue to output the bulk control voltage Vctr_b when a match is achieved, based on the selection signal Vsw+2 to Vsw-2 output from the selection signal generation circuit 56, even during normal operation after the waiting time compensation operation is complete.

[0176] As described above, the spiking neuron circuit system 100 according to this embodiment 1 includes a control circuit 50 that controls the output current I of the transistor 11 by controlling the bulk voltage Vb of the transistor 11 included in the charging circuit 10. Due to these features, the spiking neuron circuit system 100 can accurately determine the waiting time from when an input voltage is applied by an external power supply (not shown) during normal operation until the pulse signal Vpls is output.

[0177] In particular, the variation due to temperature changes during a predetermined time from when the compensation input voltage Vin_bit is applied until the reference signal Vref is output is smaller than the variation due to temperature changes during the waiting time from when the compensation input voltage Vin_bit is applied until the pulse signal Vpls is output. Therefore, even if the temperature environment changes during the operation of the spiking neuron circuit system 100, the variation due to temperature changes in the waiting time can be compensated by performing the waiting time compensation operation at predetermined time intervals.

[0178] Furthermore, the resistor R and capacitor C included in the CR time constant circuit 30 of the spiking neuron circuit system 100 are composed of discrete elements externally mounted on the semiconductor substrate. In contrast, the charging circuit 10 is mounted on the semiconductor substrate. Therefore, the accuracy of the predetermined time from when the compensating input voltage Vin_bit is applied until the reference signal Vref is output is higher than the accuracy of the waiting time from when the compensating input voltage Vin_bit is applied until the pulse signal Vpls is output. The spiking neuron circuit system 100 can accurately determine the waiting time by compensating the waiting time to match the highly accurate predetermined time defined by the CR time constant circuit 30.

[0179] However, resistors R and capacitors C, which are composed of discrete elements, are more precise than transistors and capacitors mounted on a semiconductor substrate, but they consume more power. For example, the power consumption of a charging circuit 10 with a charging time set to 0.15 seconds is 10 -12While the power consumption is around W, the power consumption of the CR time constant circuit 30 with the same charging time set to 0.15 seconds is 10 -9 It's about W.

[0180] To address this power consumption issue, the spiking neuron circuit system 100 includes an AND gate 31 that functions as a switch to control the power supply to the resistor R and capacitor C. The AND gate 31 allows power to be supplied to the resistor R and capacitor C only when performing latency compensation operation, and cuts off power supply during normal operation. This enables the spiking neuron circuit system 100 to achieve both high latency and low power consumption.

[0181] In the above-described embodiment 1, the selection signals generated by the selection signal generation circuit 56 of the control circuit 50 were five in number, from Vsw+2 to Vsw-2, and correspondingly the change in the bulk control voltage Vctr_b output from the control voltage generation circuit 57 was also five steps. However, the number of selection signals is not limited to five, nor is the change in the bulk control voltage Vctr_b corresponding to them limited to five steps.

[0182] By increasing the number of elements constituting the selection signal generation circuit 56, even more selection signals can be generated, and by correspondingly increasing the number of switches in the control voltage generation circuit 57, the bulk control voltage Vctr_b can be varied in even more steps. Furthermore, the range in which the bulk control voltage Vctr_b changes is not limited to the range from 0V-2δ=-0.34V to 0V+2δ=0.34V. In the case of an N-channel MOSFET, with the power supply voltage of the spiking neuron circuit system 100 as VDD, the bulk control voltage Vctr_b can be varied in the range from -VDD to 0.4VDD, for example.

[0183] Furthermore, in the above embodiment 1, the SR latches 56i to 56l of the selection signal generation circuit 56 stored information for generating the selection signal Vsw+2 to Vsw-2 when a match was achieved as an internal state Q. During normal operation after the waiting time compensation operation was completed, the control voltage generation circuit 57 output the bulk control voltage Vctr_b based on the selection signal Vsw+2 to Vsw-2 output from the selection signal generation circuit 56. Alternatively, a separate circuit may be provided to store the bulk control voltage Vctr_b itself, and the bulk control voltage Vctr_b may be output by referring to this during normal operation. Or, a separate circuit may be provided to store the selection signal Vsw+2 to Vsw-2 when a match was achieved.

[0184] [Embodiment 2] (Spiking Neuron Circuit System 200) Next, a spiking neuron circuit system 200 according to Embodiment 2 of this disclosure will be described. In the following description, components that are the same as or similar to those in Embodiment 1 will be given the same reference numerals and detailed descriptions will be omitted.

[0185] Figure 14 shows the configuration of the spiking neuron circuit system 200 according to Embodiment 2 of this disclosure. The spiking neuron circuit system 200 is obtained by replacing the transistor 11, which is an N-channel MOSFET included in the charging circuit 10 of the spiking neuron circuit system 100 according to Embodiment 1, with a transistor 211, which is a P-channel MOSFET.

[0186] Comparing the spiking neuron circuit system 200 with the spiking neuron circuit system 100 according to Embodiment 1, only the charging circuit 210 and the control circuit 250 are different. Therefore, these charging circuit 210 and control circuit 250 will be described in detail.

[0187] (Charging circuit 210) The charging circuit 210 includes a transistor 211, which is a P-channel MOSFET, and a capacitor 12. The source terminal of transistor 211 is connected to input node N0 of the charging circuit 210. The drain terminal of transistor 211 is connected to one terminal of capacitor 12 and to input node N1 of pulse generation circuit 20. The gate terminal and source terminal of transistor 211 are short-circuited. When an input voltage is applied to the input terminal Tin of the charging circuit 210 from an external power supply (not shown) or a control circuit 250 via the OR gate 60, the charging circuit 210 starts charging capacitor 12 with an output current I, which is the subthreshold current of transistor 211.

[0188] (Control circuit 250) Comparing the control circuit 250 with the control circuit 50 of Embodiment 1, only the selection signal generation circuit 256 and the control voltage generation circuit 257 are different; the other components are identical. Therefore, the selection signal generation circuit 256 and the control voltage generation circuit 257 will be described in detail.

[0189] (Selection signal generation circuit 256) Figure 15 shows the internal configuration of the selection signal generation circuit 256. Similar to the selection signal generation circuit 56 of Embodiment 1, the selection signal generation circuit 256 includes eight AND gates 56a to 56h, four SR latches 56i to 56l, and five EXOR gates 56m to 56q.

[0190] Comparing the selection signal generation circuit 256 with the selection signal generation circuit 56 of Embodiment 1, the Long_bit signal and Short_bit signal input from each AND gate 56a to 56h are swapped. In Figure 15, the differences from Embodiment 1 are highlighted in underlined italics.

[0191] In the selection signal generation circuit 256, the Long_bit signal and Short_bit signal are swapped for the following reason: In an N-channel MOSFET, increasing the bulk voltage Vb increases the output current and shortens the waiting time, while decreasing the bulk voltage Vb decreases the output current and lengthens the waiting time. In contrast, in a P-channel MOSFET, increasing the bulk voltage Vb decreases the output current and lengthens the waiting time, while decreasing the bulk voltage Vb increases the output current and shortens the waiting time.

[0192] In other words, with an N-channel MOSFET, the bulk voltage Vb needs to be "increased" to shorten the latency and "decreased" to lengthen the latency, whereas with a P-channel MOSFET, the bulk voltage Vb needs to be "decreased" to shorten the latency and "increased" to lengthen the latency; the two are in a symmetrical relationship.

[0193] Therefore, by swapping the Long_bit signal and Short_bit signal input to each AND gate 56a to 56h of the selection signal generation circuit 56 of Embodiment 1, which is designed for an N-channel MOSFET, a selection signal generation circuit 256 for a P-channel MOSFET can be constructed.

[0194] The selection signal generation circuit 256 generates Vsw-2 from selection signal Vsw+2, which lowers the bulk voltage Vb by one step to shorten the waiting time, when the Long_bit signal = 1V and the Short_bit signal = 0V. When the Long_bit signal = 0V and the Short_bit signal = 1V, it generates Vsw-2 from selection signal Vsw+2, which raises the bulk voltage Vb by one step to lengthen the waiting time.

[0195] (Control voltage generation circuit 257) Figure 16 shows the internal configuration of the control voltage generation circuit 257. Similar to the control voltage generation circuit 57 of Embodiment 1, the control voltage generation circuit 257 includes 12 diodes 57a to 57l and 5 switches 57m to 57q.

[0196] Comparing the control voltage generation circuit 257 with the control voltage generation circuit 57 of Embodiment 1, the connection destinations of the first power line L1 and the second power line L2 across the diodes connected in series in the forward direction are different. Specifically, in Embodiment 1, the first power line L1 was connected to power line VDD and the second power line L2 was connected to power line -VDD, whereas in the control voltage generation circuit 257, the first power line L1 is connected to power line 2VDD and the second power line L2 is connected to ground GND. In Figure 16, the differences from Embodiment 1 are highlighted in underlined italics.

[0197] In an N-channel MOSFET, the bulk voltage Vb can be varied within a range of, for example, -VDD to 0.4VDD, where VDD is the power supply voltage. Therefore, in Embodiment 1, the bulk control voltage Vctr_b was generated in a range from 0V-2δ=-0.34V to 0V+2δ=0.34V, centered around 0V. Here, δ=2VDD / 12 ≈ 0.17V.

[0198] In contrast, with a P-channel MOSFET, the bulk voltage Vb can be varied within a range of, for example, 0.6VDD to 2VDD, where VDD is the power supply voltage. Therefore, the control voltage generation circuit 257 generates a bulk control voltage Vctr_b centered at 1V, in the range of 1V-2δ=0.66V to 1V+2δ=1.34V. Here, δ=2VDD / 12 ≈ 0.17V.

[0199] (Latency compensation operation of the spiking neuron circuit system 200) Figure 17 is a timing chart illustrating an example of the latency compensation operation of the spiking neuron circuit system 200. In the timing chart of Figure 17, the latency from the application of the compensation input voltage Vin_bit until the output of the pulse signal Vpls is longer than a predetermined time until the output of the reference signal Vref, so control is performed to shorten the latency. Specifically, in order to lower the bulk voltage Vb of the transistor 211 of the charging circuit 210, control is performed to gradually lower the bulk control voltage Vctr_b.

[0200] As described above, the spiking neuron circuit system 200 according to this second embodiment includes a control circuit 250 that controls the output current I of transistor 211, which is a P-channel MOSFET included in the charging circuit 210, by controlling the bulk voltage Vb of transistor 211. Even with this configuration, the waiting time from when the input voltage is applied by an external power supply (not shown) during normal operation until the pulse signal Vpls is output can be determined with high precision.

[0201] However, N-channel and P-channel MOSFETs have different subthreshold currents. Therefore, it is best to choose between N-channel and P-channel MOSFETs depending on the range of subthreshold currents suitable for obtaining the desired latency. Also, if such constraints do not exist, P-channel MOSFETs, whose bulk terminals are isolated from the semiconductor substrate, require less mounting area. In the case of N-channel MOSFETs, NBL-NMOS is required to isolate the bulk terminals from the semiconductor substrate, which increases the mounting area.

[0202] [Embodiment 3] (Spiking Neuron Circuit System 300) Next, a spiking neuron circuit system 300 according to Embodiment 3 of this disclosure will be described.

[0203] Figure 18 shows the configuration of a spiking neuron circuit system 300 according to Embodiment 3 of this disclosure. In the spiking neuron circuit systems according to Embodiments 1 and 2, the delay time was compensated by controlling the bulk voltage Vb of the MOSFET included in the charging circuit. In contrast, in the spiking neuron circuit system 300 according to Embodiment 3, the delay time is compensated by controlling the gate voltage Vg of the N-channel type MOSFET.

[0204] Comparing the spiking neuron circuit system 300 with the spiking neuron circuit system 100 according to Embodiment 1, only the charging circuit 310 and the control circuit 350 are different. Therefore, these charging circuit 310 and control circuit 350 will be described in detail.

[0205] (Charging circuit 310) The charging circuit 310 includes a transistor 311, which is an N-channel MOSFET, and a capacitor 12. The drain terminal of transistor 311 is connected to input node N0 of the charging circuit 310. The source terminal of transistor 311 is connected to one terminal of capacitor 12 and to input node N1 of the pulse generation circuit 20. Note that the gate terminal and source terminal of transistor 311 are not short-circuited.

[0206] (Control circuit 350) Comparing the control circuit 350 with the control circuit 50 of Embodiment 1, only the control voltage generation circuit 357 is different; the other components are identical. Therefore, the control voltage generation circuit 357 will be described in detail.

[0207] The reason why the configuration of the selection signal generation circuit 56 is the same in Embodiment 3 and Embodiment 1 is as follows: In the case of an N-channel MOSFET, the output current increases whether the bulk voltage Vb or the gate voltage Vg is increased, and the output current decreases whether the bulk voltage Vb or the gate voltage Vg is decreased. Therefore, when the selection signal generation circuit 56 generates Vsw-2 from the selection signal Vsw+2, it is not necessary to distinguish whether the controlled object is the bulk voltage Vb or the gate voltage Vg.

[0208] (Control voltage generation circuit 357) The control voltage generation circuit 357 generates and outputs a gate control voltage Vctr_g based on the selection signal Vsw+2 output from the selection signal generation circuit 56, and Vsw-2. This gate control voltage Vctr_g is applied to the gate terminal of transistor 311 included in the charging circuit 310.

[0209] Figure 19 shows the internal configuration of the control voltage generation circuit 357. The control voltage generation circuit 357 includes twelve diodes 57a to 57l and five switches 357m to 357q. The first power line L1 is connected to the power line VDD, and the second power line L2 is connected to ground GND.

[0210] In an N-channel MOSFET, the gate voltage Vg can be varied within a range from 0 to VDD, where VDD is the power supply voltage. Therefore, the control voltage generation circuit 357 generates a gate control voltage Vctr_g centered around 0.67V, in the range from 0.67V-2δ=0.5V to 0.67V+2δ=0.83V, where δ=VDD / 12 ≈ 0.083V.

[0211] As described above, the spiking neuron circuit system 300 according to this third embodiment includes a control circuit 350 that controls the output current I of transistor 311, which is an N-channel MOSFET included in the charging circuit 310, by controlling the gate voltage Vg of transistor 311. Even with this configuration, the waiting time from when the input voltage is applied by an external power supply (not shown) during normal operation until the pulse signal Vpls is output can be determined with high precision. However, since the bulk voltage Vb has a smaller influence on the channel current of the MOSFET than the gate voltage Vg, controlling the bulk voltage Vb allows for more precise compensation of the waiting time. Furthermore, by combining this third embodiment with the first embodiment, both the bulk voltage Vb and the gate voltage Vg of the N-channel MOSFET included in the charging circuit may be controlled.

[0212] [Embodiment 4] (Spiking Neuron Circuit System 400) Next, a spiking neuron circuit system 400 according to Embodiment 4 of this disclosure will be described.

[0213] Figure 20 shows the configuration of a spiking neuron circuit system 400 according to Embodiment 4 of this disclosure. In the spiking neuron circuit system 400 according to Embodiment 4, latency is compensated by controlling the gate voltage Vg of a P-channel type MOSFET.

[0214] Comparing the spiking neuron circuit system 400 with the spiking neuron circuit system 200 according to Embodiment 2, only the charging circuit 410 and the control circuit 450 are different. Therefore, these charging circuit 410 and control circuit 450 will be described in detail.

[0215] (Charging circuit 410) The charging circuit 410 includes a transistor 411, which is a P-channel MOSFET, and a capacitor 12. The source terminal of transistor 411 is connected to input node N0 of the charging circuit 410. The drain terminal of transistor 411 is connected to one terminal of capacitor 12 and to input node N1 of the pulse generation circuit 20. The gate terminal and source terminal of transistor 411 are not short-circuited.

[0216] (Control circuit 450) Comparing control circuit 450 with control circuit 250 of Embodiment 2, only the control voltage generation circuit 457 is different; the other components are identical. Therefore, the control voltage generation circuit 457 will be described in detail.

[0217] The reason why the configuration of the selection signal generation circuit 256 is the same in Embodiment 4 and Embodiment 2 is as follows: In the case of a P-channel MOSFET, increasing the bulk voltage Vb or increasing the gate voltage Vg will decrease the output current, and decreasing the bulk voltage Vb or decreasing the gate voltage Vg will increase the output current. Therefore, when the selection signal generation circuit 256 generates Vsw-2 from the selection signal Vsw+2, it is not necessary to distinguish whether the controlled object is the bulk voltage Vb or the gate voltage Vg.

[0218] (Control voltage generation circuit 457) The control voltage generation circuit 457 generates and outputs a gate control voltage Vctr_g based on the selection signal Vsw+2 output from the selection signal generation circuit 256, using Vsw-2. This gate control voltage Vctr_g is applied to the gate terminal of transistor 411 included in the charging circuit 410.

[0219] Figure 21 shows the internal configuration of the control voltage generation circuit 457. The control voltage generation circuit 457 includes twelve diodes 57a to 57l and five switches 457m to 457q. The first power line L1 is connected to the power line VDD, and the second power line L2 is connected to ground GND.

[0220] In a P-channel MOSFET, the gate voltage Vg can be varied within a range from 0 to VDD, where VDD is the power supply voltage. Therefore, the control voltage generation circuit 457 generates a gate control voltage Vctr_g centered around 0.17V, in the range from 0.17V-2δ=0V to 0.17V+2δ=0.33V, where δ=VDD / 12 ≈ 0.083V.

[0221] As described above, the spiking neuron circuit system 400 according to this embodiment 4 includes a control circuit 450 that controls the output current I of transistor 411, which is a P-channel MOSFET included in the charging circuit 410, by controlling the gate voltage Vg of transistor 411. Even with this configuration, the waiting time from when the input voltage is applied by an external power supply (not shown) during normal operation until the pulse signal Vpls is output can be determined with high precision. However, since the bulk voltage Vb has a smaller influence on the channel current of the MOSFET than the gate voltage Vg, controlling the bulk voltage Vb allows for more precise compensation of the waiting time. Furthermore, by combining this embodiment 4 with embodiment 2, both the bulk voltage Vb and the gate voltage Vg of the P-channel MOSFET included in the charging circuit may be controlled.

[0222] [Embodiment 5] (Variations of the charging circuit) Embodiment 5 of this disclosure describes various variations of the charging circuit of the spiking neuron circuit system.

[0223] (First transformation form) Figure 22 shows the configuration of the charging circuit 510A according to the first modified form of this embodiment 5. The charging circuit 510A includes a transistor 511a which is a P-channel MOSFET, a transistor 512a which is an N-channel MOSFET, and an inverter 513.

[0224] When the input node N1 of the charging circuit 510A is 0V, the inverter 513 outputs 1V. At this time, transistor 511a is off and transistor 512a is on. Therefore, node N2 is 0V.

[0225] When an input voltage of 1V is applied to the input node N1 of the charging circuit 510A, the output of the inverter 513 becomes 0V. At this time, transistor 511a turns on, and an output current I flows. On the other hand, transistor 512a turns off, and no current flows between its drain and source. In this state, the parasitic capacitance Cds between the drain and source of transistor 512a functions as the capacitive component in this disclosure. As a result, the output current I of transistor 511a charges the parasitic capacitance Cds of transistor 512a. By charging using the on-current of transistor 511a, which is a P-channel MOSFET, a much shorter waiting time can be obtained than when charging using the subthreshold current described above.

[0226] (Second transformation form) Figure 23 shows the configuration of a charging circuit 510B according to a second modification of this embodiment 5. The charging circuit 510B includes a transistor 511b which is a P-channel MOSFET, a transistor 512b which is an N-channel MOSFET, and three inverters 514 to 516 connected in multiple stages. Since the gate terminal and source terminal of transistor 511b are short-circuited, a subthreshold current I flows.

[0227] When the input node N1 of the charging circuit 510B is 0V, the inverter 516 outputs 1V, and transistor 512b is on. Therefore, node N2 is 0V.

[0228] When an input voltage of 1V is applied to the input node N1 of the charging circuit 510B, the output of the inverter 516 becomes 0V after a certain delay time. At this time, transistor 512b is turned off, and no current flows between its drain and source. In this state, the parasitic capacitance Cds between the drain and source of transistor 512b functions as the capacitive component in this disclosure. As a result, the subthreshold current I of transistor 511b charges the parasitic capacitance Cds of transistor 512b.

[0229] (Third transformation form) Figure 24 shows the configuration of a charging circuit 510C according to a third modification of this embodiment 5. The charging circuit 510C includes a transistor 511c which is a P-channel MOSFET, a transistor 512c which is an N-channel MOSFET, three inverters 514 to 516 connected in multiple stages, and a capacitor 517 connected in parallel with transistor 512c. Since the gate terminal and source terminal of transistor 511c are short-circuited, a subthreshold current I flows.

[0230] When the input node N1 of the charging circuit 510C is 0V, the inverter 516 outputs 1V, and transistor 512c is on. Therefore, node N2 is 0V.

[0231] When an input voltage of 1V is applied to the input node N1 of the charging circuit 510C, the output of the inverter 516 becomes 0V after a certain delay time. At this time, transistor 512c is turned off, and no current flows between the drain and source. In this state, the parasitic capacitance Cds and capacitor 517 between the drain and source of transistor 512c function as capacitive components in this disclosure. As a result, the subthreshold current I of transistor 511c charges the parasitic capacitance Cds and capacitor 517 of transistor 512c. In this case, because capacitor 517 is added, a longer delay time can be generated.

[0232] (Fourth transformation form) Figure 25 shows the configuration of a charging circuit 510D according to the fourth modification of this embodiment 5. The charging circuit 510D includes a transistor 511d which is a P-channel MOSFET, a transistor 512d which is an N-channel MOSFET, three inverters 514 to 516 connected in multiple stages, and three transistors 518 to 520 which are cascode-connected MOSFETs.

[0233] Since the gate and source terminals of transistor 520 are short-circuited, a subthreshold current I flows. This subthreshold current I is amplified to become the output current I of transistor 511d.

[0234] When the input node N1 of the charging circuit 510D is 0V, the inverter 516 outputs 1V, and the transistor 512d is on. Therefore, node N2 is 0V.

[0235] When an input voltage of 1V is applied to the input node N1 of the charging circuit 510D, the output of the inverter 516 becomes 0V after a certain delay time. At this time, transistor 512d is turned off, and no current flows between the drain and source. In this state, the parasitic capacitance Cds between the drain and source of transistor 512d functions as the capacitive component in this disclosure. As a result, the output current I of transistor 511d charges the parasitic capacitance Cds of transistor 512d.

[0236] [Embodiment 6] (Variations of pulse generation circuits) Embodiment 6 of this disclosure describes various variations of the pulse generation circuit of the spiking neuron circuit system.

[0237] (First transformation form) Figure 26 shows the configuration of the pulse generation circuit 620A according to the first modified form of this embodiment 6. The pulse generation circuit 620A is the same as the pulse generation circuit 20 according to embodiment 1, but with the first stage inverter 21 replaced by a comparator 628.

[0238] In detail, the pulse generation circuit 620A comprises inverters 22 to 24, a transistor 27 which is an N-channel MOSFET, and a comparator 628. The negative terminal of comparator 628 is connected to input node N1 of the pulse generation circuit 620A. The positive terminal of comparator 628 is connected to node N6 which has an intermediate potential between the power line VDD and ground GND. In this embodiment 6, the voltage at node N6 is set to 0.5V by four diodes 629 to 632 connected in series in the forward direction.

[0239] When the voltage at input node N1 is lower than the voltage at node N6, which is 0.5V, comparator 628 outputs 1V. At this time, inverter 22 outputs 0V, inverter 23 outputs 1V, and inverter 24 outputs 0V, so the voltage at output node N2 is 0V.

[0240] When the voltage at input node N1 rises above the voltage at node N6, which is 0.5V, comparator 628 outputs 0V. At this time, inverter 22 outputs 1V, inverter 23 outputs 0V, and inverter 24 outputs 1V, so the voltage at output node N2 becomes 1V. Therefore, when the voltage at input node N1 rises above 0.5V, the output of pulse generation circuit 620A rises sharply from 0V to 1V after a certain delay time.

[0241] When the voltage at output node N2 reaches 1V, transistor 27 turns on, and the voltage at input node N1 becomes 0V. As a result, comparator 628 outputs 1V, inverter 22 outputs 0V, inverter 23 outputs 1V, and inverter 24 outputs 0V, so the voltage at output node N2 becomes 0V. Consequently, the output of pulse generation circuit 620A drops sharply from 1V to 0V.

[0242] In the pulse generation circuit 620A described above, the voltage of node N6, which is the threshold at which the output changes, can be freely set between 0V and 1V depending on the application of the pulse generation circuit 620A.

[0243] (Second Modified Form) FIG. 27 is a diagram showing the configuration of the pulse generation circuit 620B according to the second modified form of Embodiment 6. The pulse generation circuit 620B is obtained by replacing the first-stage inverter 21 and the second-stage inverter 22 from the top in the pulse generation circuit 20 according to Embodiment 1 with a comparator 633.

[0244] Specifically, the pulse generation circuit 620B includes inverters 23 and 24, a transistor 27 which is an N-channel MOSFET, and a comparator 633. The positive terminal of the comparator 633 is connected to the input node N1 of the pulse generation circuit 620B. The negative terminal of the comparator 633 is connected to a node N6 having an intermediate potential between the power supply line VDD and the ground GND. In Embodiment 6, the voltage of the node N6 is set to 0.5V.

[0245] When the voltage of the input node N1 is lower than 0.5V which is the voltage of the node N6, the comparator 633 outputs 0V. At this time, the inverter 23 outputs 1V and the inverter 24 outputs 0V, so the voltage of the output node N2 is 0V.

[0246] When the voltage of the input node N1 becomes higher than 0.5V which is the voltage of the node N6, the comparator 633 outputs 1V. At this time, the inverter 23 outputs 0V and the inverter 24 outputs 1V, so the voltage of the output node N2 becomes 1V. Therefore, when the input voltage becomes higher than 0.5V, the output of the pulse generation circuit 620B rapidly rises from 0V to 1V after a certain delay time.

[0247] When the voltage of the output node N2 becomes 1V, the transistor 27 turns on and the voltage of the input node N1 becomes 0V. As a result, the comparator 633 outputs 0V, the inverter 23 outputs 1V, and the inverter 24 outputs 0V, so the voltage of the output node N2 becomes 0V. As a result, the output of the pulse generation circuit 620B rapidly drops from 1V to 0V.

[0248] Also in the above-described pulse generation circuit 620B, the voltage of node N6, which is the threshold value at which its output changes, can be freely set between 0V and 1V according to the application of the pulse generation circuit 620B.

[0249] [Embodiment 7] (Pulse generation circuit 720) FIG. 28 is a diagram showing the configuration of a pulse generation circuit 720 according to Embodiment 7 of the present invention. The pulse generation circuit 720 includes a transistor 735 which is an N-channel MOSFET, a transistor 736 which is a P-channel MOSFET, an inverter 734, inverters 737 to 739 connected in multiple stages, and a transistor 740 which is a P-channel MOSFET.

[0250] The drain terminals of transistor 735 and transistor 736 are both connected to input node N1. The gate terminals of transistor 735 and transistor 736 are both connected to output node N2. The source terminal of transistor 735 is grounded to ground GND. The source terminal of transistor 736 is connected to the drain terminal of transistor 740, and the source terminal of transistor 740 is connected to the power supply line VDD. Therefore, when transistor 740 is on, transistors 735 and 736 function as an inverter in which its input is connected to output node N2 and its output is connected to input node N1.

[0251] Also, the input terminal of inverter 734 is connected to input node N1. The output terminal of inverter 734 is connected to the gate terminal of transistor 740 and the input terminal of the first stage of the three inverters 737 to 739 connected in multiple stages. The output terminal of the last stage of the three inverters 737 connected in multiple stages is connected to output node N2.

[0252] When the voltage at input node N1 is 0V, inverter 734 outputs 1V. At this time, inverter 737 outputs 0V, inverter 738 outputs 1V, and inverter 739 outputs 0V, so the voltage at output node N2 is 0V. Also, since the output of inverter 734 is 1V, transistor 740 is off.

[0253] As the voltage at input node N1 gradually increases, and reaches a predetermined threshold voltage at which the output of inverter 734 inverts, the output of inverter 734 becomes 0V. At this point, transistor 740 turns on, and the inverter composed of transistors 735 and 736 operates, causing the voltage at its output node N1 to rise sharply to 1V.

[0254] Simultaneously, inverter 737 outputs 1V, inverter 738 outputs 0V, and inverter 739 outputs 1V, resulting in a voltage of 1V at output node N2. Therefore, when the voltage at input node N1 reaches a predetermined threshold voltage, after a certain delay, the voltage at output node N2 rises sharply from 0V to 1V.

[0255] When the voltage at output node N2 reaches 1V, the voltage at node N1, which is the output of the inverter composed of transistors 735 and 736, drops sharply from 1V to 0V. As a result, the output of inverter 734 becomes 1V, and transistor 740 turns off, causing the inverter composed of transistors 735 and 736 to stop operating.

[0256] Simultaneously, inverter 737 outputs 0V, inverter 738 outputs 1V, and inverter 739 outputs 0V, causing the voltage at output node N2 to become 0V. Therefore, when the voltage at output node N2 rises sharply from 0V to 1V, after a certain delay, the voltage at output node N2 drops sharply from 1V to 0V.

[0257] As described above, the pulse generation circuit 720 generates a pulse signal. In the pulse generation circuit 720, the path from the input node N1 back to the input node N1 via the inverter composed of inverter 734, transistor 740, transistors 735 and 736 constitutes a positive feedback loop that accelerates the rise of the voltage at the input node N1, thereby making the rising edge of the pulse signal steeper.

[0258] Furthermore, the path from input node N1 through inverter 734, multi-stage connected inverters 737 to 739, output node N2, and an inverter composed of transistors 735 and 736, and returning to input node N1, constitutes a negative feedback loop that causes a sharp drop in the voltage at input node N1, thereby making the falling edge of the pulse signal steeper.

[0259] As described above, the pulse generation circuit 720 according to this embodiment 7 includes a positive feedback loop that makes the rising edge of the pulse signal steep and a negative feedback loop that makes the falling edge of the pulse signal steep. This makes it possible to generate a pulse signal with a narrow pulse width and a sharp waveform. In addition, when transistor 740 is off, no through-current flows to the inverter formed by transistors 735 and 736, so power consumption is reduced.

[0260] [Embodiment 8] (Spiking Neuron Circuit System 800) Next, a spiking neuron circuit system 800 according to Embodiment 8 of this disclosure will be described.

[0261] Figure 29 shows the configuration of a spiking neuron circuit system 800 according to Embodiment 8 of the present disclosure. The spiking neuron circuit system 800 outputs arbitrary information superimposed on the pulse signal train Vps by controlling the pulse interval of the pulse signal train Vps output from the pulse generation circuit 20. In other words, the spiking neuron circuit system 800 performs "pulse interval modulation" to modulate the pulse interval of the pulse signal train Vps as a carrier wave.

[0262] The spiking neuron circuit system 800 comprises a charging circuit 10, a pulse generation circuit 20, and a control circuit 850. The control circuit 850 receives an analog signal Sig_ang as a time-varying input signal from an external device (not shown). For example, the external device (not shown) is a temperature sensor, and the time-varying analog signal Sig_ang contains temperature information detected by the temperature sensor. However, the external device (not shown) and the time-varying analog signal Sig_ang are not limited to these. The charging circuit 10 and the pulse generation circuit 20 are the same as those in Embodiment 1. Also, the CR time constant circuit 30, reference signal circuit 40, and OR gate 60 that were present in Embodiment 1 are not present.

[0263] A 1V DC voltage is continuously applied to the input terminal Tin of the spiking neuron circuit system 800 by an external power supply (not shown). Therefore, a 1V DC voltage is continuously input to the charging circuit 10. As a result, the charging circuit 10 repeatedly charges and discharges at a constant time period, and the pulse generation circuit 20 outputs a pulse signal example Vps at regular intervals.

[0264] (Control circuit 850) The control circuit 850 controls the pulse interval of the pulse signal train Vps output from the pulse generation circuit 20 by controlling the bulk voltage Vb of the transistor 11 included in the charging circuit 10 based on a time-varying analog signal Sig_ang input from an external device (not shown). Figure 30 shows the internal configuration of the control circuit 850. The control circuit 850 includes an A / D converter circuit 858, a selection signal generation circuit 856, and a control voltage generation circuit 857.

[0265] (A / D converter circuit 858) When the analog signal Sig_ang that changes over time is input to the A / D converter circuit 858, it samples and quantizes this signal at regular time intervals, converts it into a 3-bit digital signal Sig_dig, and outputs the result. As the configuration of the A / D converter circuit 858, various well-known circuit configurations can be adopted.

[0266] (Selection signal generation circuit 856) Based on the 3-bit digital signal Sig_dig output from the A / D converter circuit 858, the selection signal generation circuit 856 generates and outputs eight selection signals Vsw+2 to Vsw-5. These eight selection signals Vsw+2 to Vsw-5 are signals in which only one of them becomes 1V and the others all become 0V corresponding to the 3-bit digital signal Sig_dig. FIG. 31 is a diagram showing the correspondence between the input and output of the selection signal generation circuit 856.

[0267] (Control voltage generation circuit 857) FIG. 32 is a diagram showing the internal configuration of the control voltage generation circuit 857. The control voltage generation circuit 857 includes twelve diodes 57a to 57l and eight switches 857m to 857t. Based on the eight selection signals Vsw+2 to Vsw-5 output from the selection signal generation circuit 856, the control voltage generation circuit 857 generates and outputs a bulk control voltage Vctr_b that changes in eight steps.

[0268] Returning to FIG. 29, the bulk control voltage Vctr_b that changes in eight steps output from the control circuit 850 is applied to the bulk terminal of the transistor 11 included in the charging circuit 10, and the bulk voltage Vb of the transistor 11 changes in eight steps. By the bulk voltage Vb of the transistor 11 changing in eight steps, the pulse interval of the pulse signal train Vps output from the pulse generation circuit 20 changes in eight steps. As a result, the pulse interval of the pulse signal example Vps changes in eight steps based on the analog signal Sig_ang input from an external device not shown. In other words, based on the analog signal Sig_ang input from an external device not shown, the pulse interval of the pulse signal example Vps is controlled in eight steps.

[0269] As described above, the spiking neuron circuit 800 according to this embodiment 8 controls the pulse interval of the pulse signal train Vps output from the pulse generation circuit 20 based on the analog signal Sig_ang as a time-varying input signal. This allows the information of the analog signal Sig_ang to be transmitted on the pulse signal train Vps. The pulse signal Vps with controlled pulse intervals can be used, for example, to control the switching frequency of a boost chopper circuit or a buck chopper circuit. Furthermore, this control makes it possible to achieve impedance matching with power supply elements.

[0270] Note that the output of the A / D converter circuit 858 is not limited to 3 bits; it may be 2 bits or less, or 4 bits or more. The number of selection signals output by the selection signal generation circuit 856 and the number of switches in the control voltage generation circuit 857 are determined according to the number of bits output by the A / D converter circuit 858. In addition, the signal input from the external device may be a digital signal instead of an analog signal. In this case, the A / D converter circuit 858 can be omitted.

[0271] Furthermore, by combining Embodiment 8 with Embodiment 2, the pulse interval of the pulse signal Vps train may be controlled by controlling the bulk voltage Vb of the P-channel MOSFET included in the charging circuit. Alternatively, by combining Embodiment 8 with Embodiment 3 or Embodiment 4, the pulse interval of the pulse signal Vps train may be controlled by controlling the gate voltage Vg of the N-channel or P-channel MOSFET included in the charging circuit.

[0272] In this embodiment 8, an example was described in which the CR time constant circuit 30, reference signal circuit 40, and OR gate 60 that were present in embodiment 1 are not present. Furthermore, by combining the CR time constant circuit 30, reference signal circuit 40, and OR gate 60 that were present in embodiment 1 with this embodiment 8, the so-called calibration operation performed in embodiment 1 on the control voltage of the transistor 11 included in the charging circuit 10 may be further controlled by the control circuit 850 of embodiment 8 after the calibration operation performed in embodiment 1. In such a case, any information to be transmitted can be transmitted with even greater accuracy.

[0273] [Embodiment 9] Figure 33 shows an example of the configuration of the control voltage generation circuit 57A according to Embodiment 9. The control voltage generation circuit 57A includes a control pulse generation circuit 571, a NOT gate 572, a transistor 573 which is a P-channel MOSFET, a transistor 574 which is an N-channel MOSFET, and a capacitor 575.

[0274] The control pulse generation circuit 571 receives a selection signal Vsw consisting of multiple bits output from the selection signal generation circuit 56 (see Figure 3). The control pulse generation circuit 571 outputs a charge control pulse Pc whose pulse width is determined according to the value of the selection signal Vsw. The control pulse generation circuit 571 also receives a reset signal Reset output from the reset generation circuit 53 (see Figure 3). The control pulse generation circuit 571 outputs a discharge control pulse Pd in ​​response to the reset signal Reset.

[0275] The charge control pulse Pc is supplied to the gate terminal of transistor 573 via the NOT gate 572. The discharge control pulse Pd is supplied to the gate terminal of transistor 574. Transistor 573 has its source connected to the power line VDD, and its drain connected to the drain of transistor 574 and one end of capacitor 575. The source of transistor 574 is grounded to GND. One end of capacitor 575 is the output node of the bulk control voltage Vctr_b. The other end of capacitor 575 is grounded to GND.

[0276] Transistor 573 remains ON for a period corresponding to the pulse width of the charge control pulse Pc. When transistor 573 is ON, capacitor 575 is charged. The charging voltage of capacitor 575 is output as the bulk control voltage Vctr_b. The level of the charging voltage of capacitor 575 corresponds to the ON period of transistor 573. That is, the level of the bulk control voltage Vctr_b is controlled by the pulse width and number of pulses of the charge control pulse Pc. The control voltage generation circuit 57 in the first embodiment described above controlled the bulk control voltage Vctr_b in five stages according to five selection signals Vsw+2 to Vsw-2. In contrast, the control voltage generation circuit 57A according to this embodiment 9 controls the control signal S CTR The bulk control voltage Vctr_b can be controlled in stages of 5 or more. The control pulse generation circuit 571 intermittently supplies the control signal S CTR The charging voltage of capacitor 575 may be updated in real time intermittently by intermittently outputting a charging control pulse Pc accordingly. Control signal S CTR This may also be a 1-bit fixed-width pulse signal.

[0277] On the other hand, transistor 574 turns on in response to the reset signal Reset. That is, transistor 574 turns on at the timing when the level of the bulk control voltage Vctr_b should be switched. When transistor 574 turns on, the charge stored in capacitor 575 is discharged. As a result, the level of the bulk control voltage Vctr_b decreases.

[0278] In the control voltage generation circuit 57 according to Embodiment 1 described above, the step size of the voltage when controlling the bulk control voltage Vctr_b was determined by the number of diodes connected in series between the first power line L1 and the second power supply L2. Furthermore, it was not possible to make the step size of the voltage when controlling the bulk control voltage Vctr_b smaller than the forward voltage of the diode. On the other hand, in the control voltage generation circuit 57A according to Embodiment 9, since the charging voltage of the capacitor 575 is output as the bulk control voltage Vctr_b, it is possible to control the voltage step size when controlling the bulk control voltage Vctr_b without adding any circuit elements. Furthermore, it is possible to control the bulk control voltage Vctr_b with a step size smaller than the forward voltage of the diode.

[0279] [Embodiment 10] Figures 34A and 34B show only the first-stage inverter 21 and the second-stage inverter 22, respectively, of the multiple inverters that constitute the pulse generation circuit 20. The first-stage inverter 21 is composed of an N-channel MOSFET transistor 21a and a P-channel MOSFET transistor 21b. Transistors 21a and 21b are turned on complementaryly. Similarly, the second-stage inverter 22 is composed of an N-channel MOSFET transistor 22a and a P-channel MOSFET transistor 22b. Transistors 22a and 22b are turned on complementaryly.

[0280] Here, we consider the ratio of the channel widths of the P-channel MOSFETs (hereinafter referred to as P-MOS) and N-channel MOSFETs (hereinafter referred to as N-MOS) that make up the inverter. Generally, the mobility of N-channel MOSFETs is higher than that of P-channel MOSFETs. The ratio of the channel widths of the P-MOS and N-MOS that make up the inverter is determined according to the ratio of their mobilities. For example, if the ratio of the mobilities of P-MOS and N-MOS (P:N) is 1:2, then the ratio of the channel widths of the P-MOS and N-MOS that make up the inverter (P:N) can be designed to be 2:1.

[0281] Figure 34A shows the signal waveforms of each part when the ratio of the channel widths of N-MOS and P-MOS transistors (N:P) in inverters 21 and 22 is set to 1:2, according to the ratio of the mobilities of these transistors. Here, the channel width ratio (N:P) = 1:2 is considered the standard value. In this case, due to the effects of MOSFET threshold voltage variations, the width of the pulses output from inverters 21 and 22 will be narrower than the pulse width of the input pulse, which may cause pulse loss. This problem can be resolved by adjusting the ratio of the channel widths of the P-MOS and N-MOS transistors constituting the inverter from the standard value. This point will be explained with reference to Figure 34B.

[0282] When a pulse signal transitioning from a high level to a low level is input to the first-stage inverter 21, the N-MOS transistor 21a turns on, and the P-MOS transistor 21b turns off. For example, by widening the channel width of the on-state transistor 21a, the ratio of the channel widths (N:P) of transistors 21b and 21a constituting the inverter 21 can be changed from the standard value of 1:2 to 1.5:2. This suppresses the narrowing of the pulse width output from the inverter 21.

[0283] The pulse signal that transitions from high level to low level, output from the first-stage inverter 21, is input to the second-stage inverter 22. When the pulse signal that transitions from high level to low level is input to the second-stage inverter 22, the P-MOS transistor 22b turns ON, and the N-MOS transistor 22a turns OFF. For example, by widening the channel width of the ON transistor 22b, the ratio of the channel widths (N:P) of transistors 22a and 22b that make up the inverter 22 can be changed from the standard value of 1:2 to 1:2.5. This makes it possible to suppress the narrowing of the pulse width output from the inverter 22. The channel width ratio in the fourth-stage (last stage) inverter 24 can be set to the same value as the channel width ratio in the second-stage inverter 22.

[0284] As described above, in the pulse generation circuit 20 according to this embodiment 10, the ratio of the channel widths of the P-MOS and N-MOS components constituting inverters 21 to 24 differs between adjacent inverters. This narrows the pulse width of the pulses output from each inverter, thus eliminating the problem of pulse loss. The above configuration can be applied not only to the pulse generation circuit 20 but also to all logic circuits such as NAND, NOR, and latches that constitute the spiking neuron circuit system. Furthermore, the numerical values ​​described above as the channel width ratio are just examples, and the channel width ratio can be changed as appropriate to prevent pulse loss.

[0285] [Embodiment 11] Figure 35 shows an example of the configuration of the spiking neuron circuit system 1100 according to Embodiment 11. The spiking neuron circuit system 1100 is composed of three spiking neuron circuits 1110A, 1110B, and 1110C, and three output control circuits 1120A, 1120B, and 1120C.

[0286] The spiking neuron circuits 1100A, 1100B, and 1100C each include a charging circuit 10 and a pulse generation circuit 20. The pulse generation circuit 20 outputs pulse signals Vpls1, Vpls2, and Vpls3, respectively. The spiking neuron circuits 1110A, 1110B, and 1110C are designed to operate independently of each other, and the pulse signals Vpls1, Vpls2, and Vpls3 output from each of the pulse generation circuits 20 are asynchronous to each other.

[0287] The output control circuits 1120A, 1120B, and 1120C are provided in correspondence to the spiking neuron circuits 1110A, 1110B, and 1110C, respectively. The pulse signals Vpls1, Vpls2, and Vpls3 output from the spiking neuron circuits 1110A, 1110B, and 1110C, respectively, are input to the corresponding input terminals (IN) of the output control circuits 1120A, 1120B, and 1120C, respectively. The output control circuits 1120A, 1120B, and 1120C output output signals Vout1, Vout2, and Vout3 from their output terminals (OUT), whose states transition at timings corresponding to the corresponding pulse signals Vpls1, Vpls2, and Vpls3, respectively. The control terminal (WAIT) of the output control circuits 1120A, 1120B, and 1120C is connected to a common standby signal S output from the timing control circuit 1140. WAIT The following is input. Output control circuits 1120A, 1120B, and 1120C each receive the standby signal S. WAIT If this is input, the standby signal S WAIT During the standby period indicated by [the specified parameter], the states of output signals Vout1, Vout2, and Vout3 are maintained. In other words, during the standby period, transitions in the states of output signals Vout1, Vout2, and Vout3 are prohibited.

[0288] FIG. 36 is a diagram showing an example of the internal configuration of the output control circuit 1120A. Note that the configurations of the output control circuits 1120A, 1120B, and 1120C are the same as each other. The output control circuit 1120A includes two SR latches 1121 and 1122, and two NOR gates 1123 and 1124. The S terminal of the SR latch 1121 is the input terminal (IN) of the output control circuit 1120A, and a pulse signal Vpls1 is input to this S terminal. The R terminal of the SR latch is the reset terminal (RESET) of the output control circuit 1120A, and a reset signal for resetting the output signal Vout1 is input to this R terminal. The Q terminal of the SR latch 1121 is connected to one input terminal of the NOR gate 1123. The / Q terminal of the SR latch 1121 is connected to one input terminal of the NOR gate 1124. Note that the / Q terminal is a terminal to which a signal obtained by inverting the logic of the signal output from the Q terminal is output.

[0289] The other input terminals of the NOR gates 1123 and 1124 are the control terminals (WAIT) of the output control circuit 1120A, and a standby signal S WAIT is input to these input terminals. The output terminal of the NOR gate 1123 is connected to the S terminal of the SR latch 1122, and the output terminal of the NOR gate 1124 is connected to the R terminal of the SR latch 1122. The Q terminal of the SR latch 1122 is the output terminal (OUT) of the output control circuit 1120A.

[0290] FIG. 37 is a timing chart showing an example of the operation of the spiking neuron circuit system 1100 according to the first embodiment 11. In FIG. 37, the standby signal S WAIT is at a high level during the period from time t2 to time t4, and at time t1 before time t2, the spiking neuron circuit 1110A outputs a pulse signal Vpls1. At time t3 after time t2 and before time t4, the spiking neuron circuit 1110B outputs a pulse signal Vpls2. At time t5 after time t4, the spiking neuron circuit 1110C outputs a pulse signal Vpls3. The standby signal S WAITThe period from time t2 to t4, when the signal level is high, is a waiting period during which the states of output signals Vout1, Vout2, and Vout3 are maintained.

[0291] At time t1, output control circuit 1120A transitions output signal Vout1 to a high level in response to pulse signal Vpls1. At time t3, pulse signal Vpls2 is input to output control circuit 1120B, but since time t3 is within the waiting period, output control circuit 1120B does not transition output signal Vout2 to a high level, but holds it in the previous state (low level). At time t4, when the waiting period ends, output control circuit 1120B transitions output signal Vout2 to a high level. At time t5, output control circuit 1120C transitions output signal Vout3 to a high level in response to pulse signal Vpls3.

[0292] According to the spiking neuron circuit system 1100 of this embodiment 11, for example, it is possible to maintain proper circuit operation by prohibiting state transitions of output signals Vout1, Vout2, and Vout3 while a high-priority process is being executed.

[0293] Figure 38 shows an example of the configuration of a boost circuit 1130 controlled by the spiking neuron circuit system 1100 according to this embodiment 11. The boost circuit 1130 comprises an inductor 1131, a current control switch 1132, a diode 1133, capacitors 1134A, 1134B, 1134C, and capacitor selection switches 1135A, 1135B, 1135C. Switches 1135A, 1135B, and 1135C are controlled by the output signals Vout1, Vout2, and Vout3 of the spiking neuron circuit system 1100 (output control circuits 1120A, 1120B, 1120C - see Figure 35), respectively. When switches 1135A, 1135B, and 1135C are turned ON, the corresponding capacitors 1134A, 1134B, and 1134C increase the current I flowing through the inductor 1131. L It is charged by [this method].

[0294] Figure 39 shows the current I flowing through inductor 1131. L This is a waveform diagram. When switch 1132 is turned ON, current I L The current increases, and when switch 1132 is turned off, current I L It decreases. Switch 1132 is in the off state during the off period t. OFF In this case, when all switches 1135A, 1135B, and 1135C are in the OFF state, the current I L The current has nowhere to go, causing a sudden voltage surge and potentially damaging the boost circuit 1130. The spiking neuron circuit system 1100 according to this embodiment 11 allows the off period t OFF In this configuration, the above problem can be avoided by prohibiting the transition of the states of output signals Vout1, Vout2, and Vout3, thereby preventing all switches 1135A, 1135B, and 1135C from being in the off state. In the above description, the example given is the use of the output signals Vout1, Vout2, and Vout3 of the spiking neuron circuit system 1100 (output control circuits 1120A, 1120B, and 1120C) to select capacitors 1134A, 1134B, and 1134C in the boost circuit 1130. However, the spiking neuron circuit system 1100 according to this embodiment can also be used for other purposes. For example, it can be used to selectively activate multiple functional blocks included in an integrated circuit that perform predetermined functions. The number of pulse generation circuits and output control circuits, as well as the timing of pulse signal and output signal generation, can be appropriately changed depending on the purpose of use.

[0295] [Embodiment 12] Figure 40 shows an example of the configuration of a charging circuit 1210 according to Embodiment 12. The charging circuit 1210 includes a transistor 1211, which is an N-channel MOSFET, and a capacitor 1212 as a capacitive component. The drain terminal of transistor 1211 is connected to input node N0 of the charging circuit 1210, and input node N0 is connected to input terminal Tin. The source terminal of transistor 1211 is connected to one terminal of capacitor 1212. The other terminal of capacitor 1212 is grounded to GND.

[0296] The charging circuit 1210 according to this embodiment 12 includes capacitors 1213 and 1214. Capacitor 1213 has one end connected to the drain terminal of transistor 1211 and the other end connected to the gate terminal of transistor 1211. Capacitor 1214 has one end connected to the gate terminal of transistor 1211 and the other end connected to ground GND. A voltage determined according to the ratio of the capacitances of capacitors 1213 and 1214 is applied to the gate terminal of transistor 1211.

[0297] The charging circuit 10 according to Embodiment 1 described above charges the capacitor 12 by the off-current of the transistor 11. With this configuration, there is a risk that the control range of the waiting time from when the input voltage is applied until the pulse signal is output may not be sufficiently secured. On the other hand, with the charging circuit 1210 according to Embodiment 12, a voltage determined according to the ratio of the capacitances of capacitors 1213 and 1214 is applied to the gate terminal of the transistor 1211, and the transistor 1211 is used in a subthreshold state, so it is possible to widen the control range of the waiting time. With the charging circuit 1210 according to Embodiment 12, it is possible to control the output current of the transistor 1211 (i.e., the charging current of the capacitor 1212) in the range of, for example, 1 pA to 10 nA. Note that when the charging circuit 1210 according to Embodiment 12 is applied to a spiking neuron circuit system, the control circuit for controlling the output current of the transistor 1211 may be omitted. On the other hand, the spiking neuron circuit system may include both the charging circuit 1210 according to this embodiment 12 and a control circuit similar to those described in the previous embodiment (for example, the control circuit 50 shown in Figure 1, the control circuit 250 shown in Figure 14, and the control circuit 850 shown in Figure 29) for controlling the voltage of the back gate of the transistor 1211. For example, the output current of the transistor 1211 may be roughly adjusted by the ratio of the capacitances of capacitor 1213 and capacitor 1214, and fine adjustments may be made to compensate for process variations and temperature dependence of the transistor 1211 by a control circuit that controls the voltage of the back gate of the transistor 1211.

[0298] Furthermore, the disclosure of Japanese Patent Application No. 2021-111124, filed on July 2, 2021, is incorporated herein by reference in its entirety. In addition, all documents, patent applications, and technical standards described herein are incorporated herein by reference to the same extent as if each individual document, patent application, and technical standard were specifically and individually noted to be incorporated by reference.

Claims

1. A field-effect transistor generates a predetermined output current when an input voltage is applied, The capacitive component is mainly charged by the output current of the field-effect transistor, A pulse generation circuit generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value, A control circuit controls the output current of the field-effect transistor by controlling either or both the bulk voltage and / or gate voltage of the field-effect transistor to compensate for the waiting time from when the input voltage is applied until the pulse signal is output. A spiking neuron circuit system equipped with this system.

2. The control circuit includes a control voltage generation circuit that generates a control voltage for controlling either or both the bulk voltage and / or gate voltage of the field-effect transistor. The spiking neuron circuit system according to claim 1.

3. A field-effect transistor generates a predetermined output current when an input voltage is applied, The capacitive component is mainly charged by the output current of the field-effect transistor, A pulse generation circuit generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value, A control circuit controls the output current of the field-effect transistor by controlling either or both the bulk voltage and / or gate voltage of the field-effect transistor to compensate for the waiting time from when the input voltage is applied until the pulse signal is output. Equipped with, The control circuit includes a control voltage generating circuit that generates a control voltage for controlling either or both the bulk voltage and / or gate voltage of the field-effect transistor. The control circuit further includes a selection signal generation circuit that generates a selection signal for the control voltage generation circuit to generate the control voltage, The selection signal generation circuit has a memory circuit that stores information for generating the selection signal. Spy Pocket Neuron Circuit System.

4. The control circuit discretely controls either or both of the bulk voltage and / or gate voltage of the field-effect transistor. The spiking neuron circuit system according to claim 2 or claim 3.

5. The control voltage generation circuit includes a plurality of diodes connected in forward series between a first power line and a second power line, and generates the control voltage from any of the voltages generated at each node between the diodes. The spiking neuron circuit system according to claim 2 or claim 3.

6. A charging circuit that, when an input voltage is applied, starts charging the capacitive component with the output current of a field-effect transistor, A pulse generation circuit generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value, A control circuit that controls the output current of the field-effect transistor by controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor, Equipped with, The control circuit includes a control voltage generating circuit that generates a control voltage for controlling either or both the bulk voltage and / or gate voltage of the field-effect transistor. The control voltage generation circuit includes a control voltage generation capacitor, and generates the control voltage from the charging voltage of the control voltage generation capacitor. Spy Pocket Neuron Circuit System.

7. A charging circuit that, when an input voltage is applied, starts charging the capacitive component with the output current of a field-effect transistor, A pulse generation circuit generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value, A control circuit that controls the output current of the field-effect transistor by controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor, The circuit includes a reference signal circuit that outputs a reference signal after a predetermined time has elapsed since the aforementioned input voltage was applied, The control circuit compensates for the waiting time from when the input voltage is applied until the pulse signal is output, based on the time difference between the timing at which the reference signal is output and the timing at which the pulse signal is output. Spy Pocket Neuron Circuit System.

8. The variation in temperature change over the predetermined time is smaller than the variation in temperature change over the waiting time. The spiking neuron circuit system according to claim 7.

9. The charging circuit is mounted on a semiconductor substrate, The spiking neuron circuit system includes an external resistor and an external capacitor, which are composed of discrete elements attached externally to the semiconductor substrate, and further comprises a time constant circuit for charging the external capacitor at a predetermined time constant. The reference signal circuit outputs the reference signal when the charging voltage of the external capacitor reaches a second predetermined value. The spiking neuron circuit system according to claim 7.

10. The system further includes a switch for controlling the power supply to the external resistor and the external capacitor, The switch allows power to be supplied to the external resistor and the external capacitor only when compensating for the delay. The spiking neuron circuit system according to claim 9.

11. A charging circuit that, when an input voltage is applied, starts charging the capacitive component with the output current of a field-effect transistor, A pulse generation circuit generates and outputs a pulse signal when the charging voltage of the capacitive component reaches a first predetermined value, A control circuit that controls the output current of the field-effect transistor by controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor, A reference signal circuit that outputs a reference signal after a predetermined time has elapsed since the aforementioned input voltage was applied, Equipped with, The control circuit compensates for the waiting time from when the input voltage is applied until the pulse signal is output, based on the time difference between the timing at which the reference signal is output and the timing at which the pulse signal is output. The charging circuit is mounted on a semiconductor substrate, The spiking neuron circuit system includes an external resistor and an external capacitor, which are composed of discrete elements attached externally to the semiconductor substrate, and further comprises a time constant circuit for charging the external capacitor at a predetermined time constant. The reference signal circuit outputs the reference signal when the charging voltage of the external capacitor reaches a second predetermined value. The system further includes a switch for controlling the power supply to the external resistor and the external capacitor, The switch allows power to be supplied to the external resistor and the external capacitor only when compensating for the delay time. The control circuit steps-by-step to switch the voltage supplied to either or both of the bulk terminals and / or gate terminals of the field-effect transistor until the time difference between the timing at which the reference signal is output and the timing at which the pulse signal is output falls below a third predetermined value. Spy Pocket Neuron Circuit System.

12. The control circuit further includes a control voltage generation circuit that generates a control voltage for controlling either or both of the bulk voltage and / or gate voltage of the field-effect transistor, and a selection signal generation circuit that generates a selection signal for the control voltage generation circuit to generate the control voltage, wherein when the time difference between the timing at which the reference signal is output and the timing at which the pulse signal is output becomes less than or equal to the third predetermined value, the compensation for the waiting time is terminated. The selection signal generation circuit has a memory circuit that stores information for generating the selection signal, and stores in the memory circuit the information for generating the selection signal at the end of the waiting time compensation. The spiking neuron circuit system according to claim 11.

13. The aforementioned capacitance component includes the parasitic capacitance of the transistor. The spiking neuron circuit system according to claim 1.

14. The control circuit controls the output current of the field-effect transistor by controlling the bulk voltage. The spiking neuron circuit system according to claim 1.

15. The field-effect transistor is of the N-channel type, The control circuit controls the bulk voltage in the range of -VDD to 0.4VDD, where VDD is the power supply voltage of the spiking neuron circuit system. The spiking neuron circuit system according to claim 14.

16. The field-effect transistor is of the P-channel type, The control circuit controls the bulk voltage in the range of 0.6 VDD to 2 VDD, where VDD is the power supply voltage of the spiking neuron circuit system. The spiking neuron circuit system according to claim 14.

17. The control circuit controls the output current of the field-effect transistor by controlling the gate voltage. The spiking neuron circuit system according to claim 1.

18. The control circuit controls the gate voltage in the range from 0 to VDD, where VDD is the power supply voltage of the spiking neuron circuit system. The spiking neuron circuit system according to claim 17.

19. The pulse generation circuit has a positive feedback loop and a negative feedback loop. The spiking neuron circuit system according to claim 1.

20. The positive feedback loop makes the rising edge of the pulse signal steeper, and the negative feedback loop makes the falling edge of the pulse signal steeper. The spiking neuron circuit system according to claim 19.

21. The pulse generation circuit includes a plurality of inverters connected in cascading order. Each of the aforementioned plurality of inverters includes a P-channel type field-effect transistor and an N-channel type field-effect transistor that are complementaryally turned on. The ratio of the channel widths of the P-channel field-effect transistor and the N-channel field-effect transistor differs between adjacent inverters. The spiking neuron circuit system according to claim 1.

22. A timing control circuit that outputs a standby signal, A plurality of output control circuits are provided corresponding to at least one of the pulse generation circuits, each outputting an output signal whose state transitions at a timing corresponding to the pulse signal output from the corresponding pulse generation circuit, and which, when the standby signal is input, maintain the state of the output signal during the standby period indicated by the standby signal. The spiking neuron circuit system according to claim 1, comprising:

23. The system includes a switching element connected to the aforementioned capacitive component, As the charging of the capacitive component and the discharging of the capacitive component by the switching element are repeated, a pulse signal train is output from the pulse generation circuit. The control circuit controls the pulse interval of the pulse signal train output from the pulse generation circuit. The spiking neuron circuit system according to claim 1.

24. The control circuit controls the pulse interval of the pulse signal train based on the information to be transmitted. The spiking neuron circuit system according to claim 23.

25. The information to be transmitted is a time-varying input signal. The spiking neuron circuit system according to claim 24.

26. A field-effect transistor generates a predetermined output current when an input voltage is applied, The capacitive component is mainly charged by the output current of the field-effect transistor, A control circuit controls the output current of the field-effect transistor by controlling the gate voltage of the field-effect transistor in order to compensate for the waiting time from when the input voltage is applied until a pulse signal is output. A plurality of inverters are connected between an input node connected to the capacitive component and an output node from which a pulse signal is output. The system includes a switching element provided between the input node and the first reference voltage, the control terminal of which is connected to the output node, The inverters in the plurality of inverters do not have a feedback loop that returns from the connection point between the inverters to the input node. The first stage inverter among the plurality of inverters includes a first switching element provided between the first reference voltage and the intermediate output node, and a second switching element provided between the intermediate output node and the second reference voltage. A first diode is forward-connected between the first reference voltage and the first switching element, and a second diode is forward-connected between the second switching element and the second reference voltage. Spiking neuron circuit.

27. The comparator further includes one input terminal connected to the input node, the other input terminal connected to a predetermined intermediate potential between the first reference voltage and the second reference voltage, and an output terminal connected to the input terminal of the first stage inverter among the plurality of inverters. The spiking neuron circuit according to claim 26.

28. The capacitance component includes a plurality of charging capacitors, A voltage determined according to the ratio of the capacitances of the plurality of charging capacitors is applied to the gate terminal of the field-effect transistor. The spiking neuron circuit according to claim 26 or claim 27.

Images