Fast level shifting circuit

Abstract

The application discloses a kind of fast level conversion circuits, comprising: first inverter, for generating first inverted signal based on input signal;First drive unit is used to generate first logic signal based on input signal, including first input tube, the control end of first input tube receives input signal, first end is connected with first reference potential, second end is as the output end of first drive unit;First conversion unit is connected with the second end of first input tube, first output node and second power supply voltage, for generating second logic signal based on first logic signal;Second input tube, the first end of second input tube is connected with first reference potential, second end is connected with first output node and first conversion unit, control end is connected with first inverter, for generating second logic signal based on first inverted signal.The application can realize fast level conversion and the balance of rising edge, falling edge conversion speed under the premise of not increasing circuit cost.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and specifically relates to a fast level conversion circuit. Background Technology

[0002] In integrated circuits, when a signal from a low-voltage power supply domain is output to a high-voltage power supply domain, the high level in the low-voltage power supply domain may not yet be considered high relative to the voltage in the high-voltage power supply domain, or it may have a large quiescent current during operation. To solve this problem, level conversion circuits are used in integrated circuit design to connect different power supply domains, converting the high-level signal from the low-voltage power supply domain into a high-level signal from the high-voltage power supply domain.

[0003] Traditional level conversion circuits such as Figure 1 As shown, the twelfth MOSFET M12, the thirteenth MOSFET M13, the fourteenth MOSFET M14, and the fifteenth MOSFET M15 form a ring structure. MOSFETs M12 and M14 are PMOS transistors with relatively high on-resistance, while MOSFETs M13 and M15 are NMOS transistors with relatively low on-resistance. Using PMOS transistors with higher on-resistance to pull up the level is a fundamental principle of this type of switching circuit, aiming to obtain a low level between the series-connected PMOS and NMOS transistors at the moment of level transition. This results in a slower level transition, limiting the switching speed of the level conversion circuit and exacerbating the difference in the switching speed between the rising and falling edges of the signal. If the on-resistance of the PMOS transistors is designed to be too small, the level conversion may not function properly.

[0004] Therefore, to address the aforementioned technical problems, it is necessary to provide a fast level conversion circuit. Summary of the Invention

[0005] The purpose of this invention is to provide a fast level switching circuit that achieves fast level switching and a balance between rising and falling edge switching speeds without increasing circuit cost.

[0006] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0007] A fast level shifting circuit, comprising:

[0008] A first inverter is connected between a first power supply voltage and a first reference potential, and is used to generate a first inverted signal based on the input signal, wherein the level range of the input signal is from the first power supply voltage to the first reference potential;

[0009] The first driving unit includes a first input transistor. The control terminal of the first input transistor receives an input signal, the first terminal is connected to a first reference potential, and the second terminal serves as the output terminal of the first driving unit. The first driving unit is used to generate a first logic signal based on the input signal.

[0010] The first conversion unit is connected to the second terminal of the first input tube, the first output node, and the second power supply voltage, and is used to generate a second logic signal based on the first logic signal, wherein the first logic signal is inverted with the second logic signal.

[0011] The second input transistor has a first terminal connected to a first reference potential, a second terminal connected to a first output node and a first conversion unit, and a control terminal connected to the first inverter, used to generate a second logic signal based on the first inverted signal.

[0012] In one or more embodiments of the present invention, the first driving unit further includes a driving transistor, the control terminal of which is connected to the control terminal of the first input transistor and receives an input signal, the second terminal of which is connected to the second terminal of the first input transistor and outputs a first logic signal, and the first terminal is connected to a second power supply voltage.

[0013] In one or more embodiments of the present invention, the first conversion unit includes a second MOS transistor, the first terminal of the second MOS transistor is connected to a second power supply voltage, the second terminal is connected to a first output node, and the control terminal is connected to the second terminal of the first input transistor.

[0014] In one or more embodiments of the present invention, the second MOS transistor is a P-channel MOS transistor, the second input transistor is an N-channel MOS transistor, and the on-resistance of the second MOS transistor is greater than the on-resistance of the second input transistor.

[0015] In one or more embodiments of the present invention, the fast level conversion circuit further includes a shaping unit connected between the second power supply voltage and the second reference potential, for obtaining an output signal based on the second logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference potential.

[0016] In one or more embodiments of the present invention, when the input signal changes from high level to low level, the first inverting signal is high level, the second input transistor is quickly turned on, and the second MOS transistor is gradually turned off, so that the source-drain resistance of the second MOS transistor changes from low to high. When the source-drain resistance of the second MOS transistor is greater than the source-drain resistance of the second input transistor, the second logic signal is low level, and the shaping unit outputs a low level output signal.

[0017] When the input signal changes from low level to high level, the first inverting signal is low level, the second input transistor is turned off, the first input transistor is turned on and pulls the first logic signal down to low level, the second MOS transistor is turned on and pulls the second logic signal up to high level, and the shaping unit outputs a high-level output signal.

[0018] In one or more embodiments of the present invention, the first driving unit further includes a latching unit, the latching unit including a first latching MOS transistor and a second latching MOS transistor, the control terminal of the first latching MOS transistor is connected to the first output node, the second terminal is connected to the second terminal of the first input transistor, and the first terminal is connected to the second power supply voltage; the control terminal of the second latching MOS transistor is connected to the second terminal of the first input transistor, the second terminal is connected to the first output node, and the first terminal is connected to the second power supply voltage.

[0019] In one or more embodiments of the present invention, the first conversion unit includes a second inverter and a third inverter, for obtaining an output signal based on the first logic signal and / or the second logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference potential;

[0020] The second inverter is connected between the second power supply voltage and the second reference potential. The input terminal of the second inverter is connected to the first output node, and the output terminal is connected to the input terminal of the third inverter.

[0021] The input terminal of the third inverter is connected to the second terminal of the first input transistor to receive the first logic signal, and is used to generate a second logic signal based on the first logic signal, and use the second logic signal as the output signal. The output terminal of the third inverter is used to output the output signal.

[0022] In one or more embodiments of the present invention, when the input signal changes from high level to low level, the first input transistor is quickly turned off, the first inverting signal is high level, the second input transistor is quickly turned on, the level on the first output node is pulled down to low level, and a low-level output signal is output after passing through the second inverter and the third inverter.

[0023] When the input signal changes from low level to high level, the first inverting signal is low level, the second input transistor is quickly turned off, the first input transistor is quickly turned on and pulls the first logic signal down to low level. Before the second inverter converts the level on the first output node to low level, the first logic signal is pulled low by the first input transistor, and the third inverter outputs a high-level output signal based on the first logic signal.

[0024] In one or more embodiments of the present invention, the level range of the first logic signal is from the second power supply voltage to the second reference potential; the level range of the second logic signal is from the second power supply voltage to the second reference potential.

[0025] Compared with the prior art, the fast level conversion circuit of the present invention, when the input signal transitions to a low level, first converts the low-level input signal into a high-level signal in the input power domain, then converts this high-level signal into a low-level signal in the output power domain through an NMOS transistor, and then outputs a low-level signal after buffering; when the input signal transitions to a high level, the first input transistor directly generates a low-level signal in the output power domain, and then outputs a high-level signal after inversion and buffering.

[0026] This invention solves the problems of level switching speed and edge balance by setting a first driving unit and a second input tube to process the rising and falling edges of the input signal separately. By skipping the slow pull-up phase of the PMOS, the invention generates an inverted second logic signal based on the first logic signal to improve the switching speed.

[0027] The circuit structure of the present invention is simple and the circuit area is small. It can be implemented by two structures, one with a latching ring and one without a latching ring. Moreover, the present invention has a significant advantage in scenarios where the second power supply voltage is lower than the first power supply voltage. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a circuit diagram of a level conversion circuit in the prior art;

[0030] Figure 2 This is a circuit diagram of the fast level conversion circuit in Embodiment 1 of the present invention;

[0031] Figure 3 This is a circuit diagram of the fast level conversion circuit in Embodiment 2 of the present invention. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0033] As stated in the background section, for Figure 1 In the level conversion circuit shown, the twelfth MOSFET M12 and the fourteenth MOSFET M14 are PMOS transistors with relatively high on-resistance, while the thirteenth MOSFET M13 and the fifteenth MOSFET M15 are NMOS transistors with relatively low on-resistance.

[0034] When the input voltage IN' changes from high level (1) to low level (0), the inverter output INB=1, and the fifteenth MOSFET M15 is turned on. However, at this time, the fifth node n5 (i.e. the second terminal of the thirteenth MOSFET M13) is still at a low level, so the fourteenth MOSFET M14 is also turned on. The sixth node n6 is at an intermediate level that is neither 0 nor 1. If the level of the sixth node n6 is high, the twelfth MOSFET M12 cannot be turned on, causing the fifth node n5 to remain at a low level, which in turn causes the fourteenth MOSFET M14 to remain turned on. Therefore, the on-resistance of the fifteenth MOSFET M15 needs to be designed to be much smaller than that of the fourteenth MOSFET M14. When both the fourteenth MOSFET M14 and the fifteenth MOSFET M15 are turned on, the sixth node n6 is at a relatively low level. The level of the sixth node n6 is shaped by the buffer and outputs a low level (0). At the same time, because the level of the sixth node n6 is low, the twelfth MOSFET M12 can be turned on, so as to gradually increase the voltage of the fifth node n5, and finally turn off the fourteenth MOSFET M14, so that the level of the sixth node n6 is completely pulled to 0.

[0035] When the input voltage IN' changes from low level (0) to high level (1), the thirteenth MOSFET M13 turns on. However, at this time, the sixth node n6 is still at level 0, so the twelfth MOSFET M12 also turns on. Because the on-resistance of the twelfth MOSFET M12 is much greater than that of the thirteenth MOSFET M13, the fifth node n5 is at a relatively low level. The on-resistance of the fourteenth MOSFET M14 is very large, and its driving capability is weak. It takes a long time to slowly pull the sixth node n6 from 0 to high level, so that the output OUT' becomes high level. However, if the on-resistance of the twelfth MOSFET M12 and the fourteenth MOSFET M14 is designed to be small, the level conversion may not work properly. If the on-resistance of the twelfth MOSFET M12 and the fourteenth MOSFET M14 is designed to be large, the level conversion speed will be limited, and the difference in the conversion speed of the rising and falling edges of the input signal IN will be aggravated.

[0036] To address the aforementioned technical problems, this disclosure provides a fast level conversion circuit. When the input signal IN transitions to a low level, the low-level input signal IN is first converted into a high-level signal in the input power domain VIN. This high-level signal is then converted into a low-level signal in the output power domain VOUT by an NMOS transistor. After buffering, a low-level signal is output. When the input signal IN transitions to a high level, an NMOS transistor (first input transistor) is directly driven to generate a low-level signal in the output power domain VOUT. This signal is then inverted and buffered to output a high-level signal.

[0037] Specifically, the fast level shifting circuit includes:

[0038] A first inverter is connected between a first power supply voltage and a first reference potential, and is used to generate a first inverted signal based on an input signal, wherein the level range of the input signal is from the first power supply voltage to the first reference potential.

[0039] The first driving unit includes a first input transistor. The control terminal of the first input transistor receives an input signal, the first terminal is connected to a first reference potential, and the second terminal serves as the output terminal of the first driving unit. The first driving unit is used to generate a first logic signal based on the input signal.

[0040] The first conversion unit is connected to the second terminal of the first input tube, the first output node, and the second power supply voltage, and is used to generate a second logic signal based on the first logic signal, wherein the first logic signal and the second logic signal are inverted.

[0041] The second input transistor has its first terminal connected to the first reference potential, its second terminal connected to the first output node and the first conversion unit, and its control terminal connected to the first inverter, and is used to generate a second logic signal based on the first inverted signal.

[0042] Compared to traditional level conversion circuits, this disclosure achieves fast level conversion and balanced rising and falling edge conversion without significantly increasing costs.

[0043] In one embodiment, the first driving unit further includes a driving transistor, the control terminal of which is connected to the control terminal of the first input transistor and receives an input signal, the second terminal of which is connected to the second terminal of the first input transistor and outputs a first logic signal, and the first terminal is connected to a second power supply voltage.

[0044] In one embodiment, the first conversion unit includes a second MOSFET, the first terminal of which is connected to a second power supply voltage, the second terminal of which is connected to a first output node, and the control terminal of which is connected to the second terminal of the first input transistor.

[0045] In one embodiment, the second MOSFET is a P-channel MOSFET, the second input MOSFET is an N-channel MOSFET, and the on-resistance of the second MOSFET is greater than the on-resistance of the second input MOSFET.

[0046] In one embodiment, the fast level conversion circuit further includes a shaping unit connected between the second power supply voltage and the second reference potential, for obtaining an output signal based on the second logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference potential.

[0047] In one embodiment, when the input signal changes from high level to low level, the first inverting signal is high level, the second MOSFET is not completely turned off, and based on the difference in conduction resistance between the second MOSFET and the second input transistor, the second input transistor turns on and pulls the second logic signal down to low level. The shaping unit outputs a low-level output signal. Specifically, the second input transistor turns on quickly, and the second MOSFET gradually changes from on to off, causing the source-drain resistance of the second MOSFET to change from low to high. When the source-drain resistance of the second MOSFET is greater than the source-drain resistance of the second input transistor, the second logic signal is low level, and the shaping unit outputs a low-level output signal.

[0048] When the input signal changes from low level to high level, the first inverting signal is low level, the second input transistor is turned off, the first input transistor is turned on and pulls the first logic signal down to low level, the second MOSFET is turned on and pulls the second logic signal up to high level, and the shaping unit outputs a high-level output signal OUT.

[0049] In one embodiment, the first driving unit further includes a latching unit, which includes a first latching MOS transistor and a second latching MOS transistor. The control terminal of the first latching MOS transistor is connected to the first output node, the second terminal is connected to the second terminal of the first input transistor, and the first terminal is connected to the second power supply voltage. The control terminal of the second latching MOS transistor is connected to the second terminal of the first input transistor, the second terminal is connected to the first output node, and the first terminal is connected to the second power supply voltage.

[0050] In one embodiment, the first conversion unit includes a second inverter and a third inverter, used to obtain an output signal based on a first logic signal and / or a second logic signal, the level range of which is from a second power supply voltage to a second reference potential; the second inverter is connected between the second power supply voltage and the second reference potential, the input terminal of the second inverter is connected to a first output node, and the output terminal is connected to the input terminal of the third inverter; the input terminal of the third inverter is connected to the second terminal of the first input transistor to receive the first logic signal, used to generate a second logic signal based on the first logic signal, and use the second logic signal as the output signal, and the output terminal of the third inverter is used to output the output signal.

[0051] In one embodiment, when the input signal changes from high level to low level, the first input transistor is quickly turned off, the first inverting signal is high level, the second input transistor is quickly turned on, the level on the first output node is pulled down to low level, and a low-level output signal is output after passing through the second inverter and the third inverter.

[0052] When the input signal changes from low to high, the first inverting signal is low, the second input transistor is quickly turned off, the first input transistor is quickly turned on, and the first logic signal is pulled down to low. Before the level at the first output node changes to high, the third inverter outputs a high-level output signal based on the first logic signal. It can be understood that before the second inverter converts the level at the first output node to low, the first logic signal has already been pulled low by the first input transistor.

[0053] In one embodiment, the level range of the first logic signal is from the second power supply voltage to the second reference potential. The level range of the second logic signal is also from the second power supply voltage to the second reference potential.

[0054] The present invention will be further described below with reference to specific embodiments.

[0055] Example 1:

[0056] like Figure 2 As shown, the fast level conversion circuit in this embodiment includes a first inverter inv1, a first driving unit 10, a first conversion unit 20, and a second input transistor M3. Specifically:

[0057] The first inverter inv1 is connected between the first power supply voltage VIN and the first reference potential, and is used to generate a first inverted signal INB based on the input signal IN. The voltage levels of both the input signal IN and the first inverted signal INB are within the range of the first power supply voltage VIN to the first reference potential. It can be understood that, in this embodiment, the voltage level range between the first power supply voltage VIN and the first reference potential is the input voltage domain, and the first reference potential is ground potential.

[0058] The first driving unit 10 is connected to the second power supply voltage VOUT. In this embodiment, the level range between the second power supply voltage VOUT and the second reference potential is the output voltage domain, and the second reference potential is the ground potential.

[0059] Specifically, in this embodiment, the first driving unit 10 includes a first input transistor M1 and a driving transistor M0. The control terminal of the first input transistor M1 receives the input signal IN, its first terminal is connected to a first reference potential, and its second terminal is connected to the second terminal of the driving transistor M0, forming the output terminal of the first driving unit 10. The first input transistor M1 generates a first logic signal S1 based on the input signal IN. The control terminal of the driving transistor M0 is connected to the control terminal of the first input transistor M1 and receives the input signal IN. Its second terminal outputs the first logic signal S1, and its first terminal is connected to the second power supply voltage VOUT. From the connection relationship of the first driving unit 10, it can be seen that the level range of the first logic signal S1 is from the second power supply voltage VOUT to the second reference potential, and the first logic signal S1 is inversely related to the second logic signal S2.

[0060] In this embodiment, the first logic signal S1 can be understood as the level of the second terminal of the first input transistor M1.

[0061] In this embodiment, the driving transistor M0 is a P-channel MOSFET, and the first input transistor M1 is an N-channel MOSFET. Furthermore, the on-resistance of the driving transistor M0 is much greater than that of the first input transistor M1 (i.e., the driving capability of the first input transistor M1 is greater than that of the driving transistor M0). It can be understood that the first input transistor M1 and the driving transistor M0 constitute an asymmetric inverter.

[0062] The first conversion unit 20 includes a second MOS transistor M2. The first terminal of the second MOS transistor M2 is connected to the second power supply voltage VOUT, the second terminal is connected to the first output node P1, and the control terminal is connected to the second terminal of the first input transistor M1. The first conversion unit 20 is used to generate a second logic signal S2 based on the first logic signal S1.

[0063] The first terminal of the second input transistor M3 is connected to the first reference potential, the second terminal is connected to the first output node, and the control terminal is connected to the first inverter inv1. It is used to generate the second logic signal S2 at the first output node based on the first inverted signal INB. It can be understood that the level of the second logic signal S2 is jointly controlled by the second MOSFET M2 and the second input transistor M3, and the level range of the second logic signal S2 is from the second power supply voltage VOUT to the second reference potential.

[0064] In this embodiment, the second MOSFET M2 is a P-channel MOSFET, and the second input MOSFET M3 is an N-channel MOSFET. The on-resistance of the second MOSFET M2 is relatively small (i.e., the driving capability of the second MOSFET M2 is relatively large) and much smaller than the on-resistance of the driving MOSFET M0. The on-resistance of the second MOSFET M2 is greater than or equal to the on-resistance of the second input MOSFET M3 (as the second MOSFET M2 is gradually turned off, its source-drain resistance will also gradually increase). It can be understood that in this embodiment, the on-resistance of the second MOSFET M2 is designed to be equal to or slightly higher than the on-resistance of the second input MOSFET M3. When the first logic signal S1 is low and the second input MOSFET M3 is turned off, the second MOSFET M2 can quickly pull the level of the first output node high (i.e., the second logic signal S2 changes to a high level).

[0065] Furthermore, the fast level conversion circuit also includes a shaping unit connected between the second power supply voltage VOUT and the second reference potential, used to obtain the output signal OUT based on the second logic signal S2, and the level range of the output signal OUT is from the second power supply voltage VOUT to the second reference potential.

[0066] like Figure 2 As shown, the shaping unit in this embodiment includes a buffer. It is understood that buffers are well known in the prior art and therefore will not be described in detail here; any known or unknown buffer may be used without restriction.

[0067] When the input signal IN changes from high to low, the first input transistor M1 turns off, the first inverting signal INB goes high, and the second input transistor M3 turns on. Because the on-resistance of the driving transistor M0 is very large (i.e., the driving capability of the driving transistor M0 is weak), the rise speed of the first logic signal S1 is slow, so the turn-off speed of the second MOSFET M2 is also slow; that is, the second MOSFET M2 is not completely turned off at this time. However, based on the design of the on-resistance of the second MOSFET M2 being equal to or slightly higher than that of the second input transistor M3, as the second MOSFET M2 gradually turns off, when the source-drain resistance of the second MOSFET M2 is greater than that of the second input transistor M3, the second logic signal S2 goes low. The buffer quickly buffers the second logic signal S2 and outputs a low-level output signal OUT.

[0068] When the input signal IN changes from low to high, the first inverting signal INB goes low, the second input transistor M3 is quickly turned off, the first input transistor M1 is quickly turned on, the first logic signal S1 is pulled down to low and drives the second MOSFET M2 to turn on. Because the second MOSFET M2 has a strong driving capability, it can quickly pull the second logic signal S2 up to high. The buffer quickly buffers the second logic signal S2 and outputs a high-level output signal OUT.

[0069] It is understood that this embodiment is applicable to application scenarios where the input voltage domain is greater than the output voltage domain and the output voltage domain is greater than the input voltage domain, and is particularly suitable for scenarios where the size relationship between the voltage domains that need to be converted within the system is unclear.

[0070] In this embodiment, no latching loop is set, so there is no need to worry about the second logic signal S2 becoming high when the input signal IN is low and the first inverting signal INB is high. This is because when the input signal IN is low, the driving transistor M0 will gradually turn on, and as the level of the first logic signal S1 increases, the second MOS transistor M2 will gradually turn off, making the output signal OUT low.

[0071] When the input signal IN is high, the second MOSFET M2 has a strong driving capability and can directly and quickly pull up the second logic signal S2, making the output signal OUT high.

[0072] In this embodiment, when the input signal IN transitions to a low level, it is first converted into a high-level signal (i.e., the first inverted signal INB) in the input power domain VIN by an inverter. Then, this high-level signal is converted into a low-level signal (i.e., the second logic signal S2) in the output power domain VOUT by an NMOS transistor (i.e., the second input transistor M3). After buffering, a low-level signal is output. When the input signal IN transitions to a high level, it directly drives an NMOS transistor (i.e., the first input transistor M1) to generate a low-level signal (i.e., the first logic signal S1) in the output power domain VOUT. After inversion (i.e., the first logic signal S1 is pulled up by the second MOS transistor M2 to generate the second logic signal S2) and buffering, a high-level signal is output.

[0073] This embodiment requires no capacitors, resistors, or current sources, making it suitable for chip integration. Furthermore, this embodiment has a similar area to traditional level-shifting circuits but improves conversion speed. This embodiment does not generate static power consumption when the voltages of the input signal IN and the output signal OUT are equal, or when the voltage of the input signal IN is greater than the voltage of the output signal OUT.

[0074] Example 2:

[0075] like Figure 3As shown, the fast level conversion circuit in this embodiment includes a first inverter inv1, a first driving unit 10, a first conversion unit 20, and a second input transistor M3. Specifically:

[0076] The first inverter inv1 is connected between the first power supply voltage VIN and the first reference potential, and is used to generate a first inverted signal INB based on the input signal IN. The voltage levels of both the input signal IN and the first inverted signal INB are within the range of the first power supply voltage VIN to the first reference potential. It can be understood that, in this embodiment, the voltage level range between the first power supply voltage VIN and the first reference potential is the input voltage domain, and the first reference potential is ground potential.

[0077] The first driving unit 10 is connected to the second power supply voltage VOUT. In this embodiment, the level range between the second power supply voltage VOUT and the second reference potential is the output voltage domain, and the second reference potential is the ground potential.

[0078] The difference from Embodiment 1 is that the first driving unit 10 in this embodiment includes a first input transistor M1 and a latching unit 11. The control terminal of the first input transistor M1 receives the input signal IN, the first terminal is connected to the first reference potential, and the second terminal is connected to the latching unit 11 and generates a first logic signal S1.

[0079] The latching unit 11 in this embodiment includes a first latching MOSFET M4 and a second latching MOSFET M5. The control terminal of the first latching MOSFET M4 is connected to the first output node P1, the second terminal is connected to the second terminal of the first input MOSFET M1, and the first terminal is connected to the second power supply voltage VOUT. The control terminal of the second latching MOSFET M5 is connected to the second terminal of the first input MOSFET M1, the second terminal is connected to the first output node P1, and the first terminal is connected to the second power supply voltage VOUT.

[0080] As can be seen from the connection relationship of the first driving unit 10, the level range of the first logic signal S1 is from the second power supply voltage VOUT to the second reference potential.

[0081] The first conversion unit 20 in this embodiment includes a second inverter 21 and a third inverter 22. The first conversion unit 20 is used to generate an output signal OUT based on a first logic signal S1. The level range of the output signal OUT is from the second power supply voltage VOUT to the second reference potential. The first logic signal S1 is inverted with the second logic signal S2.

[0082] The first terminal of the second input transistor M3 is connected to the first reference potential, the second terminal is connected to the first output node and the first conversion unit 20, and the control terminal is connected to the first inverter inv1, which is used to generate the second logic signal S2 based on the first inverted signal INB.

[0083] likeFigure 3 As shown, the second inverter 21 is connected between the second power supply voltage VOUT and the second reference potential. The input terminal of the second inverter 21 is connected to the first output node, and the output terminal is connected to the input terminal of the third inverter 22.

[0084] The input terminal of the third inverter 22 is connected to the second terminal of the first input transistor M1 to receive the first logic signal S1, which is used to generate the second logic signal S2 based on the first logic signal S1, and the second logic signal S2 is used as the output signal OUT. The output terminal of the third inverter 22 is used to output the output signal OUT.

[0085] The second inverter 21 in this embodiment includes a sixth MOSFET M6 and a seventh MOSFET M7. The control terminals of the sixth MOSFET M6 and the seventh MOSFET M7 are connected to the first output node P1 and form the input terminals of the second inverter 21. The first terminal of the sixth MOSFET M6 is connected to the second power supply voltage VOUT, and the second terminal is connected to the second terminal of the seventh MOSFET M7 and forms the output terminal of the second inverter 21. The first terminal of the seventh MOSFET M7 is connected to the second reference potential.

[0086] The third inverter 22 in this embodiment includes an eighth MOSFET M8 and a ninth MOSFET M9. The control terminals of the eighth MOSFET M8 and the ninth MOSFET M9 are connected to the first output node P1 and form the input terminals of the third inverter 22. The first terminal of the eighth MOSFET M8 is connected to the second power supply voltage VOUT, and the second terminal is connected to the second terminal of the ninth MOSFET M9 and forms the output terminal of the third inverter 22. The first terminal of the ninth MOSFET M9 is connected to the second reference potential.

[0087] In this embodiment, the first latching MOS transistor M4 and the second latching MOS transistor M5 are P-channel MOS transistors, and the on-resistance of the first latching MOS transistor M4 and the second latching MOS transistor M5 is relatively large. The on-resistance of the first input transistor M1 and the second input transistor M3 is smaller than the on-resistance of the first latching MOS transistor M4 and the second latching MOS transistor M5.

[0088] The on-resistance of the first input transistor M1 is less than the parallel resistance of the on-resistance of the sixth MOSFET and the on-resistance of the first latching MOSFET M4.

[0089] When the input signal IN changes from high to low, the first inverting signal INB becomes high, the second input transistor M3 quickly turns on, and the level at the first output node is pulled down to low. After passing through the second inverter 21 and the third inverter 22, a low-level output signal OUT is output. It can be understood that when the first input transistor M1 quickly turns off, the first logic signal S1 is still low at the instant the input signal IN changes from high to low. Therefore, the second latching MOSFET M5 and the second input transistor M3 turn on almost simultaneously. Based on the difference in the on-resistance between the second latching MOSFET M5 and the second input transistor M3, the level at the first output node is less than VOUT / 2, thus making the level at the first output node appear low. This further turns on the first latching MOSFET M4, and the level of the first logic signal S1 gradually changes from low to high.

[0090] When the input signal IN changes from low to high, the first inverting signal INB is low, and the second input transistor M3 is quickly turned off. At this time, the level on the first output node P1 needs to be slowly pulled up by the second latching MOS transistor M5 before it changes to a high level. However, in this embodiment, since the on-resistance of the first input transistor M1 is small (i.e., the driving capability is strong), the first input transistor M1 is quickly turned on and pulls the first logic signal S1 down to a low level. Before the level on the first output node changes to a high level and is converted to a low level by the second inverter, the first logic signal has already been pulled low by the first input transistor. The third inverter 22 outputs a high-level output signal OUT based on the first logic signal S1.

[0091] In this embodiment, the level range of the first logic signal S1 is from the second power supply voltage VOUT to the second reference potential. The level range of the second logic signal S2 is from the second power supply voltage VOUT to the second reference potential.

[0092] In this embodiment, when the input signal IN transitions to a low level, it is first converted into a high-level signal (i.e., the first inverted signal INB) in the input power domain VIN by an inverter. Then, this high-level signal is converted into a low-level signal (i.e., the level on the first output node) in the output power domain VOUT by an NMOS transistor (i.e., the second input transistor M3). After two inversions, a low-level signal is output. When the input signal IN transitions to a high level, it directly drives an NMOS transistor (i.e., the first input transistor M1) to generate a low-level signal (i.e., the first logic signal S1) in the output power domain VOUT. After inversion (i.e., the first logic signal S1 is pulled up by the third inverter 22 to generate the second logic signal S2), a high-level signal is output.

[0093] This embodiment requires no capacitors, resistors, or current sources, making it suitable for chip integration. Furthermore, this embodiment has a similar area to traditional level-shifting circuits but improves conversion speed. This embodiment does not generate static power consumption when the voltages of the input signal IN and the output signal OUT are equal, or when the voltage of the input signal IN is greater than the voltage of the output signal OUT.

[0094] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0095] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A fast level conversion circuit, characterized in that, include: A first inverter is connected between a first power supply voltage and a first reference potential, and is used to generate a first inverted signal based on an input signal, wherein the level range of the input signal is from the first power supply voltage to the first reference potential; The first driving unit includes a first input transistor and a driving transistor. The control terminal of the first input transistor receives an input signal, the first terminal is connected to a first reference potential, and the second terminal serves as the output terminal of the first driving unit. The first driving unit is used to generate a first logic signal based on the input signal. The control terminal of the driving transistor is connected to the control terminal of the first input transistor and receives the input signal. The second terminal is connected to the second terminal of the first input transistor and outputs the first logic signal. The first terminal is connected to a second power supply voltage. The first conversion unit is connected to the second terminal of the first input tube, the first output node, and the second power supply voltage, and is used to generate a second logic signal based on the first logic signal, wherein the first logic signal is inverted with the second logic signal. The second input transistor has a first terminal connected to a first reference potential, a second terminal connected to a first output node and a first conversion unit, and a control terminal connected to the first inverter, used to generate a second logic signal based on the first inverted signal.

2. The fast level conversion circuit according to claim 1, characterized in that, The first conversion unit includes a second MOSFET, the first terminal of which is connected to a second power supply voltage, the second terminal of which is connected to a first output node, and the control terminal of which is connected to the second terminal of the first input transistor.

3. The fast level conversion circuit according to claim 2, characterized in that, The second MOSFET is a P-channel MOSFET, the second input MOSFET is an N-channel MOSFET, and the on-resistance of the second MOSFET is greater than the on-resistance of the second input MOSFET.

4. The fast level conversion circuit according to claim 3, characterized in that, The fast level conversion circuit further includes a shaping unit connected between the second power supply voltage and the second reference potential, used to obtain an output signal based on the second logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference potential.

5. The fast level conversion circuit according to claim 4, characterized in that, When the input signal changes from high level to low level, the first inverting signal is high level, the second input transistor is quickly turned on, and the second MOSFET is gradually turned off, causing the source-drain resistance of the second MOSFET to change from low to high. When the source-drain resistance of the second MOSFET is greater than the source-drain resistance of the second input transistor, the second logic signal is low level, and the shaping unit outputs a low-level output signal. When the input signal changes from low level to high level, the first inverting signal is low level, the second input transistor is turned off, the first input transistor is turned on and pulls the first logic signal down to low level, the second MOS transistor is turned on and pulls the second logic signal up to high level, and the shaping unit outputs a high-level output signal.

6. The fast level conversion circuit according to claim 1, characterized in that, The first driving unit further includes a latching unit, which includes a first latching MOS transistor and a second latching MOS transistor. The control terminal of the first latching MOS transistor is connected to the first output node, the second terminal is connected to the second terminal of the first input transistor, and the first terminal is connected to the second power supply voltage. The control terminal of the second latching MOS transistor is connected to the second terminal of the first input transistor, the second terminal is connected to the first output node, and the first terminal is connected to the second power supply voltage.

7. The fast level conversion circuit according to claim 1, characterized in that, The first conversion unit includes a second inverter and a third inverter, used to obtain an output signal based on the first logic signal and / or the second logic signal, wherein the level range of the output signal is from the second power supply voltage to the second reference potential; The second inverter is connected between the second power supply voltage and the second reference potential. The input terminal of the second inverter is connected to the first output node, and the output terminal is connected to the input terminal of the third inverter. The input terminal of the third inverter is connected to the second terminal of the first input transistor to receive the first logic signal, and is used to generate a second logic signal based on the first logic signal, and use the second logic signal as the output signal. The output terminal of the third inverter is used to output the output signal.

8. The fast level conversion circuit according to claim 7, characterized in that, When the input signal changes from high level to low level, the first input transistor is quickly turned off, the first inverting signal is high level, the second input transistor is quickly turned on, the level on the first output node is pulled down to low level, and a low-level output signal is output after passing through the second inverter and the third inverter. When the input signal changes from low level to high level, the first inverting signal is low level, the second input transistor is quickly turned off, the first input transistor is quickly turned on and pulls the first logic signal down to low level. Before the second inverter converts the level on the first output node to low level, the first logic signal is pulled low by the first input transistor, and the third inverter outputs a high-level output signal based on the first logic signal.

9. The fast level conversion circuit according to claim 4 or 7, characterized in that, The level range of the first logic signal is from the second power supply voltage to the second reference potential; and / or, The level range of the second logic signal is from the second power supply voltage to the second reference potential.

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