Inverters in gallium nitride technology

By employing bootstrap inverters in gallium nitride technology and utilizing n-type enhancement GaN transistors to form a pull-up network, the trade-off between switching speed and power consumption in inverters is resolved, enabling more efficient integrated circuit design.

CN122247378APending Publication Date: 2026-06-19INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW) +1
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW)
Filing Date
2025-11-13
Publication Date
2026-06-19

AI Technical Summary

⚠Technical Problem

Existing gallium nitride (GaN) technology lacks p-type enhancement-mode GaN transistors, which means that inverter designs can only be implemented using series resistors. This affects the trade-off between switching speed and power consumption, making it difficult to achieve efficient integrated circuit designs.

⚗Method used

By employing a bootstrap gallium nitride inverter, a pull-up network is constructed using at least three n-type enhancement GaN transistors and optional resistors to simulate the behavior of an n-type depletion transistor, thereby achieving direct coupling of FET logic and avoiding the use of a resistor pull-up network.

🎯Benefits of technology

It achieves faster switching speed and lower power consumption, improves the performance of inverters, and is suitable for logic gate design in integrated circuits.

✦ Generated by Eureka AI based on patent content.

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Abstract

A gallium nitride inverter is disclosed that uses only n-type enhancement transistors to implement direct-coupled FET (DCFL) logic.
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