Inverters in gallium nitride technology

Abstract

A gallium nitride inverter is disclosed that uses only n-type enhancement transistors to implement direct-coupled FET (DCFL) logic.

Description

Technical Field

[0001] This application relates to the field of electronic devices using gallium nitride (GaN) technology, and in particular to inverters in GaN technology. Background Technology

[0002] Gallium nitride (GaN) has recently attracted attention as a wide-bandgap material to replace narrow-bandgap silicon-based CMOS technology. In the fields of power electronics, RF power amplifiers, and other devices, integrated circuits fabricated using GaN technology offer advantages over silicon-based integrated circuits.

[0003] However, designing complementary logic integrated circuits (ICs) using gallium nitride (GaN) technology remains challenging. Current GaN technology only provides n-type enhancement (e-type) and n-type depletion (d-type) transistors, while exhibiting large process spread and lacking pn junctions and complementary p-type enhancement (e-type) devices.

[0004] Monolithically integrated GaN integrated circuits fully utilize the fast switching capabilities of gallium nitride (GaN) technology by reducing parasitic inductance at the transistor gates and thus ringing. This enables fast and efficient switching operations, and consequently, smooth and efficient circuits. However, circuit-level challenges exist when implementing integrated circuits with GaN technology. Due to the lack of p-type enhancement-mode GaN transistors, such integrated circuits must be designed using n-type enhancement-mode (e-mode) GaN transistors. Therefore, transistor-to-transistor-to-logic (TTL) implementation is not possible in the design of such circuits (e.g., inverter circuits).

[0005] Gallium nitride (GaN) inverters can be designed by connecting an enhancement-mode (e) n-type GaN FET in series with a resistor. Typically, this series resistor is a two-dimensional electron gas (2DEG) resistor. The pull-up mechanism of this inverter is achieved by using this series resistor to connect the inverter's output to a higher voltage line. Thus, the basic building block of this technology becomes a resistor-transistor-logic (RTL) inverter. The performance of this inverter depends primarily on the optimization of the size of the series resistor (also known as the load resistor). By increasing the size of this series resistor, the inverter's gain can be increased and power consumption reduced. However, this comes at the cost of a longer time delay in the circuit. Therefore, the trade-off between the switching speed and power consumption of this inverter depends on the size of the series resistor.

[0006] An alternative solution for designing inverters using gallium nitride (GaN) technology is to replace the 2DEG series resistors with n-type depletion-mode (d-type) GaN transistors. This is known as direct-coupled FET (DCFL) logic. DCFL logic offers the advantage of higher speeds at lower power consumption over RTL logic. However, from a process technology perspective, it requires an additional device type: n-type d-type logic transistors.

[0007] Therefore, an inverter using gallium nitride technology is needed, which requires a reduced set of device types.

[0008] Therefore, there is a need for an inverter that uses gallium nitride technology, which does not require a trade-off between switching speed and power consumption. Summary of the Invention

[0009] A gallium nitride inverter (1) includes: a first e-type n-type GaN input transistor (2) whose gate (21) is the first input terminal (V) of the inverter (1). in2 Its drain (23) is connected to the output terminal (V) of the inverter (2). out2 The drain (23) is connected to the pull-up network (3).

[0010] The pull-up network (3) is characterized by comprising at least three e-type n-type GaN transistors (4, 5, 6), wherein the first e-type n-type GaN transistor (4) is configured as a diode by connecting its gate (41) to its drain (43), the second e-type n-type GaN transistor (5) is configured as a capacitor by connecting its source (52) to its drain (53), and the third e-type n-type GaN transistor (6) has its gate (61) connected to the source (42) of the first e-type n-type GaN transistor (4) and the gate (51) of the second e-type n-type GaN transistor (5), its drain (63) connected to the gate (41) of the first e-type n-type GaN transistor (4), and its source (62) connected to the connected source (52) and drain (53) of the second e-type n-type GaN transistor (5), and connected to the drain (23) of the e-type n-type GaN transistor (2).

[0011] The pull-up network (3) of the gallium nitride inverter (1) may further include a resistor (7) inserted between the first e-type n-type GaN transistor (2) and the third e-type n-type GaN transistor (6), wherein one end (71) of the resistor (7) is connected to the source (62) of the third e-type n-type GaN transistor (6), and the opposite end (72) of the resistor (7) is connected to the source (52) and drain (53) of the second e-type n-type GaN transistor (5).

[0012] Such inverters can be used to form logic gates, such as NOT, NAND, and NOR logic gates. In the case of NAND logic gates, such inverters also include a second e-n-type GaN input transistor (8) connected in series with the first e-n-type GaN input transistor (2); its drain (83) is connected to the source (22) of the first e-n-type GaN transistor (2), and its gate (81) is connected to the second input (V) of the inverter (1). in3).

[0013] In the case of NOR logic gates, this inverter also includes a second e-n type GaN input transistor (8) connected in parallel with the first e-n type GaN input transistor (2); its drain (83) is connected to the drain (23) of the first e-n type GaN input transistor (2), and its gate (81) is connected to the second input (V) of the inverter (1). in3 ).

[0014] Such inverters and / or any logic gates including such inverters can be used in integrated circuits.

[0015] The inverter and / or the e-type n-type GaN transistor in the logic gate including such an inverter can be a HEMT. Attached Figure Description

[0016] Figure 1 An inverter based on the prior art is shown.

[0017] Figure 2 An inverter according to one embodiment is shown.

[0018] Figure 3 A comparison is shown between an inverter according to the prior art and an inverter of one embodiment.

[0019] Figure 4 A NAND logic gate according to one embodiment is shown.

[0020] Figure 5 A NOR logic gate according to one embodiment is shown. Detailed Implementation

[0021] This invention addresses the aforementioned problems by implementing directly coupled FET (DCFL) logic using gallium nitride (GaN) technology without the need for n-type depletion-mode (d-mode) transistors. This situation, frequently encountered in prior art GaN technology, where only n-type enhancement-mode (e-mode) GaN transistors, particularly high electron mobility transistors (HEMTs), is particularly useful for the bootstrap GaN inverter according to this disclosure. The pull-up network of the bootstrap inverter simulates the behavior of an n-type depletion-mode transistor, which is a constant current source. Compared to inverters using resistor pull-up networks (as in resistor-transistor-logic (RTL) cases), the use of only n-type e-mode GaN transistors as the active components of the inverter, employing the bootstrap principle, results in a better inverter performance.

[0022] Figure 1An inverter (1) of the prior art in gallium nitride (GaN) technology is shown, comprising an enhancement-mode (e-)n-type GaN transistor and a resistor (8) connected in series. The enhancement-mode (e-)n-type GaN transistor, particularly HEMT (2), is also called a pull-down network, while the resistor (8) is also called a pull-up network (3). The resistor (8) is connected at one end (82) to the drain (23) of the transistor (2), and at the opposite end (81) to a higher voltage line (V). dd Typically, the series resistor (8) is a two-dimensional electron gas (2DEG) resistor. The pull-up mechanism of this inverter (1) is achieved by connecting the output of the inverters (23, 82) to the higher voltage line (V). dd This is achieved by using a series resistor (8). Therefore, the basic building block in this technology becomes a resistor-transistor-logic (RTL) inverter.

[0023] The n-type e-input GaN transistor (2) receives the first input voltage signal (V) at its gate (21). in1 When the input voltage signal positively biases the gate (21) relative to the source (22) of the transistor (2), the voltage rises from the higher voltage line (V). dd The current supplied via resistor (8) can flow from the drain (23) to the source (22) of transistor (2). The output voltage signal (V) at the drain (23) of transistor (2) out1 ) is set as the voltage at the source (22) of transistor (2).

[0024] When the first input voltage signal (V) in1 When the gate (21) is biased to be equal to or negative relative to the source (22) of transistor (2), the voltage from the higher voltage line (V) is transferred through resistor (8). dd The current supplied can no longer flow from the drain (23) to the source (22) of transistor (2). The output voltage signal (V) at the drain (23) of transistor (2) is reduced. out1 The voltage (V) is then set at the opposite terminals (81) of resistor (8). dd The source (22) of transistor (2) is connected to a lower voltage line (V). ss ).

[0025] Figure 2 An inverter (1) according to one embodiment is shown.

[0026] The inverter includes a pull-down network (2) and a pull-up network (3). The pull-up network (3) of the inverter (1) consists of at least three n-type GaN transistors (particularly HEMT transistors): a first transistor (4), a second transistor (5), and a third transistor (6), and an optional resistor (7). The resistor is compatible with gallium nitride technology in which the GaN transistors (2, 4, 5, 6) are fabricated.

[0027] In the pull-up network (3), the first transistor (4) behaves as a diode because its drain (43) and its gate (41) are connected. The second transistor (5) behaves as a capacitor because its drain (52) and its source (53) are connected. The third transistor (6) operates at a higher voltage line (V) at the output of the inverter (which serves as the drain (23) of the first input transistor (2)) and at the drain (63) of the third transistor (6). dd A current path is provided between the first transistor (4) and the second transistor (5). The drain (43) of the first transistor (4) is connected to the drain (63) of the third transistor (6), while its source (42) is connected to the gate (61) of the third transistor (6) and the gate (51) of the second transistor (5). The drain (53) of the second transistor (5) is connected to the drain (23) of the first input transistor (2). The source (22) of the first input transistor (2) is connected to the lower voltage line (V). ss ).

[0028] Optionally, a resistor (7) is present. This resistor (7) is then inserted between the output of the inverter (1) (i.e., the drain (23) of the first input transistor (2)) and the source (62) of the third transistor (6). When present, the resistor (7) reduces the current delivered by the third transistor (6).

[0029] When the first input voltage signal (V) at the gate (21) of the first input transistor (2) in2 When the voltage at the source (22) of the transistor (2) is higher than the voltage at the source (22), the output voltage signal (V) at the drain (23) of the transistor (2) is higher. out2 The voltage at the source (22) of the transistor (2) is set. The transistor (2) then charges the capacitor-connected second transistor (5) through the diode-connected first transistor (4). The voltage (V) at the gate (61) of the third transistor (6) is set to the voltage at the source (22) of the transistor (2). B This voltage level is increased across the second transistor (5) connected across the capacitor. This voltage level is typically the voltage (V) at the drain (63) of the third transistor (6). dd Subtract the threshold voltage (V) of the first transistor (4) connected to the diode. th_4 ):V dd – V th_4As the voltage increases, the third transistor (6) turns on, supplying current to the drain (23) of the first input transistor (2).

[0030] When the first input voltage signal (V) at the gate (21) of the first input transistor (2) in2 When the voltage at the source (22) of the transistor (2) is lower or negative than the voltage at the source (22), the output voltage signal (V) at the drain (23) of the transistor (2) is... out2 The voltage at the drain (63) of the third transistor (6) is set. The capacitor-connected second transistor (5) can no longer discharge through the first input transistor (2). The voltage (V) at the gate (61) of the third transistor (6) is set. B The output voltage signal (V) at the drain (23) of the first input transistor (2) follows the output voltage signal (V). out2 The voltage (V) increases. B The voltage (V) at the drain (63) of the third transistor (6) reaches dd Subtract the threshold voltage (V) of the first transistor (4) connected to the diode. th_4 Twice the voltage level: Since the first transistor (4) connected by the diode is now turned off, the voltage at the gate (61) of the third transistor (6) remains constant. The third transistor (6) now resembles an n-type depletion-type (d-type) transistor.

[0031] Figure 3 As shown Figure 1 The prior art inverter shown and such Figure 2 The voltage change of the inverter according to this embodiment is shown. Assume the power supply voltage (V) at the drain (63) of the third transistor (6) is... dd The value is 6 V.

[0032] Figure 3 (a) shows the first input voltage signal (V) in1 (Changes over time)

[0033] Figure 3 (b) shows the first input voltage signal (V) in1 When the input voltage (V) is low and when the input voltage (V) is low in1 When ) is high, the voltage (V) at the gate (61) of the third transistor (6) is B (The corresponding changes over time.)

[0034] Figure 3 (c) Comparison Figure 2 The output voltage signal (V) of the inverter according to this embodiment is shown. out2 )and Figure 1 The output voltage signal (V) of the prior art inverter shownout1 The corresponding changes over time. The main difference between the two output voltage signals is the rise time. The inverter according to this embodiment is faster than prior art inverters. When the transistor (1) in the pull-down network is turned off, the current from the pull-up network (3) charges the capacitor (not shown) at the output terminal of the inverter (1). For prior art inverters, the current flowing through the resistor (8) changes with its output voltage (V out1 As the voltage increases, it decreases, as defined by Ohm's law, thus slowing down the output voltage (V). out2 The low-to-high transition of the inverter according to this embodiment. For the inverter according to this embodiment, due to the bootstrap principle, its pull-up network (1) generates a constant current, which biases the third transistor (6) with a constant gate (61) to source (62) voltage. Therefore, the inventor's output voltage (V) according to this embodiment out2 It shows a faster transition from low to high.

[0035] Figure 4 A NAND logic gate according to one embodiment is shown. Although Figure 2 The inverter circuit shown only has the capability to receive the first input voltage signal (V) at its gate (21). in2 The first n-type GaN input transistor (2) is used in the NAND logic gate (1), but the NAND logic gate (1) has a second n-type GaN input transistor (8), especially in HEMT. The second input transistor (8) is connected in series with the first input transistor (2) and the low voltage line (V). ss Between. The drain (83) of the second input transistor (8) is connected to the source (22) of the first input transistor (2), while the source (82) of the second input transistor (8) is connected to the low voltage line (V). ss The second input transistor (8) receives the second input voltage signal (V) at its gate (81). in3 ).

[0036] Figure 5 A NOR logic gate according to one embodiment is shown. Although Figure 2 The inverter circuit shown only has the capability to receive the first input voltage signal (V) at its gate (21). in2 The first n-type GaN input transistor (2) is used in the NAND logic gate (1), but the NAND logic gate (1) has a second n-type GaN input transistor (8), specifically a HEMT. The second input transistor (8) is connected in parallel to the first input transistor (2). The drain (83) of the second input transistor (8) is connected to the drain (23) of the first input transistor (2), while the source (82) of the second input transistor (8) is connected to the low voltage line (V). ssThe second input transistor (8) receives the second input voltage signal (V) at its gate (81). in3 ).

Claims

1. A gallium nitride inverter (1), comprising: First e-type n-type GaN input transistor; (2) The gate (21) thereof is the first input end (V in2 ) of the inverter (1), and The drain (23) thereof is connected to the output (V out2 ) of the inverter (2), The drain (23) is connected to the pull-up network (3). Its features are: The pull-up network (3) includes at least three e-type n-type GaN transistors (4, 5, 6), thereby: The first type n GaN transistor (4) is configured as a diode by connecting its gate (41) to its drain (43). The second type n GaN transistor (5) is configured as a capacitor by connecting its source (52) to its drain (53), and The third type n-type GaN transistor (6). Its gate (61) is connected to the source (42) of the first e-type n-type GaN transistor (4) and the gate (51) of the second e-type n-type GaN transistor (5). Its drain (63) is connected to the gate (41) of the first e-type n-type GaN transistor (4), and Its source (62) is connected to the source (52) and drain (53) of the second e-type n-type GaN transistor (5), and is connected to the drain (23) of the e-type n-type GaN input transistor (2).

2. The inverter of claim 1, wherein, The pull network (3) further includes: A resistor (7) is inserted between the first e-type n-type GaN transistor (2) and the third e-type n-type GaN transistor (6), thereby: One end (71) of the resistor (7) is connected to the source (62) of the third type n GaN transistor (6), and The opposite end (72) of the resistor (7) is connected to: The source (52) and drain (53) of the second e-type n-type GaN transistor (5), and the drain (23) of the e-type n-type GaN input transistor (2).

3. A logic gate comprising an inverter as described in claim 1 or 2.

4. The logic gate of claim 3, wherein, The logic gate is a NOT gate.

5. The logic gate of claim 3, wherein, The logic gate is a NAND gate, and also includes: A second e-type n-type GaN input transistor (8) connected in series with the first e-type n-type GaN input transistor (2); Its drain (83) is connected to the source (22) of the first e-type n-type GaN transistor (2), and The gate (81) thereof is the second input (V in3 ) of the inverter (1).

6. The logic gate of claim 3, wherein, The logic gate is a NOR gate, and also includes: A second e-type n-type GaN input transistor (8) is connected in parallel with the first e-type n-type GaN input transistor (2); Its drain (83) is connected to the drain (23) of the first type n GaN. Input transistor (2), and The gate (81) thereof is the second input (V in3 ) of the inverter (1).

7. The device according to any one of claims 1 to 6, wherein the e-type n-type GaN transistor is a HEMT.

8. An integrated circuit comprising at least one device as described in any one of claims 1 to 7.

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