Digital isolator circuit with additional delay

Abstract

This invention discloses a digital isolator circuit with additional delay, including a transmitter circuit that receives a data input signal and generates first and second transmitter output signals, wherein the second transmitter output signal is a delayed version of the first transmitter output signal. Subsequently, an isolation barrier generates the first and second isolation output signals, causing a receiver circuit to generate a data output signal in response to these isolation output signals. By further incorporating a delay circuit in the transmitter circuit to delay the first transmitter output signal and generate the second transmitter output signal, this invention effectively enhances the received signal at the receiver circuit, maintaining the stability of the common-mode signal and the robustness of data transmission. A pulse carrier modulation mechanism is also employed to effectively reduce power consumption, electromagnetic interference, and signal jitter.

Description

Technical Field

[0001] This invention relates to a circuit architecture for a digital isolator, and more particularly to a digital isolator circuit with an additional delay path that can effectively amplify the signal at its receiver input by more than two times, while simultaneously enhancing the robustness of its data transmission and preventing drift of the common-mode voltage signal. Background Technology

[0002] As is well known, many electronic circuit systems require the isolation of electrical signals from one part of the system to those from another. For example, in many control systems, both high-voltage and low-voltage signals are generated and monitored; therefore, providing appropriate isolation between these signals is essential to ensure the proper operation of the electronic circuit system. Currently, existing isolation circuits are known to be intermediary circuits that provide voltage isolation between two communication blocks, such as a transmitter circuit (TX) and a receiver circuit (RX). Such isolation circuits are generally used to eliminate unavoidable ground loops and protect high-voltage sensitive circuits. Using isolation circuits not only ensures electrical insulation and signal isolation between circuits but also establishes reliable data transmission between two dissimilar communication circuits, preventing signal interference from fast transient common-mode noise.

[0003] In practical applications, various existing devices and technologies have been proposed to transmit signals from one part of a system to another while maintaining isolation between the parts. Among these, digital isolators (DIS) circuits are commonly used to effectively provide communication and isolation functions. In actual operation, a DIS circuit first receives an input electrical signal from a first part of the system, converts the signal into a corresponding signal, and then passes it through an isolation barrier. After passing through the barrier, it is converted into an isolated output electrical signal, which is then received by a second part of the system. In this case, the electrical signal received by the second part of the system responds to the input electrical signal from the first part of the system.

[0004] Please see Figure 1 The diagram shows a schematic of a conventional digital isolator architecture in the prior art. The digital isolation architecture 1 includes a first part 10, a second part 20, and a signal coupling part 30 electrically coupled between the first part 10 and the second part 20. The first part 10 is electrically connected to a first ground voltage V. ss1And adapted to receive an input signal V I Part 20 is electrically connected to the second ground voltage V. ss2 And based on the input signal V received in the system I , generates output signal V OUT The signal coupling section 30 is electrically connected between the first section 10 and the second section 20, so that the signal is converted into an isolated output electrical signal through the signal coupling effect of the signal coupling section 30, which can be received by the second section 20 in the system.

[0005] However, it is worth noting that common-mode transient immunity (CMTI) is a critical factor when considering the design of digital isolation circuits, because both high slew rates and high-frequency transient events will affect the circuitry. Figure 1 Data transmission on the signal coupling section 30 (also known as the isolation barrier) shown is disrupted. The isolation barrier is affected on both sides (e.g., by the first ground voltage V). ss1 With the second ground voltage V ss2 The coupling capacitance generated between the two sides of the isolation barrier provides a path for these fast transient events to cross the barrier and disrupt the output signal. This effect is undesirable in existing technologies and is one of the problems that urgently needs to be improved. Therefore, how to effectively enhance the robustness of data transmission on both sides of the isolation barrier and avoid its common-mode voltage signal (V) is a key challenge. CM The drift and instability caused by drift are unresolved issues in this technical field. While several feasible approaches exist in the existing technical field to achieve these goals, their effectiveness has not been significant. Therefore, further improvements and alternative methods in this field are urgently needed.

[0006] Therefore, considering the numerous problems listed above, it is essential to adopt a multi-faceted approach. Consequently, recognizing the potential for improvement in these deficiencies and drawing upon years of experience in this field, the inventor has carefully observed and researched the issue, applying theoretical principles to propose a novel design that effectively addresses these shortcomings. This invention provides a novel digital isolator circuit architecture. This innovative digital isolator circuit architecture solves many long-standing deficiencies in existing technologies and effectively enhances the signal at the receiving end. The specific architecture and implementation methods of this invention will be detailed in the following paragraphs for reference. Summary of the Invention

[0007] To address the problems of existing technologies, one objective of this invention is to provide a novel and highly innovative digital isolator circuit. This circuit incorporates an additional signal delay path in its transmitter circuit, thereby generating a delayed transmitter output signal in response to the data input signal. Simultaneously, this invention employs a pulse carrier modulation mechanism. By applying this mechanism to the transmitter circuit, the circuit generates a first transmitter output signal, which contains different numbers of pulse carriers in response to the rising and falling edges of the data input signal. Therefore, through the pulse carrier modulation technology provided by this invention, the digital isolator can transmit data signals within a data transmission channel architecture while maintaining accurate data transmission results. Furthermore, based on the first transmitter output signal, a delayed signal (i.e., the second transmitter output signal described below) is further generated. In this way, the invention can amplify the receiver input signal by at least two times, while simultaneously improving the robustness of data transmission and preventing common-mode voltage signal drift.

[0008] On the other hand, another object of the present invention is to provide a novel digital isolator circuit with pulse carrier modulation, wherein the transmitter circuit can generate a first transmitter output signal, and the first transmitter output signal contains different numbers of pulse carriers in response to the rising and falling edges of the data input signal, such that the number of the first group of pulse carriers in the first part of the first transmitter output signal is different from the number of the second group of pulse carriers in the second part of the first transmitter output signal. Since conventional transmitter output signals always generate an infinite number of continuous pulse carriers regardless of whether the data input signal is at a high or low voltage level, the first transmitter output signal improved by the present invention is successfully modulated to have a smaller number of pulse carriers. Therefore, in view of this innovative improvement, the present invention can effectively eliminate the problems of huge power consumption and severe electromagnetic interference in the prior art.

[0009] It is evident that the digital isolator circuit provided by this invention not only has an additional signal delay path, but also adopts innovative pulse carrier modulation technology. By applying the technical solution provided by this invention, it possesses extremely high industrial applicability and value. At the same time, the jitter interference problem of the data output signal at the traditional transmitter circuit end can also be effectively suppressed. It is clear that this invention can successfully solve the long-standing deficiencies of the prior art, while maintaining accurate data transmission results and superior system robustness. It is evident that the digital isolator circuit with pulse carrier modulation and an additional delay path provided by this invention has high industrial competitiveness and can be widely applied in any related industrial technology.

[0010] In view of the numerous inventive objectives of the present invention provided above, these are aspects that significantly improve upon what prior art patents or papers cannot achieve or apply. Therefore, based on achieving the aforementioned numerous inventive objectives, the present invention aims to provide a digital isolator circuit with additional delay, comprising: a transmitter circuit that receives a data input signal and generates a first transmitter output signal and a second transmitter output signal based on the data input signal, wherein the second transmitter output signal is a delayed signal of the first transmitter output signal.

[0011] Subsequently, an isolation barrier is electrically coupled to the transmitter circuit and receives the first transmitter output signal and the second transmitter output signal. The isolation barrier generates a first isolated output signal and a second isolated output signal based on the received first and second transmitter output signals. According to an embodiment of the present invention, the isolation barrier provided by the present invention may, for example, include at least one set of isolation capacitors, wherein one capacitor in the set of isolation capacitors is adapted to receive the first transmitter output signal and generate the first isolated output signal, and another capacitor in the set of isolation capacitors is adapted to receive the second transmitter output signal and generate the second isolated output signal.

[0012] Next, a receiver circuit is electrically coupled to the isolation barrier to receive the first isolation output signal and the second isolation output signal, thereby causing the receiver circuit to respond to the first isolation output signal and the second isolation output signal to generate a data output signal.

[0013] The transmitter circuit disclosed in this invention generates a first transmitter output signal (TXO) based on the data input signal, and uses the first transmitter output signal as an input signal for the isolation barrier. The first transmitter output signal (TXO) includes a first partial signal and a second partial signal. The transmitter circuit disclosed in this invention begins generating the first partial signal in response to a first transition state from a first logic state to a second logic state of the data input signal, and stops generating the first partial signal while the data input signal is still in the second logic state.

[0014] Subsequently, the transmitter circuit begins generating the second partial signal in response to a second transition of the data input signal from the second logic state to the first logic state, and stops generating the second partial signal while the data input signal is still in the first logic state. According to an embodiment of the invention, the first partial signal includes a first group of pulse carriers, the second partial signal includes a second group of pulse carriers, and the number of pulse carriers in the first group of pulse carriers of the first partial signal is different from the number of pulse carriers in the second group of pulse carriers of the second partial signal.

[0015] Meanwhile, according to an embodiment of the present invention, based on the fact that the data input signal is periodic, and the voltage level of the first transmitter output signal (TXO) follows the voltage level of the data input signal, the first transmitter output signal (TXO) disclosed in the present invention is periodic.

[0016] Furthermore, since the second transmitter output signal (TXOD) disclosed in this invention is a delayed signal of the first transmitter output signal (TXO), and the voltage level of the second transmitter output signal (TXOD) also follows the voltage level of the data input signal, the second transmitter output signal (TXOD) disclosed in this invention is also periodic.

[0017] In addition, in one embodiment of the present invention, the frequency of the first group of pulse carriers of the first segment signal and the frequency of the second group of pulse carriers of the second segment signal can each be a variable. In another embodiment of the present invention, the amplitude of the first group of pulse carriers of the first segment signal and the amplitude of the second group of pulse carriers of the second segment signal can also be selectively each a variable. Furthermore, in yet another embodiment of the present invention, after the transmitter circuit stops generating the first segment signal or the second segment signal, the first transmitter output signal can have an adjustable voltage level. In summary, those skilled in the art or those with common knowledge can make appropriate modifications or variations based on the technical solutions disclosed in the present invention without departing from the spirit of the invention. However, it is worth noting that these modifications or variations should still fall within the scope of the present invention. Generally speaking, this invention is not limited to the frequency, amplitude, or voltage level of the first and second portions of the first transmitter output signal disclosed in the various embodiments of this invention. These values ​​are merely illustrative examples used to explain the technical concept of this invention and are not intended to limit the scope of this invention.

[0018] On the other hand, the transmitter circuit provided by the present invention preferably includes: a top-to-bottom edge converter, an oscillator for generating an oscillation signal, an AND logic gate electrically coupled to the top-to-bottom edge converter and the oscillator, and a delay circuit connected to the output of the AND logic gate. The top-to-bottom edge converter receives a data input signal and outputs a converted data signal in response to a rising edge and a falling edge of the data input signal. The converted data signal includes a first partition signal and a second partition signal. The top-to-bottom edge converter generates the first partition signal in response to the rising edge of the data input signal, and terminates the generation of the first partition signal before the data input signal reaches the falling edge. Then, the top-to-bottom edge converter generates the second partition signal in response to the falling edge of the data input signal, and terminates the generation of the second partition signal before the data input signal reaches the next rising edge. Furthermore, a first operating time of the first partition signal and a second operating time of the second partition signal are different.

[0019] The AND logic gate is electrically coupled to the upper and lower edge converter and the oscillator to receive the converted data signal and the oscillation signal, thereby generating the first transmitter output signal.

[0020] Subsequently, the delay circuit is electrically connected to the output terminal of the AND logic gate and receives the first transmitter output signal. The delay circuit delays the first transmitter output signal to generate and output the second transmitter output signal.

[0021] According to one embodiment of the present invention, when the output signal of the first transmitter has a duty time T, the output signal of the second transmitter can be generated, for example, by delaying the output signal of the first transmitter by half a duty time (T*1 / 2).

[0022] According to one embodiment of the present invention, the delay circuit includes at least one inverting unit, which is composed of two inverters connected in series, such that the at least one inverting unit receives the first transmitter output signal, delays the first transmitter output signal, and generates the second transmitter output signal accordingly. In another embodiment of the present invention, the delay circuit may optionally include multiple inverting units, which are connected in series and receive the first transmitter output signal to generate the second transmitter output signal, thus similarly enabling the implementation of the inventive objective of the present invention.

[0023] Furthermore, according to an embodiment of the present invention, the first transition state of the data input signal from the first logic state to the second logic state responds to the rising edge of the data input signal. Similarly, the second transition state of the data input signal from the second logic state to the first logic state responds to the falling edge of the data input signal.

[0024] Specifically, according to an embodiment of the present invention, the first portion of the first transmitter output signal has a first operating time, which is a first time interval between the transmitter circuit starting to generate the first group of pulse carriers and the transmitter circuit stopping the generation of the first group of pulse carriers. Similarly, the second portion of the first transmitter output signal has a second operating time, which is a second time interval between the transmitter circuit starting to generate the second group of pulse carriers and the transmitter circuit stopping the generation of the second group of pulse carriers. The first operating time of the first portion of the signal and the second operating time of the second portion of the signal are different.

[0025] Furthermore, the first operating time of the first portion of the first transmitter output signal (TXO) is equal to the first operating time of the first partition of the converted data signal, and the second operating time of the second portion of the first transmitter output signal (TXO) is equal to the second operating time of the second partition of the converted data signal.

[0026] On the other hand, regarding the circuit configuration of the top and bottom edge converter, according to a preferred embodiment of the present invention, the present invention designs the top and bottom edge converter to include an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and an inverting OR gate, wherein the inverter receives the data input signal and outputs an inverted data input signal, a first input terminal of the inverting OR gate is electrically coupled to the first transmission gate and the second transmission gate, a second input terminal of the inverting OR gate is electrically coupled to the third transmission gate and the fourth transmission gate, and the first transmission gate and the third transmission gate are each connected to an input terminal and an output terminal of the inverter.

[0027] In this configuration, the data input signals are each delayed by a first period and a second period to control the first transmission gate and the fourth transmission gate, respectively, and the inverted data input signals are each delayed by the first period and the second period to control the second transmission gate and the third transmission gate, respectively, so that the inverted gate outputs the converted data signal.

[0028] In one embodiment of the present invention, when the first period is designed to be longer than the second period, the first operating time of the first partition signal of the converted data signal will be longer than the second operating time of the second partition signal of the converted data signal. However, the present invention is not limited thereto.

[0029] In another alternative embodiment of the invention, when the second period is designed to be longer than the first period, the second operating time of the second partition signal of the converted data signal will be longer than the first operating time of the first partition signal of the converted data signal. It should be understood that all of the above-described variations can be used to achieve the inventive objectives and effects of the invention, and are not intended to limit the scope of the invention.

[0030] Therefore, in summary, it can be confidently stated that the present invention provides a well-designed pulse carrier modulation mechanism suitable for digital isolator circuits. This innovative pulse carrier modulation mechanism can be applied to the transmitting circuit (TX) and has been proven to successfully minimize system power consumption and electromagnetic interference (EMI), while effectively avoiding output signal jitter interference. Thus, it can be confidently stated that the digital isolator circuit with pulse carrier modulation disclosed in this invention can contribute to achieving excellent system robustness and accurate data transmission results. Compared with the prior art, the advantage of the present invention lies in its ability to provide good system-level control stability and maintain precise control over the isolation circuit.

[0031] In addition, this invention also discloses a digital isolator circuit with additional delay, which generates a second transmitter output signal (TXOD) by delaying the first transmitter output signal (TXO). This effectively amplifies the receiver input signal by more than two times, thus greatly improving the robustness of data transmission. Furthermore, by employing the technical solution disclosed in this invention, common-mode voltage instability and drift can also be suppressed and minimized.

[0032] The present invention will be further described in detail below through specific disclosed embodiments, in conjunction with the accompanying drawings, so that those skilled in the art can more easily understand the purpose, technical content, features and effects achieved by the present invention for reference. Attached Figure Description

[0033] Figure 1 A schematic diagram of a conventional digital isolator architecture in the prior art is disclosed.

[0034] Figure 2 A schematic diagram of the architecture of a digital isolator circuit with additional delay according to an embodiment of the present invention is disclosed.

[0035] Figure 3 According to Figure 2 The waveform diagram of the data input signal DI, the first transmitter output signal TXO, the second transmitter output signal TXOD, the first isolation output signal RXIN, the second isolation output signal RXIND, and the data output signal RO in the digital isolator circuit.

[0036] Figure 4 Disclosed according to the present invention Figure 2 In a digital isolator circuit, the waveform diagram of the first transmitter output signal TXO compared to the data input signal DI is shown.

[0037] Figure 5 Disclosed according to the present invention Figure 2 The transmitter circuit disclosed in the embodiments is shown in the detailed circuit diagram.

[0038] Figure 6 A waveform diagram of the second transmitter output signal TXOD compared to the first transmitter output signal TXO in an embodiment of the present invention is disclosed.

[0039] Figure 7 A detailed circuit diagram of a delay circuit according to an embodiment of the present invention is disclosed.

[0040] Figure 8 A detailed circuit diagram of a delay circuit according to another embodiment of the present invention, consisting of three inverting units connected in series, is disclosed.

[0041] Figure 9 According to Figure 5 The waveform diagram of the transmitter circuit shown includes the data input signal DI, the converted data signal DI_C, the oscillation signal OSC, and the generated first transmitter output signal TXO.

[0042] Figure 10 This is a detailed circuit diagram of the top and bottom edge converter according to a first embodiment of the present invention.

[0043] Figure 11 According to Figure 10 The waveform diagrams of each node in the circuit shown are illustrated.

[0044] Figure 12 This is a detailed circuit diagram of the top and bottom edge converter according to a second embodiment of the present invention.

[0045] Figure 13 According to Figure 12 The waveform diagrams of each node in the circuit shown are illustrated.

[0046] Figure reference numerals: 1-Digital isolation architecture; 10-First part; 20-Second part; 30-Signal coupling section; 50, 50'-Top and bottom edge converters; 52-Oscillator; 54-AND logic gate; 56, 56'-Delay circuit; 70-Inverting unit; 100-Digital isolator circuit; 202-Transmitter circuit; 204-Isolation barrier; 206-Receiver circuit; V I -Input signal; V OUT - Output signal; V ss1 - First grounding voltage; V ss2- Second ground voltage; DI - Data input signal; DI_C - Conversion data signal; DI_CP1 - First partition signal; DI_CP2 - Second partition signal; t1' - First operating time; t2' - Second operating time; RXIN - First isolation output signal; RXIND - Second isolation output signal; RO - Data output signal; TXO - First transmitter output signal; TXOD - Second transmitter output signal; TXO_D1 - First branch signal; TXO_D2 - Second branch signal; RE - Rising edge; FE - Falling edge; t1 - First operating time Operating time; t2 - Second operating time; INV, INV1, INV2 - Inverters; TG1 - First transmission gate; TG2 - Second transmission gate; TG3 - Third transmission gate; TG4 - Fourth transmission gate; NOR - Inverting OR gate; N1 - First input terminal; N2 - Second input terminal; DI_B - Inverted data input signal; DI_D - Delayed signal of data input signal; DI_3D - Delayed signal of data input signal; DI_DB - Delayed signal of inverted data input signal; DI_3DB - Delayed signal of inverted data input signal; OSC - Oscillation signal. Detailed Implementation

[0047] The foregoing description of the present invention, along with the following embodiments, serves to demonstrate and explain the spirit and principles of the invention, and provides a further explanation of the claims. Please refer in detail to the preferred embodiments of the invention, examples of which are shown in the accompanying drawings. Where possible, the same reference numerals will be used in the drawings and description to refer to the same or similar elements. It should be understood that, for clarity and convenience, the invention may be enlarged in terms of shape and thickness in the drawings, and elements not specifically shown or described may take various forms known to those skilled in the art. Once disclosed by the present invention, such alternatives and modifications will be readily apparent to those skilled in the art.

[0048] To illustrate the technical content and features of this invention and to enable those skilled in the art to understand, make, and use it, numerous embodiments are described below. However, it should be noted that these embodiments are not intended to limit the scope of the invention. Therefore, all equivalent modifications or variations made in accordance with the spirit of this invention should be included within the scope of protection of this invention.

[0049] Unless otherwise stated, certain conditional phrases or words, such as “may” or “possibly,” are generally used to express that embodiments of the invention “have,” but may also be interpreted as unnecessary features, elements, or steps. In other embodiments, these features, elements, or steps may not be required.

[0050] In the embodiments described in this specification, the reference to "one embodiment" or "in one embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, "one embodiment" or "in one embodiment" appearing in various places in this specification do not necessarily refer to the same embodiment.

[0051] In the embodiments and claims of this invention, specific terms are used to refer to specific elements. Those skilled in the art should understand that the same element can be referred to by different names. This invention does not distinguish between elements with different names but the same function. In this specification and claims, "comprising" is used in an open-ended manner and should therefore be interpreted as "including but not limited to". "Coupled to" is intended to cover any indirect or direct connection. In other words, if this invention provides a first device coupled to a second device, it means that the first device can be connected to the second device directly or indirectly through other intermediate devices or connection methods via electrical connection, wireless communication, optical communication, or other signal connections, with or without signal connections.

[0052] The present invention is described in detail through the following embodiments, which are merely illustrative examples. Those skilled in the art can readily make appropriate modifications and variations to the apparatus and methods while retaining the teachings of the invention. Therefore, the following disclosure of the invention should be interpreted as being limited only by the scope of the appended claims. Throughout the specification and claims, except where explicitly described, the meanings of “a” and “the” include “one or at least one” of an element or component. Furthermore, throughout the specification and claims, the singular includes descriptions of multiple elements or components, except where the context clearly excludes multiples. Throughout the specification and claims, unless the meaning of certain words is explicitly defined, the meaning of the word “wherein” includes “among” or “above”. Generally, the meaning of each term used in the claims and specification of this invention refers to its common meaning known to those skilled in the art, unless otherwise noted. Some terms used to describe the invention and to guide those skilled in the art in understanding the invention may be discussed. Each illustrative example in this specification should not be used to limit the scope of protection of the invention.

[0053] The terms “basically,” “approximately,” “about,” and “probably” can refer to a value within 20% of a given value or range, preferably within 10%. Furthermore, the quantities or figures provided in this invention can be approximate values, and unless otherwise specified, can be described using the terms described above. When a quantity, density, or other parameter includes a specified range, preferred range, or listed ideal value, its value can be considered as any number within that given range.

[0054] As described in the prior art, existing digital isolator architectures often lack circuit design margins, making them unsuitable for mass production. Furthermore, existing digital isolator circuits typically employ common On / Off Keying (OOK), Frequency Shift Keying (FSK), or Amplitude Shift Keying (ASK) modulation mechanisms for data signal transmission and coupling. These existing signal modulation methods are known to suffer from severe power consumption and electromagnetic interference problems. Therefore, recognizing these shortcomings, this invention proposes a novel digital isolator circuit that addresses these deficiencies by employing an innovative pulse carrier modulation (PCM) mechanism combined with an additional signal delay path. Compared to existing technologies, this invention enhances the data robustness of the transmission system. The specific implementation methods and technical features are detailed below for reference.

[0055] Please refer to the accompanying drawings of this invention first. Figure 2 The figure shows a schematic diagram of the architecture of a digital isolator circuit with additional delay according to an embodiment of the present invention. As shown, this digital isolator circuit 100 with additional delay includes a transmitter circuit 202, an isolation barrier 204 electrically coupled to the transmitter circuit 202, and a receiver circuit 206 electrically coupled to the isolation barrier 204. The transmitter circuit 202 is electrically coupled to a first ground voltage V. ss1 The receiver circuit 206 is electrically coupled to a second ground voltage V. ss2The isolation barrier 204 is electrically coupled between the transmitter circuit 202 and the receiver circuit 206, thereby providing coupling and appropriate isolation for the transmitted signal. According to an embodiment of the present invention, the transmitter circuit 202 is used to receive a data input signal DI and generate a first transmitter output signal TXO and a second transmitter output signal TXOD based on the data input signal DI, wherein the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO.

[0056] An isolation barrier 204 is electrically coupled to the transmitter circuit 202 and receives the first transmitter output signal TXO and the second transmitter output signal TXOD, enabling the isolation barrier 204 to generate a first isolated output signal and a second isolated output signal based on the received first transmitter output signal TXO and second transmitter output signal TXOD. According to an embodiment of the present invention, the isolation barrier 204 may, for example, include at least one set of isolation capacitors, or be composed of equal elements thereof. One capacitor in the set of isolation capacitors is adapted to receive the first transmitter output signal TXO and generate the first isolated output signal, and another capacitor in the set of isolation capacitors is adapted to receive the second transmitter output signal TXOD and generate the second isolated output signal.

[0057] Please refer to the drawings of this invention. Figure 2 As shown, the first isolated output signal and the second isolated output signal are the input signals of the receiver circuit 206, which are the receiver input signals (first isolated output signal RXIN and second isolated output signal RXIND) indicated in the figure.

[0058] Therefore, with such a circuit configuration, the receiver circuit 206 electrically coupled to the isolation barrier 204 can receive the first isolation output signal RXIN and the second isolation output signal RXIND, so that the receiver circuit 206 responds to the first isolation output signal RXIN and the second isolation output signal RXIND, thereby generating and outputting a data output signal RO.

[0059] According to a preferred embodiment of the present invention, the transmitter circuit 202 disclosed herein generates a first transmitter output signal TXO based on the data input signal DI, and simultaneously, a second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO. To enable those skilled in the art to better understand the technical means employed in this invention, please also refer to... Figure 3 As shown, it is according to the present invention. Figure 2The digital isolator circuit includes waveform diagrams of its data input signal DI, first transmitter output signal TXO, second transmitter output signal TXOD, first isolation output signal RXIN, second isolation output signal RXIND, and data output signal RO. These waveform diagrams clearly show that the second transmitter output signal TXOD is a delayed version of the first transmitter output signal TXO. In one embodiment, when the first transmitter output signal TXO has a duty time T, the second transmitter output signal TXOD can be generated, for example, by delaying the first transmitter output signal TXO by half a duty time (T*1 / 2). The invention will be further explained in subsequent paragraphs as to how the invention generates the desired second transmitter output signal TXOD by delaying the first transmitter output signal TXO; this will be detailed later.

[0060] Here, the present invention first describes the signal modulation mechanism employed. Please refer to [link to documentation]. Figure 4 As shown, it discloses according to the present invention Figure 2 In a digital isolator circuit, the waveform diagram of its first transmitter output signal TXO compared to the data input signal DI is shown below. Figure 4 As shown, the first transmitter output signal TXO disclosed in this invention includes a first component signal TXO_D1 and a second component signal TXO_D2. Furthermore, since the data input signal DI is periodic, and the voltage level of the first transmitter output signal TXO typically follows the voltage level of the data input signal DI, the first transmitter output signal TXO is also periodic. According to embodiments of the present invention, under the same principle, as... Figure 3 As shown, the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO. Furthermore, the voltage level of the second transmitter output signal TXOD will also follow the voltage level of the data input signal DI, so that the generated second transmitter output signal TXOD is also a periodic signal.

[0061] Please also refer to Figure 2 and Figure 4As shown, in detail, the transmitter circuit 202 begins generating the first partial signal TXO_D1 in response to a first transition of the data input signal DI from a first logic state to a second logic state, and stops generating the first partial signal TXO_D1 while the data input signal DI is still in the second logic state. In this embodiment, the first logic state refers to when the data input signal DI is at a low voltage level, which can be represented as digital logic "0". The second logic state refers to when the data input signal DI is at a high voltage level, which can be represented as digital logic "1". The "first transition" of the data input signal DI from the first logic state to the second logic state refers to the transition of the data input signal DI from digital logic "0" to digital logic "1", which is in response to a rising edge RE of the data input signal DI. Similarly, the "second transition" of the data input signal DI from the second logic state to the first logic state refers to the response of the data input signal DI to a falling edge FE when the data input signal DI transitions from digital logic "1" to digital logic "0".

[0062] As shown in the figure, the transmitter circuit 202 starts generating the second partial signal TXO_D2 in response to the data input signal DI transitioning from the second logic state "1" to the first logic state "0", and stops generating the second partial signal TXO_D2 while the data input signal DI is still in the first logic state "0". According to a preferred embodiment of the invention, the first partial signal TXO_D1 includes a first group of pulse carriers, the second partial signal TXO_D2 includes a second group of pulse carriers, and the number of pulse carriers in the first group of pulse carriers of the first partial signal TXO_D1 is different from the number of pulse carriers in the second group of pulse carriers of the second partial signal TXO_D2. The pulse carrier modulation mechanism provided by the invention, for example, can be as described in the invention... Figure 4The illustrated embodiment is designed such that the first segment signal TXO_D1 has a greater number of pulse carriers than the second segment signal TXO_D2. However, the invention is not limited thereto. In other implementable embodiments of the invention, the second segment signal TXO_D2 may also be selectively designed to have a greater number of pulse carriers than the first segment signal TXO_D1. The invention is not limited to whether the first segment signal TXO_D1 or the second segment signal TXO_D2 has a greater number of pulse carriers in its claims. Generally speaking, those skilled in the art can make modifications or variations according to the specifications and requirements of their actual circuits without departing from the spirit and intent of the invention; however, even with equivalent variations, these modifications should still fall within the scope of the invention. In other words, the invention is not limited to the several embodiments described above.

[0063] In summary, this invention improves upon existing signal modulation mechanisms and employs an innovative Pulse Carrier Modulation (PCM) mechanism. When the data input signal DI transitions from digital logic "0" to digital logic "1" and from digital logic "1" to digital logic "0", the transmitter circuit can generate different numbers of pulse carriers.

[0064] For example, according to the PCM modulation mechanism disclosed in this invention, such as Figure 4 As shown, the first portion of the first transmitter output signal TXO, TXO_D1, can have more pulse carriers than the second portion, TXO_D2. In other embodiments, those skilled in the art may optionally design the second portion, TXO_D2, to have more pulse carriers than the first portion, TXO_D1; this is not intended to limit the claims of the present invention. Generally speaking, it is believed that those skilled in the art, with a proper understanding and technical background of the present invention, can make appropriate modifications or improvements according to the actual needs and specifications of different circuits without departing from the core technology of the present invention; however, such modifications or improvements should still fall within the protection scope claimed by the present invention.

[0065] In addition, according to an embodiment of the present invention, the frequency of the first group of pulse carriers of the first segment signal TXO_D1 and the frequency of the second group of pulse carriers of the second segment signal TXO_D2 can each be a variable. Similarly, according to another embodiment of the present invention, the amplitude of the first group of pulse carriers of the first segment signal TXO_D1 and the amplitude of the second group of pulse carriers of the second segment signal TXO_D2 can also be selectively each a variable.

[0066] On the other hand, specifically speaking, such as Figure 4 As shown, the first segment signal TXO_D1 disclosed in this invention has a first operating time t1, which is a first time interval between the start of the transmitter circuit 202 generating the first group of pulse carriers of the first segment signal TXO_D1 and the termination of the transmitter circuit 202 generating the first group of pulse carriers of the first segment signal TXO_D1. Similarly, the second segment signal TXO_D2 has a second operating time t2, which is a second time interval between the start of the transmitter circuit 202 generating the second group of pulse carriers of the second segment signal TXO_D2 and the termination of the transmitter circuit 202 generating the second group of pulse carriers of the second segment signal TXO_D2. According to an embodiment of the present invention, the first operating time t1 of the first segment signal TXO_D1 and the second operating time t2 of the second segment signal TXO_D2 are different. Through the pulse carrier modulation mechanism provided above in this invention, for example, the first operating time t1 of the first segment signal TXO_D1 can be as follows: Figure 4 As shown, the second operation time t2 is designed to be slightly longer than the second segment signal TXO_D2. Alternatively, in other embodiments of the present invention, the second operation time t2 of the second segment signal TXO_D2 may also be selectively designed to be longer than the first operation time t1 of the first segment signal TXO_D1. However, the present invention is not limited to whether the first operation time t1 of the first segment signal TXO_D1 or the second operation time t2 of the second segment signal TXO_D2 is longer or shorter.

[0067] From these technical solutions, it is evident that the pulse carrier modulation mechanism provided by this invention can be effectively applied to a first transmitter output signal TXO generated by a transmitter circuit, enabling the first transmitter output signal TXO generated by the transmitter circuit to respond to the rising and falling edges of the data input signal DI respectively, and thus containing different numbers of pulse carriers. Through this pulse carrier modulation mechanism, this invention effectively improves upon and avoids the use of existing technologies such as on-off keying (OOK) modulation, frequency shift keying (FSK) modulation, and amplitude shift keying (ASK) modulation.

[0068] Meanwhile, according to the illustrations of the present invention Figure 4From the waveform diagram of the disclosed first transmitter output signal TXO, it can be observed that after the transmitter circuit stops generating the pulse carrier of the first sub-signal TXO_D1 or the second sub-signal TXO_D2, the first transmitter output signal TXO enters a stable state (or steady state). Under this steady state condition, the voltage level of the first transmitter output signal TXO is not necessarily limited to a certain fixed value and can be variable. In other words, according to the technical solution of the present invention, after the transmitter circuit stops generating the first sub-signal TXO_D1 or the second sub-signal TXO_D2, the first transmitter output signal TXO has an adjustable voltage level. Based on the fact that the present invention avoids the unlimited generation of continuous and uninterrupted pulse carriers in the time segment between the high voltage level (digital logic "1") and the low voltage level (digital logic "0") of the data input signal DI, as in the prior art, the present invention can successfully achieve the inventive objective of reducing power consumption and electromagnetic interference in the circuit system.

[0069] Please refer to the following. Figure 5 As shown, it is according to the present invention. Figure 2 The transmitter circuit disclosed in the embodiments is shown in the detailed circuit diagram. Figure 5 As shown, the transmitter circuit 202 disclosed in this invention includes a rising and falling converter 50, an oscillator 52, an AND logic gate 54, and a delay circuit 56. The rising and falling converter 50 is adapted to receive the data input signal DI and output a converted data signal DI_C accordingly. The oscillator 52 is used to generate an oscillation signal OSC. The AND logic gate 54 is electrically coupled to the rising and falling converter 50 and the oscillator 52 to receive the converted data signal DI_C and the oscillation signal OSC, and generates and outputs the first transmitter output signal TXO through an AND logic algorithm. The delay circuit 56 is further electrically coupled to the output terminal of the AND logic gate 54. With this circuit configuration, the delay circuit 56 receives the first transmitter output signal TXO, delays the first transmitter output signal TXO, and thereby generates a second transmitter output signal TXOD. As mentioned above, since the second transmitter output signal TXOD is a delayed signal of the first transmitter output signal TXO, when the first transmitter output signal TXO has a duty time T, the second transmitter output signal TXOD can be generated, for example, by delaying the first transmitter output signal TXO by half a duty time (T*1 / 2). Figure 6A waveform diagram of the second transmitter output signal TXOD compared to the first transmitter output signal TXO in an embodiment of the present invention is disclosed.

[0070] About this invention Figure 5 For the specific circuit details of the delay circuit 56 provided in the embodiment, please refer to [link / reference needed]. Figure 7 As shown in the figure, the delay circuit 56 disclosed in this invention includes at least one inverting unit 70, wherein the inverting unit 70 is composed of two inverters INV1 and INV2 connected in series, so that the inverting unit 70 can receive the aforementioned first transmitter output signal TXO, delay the first transmitter output signal TXO, and generate the aforementioned second transmitter output signal TXOD accordingly.

[0071] However, the delay circuit disclosed in this invention is not limited to such a circuit configuration. Please refer to... Figure 8 As shown, its disclosure is based on the present invention. Figure 5 Another specific implementable circuit diagram of the delay circuit provided in the embodiment. For example... Figure 8 As shown, the delay circuit 56' may, for example, include multiple inverting units 70, which are interconnected and receive the first transmitter output signal TXO, thereby generating a second transmitter output signal TXOD. For example, in Figure 8 In one embodiment, the delay circuit 56' is formed by three inverting units 70 connected in series, thereby receiving and delaying the first transmitter output signal TXO to generate the second transmitter output signal TXOD. Therefore, those skilled in the art can implement other alternative embodiments based on the technical teachings of this invention. For example, the number of inverting units 70 connected in series in the delay circuit can be any positive integer greater than 1. This invention does not limit... Figure 8 The three inverting units 70 shown in series are a limitation. Regardless of the number of inverting units and / or inverters included in the delay circuit, the present invention covers modifications and equivalent embodiments based on the technical content provided by the present invention, and such embodiments are still suitable for achieving the inventive objectives of the present invention, thereby delaying a signal based on an original transmitter output signal (the first transmitter output signal TXO of the present invention) to generate a delayed transmitter output signal (the second transmitter output signal TXOD of the present invention).

[0072] On the other hand, such as Figure 5 The circuit architecture shown is based on a top-to-bottom edge transition 50 series adapted to receive the data input signal DI, and generates a converted data signal DI_C according to the data input signal DI. The present invention further... Figure 9 The waveform diagram disclosed herein is based on the accompanying drawings of the present invention. Figure 5The waveform diagram of the transmitter circuit shown includes the data input signal DI, the converted data signal DI_C, the oscillation signal OSC, and the generated first transmitter output signal TXO.

[0073] Depend on Figure 9 As shown in the waveform diagram, the top-to-bottom edge converter 50 is adapted to receive the data input signal DI and generate the converted data signal DI_C based on and in response to the rising edge RE and falling edge FE of the data input signal DI. Specifically, the converted data signal DI_C includes a first partition signal DI_CP1 and a second partition signal DI_CP2. Since the data input signal DI is periodic, the voltage level of the converted data signal DI_C follows the voltage level of the data input signal DI, making the converted data signal DI_C also periodic. According to an embodiment of the present invention, the top-to-bottom edge converter 50 generates the first partition signal DI_CP1 in response to the rising edge RE of the data input signal DI, and terminates the generation of the first partition signal DI_CP1 before the data input signal DI reaches its falling edge FE. Then, the top-to-bottom edge converter 50 generates the second partition signal DI_CP2 in response to the falling edge FE of the data input signal DI, and terminates the generation of the second partition signal DI_CP2 before the data input signal DI reaches its next rising edge RE.

[0074] According to a preferred embodiment of the present invention, the first partition signal DI_CP1 has a first operating time t1', which is the time interval between the start of generation of the first partition signal DI_CP1 by the top-to-bottom edge converter 50 and the termination of generation of the first partition signal DI_CP1 by the top-to-bottom edge converter 50. Similarly, the second partition signal DI_CP2 has a second operating time t2', which is the time interval between the start of generation of the second partition signal DI_CP2 by the top-to-bottom edge converter 50 and the termination of generation of the second partition signal DI_CP2. In a preferred embodiment of the present invention, the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C and the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C are different.

[0075] Subsequently, the AND logic gate 54 is electrically coupled to the upper and lower edge converters 50 and the oscillator 52, and receives the converted data signal DI_C and the oscillation signal OSC as input signals to the AND logic gate 54. The AND logic gate 54 can generate the first transmitter output signal TXO at its output terminal by performing intersection logic on the converted data signal DI_C and the oscillation signal OSC. It is worth noting that, due to the effect of the intersection logic provided by the AND logic gate 54, the first operating time t1 of the first part signal TXO_D1 of the first transmitter output signal TXO is controlled to be equal to the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C, and the second operating time t2 of the second part signal TXO_D2 of the first transmitter output signal TXO is controlled to be equal to the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0076] To go even further, please refer to Figure 10 As shown, it is a detailed circuit diagram of the top and bottom edge converter according to a first embodiment of the present invention. Figure 11 According to Figure 10 The circuit diagram shown illustrates the waveforms at each node. Please also refer to... Figure 10 and Figure 11 As shown, the top-to-bottom edge converter 50 includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and a NOR gate NOR. The inverter INV receives a data input signal DI and outputs an inverted data input signal DI_B. One input terminal of the inverter INV receives the data input signal DI, and one output terminal of the inverter INV generates the inverted data input signal DI_B. Simultaneously, the input terminal of the inverter INV is connected to the first transmission gate TG1, and the output terminal of the inverter INV is connected to the third transmission gate TG3. According to a first embodiment of the top-to-bottom edge converter provided by the present invention, the data input signal DI is delayed by a first period 3Z to form a signal as shown in the delayed signal "DI_3D" of the data input signal, and the data input signal DI is delayed by a second period 1Z to form a signal as shown in the delayed signal "DI_D" of the data input signal. In this first embodiment, the first period 3Z is longer than the second period 1Z. Furthermore, the delayed signal DI_3D of the data input signal formed by delaying the data input signal DI by the first period 3Z is used to control the first transmission gate TG1, and the delayed signal DI_D of the data input signal formed by delaying the data input signal DI by the second period 1Z is used to control the fourth transmission gate TG4.

[0077] Similarly, the inverted data input signal DI_B is delayed by the first period 3Z to form a signal as shown in the delayed signal "DI_3DB" of the inverted data input signal, and the inverted data input signal DI_B is delayed by the second period 1Z to form a signal as shown in the delayed signal "DI_DB" of the inverted data input signal. These delayed signals "DI_3DB" and "DI_DB" of the inverted data input signal are used to control the second transmission gate TG2 and the third transmission gate TG3, respectively. A first input terminal N1 of the NOR gate is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the NOR gate is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. According to an embodiment of the present invention, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a high voltage level (digital logic "1"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned on; otherwise, when the control signals of the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are at a low voltage level (digital logic "0"), the first transmission gate TG1, the second transmission gate TG2, the third transmission gate TG3, and the fourth transmission gate TG4 are turned off. Through this design, the present invention can achieve the following... Figure 11 The diagram shows the waveforms of the first input terminal N1 and the second input terminal N2. Subsequently, the inverting NOR gate can generate and output the waveforms shown in the diagram based on the input signal waveforms of its first input terminal N1 and second input terminal N2. Figure 11 The converted data signal DI_C is shown in the figure. It is worth noting that in the first embodiment of the upper and lower edge converter provided by the present invention, since the first period 3Z is longer than the second period 1Z, it can be controlled such that the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C is longer than the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C.

[0078] On the other hand, please see Figure 12 As shown, it is a detailed circuit diagram of the top and bottom edge converter according to a second embodiment of the present invention. Figure 13 According to Figure 12The diagram shows the waveforms of each node in the circuit. As shown, the top-to-bottom edge converter 50' includes an inverter INV, a first transmission gate TG1, a second transmission gate TG2, a third transmission gate TG3, a fourth transmission gate TG4, and an inverting OR gate NOR. The inverter INV receives the data input signal DI and outputs an inverted data input signal DI_B. A first input terminal N1 of the inverting OR gate NOR is electrically coupled to the first transmission gate TG1 and the second transmission gate TG2, and a second input terminal N2 of the inverting OR gate NOR is electrically coupled to the third transmission gate TG3 and the fourth transmission gate TG4. Therefore, the inverting OR gate NOR can generate and output a waveform based on the input signal waveforms at its first input terminal N1 and second input terminal N2. Figure 13 The conversion data signal DI_C is shown in the figure. When we compare this second embodiment's upper and lower edge converter 50' with the previous first embodiment (such as...), Figures 10 to 11 When comparing the upper and lower edge converters (50) shown, it can be observed that in this second embodiment, the first period for delaying the data input signal DI and the inverted data input signal DI_B is 1Z, and the second period for delaying the data input signal DI and the inverted data input signal DI_B is 3Z. Therefore, in this second embodiment, the control signals of the first transmission gate TG1 and the fourth transmission gate TG4 are respectively the delayed signal DI_D and the delayed signal DI_3D of the data input signal, while the control signals of the second transmission gate TG2 and the third transmission gate TG3 are respectively the delayed signal DI_DB and the delayed signal DI_3DB of the inverted data input signal.

[0079] Therefore, in the second embodiment of the upper and lower edge converter 50' provided by the present invention, since the second period 3Z is longer than the first period 1Z, it can be controlled such that the second working time t2' of the second partition signal DI_CP2 of the converted data signal DI_C will be longer than the first working time t1' of the first partition signal DI_CP1 of the converted data signal DI_C, as shown in the accompanying drawings of the present invention. Figure 13 The waveform diagram is shown below.

[0080] Therefore, in view of the above Figures 10-11 as well as Figures 12-13The disclosed embodiments effectively demonstrate how the present invention precisely and ingeniously designs the aforementioned top and bottom edge converters, ensuring that the first operating time t1' of the first partition signal DI_CP1 of the converted data signal DI_C is different from the second operating time t2' of the second partition signal DI_CP2 of the converted data signal DI_C. According to the technical solution disclosed in the present invention, the first operating time t1' of the first partition signal DI_CP1 is not limited to whether it must be longer or shorter than the second operating time t2' of the second partition signal DI_CP2. As long as the first operating time t1' of the first partition signal DI_CP1 and the second operating time t2' of the second partition signal DI_CP2 are different, the first operating time t1 of the first branch signal TXO_D1 of the first transmitter output signal TXO and the second operating time t2 of the second branch signal TXO_D2 of the first transmitter output signal TXO are also different. Therefore, the present invention can successfully control the number of the first group of pulse carriers contained in the first branch signal TXO_D1 to be different from the number of the second group of pulse carriers contained in the second branch signal TXO_D2. The transmitter output signals (first component signal TXO_D1 and second component signal TXO_D2) generated by the transmitter circuit can each be designed with different numbers of pulse carriers based on the rising and falling edges of the data input signal DI. This PCM pulse carrier modulation mechanism disclosed in this invention effectively avoids the use of excessive data transmission channels during signal transmission and coupling. Furthermore, compared to existing technologies, traditional transmitter circuits continuously and uninterruptedly output an infinite number of pulse carriers regardless of whether the data input signal is at a high or low voltage level. The pulse carrier modulation mechanism provided by this invention reduces the number of pulse carriers in the transmitter output signal. Therefore, compared to existing technologies, this invention can effectively reduce power consumption and electromagnetic interference in the system.

[0081] Therefore, based on at least one embodiment disclosed in the present invention, it is certain that the digital isolator circuit provided by the present invention is novel and unprecedented. It provides an innovative pulse carrier modulation mechanism. By applying this innovative pulse carrier modulation mechanism to a transmitter circuit, the transmitter circuit can generate different numbers of pulse carriers according to the data input signal and in response to the rising and falling edges of the data input signal. Since the transmitter circuit can output a first group of pulse carriers when the data input signal transitions from digital logic "0" to digital logic "1", and can also output a second group of pulse carriers when the data input signal transitions from digital logic "1" to digital logic "0", and the number of the first group of pulse carriers is different from the number of the second group of pulse carriers, the present invention successfully improves upon the problems of the prior art through these technical solutions. In view of this, it is evident that the present invention helps to reduce circuit power consumption and significant electromagnetic interference. Meanwhile, by using the digital isolator circuit with pulse carrier modulation provided by this invention, the accuracy of data transmission can be ensured, and the robustness of the system output voltage can be successfully maintained while reducing signal jitter interference.

[0082] In addition, the digital isolator circuit provided by this invention has an additional signal delay path, which can delay the original transmitter output signal (the first transmitter output signal TXO of this invention) to generate a delayed transmitter output signal (the second transmitter output signal TXOD of this invention). This invention can effectively amplify the receiver input signal by more than two times. Simultaneously, based on this gain and improvement, the robustness of data transmission of the digital isolator circuit provided by this invention can also be significantly improved, while avoiding common-mode voltage signal drift. This not only ensures the correctness of the data output signal but also avoids signal jitter disturbance. Furthermore, this invention can further reduce the enormous power consumption and severe electromagnetic interference problems in the prior art, verifying the inventive efficacy achieved by this invention.

[0083] Therefore, in view of the above, compared with the prior art, it is obvious that the embodiments and circuit architecture disclosed in this invention can effectively solve many shortcomings of the prior art and present more efficient circuit performance. Furthermore, the technical solution provided by this invention can be applied not only to common electronic components, but also widely to various electronic circuit components in the semiconductor industry, integrated circuit industry, or power electronics. Clearly, the technical solution claimed herein has excellent industrial applicability and competitiveness. At the same time, the applicant has also verified through various experimental data and empirical data that the technical features, methods, and effects achieved by this invention are significantly different from existing solutions and cannot be easily accomplished by those skilled in the art.

[0084] The embodiments described above are merely illustrative of the technical ideas and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should still be covered within the protection scope of the present invention.

Claims

1. A digital isolator circuit with additional delay, characterized in that, include: A transmitter circuit receives a data input signal and generates a first transmitter output signal and a second transmitter output signal based on the data input signal, wherein the second transmitter output signal is a delayed signal of the first transmitter output signal; An isolation barrier is electrically coupled to the transmitter circuit and receives the output signal of the first transmitter and the output signal of the second transmitter. The isolation barrier generates a first isolation output signal and a second isolation output signal based on the received first and second transmitter output signals. as well as A receiver circuit electrically coupled to the isolation barrier to receive the first isolation output signal and the second isolation output signal, thereby generating a data output signal in response to the first isolation output signal and the second isolation output signal.

2. The digital isolator circuit with additional delay as described in claim 1, characterized in that, The first transmitter output signal includes a first part signal and a second part signal. The transmitter circuit starts generating the first part signal of the first transmitter output signal in response to a first transition state of the data input signal from a first logic state to a second logic state. When the data input signal is still in the second logic state, the transmitter circuit stops generating the first part signal of the first transmitter output signal. The transmitter circuit starts generating the second part signal of the first transmitter output signal in response to a second transition state of the data input signal from the second logic state to the first logic state. When the data input signal is still in the first logic state, the transmitter circuit stops generating the second part signal of the first transmitter output signal.

3. The digital isolator circuit with additional delay as described in claim 2, characterized in that, The first part of the signal output by the first transmitter includes a first group of pulse carriers, and the second part of the signal output by the first transmitter includes a second group of pulse carriers, wherein the number of the first group of pulse carriers in the first part of the signal is different from the number of the second group of pulse carriers in the second part of the signal.

4. The digital isolator circuit with additional delay as described in claim 3, characterized in that, The frequency of the first group of pulse carriers in the first segment signal and the frequency of the second group of pulse carriers in the second segment signal are each a variable.

5. The digital isolator circuit with additional delay as described in claim 3, characterized in that, The amplitude of the first group of pulse carriers in the first segment signal and the amplitude of the second group of pulse carriers in the second segment signal are each a variable.

6. The digital isolator circuit with additional delay as described in claim 2, characterized in that, After the transmitter circuit stops generating the first or second component signal of the first transmitter output signal, the first transmitter output signal has a moduloable voltage level.

7. The digital isolator circuit with additional delay as described in claim 3, characterized in that, The first portion of the first transmitter output signal has a first operating time, which is a first time interval between the transmitter circuit starting to generate the first group of pulse carriers and the transmitter circuit stopping the generation of the first group of pulse carriers. The second portion of the first transmitter output signal has a second operating time, which is a second time interval between the transmitter circuit starting to generate the second group of pulse carriers and the transmitter circuit stopping the generation of the second group of pulse carriers. Furthermore, the first operating time of the first portion of the signal and the second operating time of the second portion of the signal are different.

8. The digital isolator circuit with additional delay as described in claim 1, characterized in that, Based on the fact that the data input signal is periodic, and the voltage level of the first transmitter output signal follows the voltage level of the data input signal, the first transmitter output signal is periodic.

9. The digital isolator circuit with additional delay as claimed in claim 1, characterized in that, Since the data input signal is periodic, and the voltage level of the second transmitter output signal follows the voltage level of the data input signal, the second transmitter output signal is periodic.

10. The digital isolator circuit with additional delay as claimed in claim 1, characterized in that, The first transmitter outputs a signal with one duty cycle, and the second transmitter outputs a signal by delaying the first transmitter output signal by half of that duty cycle.

11. The digital isolator circuit with additional delay as described in claim 7, characterized in that, The transmitter circuitry includes: A top-to-bottom edge converter receives a data input signal and outputs a converted data signal in response to a rising edge and a falling edge of the data input signal. The converted data signal includes a first partition signal and a second partition signal. The top-to-bottom edge converter generates the first partition signal in response to the rising edge of the data input signal, and terminates the generation of the first partition signal before the data input signal reaches the falling edge. The top-to-bottom edge converter generates the second partition signal in response to the falling edge of the data input signal, and terminates the generation of the second partition signal before the data input signal reaches the next rising edge. A first operating time of the first partition signal and a second operating time of the second partition signal are different. An oscillator that generates an oscillating signal; An AND logic gate, electrically coupled to the upper and lower edge converter and the oscillator, receives the converted data signal and the oscillation signal to generate the first transmitter output signal; and A delay circuit is electrically coupled to the AND logic gate. The delay circuit receives the output signal of the first transmitter, delays the output signal of the first transmitter, and thus generates the output signal of the second transmitter.

12. The digital isolator circuit with additional delay as described in claim 2, characterized in that, The first transition state of the data input signal from the first logic state to the second logic state is responded to a rising edge of the data input signal.

13. The digital isolator circuit with additional delay as described in claim 2, characterized in that, The second transition state of the data input signal from the second logic state to the first logic state is responded to a falling edge of the data input signal.

14. The digital isolator circuit with additional delay as claimed in claim 11, characterized in that, The first operation time of the first segment signal of the first transmitter output signal is equal to the first working time of the first partition signal of the converted data signal, and the second operation time of the second segment signal of the first transmitter output signal is equal to the second working time of the second partition signal of the converted data signal.

15. The digital isolator circuit with additional delay as claimed in claim 11, characterized in that, The top-to-bottom edge converter includes an inverter, a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, and an inverting OR gate. The inverter receives the data input signal and outputs an inverted data input signal. A first input terminal of the inverting OR gate is electrically coupled to the first transmission gate and the second transmission gate. A second input terminal of the inverting OR gate is electrically coupled to the third transmission gate and the fourth transmission gate. The first and third transmission gates are also connected to an input terminal and an output terminal of the inverter, respectively. The data input signal is delayed by a first period and a second period to control the first and fourth transmission gates, respectively. The inverted data input signal is delayed by the first and second periods to control the second and third transmission gates, respectively, so that the inverting OR gate outputs the converted data signal.

16. The digital isolator circuit with additional delay as described in claim 15, characterized in that, When the first period is longer than the second period, the first working time of the first partition signal of the converted data signal is longer than the second working time of the second partition signal of the converted data signal.

17. The digital isolator circuit with additional delay as described in claim 15, characterized in that, When the second period is longer than the first period, the second working time of the second partition signal of the converted data signal is longer than the first working time of the first partition signal of the converted data signal.

18. The digital isolator circuit with additional delay as claimed in claim 11, characterized in that, The delay circuit includes at least one inverting unit, which is composed of two inverters connected in series, such that the at least one inverting unit receives the output signal of the first transmitter and generates the output signal of the second transmitter accordingly.

19. The digital isolator circuit with additional delay as described in claim 18, characterized in that, The delay circuit also includes multiple inverting units, which are connected in series to receive the output signal of the first transmitter, thereby generating the output signal of the second transmitter.

20. The digital isolator circuit with additional delay as claimed in claim 1, characterized in that, The isolation barrier includes at least one set of isolation capacitors, one capacitor in the set of isolation capacitors being adapted to receive the output signal of the first transmitter and generate the first isolated output signal, and another capacitor in the set of isolation capacitors being adapted to receive the output signal of the second transmitter and generate the second isolated output signal.

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