METHOD FOR ENGRAVING A LAYER OF MATERIAL III-N
A two-step etching process using chlorine and fluorine plasmas minimizes damage to III-N materials, addressing defects in existing methods and enhancing square resistance, achieving faster and more precise etching.
Patent Information
- Application Number
- FR2020006295
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2020-06-16
- Publication Date
- 2025-01-17
- Estimated Expiration
- 2040-06-16
AI Technical Summary
Existing etching processes for III-N materials, such as AlGaN/GaN heterostructures, cause defects like structural damage, stoichiometry modification, and charge implantation, leading to degraded electrical properties and poor control over etch depth, especially when using chlorinated, bromine, or fluorine-based plasmas, and atomic layer etching (ALE) is time-consuming and damaging.
A two-step etching process using a chlorine-based plasma followed by a fluorine-based plasma with a low bias voltage to minimize damage, where the first etching quickly removes most of the material and the second etching completes the process with minimal impact on the remaining material, avoiding purging phases and enhancing square resistance.
The method achieves faster etching with reduced material damage, improving the square resistance of III-N materials compared to existing methods, while maintaining high etching rates and precise control over depth.
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Abstract
Description
Title of the invention: METHOD FOR ETCHING A LAYER OF III-N MATERIAL Technical field
[0001] The invention relates to a method for etching a layer of III-N material. The invention also relates to a method for producing one or more power electronic components during which this etching method is implemented. PREVIOUS ART
[0002] Thanks to their electrical properties, which are better than those of silicon or SiC-based structures, AlGaN / GaN heterostructures, which allow the formation of a two-dimensional electron gas, represent a judicious choice for the production of power electronic components such as HEMT (High-Electron-Mobility Transistor) type transistors or diodes. The advantages provided by this type of heterostructure include a reduced size of the components that can be produced, good voltage resistance, significant carrier mobility and low series resistance.
[0003] This heterostructure, when used to make a transistor or a diode, is etched to form the locations of the gate and the electrical contacts of the transistor, or to form the locations of the electrical contacts of the diode. For this, plasma etching is implemented in ICP (“Inductive Coupled Plasma”) type equipment using a chlorinated plasma, for example based on SiCl4 or BC13. The speed of such etching is high thanks to the desorption of the GaCl3 and A1C13 species which are volatile. However, it induces defects in the etched heterostructure, such as for example: creation of structural defects, modification of stoichiometry or even implantation of elements and generation of charges in the etched materials.These defects modify the electrical properties of the etched materials and degrade those of the device made from the etched heterostructure, such as the transistor channel when this etching is implemented to produce the transistor gate. In addition, such plasma etching does not allow good control of the depth of the etched material due to the absence of an etching stop layer in the etched structure, this depth being determined by the duration during which the etching is implemented.
[0004] The documents “Reactive ion etching of gallium nitride using hydrogen bromide plasmas” by AT Ping et al. Electron. Lett., vol. 30, no. 22, pp. 1895-1897, 1994, and “Reactive ion etching of GaN using CHF3 / Ar and C2C1F5 / Ar plasmas” by H. Lee et al., Appl. Phys. Lett., vol. 67, p. 1754, 1995, describes the possibility of etching GaN using bromine or fluorine-based plasmas. The etching rates obtained are, however, much lower than those obtained using chlorine-based plasmas due to the species formed being more difficult to desorb than those formed by chlorine-based plasmas. Increasing the ion energy of the plasma used allows for an increase in the etching rate, but creates defects in the etched material.
[0005] To overcome these problems, the document “Atomic layer etching of GaN and AlGaN using directional plasma-enhanced approach,” by T. Ohba et al., Jpn. J. Appl. Phys., vol. 56, no. 6, 2017 proposes to implement a conventional chlorinated plasma etching followed by an ALE type over-etching (“Atomic Layer Etching”) to etch a GaN layer. This over-etching is obtained by cyclically repeating the following two steps:
[0006] - chlorination by a C12 / BC13 plasma of the GaN surface intended to be etched, modifying the GaN to a small thickness and forming a thin layer based on Cl2;
[0007] - an etching of the Cl2-based layer selectively with respect to the GaN located under the Cl2-based layer and which has not been modified by the previous chlorination step, implemented by an Ar-based plasma with low polarization.
[0008] Between each of the two steps of each over-etching cycle, it is necessary to perform a purge and stabilization of the gases for approximately 10 seconds. During this phase, the plasma is cut off in order to avoid interactions and gas mixing. Given the numerous over-etching cycles to be implemented to etch the desired thickness, the time required to implement this process represents a major drawback. In addition, the range of ion energy values with which the etching of the Cl2-based layers must be implemented to completely etch the Cl2-based layer without damaging the underlying GaN is very restricted. Finally, even if the square resistance of the layer etched with this process is lower than that obtained with etching by a chlorine plasma, the etched material is still damaged by the over-etching implemented.For example, considering that the square resistance of the unetched material is equal to 1, the square resistance of this same material etched with ALE type over-etching is equal to 1.41 and that of this same material etched with etching using a chlorine plasma is equal to 2.35. Statement of the invention
[0009] An aim of the present invention is to propose a method of etching at least a portion of a layer of III-N material not having the disadvantages of the etching methods of the prior art, that is to say which damages the etched material less than an etching carried out with a chlorine plasma, which is faster than an etching carried out with a bromine or fluorine-based plasma or which implements an ALE type over-etching, and which improves the square resistance of the remaining material of the layer of III-N material after etching.
[0010] For this, the present invention proposes a method for etching at least a portion of a layer of III-N material, comprising the implementation of the following steps:
[0011] - first etching of a first part of the thickness of the portion of the layer of III-N material, implemented using a first plasma comprising chlorine;
[0012] - second etching of a remaining thickness of the portion of the material layer III-N, implemented using a second plasma comprising fluorine and subjected to a non-zero bias voltage less than or equal to 200 V.
[0013] This method proposes to implement a first etching of the portion of the III-N material layer using a first plasma comprising chlorine in order to quickly etch a first part of the thickness of the portion of the III-N material layer to be etched. The second etching which is then implemented completes the etching of the portion of the III-N material layer using a second plasma comprising fluorine and with a low bias voltage in order not to damage the III-N material remaining under the etched portion. Since the first etching is stopped before having etched the entire desired thickness of III-N material, this first etching does not damage the III-N material remaining at the end of the etching process.
[0014] Furthermore, for the same etched thickness of IILN material, this method makes it possible to etch the material more quickly than a single etching carried out with a bromine or fluorine-based plasma, or which uses, after etching by chlorinated plasma, an ALE type over-etching because the method according to the invention does not require a gas purging and stabilization phase between the two steps of the ALE type over-etching.
[0015] During the second etching, the second plasma is subjected to a non-zero bias voltage of less than 150 V, which limits any damage to the etched material.
[0016] Furthermore, the square resistance of the IILN material remaining after the implementation of this etching method is lower than that obtained with the etching methods of the prior art (considering that the square resistance of the non-etched material is equal to 1, the square resistance of the etched material is here equal to 1.2).
[0017] The second plasma etching can be implemented by subjecting the second plasma at a bias voltage between 50 V and 100 V.
[0018] The remaining thickness of the portion of the III-N material layer may be equal to about 10 nm, or between about 5 nm and 15 nm, or less than about 20 nm. Thus, a large part of the portion of the III-N material layer is etched quickly using the first chlorine plasma, which minimizes the total time required to etch the portion of the III-N material layer.
[0019] The second plasma may comprise CF4. The use of such a plasma is advantageous compared to CXFY type plasmas (excluding CF4) which will promote deposition, or compared to CXHYFZ type plasmas which risk damaging the film due to the addition of hydrogen into the plasma.
[0020] The first and second etchings can be implemented in ICP-RIE (“Inductive Coupled Plasma - Reactive Ion Etching”) type etching equipment.
[0021] The second etching can be implemented with a pulsed plasma. The use of a pulsed plasma makes it possible to reduce the damage to the etched layer for a given self-bias voltage, and to reduce the damage compared to a continuous plasma.
[0022] The second engraving can be implemented:
[0023] - using a power source between 100 W and 1000 W, and / or
[0024] - in an etching chamber in which the pressure is between 1.33 Pa and 10.67 Pa, and / or
[0025] - with a flow of the second plasma between 15 sccm and 100 sccm, and / or
[0026] - in the etching chamber in which the temperature is between 40°C and 80°C.
[0027] The method is advantageously implemented to etch a layer of III-N material comprising GaN and / or FAlGaN and / or AlN.
[0028] Furthermore, the III-N material layer may be part of an AlGaN / GaN heterostructure.
[0029] The invention also relates to a method for producing at least one power electronic component, comprising the implementation of the following steps:
[0030] - production of an AlGaN / GaN heterostructure;
[0031] - production of electrical contact locations of the electronic component of power in the AlGaN / GaN heterostructure, comprising the implementation of an etching process as described above. Brief description of the drawings
[0032] The present invention will be better understood upon reading the description of examples of realization given for purely indicative purposes and in no way limiting, with reference to the attached drawings on which:
[0033] [Fig-1] schematically represents the steps of a method of etching at least a portion of a layer of III-N material, object of the present invention, according to a particular embodiment;
[0034] [Fig.2] schematically represents the steps of a part of a rea process lization of an electronic power component, object of the present invention, according to a particular embodiment.
[0035] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.
[0036] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.
[0037] The different possibilities (variants and embodiments) must be understood as not being mutually exclusive and can be combined with each other.
[0038] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS
[0039] [Fig.l] described below schematically represents the steps of a method of etching at least a portion of at least one layer of IILN material according to a particular embodiment.
[0040] The layer of IILN material here corresponds to a layer of GaN and / or AlGaN and / or AlN. Other IILN materials can however be etched with the method described here.
[0041] The thickness of the portion of the IILN material layer intended to be etched is for example between 20 nm and 110 nm.
[0042] This etching process is implemented in RIE type etching equipment, and advantageously ICP-RIE type.
[0043] A first part of the thickness of the portion of the IILN material layer is first etched during a first etching 102. This first etching 102 is carried out using a first plasma comprising chlorine, such as for example Cl2 / BCl3 / Ar.
[0044] This first etching 102 is carried out for a sufficient duration to etch a large part of the thickness of the portion of the IILN material layer intended to be etched. The value of the remaining thickness to be etched (at the end of the first etching) of the portion of the IILN material layer may be equal to approximately 10 nm, or between approximately 5 nm and 15 nm, or less than approximately 20 nm.
[0045] After having implemented this first etching 102, a second etching 104 by plasma is implemented to etch the remaining thickness to be etched of the portion of the layer of III-N material. Unlike the first etching 102, this second etching 104 is implemented using a second plasma comprising fluorine, advantageously CF4 or CF4 / Ar. Argon may be present in the second plasma, with a flux preferably less than or equal to 200 sccm.
[0046] During this second etching 104, the second plasma is subjected to a non-zero bias voltage less than 150 V, and advantageously between 50 V and 100 V and preferably equal to 100 V. The other parameters for implementing this second etching 104 are:
[0047] - power of the source of the second plasma between 100 W and 1000 W, and preferably equal to 400 W,
[0048] - pressure in the etching chamber between 1.33 Pa and 10.67 Pa, and preference equal to 4.27 Pa,
[0049] - flux of the second plasma between 15 sccm and 100 sccm, and preferably equal at 30 sccm,
[0050] - temperature in the etching chamber between 40°C and 80°C, and preferably equal to 60°C.
[0051] The speed of this second etching is of the order of 1 nm / min to 2 nm / min depending on the energy of the ions of the second plasma. With the preferred values indicated above, the etching speed obtained is equal to approximately 1.5 nm / min.
[0052] Optionally, a stabilization step can be implemented between the first and second etchings 102, 104, in order to stabilize the gases, the pressure and the temperature before implementing the second etching 104. This stabilization phase can be implemented for a duration of a few seconds.
[0053] As a variant of the method described above, the second etching 104 can be implemented with a pulsed plasma. Such a pulsed plasma can be obtained by operating the source and / or the polarization intermittently, i.e. periodically. It is possible to adjust the properties of this pulsed plasma by modifying the duty cycle (ratio between the start-up time and the stop-up time) and / or the frequency of the signal controlling the power of the source, and / or by modifying the duty cycle and / or the frequency of the polarization signal.
[0054] The etching method described above is advantageously implemented when producing power electronic components. [Fig. 2] described below illustrates steps implemented when producing a power electronic component 200 for etching a given thickness of an AlGaN / GaN heterostructure. The steps described in connection with [Fig. 2] correspond to the steps implemented to produce the gate of a HEMT transistor.
[0055] The HEMT transistor is made from a stack of layers comprising a substrate 202, one or more buffer layers 204 arranged on the substrate 202, and a AlGaN / GaN heterostructure formed here from a GaN layer 206 arranged on the buffer layer(s) 204, an AlN layer 208 arranged on the GaN layer 206 and an AlGaN layer 210 arranged on the AlN layer 208. The layers 204, 206, 208 and 210 are for example produced by epitaxy.
[0056] The substrate 202 corresponds to a semiconductor substrate, for example silicon. The buffer layer(s) 204, which make it possible to reduce the problems of mesh mismatch and thermal expansion coefficients between the substrate 202 and the AlGaN / GaN heterostructure, comprise for example AIN and / or AlGaN at different concentrations to create a gradient of Al and / or Ga, which makes it possible to grow the AlGaN / GaN heterostructure by epitaxy under good conditions.
[0057] The thickness of the AlGaN / GaN heterostructure (layers 206, 208, 210) is for example between 300 nm and 1 pm.
[0058] In the example described here, the AlGaN layer 210 is covered with a thin passivation layer 212 of SiN, with a thickness for example equal to 10 nm, deposited in situ in the epitaxy frame used to produce the layers 204, 206, 208 and 210, making it possible to protect the upper surface of the AlGaN layer 210, and to avoid relaxations as well as the opening of dislocations on the surface of the AlGaN layer 210. The structure obtained at this stage of the process corresponds to the structure a) of [Fig.2].
[0059] The passivation layer 212 can then be completed by depositing, for example by LPCVD (Low-Pressure Chemical Vapor Deposition), a greater thickness of passivation material, here silicon nitride (Si3N4). The final thickness of the passivation layer is for example between 10 nm and 100 nm. The structure obtained at this stage of the process corresponds to the structure b) visible in [Fig.2].
[0060] An etching mask 214 is then produced on the passivation layer 212. The pattern of this etching mask 214 makes it possible to define the shape and location of the gate of the produced transistor. This pattern corresponds for example to that of a trench whose width “1” is for example between 250 nm and 50 pm. This mask 214 is for example obtained by lithography of a resin. The structure obtained at this stage of the process corresponds to the structure c) visible in [Fig.2].
[0061] Plasma etching is first performed using a fluorocarbon plasma, for example C2F6, CHF3 or CF4, with a mixture of other gases such as Ar, N2 or O2, in order to etch the passivation layer 212 in accordance with the pattern of the etching mask 214.
[0062] The two etching steps previously described in connection with the method shown in [Fig.l] are then implemented to etch a portion of the thickness of the AlGAN / GaN heterostructure formed by the layers 206, 208 and 210. In the example described here, these etchings are implemented in order to etch the entire thickness of the layers 210 and 208, and a portion of the thickness of layer 206. The total etched thickness is for example between 20 nm and 110 nm. The first etching implemented using a first plasma comprising chlorine can for example be used to etch the entire thickness of layers 210 and 208, and to etch a large portion of the desired thickness of layer 206. Thus, the second etching implemented using a second plasma comprising fluorine only serves to etch a small remaining thickness of the material of layer 206 until reaching the desired depth, and thus preserve the quality of the material of layer 206 remaining after the second etching. The etching steps implemented form a gate location 216 in the AlGaN / GaN heterostructure. Part of the thickness of the etching mask 214 is also consumed by these etching steps. The structure obtained at this stage of the process corresponds to structure d) visible in [Fig.2].
[0063] The etching mask 214 is then removed (see structure e) of [Fig.2]), then the gate materials (gate dielectric and gate conductor) are deposited in the location 216 and on the passivation layer 212, forming a gate 218. The structure obtained at the end of the process corresponds to the structure f) visible in [Fig.2], and schematically represents the component 200 produced.
[0064] Similar steps can be implemented for producing the contacts of the source and drain regions of the component 200.
[0065] Alternatively, the etching method described above can be implemented to produce the contact locations of another type of power electronic component 200, for example a diode.
Claims
Claims
1. Method for etching at least a portion of a layer of III-N material (206, 208, 210), comprising the implementation of the following steps: - first etching (102) of a first part of the thickness of the portion of the layer of III-N material (206, 208, 210), carried out using a first plasma comprising chlorine; - second etching (104) of a remaining thickness of the portion of the layer of III-N material (206, 208, 210), carried out using a second pulsed plasma comprising fluorine, subjected to a non-zero bias voltage and less than or equal to 150 V and obtained by intermittently operating a source and / or a bias of this second plasma.
2. The etching method of claim 1, wherein the second plasma comprises CF4.
3. Etching method according to one of the preceding claims, in which the second plasma etching (104) is carried out by subjecting the second plasma to a bias voltage of between 50 V and 100 V.
4. Etching method according to one of the preceding claims, wherein the remaining thickness of the portion of the III-N material layer (206, 208, 210) is less than approximately 20 nm.
5. Etching method according to one of the preceding claims, in which the first and second etchings (102, 104) are implemented in ICP-RIE type etching equipment.
6. Etching method according to one of the preceding claims, in which the second etching (104) is carried out: - using a power source of between 100 W and 1000 W, and / or - in an etching chamber in which the pressure is between 1.33 Pa and 10.67 Pa, and / or - with a flow of the second plasma of between 15 sccm and 100 sccm, and / or - in the etching chamber in which the temperature is between 40°C and 80°C.
7. Etching method according to one of the preceding claims, in which the layer of III-N material (206, 208, 210) comprises GaN and / or AlGaN and / or AlN.
8. Etching method according to one of the preceding claims, in which the layer of III-N material (206, 208, 210) is part of an AlGaN / GaN heterostructure.
9. Method for producing at least one power electronic component (200), comprising the implementation of the following steps: - producing an AlGaN / GaN heterostructure (206, 208, 210); - producing locations (216) of electrical contacts (218) of the power electronic component (200) in the AlGaN / GaN heterostructure (206, 208, 210), comprising the implementation of an etching method according to claim 8.