Matrix detector with multiple groups of control modules and detector implementation method.

Abstract

The invention relates to a matrix detector and a method for implementing the detector. The detector comprises: - an array of pixels sensitive to a physical phenomenon and arranged in a matrix of rows and columns, each pixel generating a signal that is a function of the physical phenomenon; - line conductors (L), each driving the pixels of a row; - a first group (A) of driver modules (SR_A), each delivering selection signals (Out_A) to a line conductor (L) of a first group of line conductors; - a second group (B) of driver modules (SR_B), each delivering selection signals (Out_B) to a line conductor (L) of a first group of line conductors, the first and second groups of line conductors being interleaved. Figure for the abstract: Fig. 3.

Description

Title of the invention: Matrix detector with several groups of control modules and method for implementing the detector

[0001] The present invention relates to a matrix detector and to a method for implementing the detector. The invention is useful in producing visible images but is not limited to this field. For example, pressure or temperature maps or two-dimensional representations of chemical or electrical potentials can be produced. These maps or representations form images of physical quantities. The invention applies in particular to active matrix detectors used, for example, for detection purposes in ionizing radiation imaging devices, for example X-rays, such as TFT type panels, according to the acronym designating the English terminology: "Thin Film Transistor" or thin-film transistor.

[0002] In a matrix detector, a pixel represents the elementary sensitive element of the detector. Each pixel converts a physical phenomenon to which it is subjected into an electrical signal. The electrical signals from the different pixels are collected during a reading phase of the matrix and then digitized so that they can be processed and stored to form an image. The pixels are formed of an area sensitive to the physical phenomenon and deliver, for example, a current of electrical charges. The physical phenomenon can be electromagnetic radiation carrying a flux of photons and subsequently, the invention will be explained by means of this type of radiation and the charge current is a function of the flux of photons received by the sensitive area. Generalization to any matrix detector will be easy.

[0003] A matrix image detector comprises row conductors, each connecting the pixels of the same row, and column conductors, each connecting the pixels of the same column. The column conductors are connected to conversion circuits generally arranged on an edge of the matrix which can be called the "column foot".

[0004] Each pixel generally comprises a photosensitive element, or photodetector, which may for example be a photodiode, a photoresistor or a phototransistor. Large photosensitive matrices are found which may have several million pixels organized in rows and columns. Each pixel further comprises an electronic circuit consisting for example of switches, capacitors, resistors, downstream of which an actuator is placed. The assembly consisting of the photosensitive element and the electronic circuit makes it possible to generate electrical charges and to collect them. The electronic circuit generally allows the resetting of the charge collected in each pixel after a charge transfer. The role of the actuator is to transfer or copy the charges collected by the circuit into a column conductor. This transfer is carried out when the actuator receives an instruction from a row conductor. The output of the actuator corresponds to the output of the pixel. The names "row conductor" and "column conductor" are purely arbitrary. It is of course possible to reverse these names.

[0005] In this type of detector, a pixel operates in two phases: an image capture phase, during which the electronic circuit of the pixel accumulates the electrical charges generated by the photosensitive element, and a reading phase, during which the collected charges are transferred or copied into the column conductor, thanks to the actuator.

[0006] During the reading phase, a reading instruction is sent to all the actuators of the same row of the matrix by means of a row conductor. Each of the pixels of this row is read by transferring its electrical information, charge, voltage, current, frequency, etc. to the column conductor with which it is associated.

[0007] For an image frame, the lines of pixels can be selected in sequence, one after the other following a scanning direction of the lines of the matrix, during a line selection time corresponding to a fraction of the duration of the frame, allowing the application to the pixels of the line in question of appropriate signals, for example voltages. Thus the selection of a line corresponds to the application during a corresponding line selection time, of a high level signal controlling the on state of the switching devices of the corresponding line of pixels. Outside the line selection time, the switching devices are maintained in a blocked state via the application of an appropriate low level signal.For example, when the switching devices are transistors, the signals to be applied being voltages, it is usual to designate VGon the voltage corresponding to the high level and therefore to the on state of the switching transistor, and VGoff the voltage corresponding to the low level and to the off state of the switching transistor.

[0008] The control of the lines can be ensured by control circuits comprising one or more serial shift registers, each of the shift registers comprising a plurality of cascaded stages, each stage being capable of switching the high and low levels of the signal applied to the actuators of the pixels of a corresponding line of the matrix, according to the sequencing of the selection of the lines, for example according to a vertical scan. The control circuits can be implemented in integrated circuits, the same integrated circuit being able for example to comprise a plurality of control circuits for a plurality of lines of the matrix. The integrated circuits can for example be external to the matrix, and be connected to it by wired means, for example flexible ribbons. The control circuits control can also be implanted on the panel carrying the pixels as described in patent application WO 2012 / 152836 A1 filed in the name of the applicant.

[0009] This makes it possible to reduce the number of signals applied to the panel and therefore the size and number of flexible connectors used to connect the panel to its electronic environment. This integrated control circuit architecture provides a significant simplification of the detector architecture by reducing the number of components and simplifying the manufacturing process.

[0010] However, this architecture imposes the order in which the matrix lines are driven. This order is imposed by the connections of the control circuits and the matrix lines. In some cases, it may be desirable to vary the order in which the matrix lines are driven. More precisely, it may be desirable to group several pixels to read them collectively. This grouping, known in the English literature as "binning", makes it possible to improve the signal-to-noise ratio of each element read. Another advantage of pixel grouping is to improve the sensitivity of the detector. However, grouping is done at the expense of spatial resolution.

[0011] In the case where the information from each pixel is an electrical charge, the grouping of pixels can be carried out by a redistribution of the charges of the pixels to be grouped on a common capacitor, for example arranged in the conversion circuit at the bottom of the column. This can be carried out in a detector as described in patent application WO 2012 / 152836 A1 by reading each row of pixels successively. However, in such a detector, the grouping of pixels of consecutive rows does not make it possible to improve the reading speed of the detector and therefore to increase the frequency of the images produced by the detector.

[0012] The invention aims to overcome all or part of the problems mentioned above by proposing a detector whose control circuits allow either conventional sequential reading or the grouping of pixels belonging to successive lines by increasing the reading speed. The invention finds a particular advantage in a detector where the control circuits and the pixels are produced on the same substrate.

[0013] To this end, the invention relates to a matrix detector comprising: - a set of pixels sensitive to a physical phenomenon and organized in a matrix according to rows and columns of pixels, each pixel generating a signal depending on the physical phenomenon, - line conductors each enabling the pixels of a line to be driven, the line conductors being divided into at least two groups of interlaced line conductors, - a first group of control modules delivering selection signals, each to one of the line conductors of a first of the groups of line conductors, - a second group of control modules delivering selection signals, each to one of the line conductors of a second of the groups of line conductors.

[0014] Advantageously, the lines of the different groups of lines are ordered following the physical order of the lines of pixels of the matrix, the device further comprising a module for generating a first token delivered to an input of a first of the control modules of the first group of control modules and a second token delivered to an input of a first of the control modules of the second group of control modules, in each of the groups of control modules, an output of each module being connected to an input of the higher-ranking module, the control modules being ordered in each of their groups in the order of the lines of pixels to the conductor of which the module in question delivers the selection signal.

[0015] Advantageously, the pixels and the control modules are produced on the same substrate from thin-film transistors of type N only or type P only.

[0016] The invention also relates to a method of using a matrix detector according to the invention, in which control modules belonging to two distinct groups and connected to two consecutive line conductors can receive simultaneous control signals so as to control the consecutive lines simultaneously or alternating control signals so as to control the consecutive lines separately.

[0017] The invention will be better understood and other advantages will appear on reading the detailed description of an embodiment given by way of example, a description illustrated by the attached drawing in which:

[0018] [Fig. 1] [Fig. 1] represents an example of a pixel matrix that can be implemented in a detector according to the invention;

[0019] [Fig.2] [Fig.2] represents an example of a detector according to the invention;

[0020] [Fig.3] [Fig.3] represents an example of the realization of several modules of control implemented in the detector of [Fig.2];

[0021] [Fig.4] [Fig.4] represents another example of the embodiment of several control modules implemented in the detector of [Fig.2];

[0022] [Fig.5] [Fig.5] represents a detailed example of a control module of [Fig.4];

[0023] [Fig.6] [Fig.6] represents in the form of a timing diagram, an example of operation of a detector implementing control modules such as represented in [Fig.5] and chained in a single group;

[0024] [Fig.7] [Fig.7] represents in the form of a chronogram, an example of func operation of a detector implementing control modules as shown in [Fig.5] and chained in two groups for individual reading of the detector pixels;

[0025] [Fig.8] [Fig.8] represents in the form of a timing diagram, an example of operation of a detector implementing control modules such as those represented in [Fig.5] and chained in two groups for a common reading of pixels of two consecutive lines.

[0026] For the sake of clarity, the same elements will bear the same references in the different figures.

[0027] The following description is given in relation to a matrix detector comprising several elementary electronic circuits called pixels, each comprising an element sensitive to a physical quantity. The elementary electronic circuits are, in the example described, pixels sensitive to light radiation. It is understood that the invention can be implemented for other detectors sensitive to any form of physical quantity, making it possible, for example, to produce a pressure or temperature map.

[0028] [Fig.l] schematically represents the detection zone 10 of a matrix detector. This zone comprises a matrix of two rows and two columns to simplify understanding. Four pixels P are formed, each at the intersection of a row and a column. It is understood that real matrices are generally much larger and have a large number of rows and columns. The pixel matrix belongs to a matrix detector 12 for producing digitized images.

[0029] Each pixel P comprises a photosensitive zone, represented here by a photodiode D, and an electronic processing circuit formed, in the example of [Fig.l], by a single transistor T. The references of the components D and T are followed by two coordinates specifying the rank of the row, respectively i and i+1, and that of the column respectively] and j+1. The rows and columns are ordered in the physical order that they occupy in the pixel matrix. The pixels represented are also called 1T type pixels because each one has a transistor whose function will be described later.

[0030] Generally speaking, it is known to produce pixel matrices comprising thin-film field effect transistors known in the English literature under the name TFT for: "Thin-film transistor". TFT type transistors can be based on metal oxides such as for example transistors based on amorphous or crystalline oxide of indium, gallium and zinc known by their English abbreviation: IGZO. Other families of TFT type transistors can be implemented such as for example organic TFTs, TFTs in amorphous silicon, polycrystalline silicon TFTs. In this last type of TFT transistor, some have been synthesized at low temperature. They are known by their Anglo-Saxon abbreviation: LTPS for "Low-temperature polycrystalline Silicon".

[0031] The pixels P of the same column are connected to a column conductor Col. This conductor allows the collection of information from the pixels connected to it. The pixels P of the same row are connected to a row conductor L carrying a signal VG allowing the corresponding row of pixels to be controlled.

[0032] During an image capture phase, occurring after a reset operation, the illumination received by the photodiode D causes the potential of its cathode to decrease. This image capture phase is followed by a reading phase during which the potential of the photodiode D is read. To do this, the transistor T is turned on, which therefore has the role of a switch controlled by the control signal VG applied to its gate.

[0033] The column conductor Col is used for collecting information from a pixel of the corresponding column when it is selected by means of the signal VG.

[0034] It is possible to implement the invention in a detector whose pixels are simpler, in particular by replacing the transistor T with a simple diode made to conduct by means of the signal VG. It is also possible to implement the invention in a detector whose pixels comprise several transistors. It is in particular known to implement 3T type pixels comprising, in addition to the reading transistor described above, a photodiode reset transistor and a follower transistor. In this type of 3T pixel, a second row conductor carries a reset signal making it possible to control the reset transistor.

[0035] [Fig. 2] schematically represents the detector 12 as a whole. The detector 12 comprises a slab 14 forming the substrate on which the components of the detection zone 10 are produced. On this same slab 14 are arranged control modules 16 delivering control signals to all the line conductors L. Alternatively, the control modules 16 can be produced on a substrate separate from the slab 14. However, producing the control modules 16 on the same substrate as the pixels P makes it possible to limit the connections connecting the slab 14 to its environment.

[0036] The detector 12 comprises reading circuits 18 connected to the column conductors Col. The reading circuits 18 are, for their part, generally produced on substrates separate from the slab 14. The reading circuits 18 are connected to the slab 14 by means of ribbon cables.

[0037] The detector 12 comprises a circuit 20 for controlling the control modules 16 and for recovering the signals from the reading circuits 18, in particular to multiplex them.

[0038] [Fig. 3] represents a first exemplary embodiment of four control modules 16, each configured to control a row of pixels. It is understood that the invention can be implemented for a larger number of rows of pixels. More precisely, the output Out_A(n) of the first control module, denoted SR_A(N), is connected to a row conductor L(i) carrying a signal VG for reading row i. The output Out_B(n) of the second control module, denoted SR_B(N) is connected to a row conductor L(i+1) carrying a signal VG for reading row i+1. The output Out_A(n+1) of the third control module, denoted SR_A(N+1) is connected to a row conductor L(i+2) carrying a signal VG for reading row i+2. The output Out_B(n+l) of the fourth control module, noted SR_B(N+1) is connected to a line conductor L(i+3) carrying a signal VG for reading line i+3.The lines and the driver modules are ordered in the order of [Fig.3]. More precisely, in an individual reading of each of the pixel lines, we read line i, then line i+1, then line i+2 and finally line i+3. As we will see later, the driver modules are configured to also allow reading by grouping the lines into successive pairs.

[0039] In the example shown, the control modules are divided into two groups, SR_A(N) and SR_A(N+1) in a first group A and SR_B(N) and SR_B(N+1) in a second group B. The invention can be implemented with a larger number of control module groups. The rows are also grouped into two groups: LA for rows L(i) and L(i+2) on the one hand and LB for rows L(i+1) and L(i+3) on the other hand. The control module group A is associated with the rows of the group LA and the control module group B is associated with the rows of the group LB. The row groups LA and LB and therefore the control module groups A and B are interleaved. More precisely, in each group, the control modules are ordered following the physical order of the rows of the matrix.For two groups of driver modules A and B, in the physical order of the rows of the matrix, the first driver module of the first group A: SR_A(1) drives the first row L(l) of the matrix. The first driver module of the second group B: SR_B(1) drives the second row L(2). The second driver module of the first group A: SR_A(2) drives the third row L(4). The second driver module of the second group B: SR_B(2) drives the fourth row L(l) and so on until the last row of the matrix. More generally, with K groups of driver modules, noting: . i: the rank of a current row in the physical order of the rows of the matrix, j: the rank of the module in its group k: the rank of the group between 1 and K Line i is driven by the module of rank j of the group of rank k with: i = (jl)K+k

[0040] Distributing the lines and the control modules into different groups associated with each other makes it possible to control the groups of lines differently, in particular by adapting the synchronization of the different groups of control modules and therefore by adapting the synchronization of the control of the groups of lines.

[0041] [Fig. 3] represents an embodiment allowing a particularly simple connection of the control modules. It is understood that other connections are possible. Each control module comprises an input, respectively, In_A(n), In_B(n), In_A(n+1), In_B(n+1) allowing to receive a command from the module in question. The detector 12 comprises a generation module 30 allowing to generate a first token IN_A delivered to the input of the first control module SR_A(N) of the group A. The generation module 30 also allows to generate a second token IN_B delivered to the input of the first control module SR_B(N) of the group B. The output Out_A(n) is connected to the input In_A(n+1) and the output Out_B(n) is connected to the input In_B(n+1) so as to circulate the token from one control module to the next in the same group. More generally, generation module 30 allows you to generate as many tokens as there are groups of control modules.Furthermore, the control modules receive one or more control signals N Controls A for group A and N Controls B for group B. These control signals are, for example, clocks at the rate at which the tokens pass from one module to another in the same group. The control signals can be generated by the generation module 30 which can be arranged on the slab 14 or on a substrate separate from the slab 14, for example in the circuit 20. The connections between the different control signal control modules and the connections of the outputs to the inputs between consecutive modules can be made on the slab 14 and therefore do not require external connections.

[0042] The detector 12 can operate in different ways, either by generating the VG signals of each row sequentially in the order of the rows of the matrix, which allows individual reading of the pixels of the detector 12, or simultaneously in two control modules of the same rank in the two groups. In other words, the VG signals are emitted simultaneously by the control modules SR_A(N) and SR_B(N) then by the control modules SR_A(N+1) and SR_B(N+1), which allows the grouping of the information from pixels of different rows. The choice between the two types of reading of the detector, either individual or by group of pixels, is made by varying the times of emission of the tokens IN_A and IN_B and possibly of the control signals of the control modules. A simultaneous emission of the two tokens allows reading by group. An alternating emission of the two tokens allows individual reading.

[0043] By dividing the control modules into two groups, it is possible to group the reading of two lines of pixels. More generally, K groups make it possible to group the reading of K lines. Grouping lines by sub-multiples of the number of groups is also possible. For example, with four groups of control modules, it is possible to read the matrix, either individually, or by group of two lines or by group of four lines depending on offsets in the emission of the tokens of the different groups and the corresponding control signals.

[0044] [Fig.4] represents another example of the embodiment of four control modules 16 each being configured to drive a line of pixels. In this example, the control module comprises an input stage E and an output stage S. The input stage E delivers an activation signal Outa or Outb from the corresponding output stage S. In the event of activation by the input stage, the corresponding output stage emits the output signal of the control module, here denoted Gateline. This two-stage example corresponds to the scheme described in the patent application WO 2012 / 152836 A1 mentioned above. The transmission of the token between two successive control modules of the same group is done by means of the activation signal transmitted to the input of the input stage of the higher-ranking module. The input stages of the different modules and their connection allowing the transmission of the token form a shift register. Each output stage forms an amplifier allowing the activation signal to be adapted to the characteristics of the signal VG.

[0045] [Fig.5] shows in more detail a diagram of one of the control modules of the [Fig.4]. The integrated structure forming a row addressing device according to the present invention may essentially comprise single-type TFT transistors, i.e. P-type or N-type, the N-type being preferred for its better performance. Thus, all the transistors described below may be thin-film (TFT) and single-type N or P.

[0046] The structure illustrated by [Fig. 5] corresponds to an advantageous embodiment in which each stage n of the row addressing device comprises an input stage 50 and an output stage 51. For a stage n of the row addressing device, each of the input and output stages 50, 51 comprises, for example, most of the elements included in a row addressing stage n as described previously with reference to [Fig. 3]. It should be noted that in the described embodiments, each row n of the matrix is ​​associated with a stage n of the addressing device. It is however possible, in alternative examples not described by the figures, to envisage structures of row addressing devices in which a given stage controls a plurality of rows, or in which certain rows are not controlled by a stage.

[0047] Thus, the input stage 50 of a stage n of the line addressing device can beformed by a shift register comprising an output line restoring as output an activation signal Out(n). The input stage 50 may comprise an output transistor of the input stage T30, transmitting a pulse of a clock signal at the activation output Out(n). The gate of the output transistor of the input stage T30 may be connected to an internal node of the input stage of the addressing device, its source may be connected to the activation output Out(n) and its drain may receive the signal of a first clock CLKL. A boost capacitor of the input stage C20 may be connected between the gate and the source of the output transistor of the input stage T30. A first control transistor of the input stage T10 is capable of precharging the gate of the output transistor of the input stage T30. The source of the first control transistor of the input stage T10 is thus connected to the gate of the output transistor of the input stage T30.The gate and drain of the first control transistor of the input stage T10 are controlled by the activation output Out(nl) of the stage n-1 of the addressing device of the previous line n-1.

[0048] A second control transistor of the input stage T20 is capable of discharging the gate of the output transistor of the input stage T30. The drain of the second control transistor of the input stage T20 is thus connected to the gate of the output transistor of the input stage T30. A compensation capacitor of the input stage CIO can advantageously be arranged between the signal of a second clock CLK2, in phase opposition to the signal of the first clock CLKL

[0049] Advantageously, a discharge transistor of the input stage T40 can be connected to the activation output Out(n) of the input stage 50 of the stage n of the row addressing device. The gate of the discharge transistor of the input stage T40 is connected to the gate of the second control transistor of the input stage T20; it is also connected to the activation output signal Out(n+1) of the following stage n+1.

[0050] In a similar manner, the output stage 51 of a stage n of the row addressing device may be formed by a shift register comprising an output line restoring at output a signal Sn. The output stage 51 may comprise an output transistor of the output stage T31, transmitting a pulse of a clock signal at the output Sn. The gate of the output transistor of the output stage T31 may be connected to an internal node of the output stage of the addressing device, its source may be connected to the output Sn and its drain may receive the signal of a third clock CLK3. A boost capacitor of the output stage C21 may be connected between the gate and the source of the output transistor of the output stage T31. A first control transistor of the output stage T11 is capable of precharging the gate of the output transistor of the output stage T31.The source of the first control transistor of the output stage T1 1 is thus connected to the gate of the output transistor of the output stage T31. The gate and the drain of the first control transistor of . the output stage Tl 1 are controlled by the activation output Out(n) of the input stage 50 of stage n of the addressing device.

[0051] A second control transistor of the output stage T21 is capable of discharging the gate of the output transistor of the output stage T31. The drain of the second control transistor of the output stage T21 is thus connected to the gate of the output transistor of the output stage T31. A compensation capacitor of the output stage C11 can advantageously be arranged between the signal of a fourth clock CLK4, in phase opposition to the signal of the third clock CLK3. A particularity of the third and fourth clocks CLK3, CLK4 is that their duty cycles can be different, and that the sum of their respective periods at their high level corresponds to the period of the first and second clocks CLK1, CLK2.

[0052] Advantageously, a discharge transistor of the output stage T41 can be connected to the output Sn of the output stage 51 of the stage n of the row addressing device, delivering the activation signal of the row n. The gate of the discharge transistor of the output stage T41 is connected to the gate of the second control transistor of the output stage T21; it is also connected to the activation output Out(n+1) of the following stage n+1.

[0053] According to another specific feature of the present invention, the input stage 50 also comprises a reset transistor of the input stage TR whose gate is controlled by a pulse of a reset signal. The source of the reset transistor of the input stage TR can be connected to the sources of the second control transistor of the input stage T20. The drain of the reset transistor of the input stage TR can be connected to the drain of the second control transistor of the input stage T20.

[0054] In the same way, the output stage 51 also comprises a reset transistor of the output stage TR whose gate is, as well as the gate of the reset transistor of the input stage, controlled by a pulse of the reset signal. The source of the reset transistor of the output stage TR can be connected to the sources respectively of the second control transistor of the output stage T21 and of the discharge transistor of the output stage T41, as well as to the sources respectively of the second control transistor of the input stage T20 and of the discharge transistor of the input stage T40. The drain of the reset transistor of the output stage TR can be connected to the drain of the second control transistor of the output stage T21.

[0055] Thus, a reset pulse makes it possible to impose on the various transistors included in the input 50 and output 51 stages, their blocked state.

[0056] In addition, the output stage 51 may comprise a line reset transistor TL. The line reset transistor TL is controlled via its gate by a specific signal. The drain of the line reset transistor TL is connected to the source of the output transistor of the output stage T31. The source of the line reset transistor TL can be connected to the sources of transistors T20, T40, T21 and T41. The line reset transistor TL of an n stage is used to force the voltage on the n line to the low state. The line reset transistor TL is used to control the voltage on the lines, i.e. at the outputs of the output stages of the stages, and to apply a low impedance voltage to them, in particular during "dead times". Indeed, typically, the driving of X-ray detectors, for example, includes a reset phase, followed by a phase of application of X-ray radiation or "X window", then a reading phase.During the X-ray window, X-rays transform into electrons in the photodiodes; the duration of the X-ray window is relatively long, typically up to 3.2 seconds, so the row reset transistor TL helps to avoid any matrix drift.

[0057] Advantageously, each output stage 51 may comprise a matrix reset switch, for example formed by a matrix reset transistor TLON making it possible to carry out a complete reset of the matrix. The matrix reset transistor TLON may be controlled by a matrix reset signal applied to its gate and to its drain. The source of the matrix reset transistor TLON may be connected to the source of the output transistor of the output stage T31. The matrix reset signal controlling the matrix reset transistor TLON may be the voltage VGoff or the activation voltage VGon. When the matrix reset transistor TLON is active, that is to say when the activation voltage VGon is applied, the activation voltage is then applied to the entire matrix.

[0058] In practice, a complete reset of the matrix can be carried out following the sequence defined by an activation of the matrix reset transistors TLON for a sufficient duration, followed by an activation of the row reset transistors TL allowing the rows to be reset to the voltage VGoff.

[0059] [Fig.6] illustrates in the form of a timing diagram the operation of the control modules of [Fig.5] arranged in a single group, as described in patent application WO 2012 / 152836 AL. A single token IN is emitted to the gate and the drain of the control transistor T10 of the input stage E of the first control module. The clocks CLK1 and CLK2 are in phase opposition, with an equal share of the high and low levels. The clocks CLK3 and CLK4 are also in phase opposition with a cycle duration half the cycle duration of the clocks CLK1 and CLK2. The duration of the high level of the clock CLK4 is longer than that of the clock CLK3.

[0060] In [Fig.6], the Out(n) signal for four lines is also shown consecutive. Each Out(n) signal is shifted by half a cycle of the CLK1 clock relative to the previous one. The Gateline(n) signal is also represented for the same four lines. There is a dead time TM between two high levels of two consecutive Gateline signals. This dead time corresponds to the duration of the high level of the CLK3 clock. A minimum duration of the high level of the CLK3 clock is necessary to ensure the charging of the gate of the transistor T31. By directly chaining the control modules in a single group, it is impossible to eliminate this dead time.

[0061] On the contrary, by distributing the control modules into several groups, for individual reading of the pixels, it is possible to mask the dead time between two consecutive modules of the same group by the high level of a Gateline signal of another group.

[0062] [Fig.7] illustrates in the form of a timing diagram, an example of operation of the detector 12 implementing control modules as shown in [Fig.5] and chained in two groups for individual reading of the detector pixels. For the first group A, we find the INA token and the four clocks CLK1A, CLK2A, CLK3A and CLK4A. The clocks CLK1A, CLK2A are in phase opposition. The clocks CLK3A and CLK4A are also in phase opposition with a cycle duration twice as low as the cycle duration of the clocks CLK1 and CLK2. Unlike the clocks described with [Fig.6], the four clocks CLK1A, CLK2A, CLK3A and CLK4A have an equal share of their respective high and low levels.

[0063] In [Fig.7], also shown for group B are the INB token and the four clocks CLK1B, CLK2B, CLK3B and CLK4B. Compared to group A, the signals in group B are shifted by a quarter of a CLK1A clock cycle.

[0064] For group A, two signals OutA(l) and OutA(2) and two signals Gateline(l) and Gateline(3) correspond to two consecutive control modules of group A. The Gateline(l) and Gateline(3) signals are used to control the rows of rank 1 and 3 of the matrix. Similarly for group B, two signals OutB(l) and OutB(2) and two signals Gateline(2) and Gateline(4) correspond to two consecutive control modules of group B. The Gateline(2) and Gateline(4) signals are used to control the rows of rank 2 and 4 of the matrix. In other words, the control modules of group A generate the Gateline signals of the odd rows and the control modules of group B generate the Gateline signals of the even rows of the matrix.

[0065] The interleaving of the two groups makes it possible to extend the duration of the high level of the CLK3A clock. It is thus possible to ensure the charging of the gate of the transistor T31 without dead time between two consecutive lines. Indeed, during the charging of the gate of the transistor T31 of a control module of group A, the high level of a Gateline signal of group B occurs.

[0066] [Fig.8] illustrates in the form of a timing diagram, another example of operation of the detector 12 implementing the control modules of [Fig.5], still chained in two groups and this time for a grouped reading of pixels of consecutive lines. In other words, a consecutive even line and an odd line are read simultaneously. In the operation described with the aid of [Fig.8], the token INA is emitted simultaneously with the token INB. Similarly, the clocks CLK1A, CLK2A, CLK3A and CLK4A are emitted simultaneously with the corresponding clocks CLK1B, CLK2B, CLK3B and CLK4B. It follows that the signals OutA(l) and OutA(2), OutA(3) and OutA(4) Gateline(l) and Gateline(2), Gateline(3) and Gateline(4) are simultaneous.

[0067] The operation of [Fig.8] is similar to the operation of [Fig.6] with a dead time TM between the Gateline(2) and Gateline(3) signals. To limit the duration of this dead time, the duration of the high level of the clocks CLK3A and CLK3B is less than the duration of the low level of these same clocks.

[0068] The detector 12, equipped with several groups of control modules linked together, makes it possible to choose different operating modes depending on the need, in particular an individual reading of the pixels of the matrix by giving the possibility of eliminating any dead time between two readings of two consecutive lines of the matrix. The detector 12 also makes it possible to group the signals from several pixels to read them collectively.

[0069] The two operating examples are given for reading the pixel matrix P. In the diagram of [Fig.l], the row conductors L are used to drive the opening of a transistor T (i,j). This transistor is used both for reading and for resetting each pixel P (i,j). It is possible to drive the pixels in the same way or differently for reading and for resetting, for example, individual reading of collective resetting.

Claims

Claims

1. Matrix detector comprising: - a set (10) of pixels (P) sensitive to a physical phenomenon and organized in a matrix according to rows and columns of pixels, each pixel (P) generating a signal depending on the physical phenomenon, the rows of the different groups of rows (LA, LB) are ordered following the physical order of the rows of pixels of the matrix, - row conductors (L) each making it possible to drive the pixels (P) of a row, the row conductors (L) being distributed into at least two groups of interlaced row conductors (LA, LB), - a first group (A) of control modules (SR_A) delivering selection signals (Out_A; Gateline), each to one of the row conductors (L) of a first of the groups (LA) of row conductors, - a second group (B) of control modules (SR_B) delivering selection signals (Out_B;Gateline), each to one of the line conductors (L) of a second of the groups (LB) of line conductors, in each of the groups of control modules, an output (Out_A(n), Out_B(n)) of each module being connected to an input (In_A(n+l), In_B(n+l)) of the higher-ranking module, the control modules being ordered in each of their group (A, B) in the order of the lines of pixels to the conductor of which the control module in question delivers the selection signal.;

2. Matrix detector according to claim 1, wherein the device further comprises a generation module (30) of a first token (INA) delivered to an input (In_A(N)) of a first of the control modules (SR_A(N)) of the first group (A) of control modules and of a second token (INB) delivered to an input (In_B(N)) of a first of the control modules (SR_B(N)) of the second group (B) of control modules.

3. Matrix detector according to one of the preceding claims, in which the pixels (P) and the control modules (SR_A, SR_B) are produced on the same substrate (14) from thin-film transistors of N type only or of P type only.

4. Method of using a matrix detector according to one of the preceding claims, in which control modules (16) belonging to two distinct groups (A, B) and connected to two consecutive line conductors (L) can receive signals from simultaneous commands so as to drive consecutive lines simultaneously or alternating control signals so as to drive consecutive lines separately.

Images