Electrical contact re-establishment method

Abstract

A method for re-establishing electrical contact, comprising the steps: a) providing electronic chips (P), surmounted by electrical contact pads (1), and formed on a substrate (2); the pads (1) and the substrate (2) being coated with a passivation layer (3); b) forming a stack on the passivation layer (3), comprising: - a first flattening layer (4), made of a first material allowing selective chemical etching with respect to the passivation layer (3), and formed on the passivation layer (3) so as to be flush with the top of the pads (1); - a second flattening layer (5), made of a second material; - an interlayer layer (CI), made of a material allowing selective chemical etching of the second material; c) polishing the stack, by mechano-chemical polishing, until reaching the passivation layer (3) coating the pads (1);d) etch the passivation layer (3) coating the studs (1) so as to expose the top of the studs (1). Figure 1;

Description

Description Title of the invention: Method for re-establishing electrical contact technical field

[0001] = The invention relates to the technical field of manufacturing electronic chips electronic devices requiring re-establishment of contact on electrical contact pads.

[0002] — The invention finds particular application in the manufacture of electronic chips resistive memory chip type tronics (RRAM for "Resistive Random-Access") Memory (in English), particularly of the gap-based random access type oxygen (OxRAM for "Oxide-based Random-Access Memory" in English) English). State of the art

[0003] As illustrated in Figures 6a to 6c, a known method for re-establishing electrical contact The state of the art includes the following steps: ag) provide electronic chips P, surmounted by electrical contact pads 1, and formed on a substrate 2; the electrical contact pads 1 and the substrate 2 being coated of a passivation layer 3; bo) form a planation layer 4 on the passivation layer; the layer flattening step 4 being carried out in a material allowing chemical etching selective with respect to the passivation layer 3; Co) polish the flattening layer 4, by mechano-chemical polishing, until reach the passivation layer 3 coating the electrical contact pads 1; the chemical-mechanical polishing using selective chemical etching between the material of the planation layer 4 and the passivation layer 3; do) etch the passivation layer 3 coating the electrical contact pads 1 of in order to expose the top of the electrical contact pads 1.

[0004] — Such a prior art method is not entirely satisfactory in the to the extent that the mechano-chemical polishing of the flattening layer, carried out during (step cp), is inhomogeneous (non-uniform) depending on the position and density of the chips Electronics on the substrate. Mechano-chemical polishing of the layer The flattening process also varies depending on the wear and tear of consumables such as that the polishing solution (also called "s / urry" in English) polishing paste), or polishing pads (in English, (also known as polishing cloths).

[0005] — On the one hand, the planing layer is susceptible to being over-engraved - in the sense of a over-polishing – in the center of the substrate (as illustrated in [fig.7]), which can cause short circuits, while the leveling layer is likely to be insufficient fissionally polished at the substrate edge (as illustrated in [fig.8]), which can oc- to compartmentalize open circuits. On the other hand, the flattening layer is likely to be over-etched - in the sense of over-polishing - in regions of the substrate with low density of electronic chips (a phenomenon known as "dishing" in English), which can cause short circuits. Description of the invention The invention aims to remedy, in whole or in part, the aforementioned drawbacks. To this end, the invention relates to a method for re-establishing electrical contact, comprising the following steps: a) provide electronic chips, surmounted by electrical contact pads, and formed on a substrate; the electrical contact pads and the substrate being coated with a passivation layer; b) form a stack of planation layers on the passivation layer, the stack comprising: - a first flattening layer, made of a first material allowing selective chemical etching with respect to the passivation layer, and formed on the passivation layer so as to be flush with the top of the electrical contact pads; - a second leveling layer, made of a second material; - an intermediate layer, inserted between the first and second flattening layers, and made of a material allowing selective chemical etching of the second material: c) polish the stack, by mechano-chemical polishing, until the passivation layer coating the electrical contact pads is reached; the mechano-chemical polishing using selective chemical etching between the second material and the material of the interlayer layer: d) etch the passivation layer coating the electrical contact pads so as to expose the top of the electrical contact pads. Definitl - By "electronic chip" ("die" or "chip" in English), we mean a part of a substrate that has undergone technological steps in order to form an electronic component (intended to be mounted on an electronic board or in a case). - By "substrate", we mean a self-supporting physical support, which could be, for example, a wafer cut from a single-crystal ingot of semiconductor material. - By "passivation layer", we mean a layer adapted for neutralization electrically active defects on the surface of the substrate. Indeed, the surface of a substrate (e.g., crystalline silicon) exhibits a density of defects such as dangling bonds, impurities, crystal discontinuities, etc. - By "planarization layer" we mean a layer intended to modify the surface topology of the substrate, in order to create a flat surface for the substrate (after polishing). - By "allowing selective chemical etching," we mean that the second material can be chemically etched without attacking the interlayer. In practice, an etching agent is chosen so that the etching rate of the second material is at least 5 times (preferably 10 times) greater than the etching rate of the interlayer. - By "flush with the top of the electrical contact pads," we mean that the surface of the first leveling layer extending between two adjacent contact pads (Le, outside the step height) and the top surface of the electrical contact pads (i.e., the top) are coplanar. In other words, the surface of the first leveling layer extending between two adjacent contact pads is located at the same position (along the normal to the substrate surface) as that of the top surface of the electrical contact pads. Put another way, the surface of the first leveling layer extending between two adjacent contact pads is at the same elevation (height) as that of the top surface of the electrical contact pads. - By "chemical mechanical polishing" (CMP), we mean a polishing process using: (1) a polishing pad, brought into contact with the free (i.e. uncovered) surface of the stack, the polishing pad and the free surface of the stack being classically mobile in rotation around parallel axes of rotation (mechanical interaction); (ii) a polishing solution, classically abrasive and corrosive, impregnating the polishing pad (chemical interaction). - By "layer", we mean a single layer or a plurality of sub-layers of the same nature. Thus, such a process according to the invention makes it possible to considerably limit the consequences of the non-uniformity of a mechano-chemical polishing thanks to the stacking formed during step b), and more specifically thanks to the intercalary layer. The interlayer comprises a first part facing the electrical contact pads along the normal to the substrate, and a second part extending between the electrical contact pads, outside the step height formed by the chips. electronic components are surmounted by the electrical contact pads. The second part of the interlayer acts as a polishing stop layer, and its positioning (just above the plane formed by the electrical contact pads) significantly reduces over-polishing in the center of the substrate and in areas of the substrate with low chip density. The first part of the interlayer is not used as a polishing stop layer and simply introduces a delay in the polishing of the so-called high areas (i.e., the areas where the electrical contact pads are located). The method according to the invention may include one or more of the following characteristics. According to one feature of the invention, the mechano-chemical polishing is carried out during step c) using selective chemical etching between the first material and the passivation layer. The first material can be chemically etched without attacking the passivation layer. In practice, an etching agent is chosen so that the etching rate of the first material is at least S times greater (preferably at least 10 times greater) than the etching rate of the passivation layer. According to one feature of the invention, the mechano-chemical polishing is carried out during step c) with a single, selective chemical etching agent: - between the second material and the material of the interlayer layer, and - between the first material and the passivation layer. Thus, one advantage provided is the ability to execute step c) continuously, thereby limiting the operation time. According to one feature of the invention, the intermediate layer of the stack formed during step b) comprises a first part facing the electrical contact pads along the normal to the substrate; and step c) comprises the following successive steps: €,) polish the second flattening layer, by mechano-chemical polishing, until reaching the first part of the intercalated layer; €») engrave the first part of the intercalated layer; €3) polish the first flattening layer, by mechano-chemical polishing, until reaching the passivation layer coating the electrical contact pads. Defined By "facing [...] along the normal to the substrate", we mean that the first part of the interlayer is opposite the contact pads, along the normal to the surface of the substrate on which the electronic chips are formed. Thus, one advantage is to limit the operating time (reduce the polishing delay in high areas) when the selectivity between the second material and the the interlayer material is very strong (for example, a ratio between the etching speed of the second material and the etching speed of the interlayer material greater than 20). According to one feature of the invention, the mechano-chemical polishing is carried out in step c,) with a first chemical etching agent, selective between the second material and the material of the intercalated layer; the mechano-chemical polishing is carried out in step c;) with a second chemical etching agent, selective between the first material and the passivation layer, the second chemical etching agent being able to be identical to the first chemical etching agent. A single chemical etching agent will be preferred in order to reduce the operating time of step c). According to one feature of the invention, the first flattening layer remaining after step c) forms an etching mask around the electrical contact pads; and step d) is carried out by selective chemical etching. Thus, one advantage provided is to limit the operating time of step d); the first material extending around the electrical contact pads forms a hard mask. According to one feature of the invention, step b) is carried out so that the first and second materials are identical, and preferably being a silicon oxide. Thus, one advantage provided is to limit the operating time of step b). According to one feature of the invention, step b) is carried out so that the material of the interlayer is silicon nitride or carbon. Thus, an advantage provided by silicon nitride (e.g. SiN, Si,N4) or carbon is to allow selective etching of silicon oxide (e.g. SiO). According to one feature of the invention, step a) is carried out so that the passivation layer is made in a silicon nitride. Thus, one advantage provided by this material (devoid of oxygen atoms) is that it is particularly suitable when the electronic chips are resistive random access memory chips based on oxygen vacancies. According to one feature of the invention, step a) is performed such that: - each electronic chip, topped with an electrical contact pad, has a total thickness, denoted €; - the passivation layer has a thickness, denoted ep, less than or equal to ey / 2. Definitive - By "thickness", we mean the dimension along the normal to the surface of the substrate. - By "total thickness," we mean the thickness of the entire assembly including the chip electronics and its associated electrical contact pad. According to one feature of the invention, step b) is carried out so that the first leveling layer has a thickness, denoted e, satisfying: €, = Ep- Ep Thus, one advantage provided is the ability to form the first leveling layer so as to be flush with the top of the electrical contact pads. According to one feature of the invention, step b) is carried out so that the second leveling layer has a thickness, denoted e,, less than or equal to 1.5 e,. Thus, one advantage provided is to limit the operating time of step c). According to one feature of the invention, the interlayer formed during step b) has a thickness, denoted e, which is predetermined according to the selectivity of the chemical etching between the second material and the material of the interlayer, said chemical etching being used by the mechano-chemical polishing carried out during step c), e; being preferably between 5 nm and 15 nm. Definitive By "predetermined according to selectivity", we mean that the thickness of the intercalary layer is chosen before step b) according to the (known) ratio between the etching speed of the second material and the etching speed of the intercalary layer material. A higher thickness (e.g. 15 nm) will be chosen for the intercalated layer when said ratio is low (e.g. around 5), while a lower thickness (e.g. 5 nm) will be chosen for the intercalated layer when said ratio is high (e.g. greater than 10). According to one feature of the invention, the electronic chips provided for in step a) are resistive memory chips, preferably of the oxygen-vacancy-based random-access type. According to one feature of the invention, the electronic chips provided for in step a) each comprise a stack comprising successively: a first electrode, an active layer, and a second electrode; the active layer being preferably a metal oxide. Brief description of the drawings Other features and advantages will become apparent in the detailed description of different embodiments of the invention, the description being accompanied by examples and references to the accompanying drawings. [fig.1 ][fig.1] is a schematic cross-sectional view illustrating step b) of a process according to the invention. [fig.2][fig.2] is a schematic cross-sectional view illustrating the outcome of step c) of a process according to the invention for regions of the substrate with a high density of electronic chips. [fig.3][fig.3] is a schematic cross-sectional view illustrating the outcome of step c) of a process according to the invention for regions of the substrate with low electronic chip density. [fig.4] Figures 4a to 4f are schematic cross-sectional views illustrating steps of a process according to the invention. [fig.5][fig.5] is a schematic cross-sectional view illustrating step b) of a method according to the invention for a resistive memory type electronic chip. [fig.6] Figures 6a to 6c are schematic cross-sectional views illustrating steps of a process according to the prior art. [fig.7][fig.7] is a schematic cross-sectional view illustrating an over-engraved planar layer following a process according to the prior art. [fig.8][fig.8] is a schematic cross-sectional view illustrating an under-engraved planation layer as a result of a process according to the prior art. It should be noted that the drawings described above are schematic and not to scale for the sake of readability and to simplify understanding. The cross-sections are made along the normal to the substrate surface. The dashed lines illustrate the outcrop of the first leveling layer with the tops of the electrical contact pads. Detailed description of the implementation methods Identical elements or elements performing the same function will bear the same references for the different embodiments, for the sake of simplification. One object of the invention is a method for re-establishing electrical contact, comprising the following steps: a) provide electronic chips P, surmounted by electrical contact pads 1, and formed on a substrate 2; the electrical contact pads 1 and the substrate 2 being coated with a passivation layer 3; b) form a stack of planation layers 4, 5 on the passivation layer 3, the stack comprising: - a first flattening layer 4, made in a first material allowing a chemical etching selective with respect to the passivation layer 3, and formed on the passivation layer 3 so as to be flush with the top of the electrical contact pads 1; - a second leveling layer 5, made of a second material; - an intercalated layer CI, sandwiched between the first and second flattening layers 4, 5, and made of a material that allows chemical etching selective of the second material: c) polish the stack, by mechano-chemical polishing, until reaching the passivation layer 3 coating the electrical contact pads 1; the mechano-chemical polishing using selective chemical etching between the second material and the material of the intercalated layer CI; d) etch the passivation layer 3 coating the electrical contact pads 1 so as to expose the top of the electrical contact pads 1. The process is illustrated at the end of step b) in Figures 1, 4a and 5. The process is illustrated at the end of step c) in Figures 2, 3 and 4d. The process is illustrated at the end of step d) in [Fig. 4]e. Substrate Substrate 2 can be a wafer made of a semiconductor material, preferably silicon. Substrate 2 can be of the silicon-on-insulator (SOI) type. Substrate 2 can integrate components (e.g., transistors) in a monolithic manner, components that have been previously manufactured by a front-end-of-line (FEOL) fabrication unit. Chips el 4 Step a) is executed such that each electronic chip P, topped with an electrical contact pad 1, has a total thickness, denoted e. The total thickness e₀ is taken from the surface of the substrate 2 and does not take into account any buried elements. By way of non-limiting example, the electrical contact pads 1 may have a thickness between 120 nm and 150 nm, and each electronic chip P may have a thickness between 3 nm and 10 nm, so that e may be between 123 nm and 160 nm. The electronic chips P envisaged in step a) can be resistive memory chips, preferably of the oxygen-vacancy-based random-access type, i.e., OxRAM (Oxide-based Random-Access Memory). Other architectures are conceivable, such as resistive memory chips of the following types: - with conductive bridge (CBRAM for "Conductive Bridge Random-Access Memory" in English), - phase change (PCRAM for "Phase-Changed Random-Access Memory" in English). As illustrated in [Fig. 5], the electronic P chips planned in step a) can each comprise a stack consisting successively of: a first BE electrode, an active CA layer, and a second TE electrode. When the electronic P chips are OxRAM-type resistive memory chips, the active layer CA is a metallic oxide. Passivation layer Step a) is advantageously carried out so that the passivation layer 3 is made of silicon nitride. The silicon nitride can be SiN, or its non-staichiometric derivatives such as SiN. Step a) is advantageously carried out so that the passivation layer 3 has a thickness, denoted ep, less than or equal to e, / 2. Step a) is advantageously carried out so that the passivation layer 3 has a thickness greater than or equal to 10 nm. Step b) of formation of the stack of planation layers Step b) is advantageously carried out so that the first and second materials are identical. The first and second materials are preferably silicon oxides. The silicon oxide is preferably silicon dioxide (SiO₂); or a non-staichiometric derivative of SiO₂. Step b) is advantageously carried out so that the first leveling layer 4 has a thickness, denoted e, satisfying: €; = Ep- Cp The equality of the above equation is understood within the usual tolerances related to the experimental conditions of formation of the first planation layer 4, and not perfectly in the mathematical sense of the term. Step b) is advantageously carried out so that the second flattening layer 5 has a thickness, denoted e, less than or equal to 1.5 ey. Step b) is advantageously carried out so that the second flattening layer 5 has a thickness, denoted e, greater than or equal to 20 nm. Step b) is executed using deposition techniques that allow for following the surface topology of the passivation layer 3, which coats the electrical contact pads 1 and the substrate 2, and thereby for following the surface topology of the electrical contact pads 1. More specifically, the deposition techniques are adapted to exhibit a conformity ratio (ratio between the thickness of the deposited layer's flanks and its surface thickness) that allows for following the surface topology of the passivation layer 3. For example, the conformity ratio of the deposits can be between 50% and 100%, preferably between 75% and 100%. The first and second flattening layers 4, 5 can be deposited by chemical vapor deposition. E - î lai Step b) is advantageously carried out so that the material of the intercalated layer CI is a silicon nitride or carbon. The silicon nitride may be SisN, or its non-staichiometric derivatives such as SiN. The interlayer CI of the stack formed in step b) comprises a first portion 60 facing the electrical contact pads 1 along the normal to the substrate 2. Since step b) is performed using deposition techniques that allow following the surface topology of the electrical contact pads 1, the first portion 60 of the interlayer faces the top of the electrical contact pads 1 along the normal to the substrate 2. The first portion 60 of the interlayer CI forms the top of the interlayer CI. The interlayer CI of the stack formed in step b) comprises a second portion 61 extending between the electrical contact pads 1, i.e., outside the step height formed by the electronic chips P surmounted by the electrical contact pads 1. The second portion 61 of the interlayer CI acts as a polishing stop layer. The interlayer CI formed during step b) has a thickness, denoted e, which is advantageously predetermined according to the selectivity of the chemical etching between the second material and the material of the interlayer CI, said chemical etching being used by the mechano-chemical polishing carried out during step c). The thickness e; is preferably between 5 nm and 15 nm. The intercalated layer CI can be deposited on the first planing layer 4 by chemical vapor deposition. Step c) polishing Mechano-chemical polishing is advantageously carried out during step c) using selective chemical etching between the first material and the passivation layer 3. The mechano-chemical polishing is advantageously carried out in step c) with a single, selective chemical etching agent: - between the second material and the material of the interlayer CI, and - between the first material and the passivation layer 3. As an example, a CeO-based polishing solution (i.e., of the Ceria type) can be used as an etching agent when the first and second materials are a silicon oxide and when the interlayer material CI is a silicon nitride. According to the implementation method illustrated in figures 4a to 4d, step c) comprises the following successive steps: €) polish the second flattening layer 5, by mechano-chemical polishing, until reaching the first part 60 of the intercalated layer CI; C2) engrave the first part 60 of the intercalated layer CI; €3) polish the first flattening layer 4, by mechano-chemical polishing, until reaching the passivation layer 3 coating the electrical contact pads 1. The mechano-chemical polishing is carried out in step c ;) with a first agent Chemical etching, selective between the second material and the material of the interlayer CI. Mechano-chemical polishing is performed in step cz) with a second chemical etching agent, selective between the first material and the passivation layer 3. The second chemical etching agent is advantageously identical to the first chemical etching agent, for example, when the first and second materials are identical. Step cz) consists of etching the first part 60 of the interlayer CI, i.e., only the top of the interlayer CI. Step c») can be performed by selective or non-selective etching. As an example, step cz) can be performed by oxygen plasma when the interlayer CI is made of carbon. As illustrated in [fig.2], at the end of step c), a residual portion of the second planarization layer 5 remains on the intercalated layer CI for regions of the substrate 2 with high density of electronic chips P. As illustrated in [Fig. 3], at the end of step c), the entire second flattening layer 5 is consumed on the interlayer CI for regions of the substrate 2 with low density of electronic chips P. The second part 61 of the interlayer CI has effectively acted as a polishing stop layer. Step d) of engraving As illustrated in Figures 2, 3, and 4d, the first flattening layer 4 remaining after step c) forms an etching mask M around the electrical contact pads 1; and step d) is advantageously performed by selective chemical etching. For example, an inductively coupled plasma (ICP) etching chamber can be used, the plasma being CH,F,-based. As illustrated in [fig.4] e, at the end of step d), the top of the electrical contact pads 1 is exposed so that re-establishment of contact is possible, for example by depositing a layer of metallization 7 (illustrated in [fig.4] f) extending over the tops of the exposed electrical contact pads 1. The invention is not limited to the embodiments described. A person skilled in the art is able to consider their technically operative combinations and to substitute equivalents for them.

Claims

Demands

1. A method for resuming electrical contact, comprising the following steps: a) provide electronic chips (P), surmounted by pads (1) of electrical contact, and formed on a substrate (2); the contact pads (1) electrical and the substrate (2) being coated with a passivation layer (3); b) form a stack of planation layers (4, 5) on the passivation layer (3), the stack comprising: - a first leveling layer (4), carried out in a first material allowing for selective chemical etching with respect to the passivation layer (3), and formed on the passivation layer (3) of in such a way as to be flush with the top of the electrical contact pads (1); - a second levelling layer (5), carried out in a second material ; - an intercalated layer (IL), inserted between the first and second leveling layers (4, 5), and made of a material allowing a selective chemical etching of the second material; c) polish the stack, by mechano-chemical polishing, until reach the passivation layer (3) coating the contact pads (1) electric; mechano-chemical polishing using etching chemical selective between the second material and the material of the intercalated layer (CTI); d) etch the passivation layer (3) coating the contact pads (1) electrical so as to expose the top of the contact pads (1) electric.

2. Method according to claim |, wherein the mechanical polishing- chemical etching is performed in step c) using chemical etching selective between the first material and the passivation layer (3).

3. Method according to claim 2, wherein the mechanical polishing chemical etching is performed in step c) with a single etching agent chemical, selective: - between the second material and the material of the interlayer (CI), and - between the first material and the passivation layer (3).

4. A method according to any one of claims 1 to 3, wherein the in- layer tercalar (CT) of the stack formed during step b) includes a first part (60) facing the electrical contact pads (1) along the normal to the substrate (2); and step c) comprises the following steps Cessives: C) polish the second flattening layer (5) by polishing mechano-chemical, until reaching the first part (60) of the layer intercalary (CT); C») engrave the first part (60) of the intercalated layer (CI); C3) polish the first flattening layer (4), by polishing mechano-chemical, until reaching the passivation layer (3) covering the electrical contact pads (1).

5. A method according to claim 4, wherein the mechanical polishing chemical is carried out during step c,) with a first agent of chemical etching, selective between the second material and the material of the intercalated layer (CI); the mechano-chemical polishing is performed during step c3) with a second, selective chemical etching agent between the first material and the passivation layer (3), the second chemical etching agent that may be identical to the first agent Chemical etching.

6. A method according to any one of claims 1 to 5, wherein the first planation layer (4) remaining at the end of step c) forms a etching mask (M) around the electrical contact pads (1); and Step d) is performed by selective chemical etching.

7. A method according to any one of claims 1 to 6, wherein step b) is executed so that the first and second materials are identical, and preferably being a silicon oxide.

8. A method according to any one of claims 1 to 6, wherein step b) is executed so that the material of the interlayer (IL) is a silicon nitride or carbon.

9. A method according to any one of claims 1 to 8, wherein step a) is executed so that the passivation layer (3) is realized in a silicon nitride.

10. A method according to any one of claims 1 to 9, wherein step a) is executed in such a way that: - each electronic chip (P), surmounted by a contact pad (1) electric, has a total thickness, noted €; - the passivation layer (3) has a thickness, denoted ep, less or equal to ey / 2.

11. A method according to claim 10, wherein step b) is carried out so that the first leveling layer (4) has a thickness, denoted e, satisfying: €; = Ep - Ep.

12. A method according to claim 10 or 11, wherein step b) is executed so that the second levelling layer (5) presents a thickness, denoted e, less than or equal to 1.5 €.

13. A method according to any one of claims 1 to 12, wherein the in- layer tercalary (CI) formed during step b) has a thickness, denoted e, which is predetermined according to the selectivity of the chemical etching between the second material and the interlayer (IL) material, said Chemical etching is used by mechano-chemical polishing executed during step c), e, preferably being between 5 nm and 15nm.

14. A method according to any one of claims 1 to 13, wherein the chips (P) The electronic components planned in step a) are memory chips resistive, preferably of the gap-based random access type of oxygen.

15. A method according to any one of claims 1 to 14, wherein the chips (P) electronic devices planned during step a) each include an em- a pile comprising successively: a first electrode (BE), a active layer (CA), and a second electrode (TE); the active layer (CA) being preferably a metallic oxide.