IMPLEMENTATIONS AND PROCESSES FOR PROCESSING NEURAL NETWORKS IN SEMICONDUCTIVE HARDWARE

Abstract

Aspects of the present invention relate to artificial intelligence systems, methods, computer instructions, and processing elements (AIPEs) involving a shifter circuit or equivalent computer circuitry / hardware / instructions configured to admit a shiftable input derived from input data for a neural network operation; to admit a shift instruction derived from a corresponding logarithmically quantized parameter of a neural network or a constant value; and to shift the shiftable input in a left-hand or right-hand direction according to the shift instruction to form a shifted output representing a multiplication of the input data by the corresponding logarithmically quantized parameter of the neural network. Fig. 1

Description

Description Title of the invention: IMPLEMENTATIONS AND METHODS FOR PROCESSING NEURAL NETWORK IN HARDWARE SEMICONDUCTOR BACKGROUND REFERENCE TO RELATED REQUEST(S)

[0001] — This application claims the benefit and priority of the US Provisional Application, Serial Number 63 / 184,576, entitled “Systems and Methods Involving Artificial In- intelligence and Cloud Technology for Edge and Server SOC" (from English: "Systems and Processes involving artificial intelligence and cloud technology for Edge and Server SOC”) and filed on May 5, 2021, and US Provisional Application, No. Series 63 / 184,630, entitled “Systems and Methods Involving Artificial Intelligence and Cloud Technology for Edge and Server SOC” and filed on May 5, 2021, the di- disclosures of which being expressly incorporated by reference herein in their in- wholeness. Technical field

[0002] — The present invention is generally directed to systems artificial intelligence, and more specifically, neural network processing and artificial intelligence (AI) in hardware and software. Prior art

[0003] = A neural network is a network or circuit of artificial neurons that is represented by multiple neural network layers, each of which is instantiated by a set of parameters. Neural network layers are represented by two types of neural network parameters. One type of neural network parameter is the weights that are multiplied by the data depending on the network operation underlying neural network (e.g. for convolution, batch normalization, etc.). The other type of neural network parameter is bias, which is a value that can be added to the data or to the result of multiplying the weight with the data.

[0004] — Neural network layers of a neural network start with the layer input where the data is introduced, then hidden layers, then the layer of output. The layers are composed of artificial neurons, also called nuclei or filters in the case of the convolution layer. Examples of different types of layers that make up a neural network may involve, but are not limited to, the convolutional layer, a fully connected layer, a recurrent layer, a activation layer, a batch normalization layer, etc.

[0005] … Training or learning a neural network is a process that modifies and refines the parameter values in the neural network based on a set of objectives which is usually described in the label for the input data and the input data set known as test data. Training, learning, or optimizing a neural network involves optimizing the parameter values in the neural network for a given set of objectives by either mathematical methods such as gradient-based optimization or non-mathematical methods. In each iteration (called an epoch) training / learning / optimization, the optimizer (e.g., a software program, dedicated hardware, or a combination thereof) finds the optimized values of the parameters to produce the least errors based on the defined objective or labels. For neural network inference, once a neural network is trained, learned, or optimized, with test data and a label, one can apply / feed any arbitrary data to the trained neural network to derive the output values, and then interpret the output values based on the rules that are defined for the neural network. The following are examples of neural network training, neural network inference, and corresponding hardware implementations in the related art. [Fig. 1] illustrates an example of neural network training in accordance with the related art. To facilitate training of the neural network in the related art, first, the parameters of the neural network are initialized to random floating point numbers or integers. Then, the iterative process for training the neural network is initiated as follows. Test data is fed into the neural network to be forward propagated through all layers to derive output values. This test data may be in the form of floating point numbers or integers. The error is calculated by comparing the output values to the values of the test label. A method known in the art is then executed to determine how to modify the parameters to decrease the error of the neural network, after which the parameters are modified according to the executed method.This iterative process is repeated until the neural network produces the acceptable error (e.g., within a threshold), and the resulting neural network is said to be trained, learned, or optimized. [Fig.2] illustrates an example of a neural network inference operation, in accordance with the related art. To facilitate neural network inference, first, the inference data is fed into the neural network, which is forward propagated through all layers to derive output values. Then, the output values of the neural network are interpreted according to the objectives set by the neural network. [Fig.3] illustrates an example of neural network hardware implementations, in accordance with the related art. To implement the neural network in hardware, first, input data and parameters of the neural network are obtained. Then, using a hardware multiplier, the input data (multiplicand) are multiplied by the parameters (multiplier) to derive products. Subsequently, the products are all added together through the use of a hardware adder to obtain a sum. Finally, if necessary, the hardware adder is used to add a bias parameter to the sum as required. [Fig. 4] illustrates an example of training for a quantized neural network, in accordance with the related art. To facilitate training of the quantized neural network, first, the parameters of the neural network (e.g., weights, biases) are initialized to random floating point or integer numbers for the neural network. Then, an iterative process is performed, in which the test data is fed into the neural network and propagated forward through all layers of the neural network to derive the output values. The error is calculated by comparing the output values to the values of the test label. Methods as known in the art are used to determine how to change the parameters to reduce the error of the neural network and changed accordingly. This iterative process is repeated until the neural network produces an acceptable error within a desired threshold.Once produced, the parameters are then quantized to reduce their size (e.g. quantizing 32-bit floating point numbers to 8-bit integers). [Fig. 5] illustrates an example of neural network inference for a quantized neural network, in accordance with the related art. The inference process is the same as that for a usual neural network of [Fig. 2], except that the parameters of the neural network are quantized to integers. [Fig. 6] illustrates an example of a neural network hardware implementation for a quantized neural network in accordance with the related art. The hardware implementation is the same as that of a conventional neural network as illustrated in [Fig. 3]. In this case, the hardware multipliers and adders used for the quantized neural network are typically in the form of integer multipliers and integer adders as opposed to the floating point adders / multipliers of [Fig. 3] due to the integer quantization of the parameters. To facilitate the computations required for the operation of the neural network, Multiplier-Accumulator Circuits (MACs) or MAC-equivalent circuits (multiplier and adder) are typically used to perform the multiplication operation and the addition operation for the neural network operations. All MT processing hardware in the related art fundamentally relies on MACs or equivalent circuits. to MACs to perform calculations for most neural network operations. Technical problem Due to the complexity of the multiplication operation, MACs consume a significant amount of power and generate a fairly significant footprint when used in arrays (hereinafter referred to as grids) to process neural network and other artificial intelligence operations, as well as significant computational time. Since the amount of input data and neural network parameters can be large, large grids (e.g., tens of thousands) of MACs can be used to process neural network operations. Such requirements can make it difficult to use neural network-based algorithms for network edge or personal devices, since complex neural network operations can require large grids of MACs that require processing the neural network in contained time. Technical solution The example implementations described herein are for a second generation neural network (NN 2.0) processor as implemented in hardware, software, or a combination thereof. The proposed example implementations can replace MAC hardware in all neural network layers / operations that use multiplication and addition such as Convolutional Neural Network (CNN), Recurrent Neural Network (RNN), Fully-connected Neural Network (FNN), Auto Encoder (AE), Batch Normalization, Parametric Rectified Linear Unit, etc. In example implementations described here, NN 2.0 uses a shifter function in hardware to significantly reduce the area and power of the neural network implementation by using shifters instead of multipliers and / or adders. The technology is based on the fact that neural network training is accomplished by adjusting parameters by arbitrary factors of their calculated gradient values. In other words, in neural network training, an incremental adjustment of each parameter is made, by an arbitrary amount, based on its gradient. Whenever NN 2.0 is used to train a neural network (AI model), it ensures that neural network parameters such as weights are logarithmically quantized (e.g.,a value that can be represented by an integer power of two) so that shifters such as binary number shifters can be used in hardware or . software for neural network operations that require multiplication and / or addition operations such as a convolutional operation, batch normalization, or an activation function such as a Parametric / Leaky ReLU, thereby replacing the multiplication and / or addition operation with a shift operation. In some cases, the parameters or weights may be quantization parameters—binary logarithmically quantized to numbers that are an integer power of two. Using the example implementations described here, it is thus possible to perform computations for neural network operations in a way that is much faster than what can be accomplished with a MAC network, while consuming a fraction of the power and having only a fraction of the physical footprint. The implementation examples described herein involve novel circuitry in the form of an artificial intelligence processing element (AIPE) to facilitate dedicated circuitry for processing neural network / AI operations. However, the functions described herein may be implemented in equivalent circuitry, such as field programmable gate arrays (FPGAs) or application specific integrated circuits (ASICs), or as in-memory instructions to be loaded into generic central processing units (CPUs), depending on the desired implementation.In cases involving FPGAs, ASICs, or CPUs, the algorithmic implementations of the functions described here will always lead to a reduction in the area footprint, power, and execution time of the hardware for processing neural network or other AI operations by replacing shift multiplication or addition, thereby saving on computational cycles or computational resources that would otherwise have been consumed by normal multiplication on FPGAs, ASICs, or CPUs. Aspects of the present disclosure may involve an artificial intelligence processing element (AIPE). The AIPE may include a shifter circuit configured to accept a shiftable input derived from input data for a neural network operation; accept a shift instruction derived from a corresponding logarithmically quantized parameter of a neural network or a constant value; and shift the shiftable input in a leftward direction or a rightward direction in accordance with the shift instruction to form a shifted output representative of a multiplication of the input data with the corresponding logarithmically quantized parameter of the neural network. Aspects of this disclosure may involve a system for processing a A neural network operation comprising a shifter circuit, the shifter circuit is configured to multiply input data with a corresponding logarithmically quantized parameter associated with the operation for a neural network. To multiply the input data with a corresponding logarithmically quantized parameter, the shifter circuit is configured to accept a shiftable input derived from the input data; and shift the shiftable input in a leftward direction or a rightward direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output representative of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation. Aspects of the present disclosure may involve a method for processing a neural network operation comprising a multiplication of input data with a corresponding logarithmically quantized parameter associated with the operation for a neural network. The multiplication may comprise taking in a shiftable input derived from the input data; and shifting the shiftable input in a leftward direction or a rightward direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output representative of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation. More particularly, a method of the invention may be implemented by a processing computing entity of an artificial intelligence, and may comprise the steps of: admitting a shiftable input derived from input data for a neural network operation; admitting a shift instruction derived from a corresponding logarithmically quantized parameter of a neural network or a constant value; and shifting the shiftable input in a leftward direction or a rightward direction in accordance with the shift instruction to form a shifted output representative of a multiplication of the input data with the corresponding 1o-garithmically quantized parameter of the neural network. Aspects of the present disclosure may involve a computer program for storing instructions for processing a neural network operation comprising a multiplication of input data with a corresponding logarithmically quantized parameter associated with the operation for a neural network. The multiplication instructions may comprise taking in a shiftable input derived from the input data; and shifting the shiftable input in a leftward direction or a rightward direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output representative of the multiplication of the input data with the corresponding logarithmically quantized parameter. respondent for the neural network operation. The instructions may be stored on a medium such as a non-ephemeral computer-readable medium and executed by one or more processors. Aspects of the present disclosure may involve a system for processing a neural network operation comprising means for multiplying input data with a corresponding logarithmically quantized parameter associated with the operation for a neural network. The multiplying means may comprise means for taking in a shiftable input derived from the input data; and means for shifting the shiftable input in a leftward direction or a rightward direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output representative of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation. Aspects of the present disclosure may further involve a system that may include a memory configured to store a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; one or more hardware elements configured to shift or add shiftable input data; and controller logic configured to control the one or more hardware elements to, for the each of the one or more neural network layers read from the memory, shift the shiftable input data left or right based on the corresponding logarithmically quantized parameter values to form shifted data;and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. ; Aspects of the present disclosure may further involve a method that may include managing, in a memory, a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and controlling one or more hardware elements to, for the each of the one or more neural network layers read from the memory, shift the shiftable input data left or right based on the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. Aspects of the present invention may further involve a method that may including managing, in a memory, a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and for each of the one or more neural network layers read from the memory, shifting the shiftable input data, left or right, based on the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. Aspects of the present invention may further involve a computer program having instructions that may include managing, in a memory, a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and controlling one or more hardware elements to, for the each of the one or more neural network layers read from the memory, shift the shiftable input data left or right based on the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed.The computer program and instructions may be stored in a non-ephemeral computer-readable medium for execution by hardware (e.g., processors, FPGAs, controllers, etc.). Aspects of the present invention may further involve a system, which may comprise memory means for storing a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and for the each of the one or more neural network layers read from the memory means, shifting means for shifting the shiftable input data, left or right, based on the corresponding logarithmically quantized parameter values to form shifted data; and means for adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. Aspects of the present invention may further involve a method that may include managing, in a memory, a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more plus neural network layer(s), each of the one or more neural network layer(s) representing a corresponding neural network operation to be performed; and for each of the one or more neural network layer(s) read from the memory, shifting the shiftable input data, left or right, based on the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. Aspects of the present invention may further involve a computer program having instructions, which may include managing, in a memory, a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and for the each of the one or more neural network layers read from the memory, shifting the shiftable input data, left or right, based on the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the shifted data formed according to the corresponding neural network operation to be performed.The computer program and instructions may be stored in a non-ephemeral computer-readable medium for execution by hardware (e.g., processors, FPGAs, controllers, etc.). Aspects of the present invention may further involve a system, which may comprise memory means for storing a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed; and for the each of the one or more neural network layers read from the memory means, shifting means for shifting the shiftable input data, left or right, based on the corresponding logarithmically quantized parameter values to form shifted data; and means for adding or shifting the shifted data formed according to the corresponding neural network operation to be performed. Aspects of the present disclosure may involve a method, which may involve taking in a shiftable input derived from the input data (e.g., scaling by a factor); shifting the shiftable input in a leftward direction or a rightward direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output represent- representative of multiplying the input data with the corresponding logarithmically quantized parameter for the neural network operation as described herein. As described herein, the shift instruction associated with the corresponding logarithmically quantized parameter may involve a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized parameter; wherein shifting the shiftable input involves shifting the shiftable input in the leftward direction or rightward direction in accordance with the shift direction and by a magnitude indicated by the shift magnitude. Aspects of the present disclosure may involve a method of processing an operation for a neural network, which may involve admitting shiftable input data derived from input data of the operation to the neural network; admitting an input associated with a corresponding logarithmically quantized weight parameter for the input data of the operation to the neural network, the input involving a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized weight parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized weight parameter; and shifting the shiftable input data according to the input associated with the corresponding logarithmically quantized weight parameter to generate an output for processing the operation for the neural network. Aspects of the present disclosure may involve a system for processing an operation for a neural network, which may involve means for admitting shiftable input data derived from input data of the operation for the neural network; means for admitting an input associated with a corresponding logarithmically quantized weight parameter for the input data of the operation for the neural network, the input involving a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized weight parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized weight parameter; and means for shifting the shiftable input data according to the input associated with the corresponding logarithmically quantized weight parameter to generate an output for processing the operation for the neural network. Aspects of the present disclosure may involve a computer program for processing an operation for a neural network, which may involve instructions including an intake of shiftable input data derived from input data of the operation for the neural network; an intake of an input associated with a corresponding logarithmically quantized weight parameter for the input data of the operation for the neural network, the input involving a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized weight parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized weight parameter; and shifting the shiftable input data according to the input associated with the corresponding logarithmically quantized weight parameter to generate an output for processing the operation for the neural network. The computer program and instructions may be stored in a non-ephemeral computer-readable medium and configured to be executed by one or more processors. Brief description of the drawings Other characteristics, details and advantages of the invention will appear on reading the detailed description below, and on analyzing the attached drawings, in which: [Fig.1] illustrates an example training process for a typical neural network in accordance with the related art; [Fig.2] illustrates an example of an interference process for a typical neural network in accordance with the related art; [Fig.3] illustrates an example hardware implementation for a typical neural network in accordance with the related art; [Fig.4] illustrates an example training process for a quantized neural network, in accordance with the related art; [Fig.5] illustrates an example of an interference process for a quantized neural network in accordance with the related art; [Fig.6] illustrates an exemplary hardware implementation for a quantized neural network in accordance with the related art; [Fig.7] illustrates a global architecture of a log quantized neural network, according to an example implementation; [Fig.8] illustrates an example training process for a logarithmically quantized neural network, according to an example implementation; [Fig.9A] and [Fig.9B] illustrate an example flow for logarithmically quantized neural network training, according to an example implementation; [Fig.10] illustrates an example inference process for a logarithmically quantized neural network, according to an example implementation; [Fig.11] illustrates an example hardware implementation for a logarithmically quantized neural network, according to an example implementation; [Fig.12] illustrates an example of the flowchart for a hardware implementation for a logarithmically quantized neural network, according to an example implementation; [Fig. 13] (including [Fig.13A] and [Fig.13B]) illustrates a comparison between quantization and logarithmic quantization, respectively; [Fig. 14] (including [Fig. 14A] to [Fig. 14C]) illustrates a comparison between parameter updates. [Fig. 14A] is an example of a parameter update process of a normal neural network. [Fig. 14C] and [Fig. 14B] are an example of a parameter update process of a logarithmically quantized neural network; [Fig.15] illustrates an example of an optimizer for a logarithmically quantized neural network, according to an example implementation; [Fig. 16] (including [Fig.16A] to [Fig.16C]) illustrates examples of convolution operations, according to an example implementation; [Fig. 17] (including [Fig.17A], [Fig.17B]) illustrates, together with [Fig.18], an example process of training convolution layers in a logarithmically quantized neural network, according to an example implementation; [Fig. 19] (including [Fig.19A] and [Fig.19B]) illustrates, together with [Fig.20], an example of a process for training dense layers in a logarithmically quantized neural network, according to an example implementation; [Fig.21] illustrates, together with [Fig.22], an example of a batch normalization process in a logarithmically quantized neural network, according to an example implementation; [Fig.23] illustrates, together with [Fig.24], an example of recurrent neural network (RNN) training in a logarithmically quantized neural network, according to an example implementation; [Fig.25] illustrates, with [Fig.26], an example of a forward pass of an RNN, according to an example implementation; [Fig.27] illustrates, together with [Fig.28], an example of the RNN training process in a logarithmically quantized neural network, according to an example implementation; [Fig.29] illustrates, together with [Fig.30], an example of LeakyReLU training in a logarithmically quantized neural network, according to an example implementation; [Fig.31] illustrates, together with [Fig.32], an example of training Parametric ReLU (PReLU) in a logarithmically quantized neural network, according to an example implementation; [Fig.33] illustrates an example of the difference between a network inference operation normal neural network (NN1.0) and a logarithmically quantized neural network inference operation (NN2.0); [Fig.34] illustrates an example of scaling input data and bias data for logarithmically quantized neural network inference, according to an example implementation; [Fig.35] illustrates, together with [Fig.36], an example of inference of a fully connected neural network, in a normal neural network, according to an example implementation; [Fig.37] illustrates, with [Fig.38], an example of an inference operation of a fully connected dense layer in a logarithmically quantized neural network, NN2.0, according to an example implementation; [Fig.39] illustrates, together with [Fig.40], an example of an inference operation of a convolution layer in a normal neural network, according to an example implementation; [Fig.41] illustrates, with [Fig.42], an example of inference operation of a convolution layer in a quantized neural network (NN2.0), according to an example implementation; [Fig. 43] (including [Fig.43A] and [Fig.43B]) illustrates, together with [Fig.44], an example of an inference operation of batch normalization in a quantized neural network (NN2.0), according to an example implementation; [Fig.45] illustrates, with [Fig.46], an example of an inference operation of an RNN in a normal neural network, according to an example implementation; [Fig.47] illustrates, with [Fig.48], an example of an inference operation of an RNN in a logarithmically quantized neural network (NN2.0), according to an example implementation; [Fig.49] illustrates an example graph of ReLU, LeakyReLU and PReLU functions, according to an example implementation; [Fig.50] illustrates, together with [Fig.51], an example of transforming an object detection model into a logarithmically quantized NN2.0 object detection model, according to an example implementation; [Fig. 52] (including [Fig.52A] and [Fig.52B]) illustrates examples of transforming a face detection model into a logarithmically quantized NN2.0 face detection model, according to an example implementation; [Fig. 53] (including [Fig.53A] and [Fig.53B]) illustrates examples of transforming a face recognition model into a logarithmically quantized NN2.0 face recognition model, according to an example implementation; [Fig. 54] (including [Fig.54A] and [Fig.54B]) illustrates an example of transformation from an autoencoder model to a logarithmically quantized NN2.0 autoencoder model, according to an example implementation; [Fig. 55] (including [Fig.S5A] and [Fig.55B]) illustrates an example of transforming a dense neural network model into a logarithmically quantized NN2.0 dense neural network model, according to an example implementation; [Fig.56] illustrates an example of a typical binary multiplication occurring in hardware, according to an example implementation; [Fig.57] illustrates, together with [Fig.58], an example of a shift operation for NN2.0 to replace a multiplication operation, according to an example implementation; [Fig.59] illustrates an example of a shift operation for NN2.0 to replace a multiplication operation, according to an example implementation; [Fig.60] illustrates, together with [Fig.61], an example shift operation for NN2.0 using two's compliment data to replace a multiplication operation, according to an example implementation; [Fig.62] illustrates an example shift operation for NN2.0 using two's compliment data to replace a multiplication operation, according to an example implementation; [Fig.63] illustrates, together with [Fig.64], an example of a shift operation for NN2.0 to replace an accumulation / addition operation, according to an example implementation; [Fig.65] illustrates, together with [Fig.66], an example of overflow processing for an add operation for NN2.0 using a shift operation, according to an example implementation; [Fig.67] illustrates, together with [Fig.68] and [Fig.69], an example of a segment assembly operation for NN2.0, according to an example implementation; [Fig.70] illustrates, together with [Fig.71], an example of a shift operation for NN2.0 to replace an accumulation / addition operation, according to an example implementation; [Fig.72] illustrates an example of a general architecture of an AT Processing Element (AIPE), according to an example implementation; [Fig.73] illustrates an example of AIPE having an arithmetic shift architecture, according to an example implementation; [Fig.74] illustrates examples of an AIPE shift operation to replace a multiplication operation, according to an example implementation; [Fig.75] illustrates examples of an AIPE shift operation to replace a multiplication operation, according to an example implementation; [Fig.76] illustrates, with [Fig.77] and [Fig.78], an example of an AIPE carrying out a convolution operation, according to an example implementation; [Fig.79] illustrates, together with [Fig.80], an example of an AIPE performing a batch normalization operation, according to an example implementation; [Fig.81] illustrates, with [Fig.82], an example of an AIPE performing a Parametric ReLU operation, according to an example implementation; [Fig.83] illustrates, with [Fig.84], an example of an AIPE performing an addition operation, in accordance with an example implementation; [Fig.85] illustrates an example of a NN2.0 grid, according to an example implementation; [Fig. 86] (including [Fig.86A] to [Fig.86D]) illustrates examples of AIPE structures dedicated to each neural network operation, according to an example implementation; [Fig.87] illustrates an example of an NN2.0 grid using the AIPE structures of [Fig.86A] - [Fig.86D], according to an example implementation; [Fig.88] illustrates an example of a computing environment on which certain implementation examples can be applied; [Fig.89] illustrates an example system for controlling an AIPE, according to an example implementation. Description of the embodiments The following detailed description provides details of the figures and exemplary implementations of the present application. Reference numerals and descriptions of redundant elements between figures are omitted for clarity. Terms used throughout the description are provided as examples and are not intended to be limiting. For example, use of the term "automatic" may imply fully automatic or semi-automatic implementations involving user or administrator control over certain aspects of the implementation, depending on the desired implementation by a person skilled in the art practicing implementations of the present application. The selection may be conducted by a user via a user interface or other input means, or may be implemented via a desired algorithm.The implementation examples as described herein may be used either in isolation or in combination and the functionality of the implementation examples may be implemented via any means according to the desired implementations. [Fig.7] illustrates an overall architecture of the logarithmically quantized neural network, according to an example implementation. The NN 2.0 architecture is a logarithmically quantized neural network platform that involves the training and inference platform. The training and inference process for NN 2.0 architecture is described below. Training data 701 and an untrained neural network 702 are input to training platform 703. Training platform 703 involves an optimizer 704 and a logarithmic quantizer 705. Optimizer 704 optimizes the model parameters according to any optimization algorithm known in the art. Logarithmic quantizer 705 logarithmically quantizes the optimized parameters. Optimizer 704 and logarithmic quantizer 705 are executed iteratively until the neural network is trained with an error below the desired threshold, or until another abort condition is satisfied according to the desired implementation. The resulting output is a trained neural network 706 that is represented by logarithmically quantized parameters. The trained neural network 706 and the inference data 707 are input into the inference platform 708, which may involve the following. The data and bias scaler 709 scales the inference data 707 and the bias parameters of the trained neural network 706 to form left and right shiftable data and parameters as described hereinafter. The inference engine 710 infers the scaled inference data 707 with the trained neural network 706 via hardware or a combination of hardware and software as described herein. The data scaler 711 scales the output of the inference engine 710 to the appropriate output range based on the desired implementation.The inference platform 708 may produce an output 712 based on the results of the data and bias scaler 709, the inference engine 710, and / or the data scaler 711. The elements of the architecture illustrated in [Fig. 7] may be implemented in any combination of hardware and software. The example implementations described herein involve a novel artificial intelligence processing unit (AIPE) as implemented in hardware as described herein to facilitate the multiplication and / or addition necessary in shift inference, however, such example implementations may also be implemented by other conventional hardware (e.g., field-programmable gate arrays (FPGAs), hardware processors, etc.) or processes, which will save on processing cycles, power consumption and area over such conventional hardware due to changing the multiply / add operation to a simpler shift operation, instead. [Fig.8] illustrates an example of training a logarithmically quantized neural network, according to an example implementation. Depending on the desired implementation, instead of using a "round (operand)" operation, e.g. as discussed in [Fig.4], any mathematical operation that transforms the operand into an integer may be used such as “floor(operand)” or “ceiling(operand)” or “truncate(operand)”, and the present disclosure is not specifically limited thereto. [Fig.9A] and 9B illustrate an example flow for logarithmically quantized neural network training, according to an example implementation. At 901, the flow first initializes the parameters (e.g., weights, bias) of the neural network, which may be in the form of random floating-point numbers or integers depending on the desired implementation. At 902, the test data is fed into the neural network and propagated forward through all layers of the neural network to obtain the output values processed by the neural network. At 903, the error of the output values is calculated by comparing the output values to the test label values. At 904, an optimization process is used to determine how to modify the parameters to reduce the error of the neural network, and the parameters are modified accordingly. At 905, a determination is made as to whether the parameters are acceptable; that is, whether the neural network produces an error within the threshold or whether some other termination condition is met.If so (Yes), then the flow proceeds to 906, otherwise (No) the flow proceeds to 902. As a result, the flow from 902 to 905 is iterated until the desired error is met or a completion condition is met (e.g. manual completion, a certain number of iterations is met, etc.). At 906, the resulting parameters are then logarithmically quantized to reduce the size of the parameters and thus prepare them for the hardware implementation of the shifter. In one example, 32-bit floating point numbers are logarithmically quantized to 7-bit data, however, the present disclosure is not limited to the example and other implementations depending on the desired implementation may be used. For example, 64-bit floating point numbers may be logarithmically quantized to 8-bit data. Furthermore, the flow at 906 does not necessarily have to be executed at the end to logarithmically quantize the parameters. In one example implementation, the logarithmic quantization of the parameters may be part of the iterative process between 902 and 905 (e.g.executed before 905) so that logarithmic quantization can be used as part of the iterative parameter training process, as illustrated at 916 of [Fig.9B]. Such an example implementation can be used depending on the desired implementation therein, so that optimization and logarithmic quantization occur together to produce parameters (e.g., 7-bit data parameters). The resulting logarithmically quantized neural network can thus accept any input (e.g., floating-point numbers, integers) and provide . output data accordingly (e.g. proprietary data format, integers, floating point numbers). [Fig. 10] illustrates an example inference process for a logarithmically quantized neural network, according to an example implementation. To facilitate neural network inference, first, the inference data is fed into the neural network, which is forward propagated through all layers to derive the output values. Then, the output values of the neural network are interpreted according to the objectives set by the neural network. However, in this example, the parameters are logarithmically quantized. Thus, the inference process can be conducted via shifter circuits or AIPEs as described here, or can be conducted in software using hardware processors and shift operations depending on the desired implementation. [Fig. 11] illustrates an example of a hardware implementation for the logarithmically quantized neural network, according to an example implementation. To implement the logarithmically quantized neural network in hardware, first, input data and parameters of the neural network are obtained. Then, through the use of a hardware or software data scaling device, the input data and biases are scaled by a factor in preparation for a shift operation by a hardware shifter. Through the use of the hardware shifter, the input data is shifted based on the logarithmically quantized parameter value. Then, through the use of a hardware adder, all shifted values are added together. Finally, the hardware adder is used to add the bias to the sum. In the example implementation of [Fig.11], a 32-bit shifter is used to facilitate multiplication of a scaled input data value (e.g., scaling by 2!°) with a logarithmically quantized parameter (e.g., a 7-bit logarithmically quantized parameter), as well as for the addition operation. However, other variations may be used depending on the desired implementation, and the present disclosure is not limited thereto. The input data values may be scaled by any factor, and the logarithmically quantized parameters may similarly be any type of logarithmically quantized factor (e.g., 8 bits, 9 bits) with the shifter appropriately sized (e.g., 16 bits, 32 bits, 64 bits, etc.) to facilitate the desired implementation. [Fig.12] illustrates an example of the flowchart of logarithmically quantized neural network inference in the hardware implementation, according to an example implementation. At 1201, the flow obtains the input data and the logarithmically quantized neural network parameters. At 1202, the flow scales the input data and biases by an appropriate factor to convert the input data and biases into a shiftable form for the shift operation. At 1203, the shiftable input data is shifted by the shift instruction derived from the logarithmically quantized parameter. The shifting may be performed by a hardware shifter as described herein, or may be performed by hardware processors or field-programmable gate arrays (FPGAs) depending on the desired implementation. Further details of the shifting will be described herein. At 1204, all shifted values are added together. The addition operation may be performed by a hardware adder as described here, or may be performed by hardware processors or FPGAs depending on the desired implementation. Similarly, at 1205, the scaled bias is added to the resulting sum of the addition operation at 1204 by a hardware adder, hardware processors, or FPGAs. [Fig. 13A] and 13B illustrate a comparison between quantization and logarithmic quantization, respectively. [Fig. 13A] illustrates an example of quantization of integers from 0 to 104 by qv=10, where Quantization (n) = round(n / qv) * qv. [Fig. 13B] illustrates an example of logarithmic quantization of integers from 2 to 180, where Logarithmic Quantization (+-n) = +-2"wondi(082), As illustrated in the comparison of [Fig. 13A] and 13B, logarithmic quantization allows for better accuracy of smaller parameters due to the fact that the intervals are in the form of 2" as opposed to the same intervals regardless of the parameter values. [Fig. 14A] to 14C illustrate a comparison between parameter updates for normal neural network training and for logarithmically quantized neural network training, respectively. Although the implementation examples described herein involve performing logarithmic quantization of the weight parameter by adjusting the gradient appropriately, logarithmic quantization of the updated weight parameter after gradient adjustment can also be performed in accordance with the implementation examples described herein. In such an implementation example, the flow and 916 of [Fig. 9B] can be modified by determining an appropriate training rate with which to multiply the gradient such that the resulting parameter value is a logarithmically quantized value. In the implementation examples described here, the input data is scaled according to the desired implementation to accommodate the shift operation. Most parameters in a model will result in a “right shift” operation that corresponds to values less than 1.0 such as 0.5, 0.25, 0.125, etc. Therefore, the input data is shifted to the left, which is equivalent to multiplying the input by 25 where N is a positive integer. As an example, suppose the raw input value is X,n = 0.85. The input is scaled by 2% to give 0.85 x 2 = 0.85 x 1,048,576 = 891,289.6. This scaled input is rounded to an integer such that rounded (891,289.6) = 891,290, which is used as the new input value Xpouv = 891,290. Bias is defined as a parameter that is added (not multiplied) in neural network operations. In a typical neural network operation such as the following, the bias term is the additional term. a=x*p+b Where, a is the axon (output), x is the input, p is the weight, and b is the bias. In example implementations described here, the input and biases are scaled by the same magnitude. For example, if the input is scaled by 2”, then the bias is scaled by 2%, [Fig. 15] illustrates an example optimizer, according to an example implementation. In the example implementations described here, the optimization can be built following any other gradient-based optimizer. The optimization can be done in stages, with the number of stages defined by the user, in addition to the following for each stage: how often (in training steps) a step is performed, which layers are affected by the steps in each stage, and / or whether to quantize variables within a user-defined threshold ("quant" - quantize values that are below the quantization threshold), or force quantization of all variables in the selected layers ("force" - quantize all parameters regardless of the threshold). Each stage is defined by a number of stage steps (e.g., the number of optimizations per stage), a step interval (e.g.,the number of operations per stage) and an operation (e.g. the type of operation (quant / force) and which layers to quantize). Depending on the desired implementation, the user can also set the following parameters. quant_proc: 'truncate' or 'nearest'; the rounding process to use when quantizing freeze_threshold: Threshold to determine the percentage of weights that must be quantized before forcing a quantize + freeze operation for the remaining weights. mask_threshold: threshold to determine how close the weights must be to the logarithmically quantized form to quantize + freeze that weight. In example implementations, the quant_proc template might be as follows. Nearest: For an x value, quantify to the nearest log value. Bottom: For a value x, quantify to the floor closest to log, Stochastic: For a value x, find the ceiling and floor of log. The probability that the ceiling is selected is (x - floor) / (ceiling - floor) In implementation examples, the model freezing process is as follows. Threshold: During a freeze operation, freeze any layer where the layer has a frozen weight percentage greater than or equal to fz_threshold. At the end of training, all remaining layers are also frozen. Hierarchy: During a freeze operation, layers are ranked by percentage of frozen weight. The highest hierarchy layers are then frozen and managed so that an equal number of layers are frozen each time a freeze operation is performed. Order: During a freeze operation, layers are frozen in order of input -> output and managed so that an equal number of layers are frozen. Training stage options in example implementations can be as follows. The default is assumed to be a normal neural network (NN 1.0) operation. Fz_tout: Quantizes, freezes and applies a mask to the layers if it is an NN2.0 operation. Fz_nl: Quantizes, freezes and applies a mask to the Norm Lot layers if it is an NN2.0 operation. Fz_conv: Quantizes, freezes and applies a mask to the convolutional layer if it is an NN2.0 operation. Quant_all: Quantizes and applies a mask to all layers if it is an NN2.0 operation. Quant_nl: Quantizes and applies a mask to the Norm Lot layers if it is an NN2.0 operation. Quant_conv: Quantizes and applies a mask to the convolutional layers if it is an NN2.0 operation. The decomposition of training implementation examples can be as follows. Input: Tuple of training stage tuples. Example To: ((4, 1, Fz_tout),) The first input dictates how many epochs are conducted for the floor operation (in this case, fz_tout for four epochs). The second entry dictates how often an NN2.0 operation will be performed. In other words, this tuple indicates that the operation (z_ all) is performed every epoch. The third input indicates which stage operation of NN2.0 should be performed. Example B: ((2, 1, Default), (4, 1, Fz_conv), (4, 2, £z_nl)) In this example, training is done for a total of ten epochs. The first two epochs will be trained with an NN1.0. The next four epochs will be executed will perform an NN2.0 operation at the end of each epoch. At the end of the four epochs, all convolution layers will be frozen. The last four epochs will perform an NN2.0 every other epoch. At the end of the fourth epoch, all batch normalization layers will be frozen. [Fig. 16A], 16B and 16C illustrate examples of convolution operations, according to an implementation example. Specifically, [Fig. 16A] illustrates an example of convolution, [Fig. 16B] illustrates an example of depthwise convolution, and [Fig. 16C] illustrates an example of separable convolution. In the convolution example of [Fig. 16A], a two-dimensional (2D) convolution is applied to an input signal such that Conv(x) = Z(weight * x) + bias In the depth-first convolution example of [Fig.16B], a 2D convolution is applied to each channel separately, with the outputs concatenated. In the separable convolution example of [Fig.16C], a 2D convolution is applied to each channel separately, with the outputs concatenated, and the convolution is conducted depth-first. [Fig.17A], 17B and 18 illustrate an example process for training convolution layers, according to an example implementation. Specifically, [Fig.17A] illustrates an example of a forward pass of a convolution, [Fig.17B] illustrates an example of convolution weight updates and logarithmic quantization, and [Fig.18] illustrates an example flow for training convolution layers with reference to [Fig.17A] and [Fig.17B]. In the flow of [Fig.18], at 1801, the flow convolves each kernel (3x3x3 in [Fig.17A]) on the input data, multiplying each value, and then accumulating the products. An output matrix (3x3 in [Fig.17A]) will be generated for each kernel. In 1802, the flow calculates the weight gradients after calculating the error between the outputs and the ground truth data.In 1803, using the weight gradients, the stream updates the weights according to a predefined update algorithm as shown in [Fig.17B]. In 1804, the stream logarithmically quantizes the weight values that have a low log quantization cost. Weights with a high quantization loss can be left unquantized until a future iteration, or can be quantized immediately depending on the desired implementation. In the example in [Fig.17B], the value "2.99" is left unquantized because the log quantization cost would be 2.99 - 2.00 = 0.99, greater than the maximum log quantization loss of 0.5. In 1805, the process from 1801 to 1804 is iterated until the convolution training is complete. [Fig.19A], 19B and 20 illustrate an example of a dense layer training process, according to an example implementation. More precisely, the [Fig.19A] illustrates an example of a forward pass of a dense layer, [Fig.19B] illustrates an example of dense layer weight updates and logarithmic quantization, and [Fig.20] illustrates an example flow for training dense layers with reference to [Fig.19A] and [Fig.19B]. In the flow of [Fig.20], in 2001, the flow multiplies each input row data (Inputs (1x3) of [Fig.19A]) with each column of the weight matrix (Weights (3x4) of [Fig.19A]) and then accumulates the products, resulting in an output (1x4) as shown in [Fig.19A]. In 2002, the flow calculates the weight gradients after calculating an error between the outputs and the ground truth data. In 2003, using weight gradients, the flow updates the weights according to a predefined update algorithm as illustrated in [Fig.19B].In 2004, the stream logarithmically quantizes weight values that have low logarithmic quantization cost. Weights with high quantization loss can be left unquantized until a future iteration or can be quantized immediately depending on the desired implementation. In 2005, the process from 2001 to 2004 is iterated until the dense layer training is complete. Regarding batch normalization training, for a layer with a d-dimensional input y — ( x} ; x (8) ) , each dimension is normalized. The dimension can represent the channel based on the following: kki é g69 _ x. mean ( x(F) ) where the mean and variance are calculated on the ; variance {x"") + € training dataset. For each activation x} , a parameter pair yp can scale and shift the normalized value as follows NL“ >- y 4 +p” ). The parameter pair is learned along with the original model parameters. Regarding the batch normalization data, the batch normalization j follows: X-AVGy (NL) is represented by the following: NZ, ( x ) = r( Évse ) +6 The mean and variance of the data are calculated. The value of epsilon (É) is usually a small number to avoid division by zero. The NL is then converted to the form Px + B. -— ” n - TOY Where,p= and NL= (yarre ) ++ (0-5 (Garre ))09P= gare B=By. ( te ) The P term is logarithmically quantized and the bias term B is scaled appropriately. Then, P is multiplied by the input x and the bias B is added to the result of the multiplication. [Fig.21] and 22 illustrate an example of batch normalization training, according to an example implementation. Specifically, [Fig. 22] illustrates a flow of the batch normalization training that is used in the example of [Fig. 21]. In 2201, the flow performs an element-wise multiplication of the input, with the batch normalization weights. In 2202, the flow adds the batch normalization bias. In 2203, the flow computes gradients by comparing the axon output to the label. In 2204, the flow updates the variables for batch normalization. In 2205, the flow logarithmically quantizes the batch normalization weights that are close (e.g., within a threshold) to the logarithmically quantized values. In 2206, the flow repeats 2205 until the batch normalization weights are fully logarithmically quantized. [Fig.23] and 24 illustrate an example of a forward pass of a recurrent neural network (RNN), according to an example implementation. Specifically, [Fig.23] and [Fig.24] illustrate an example of the forward pass of an RNN. In 2401, the stream multiplies a first data from [Fig.23] and Weight (2x2). In 2402, the stream accumulates all products of the first data and Weight. In 2403, for the first iteration, the stream multiplies a null grid having the same shape as the data by Hidden (2x2). In 2404, the stream accumulates all products of the null grid and Hidden. In 2405, the stream records the sum of the outputs of 2402 and 2404 and will be used in the next or a later iteration. At 2406, the stream multiplies a second data from [Fig.23] by Weight (2x2). At 2407, the stream accumulates all the products of the second data and Weight. At 2408, the stream multiplies the output of 2407 by Hidden (2x2).At 2409, the stream accumulates all products from the stored and cached output. At 2410, the stream repeats until the data is fully processed. [Fig.25] and 26 illustrate another example of a forward pass of an RNN, according to an example implementation. Specifically, [Fig.25] and [Fig.26] illustrate an example of the forward pass of an RNN. In 2601, the flow multiplies a first data from [Fig.25] by Weight (2x2). In 2602, the flow accumulates all products of the first data and the weight. In 2603, for the first iteration, the flow multiplies a null grid (state_init) having the same shape as the data (1x2) by Hidden (2x2). In 2604, the flow accumulates all products of the null grid and Hidden (2x2). In 2605, the flow records the sum of the outputs of 2602 and 2604 and will be used in the next or a later iteration. At 2606, the stream multiplies a second data item from [Fig.25] by Weight (2x2). At 2607, the stream accumulates all the products of the second data items and Weight (2x2). At 2608, the stream multiplies the output of 2607 by Cachée (2x2).At 2609, the stream accumulates all products of the stored and cached output (2x2). At 2610, the stream repeats until the data is fully processed. [Fig.27] and 28 illustrate an example of RNN weight update and logarithmic quantization, according to an example implementation. Specifically, [Fig.27] illustrates an example of RNN weight update and quantization, and [Fig.28] illustrates an example flow of RNN weight update and quantization. In 2801, the flow computes weight gradients by computing errors between the outputs and the ground truth data. In some cases, the Weight (2x2) and Hidden (2x2) may each be dense layers. In 2802, the flow updates the weights using the weight gradients based on a predefined or preconfigured update algorithm. In 2803, the stream logarithmically quantizes weight values that have a low logarithmic quantization cost (e.g., within a threshold). Weights that have a high quantization loss (e.g.,exceed the threshold) are not quantified and left for future or subsequent iteration. [Fig. 29] and 30 illustrate an example of training LeakyReLU, according to an example implementation. Specifically, [Fig. 29] illustrates an example of training LeakyReLU, and [Fig. 30] illustrates an example flow of training LeakyReLU. LeakyReLU can apply an element-wise function, which corresponds to the following: LeakyReLU(x) = max(0,x) + negative_slope*min(0,x), where LeakyReLU(x) = x if x>0; or LeakyReLU(x) = negative_slope*x otherwise. At 3001, the flow determines whether y is greater than or equal to zero (0). At 3002, in response to a determination by the flow that y is greater than or equal to zero (0), y is set to the value of x, and the training process is terminated. In 3003, in response to a determination by the stream that y is not greater than or equal to zero (0), x is multiplied by the negative slope. In typical neural network operations, the negative slope is set to 0.3, by default. In a NN2.0, the negative slope is set to 0.25 or 27 by logarithmically quantizing the value of 0.3. At 3004, the flow trains the NN with the updated slope value. The NN is trained with the updated slope value because the axon value may change for other layers during training. [Fig. 31] and 32 illustrate an example of Parametric ReLU (PReLU) training, according to an example implementation. Specifically, [Fig. 31] illustrates an example of PReLU training, and [Fig. 32] illustrates an example stream of PReLU training. PReLU training may apply an element-wise function, which corresponds to the following: PReLU(x) = max(0,x) + a*min(0,x), where PReLU(x) = x if x20; or PReLU(x) = a*x otherwise. In such cases, œ is a trainable parameter. At 3201, the stream determines whether y is greater than or equal to zero (0). At 3202, in response to a determination by the stream that y is greater than or equal to zero (0), y is set to the value of x, and the PReLU training process is terminated. At 3203, in response to a determination by the stream that y is not greater than or equal to zero (0), x is multiplied by to calculate the gradients for update the layer weights. In 3204, if a is close to a logarithmically quantized weight (e.g., within a threshold), the flow changes the a to a logarithmically quantized number. In 3205, if a is not logarithmically quantized in 3204, then the process of 3203 and 3204 repeats until a is logarithmically quantized. [Fig.33] illustrates an example of the difference between a normal neural network (NN1.0) operation and a NN2.0 operation. Once a neural network is trained, learned, or optimized, inference data (arbitrary data) can be applied to the trained neural network to obtain output values. The output values are interpreted based on the rules that are defined for the neural network. For example, in a NN1.0, the data can be multiplied by the weights to produce an output. In NN2.0, the data can be shifted based on the logarithmically quantized weights of NN2.0 to produce the resulting output for the neural network operation. When using shift operations in NN2.0, one problem that can arise is that information (digits in layer axons) can be lost in right-shift operations. For example, suppose the input to a dense layer is 4 (0100 -- in binary) and the weight is 27, which means the input (4 = 0100) must be shifted right by 5, producing the result 0, instead of the normal 0.125 by multiplication. This can lead to information loss due to right-shifting in NN2.0. This problem can be addressed by upscaling (left-shifting) all input data by a factor that leaves enough room to sufficiently apply all right-shift operations. The exact value of the factor may depend on individual neural networks and / or the datasets used in conjunction with the neural networks.For example, a factor of 24 can be used. However, the disclosure is not intended to be limited to factor 24, so other factor values can be used. The biases of each layer should be scaled (left-shifted) by the same factor as used for the input data, to maintain consistency with the scaled inputs, for example, as shown in [Fig.34]. [Fig.35] and [Fig.36] illustrate an example of inference of a fully connected neural network having dense layers, in a normal neural network, according to an example implementation. Specifically, [Fig.35] illustrates an example of the fully connected neural network (e.g.: NN1.0) having the dense layers, and [Fig.36] illustrates an example flow of the fully connected neural network having the dense layers. The neural network in [Fig.35] comprises an input layer, a hidden layer and an output layer. The input layer can comprise a plurality of inputs with which the hidden layer is fed. At 3601, the stream obtains the input data. The input data with which the hidden layers are fed comprises floating point numbers. At 3602, the stream multiplies the input data with the optimized weights. At 3603, the stream calculates the sum of the input data multiplied by the corresponding optimized weights and a bias to generate an output. [Fig. 37] and 38 illustrate an example of an inference of a fully connected dense layers in a logarithmically quantized neural network, NN2.0, according to an example implementation. More specifically, [Fig. 37] illustrates an example of a fully connected NN2.0 having the dense layers, and [Fig. 38] illustrates an example stream of the fully connected NN2.0 having the dense layers. The NN2.0 of [Fig. 37] includes an input layer, a hidden layer, and an output layer. The input layer may include a plurality of inputs with which the hidden layer is fed. At 3801, the stream scales the input data. The input data includes floating point numbers that have been scaled by a factor.For example, floating-point numbers can be scaled by a factor of 2°. The description is not intended to be limited to the example scaling factor described here, so different scaling factor values can be used. At 3802, the stream shifts the input data based on the shift instruction derived from the corresponding logarithmically quantized weights. The weights may include 7-bit data derived from logarithmically quantizing the parameters. At 3803, the stream adds the bias. The bias is scaled by the same factor used to scale the input data. [Fig.39] and 40 illustrate an example of a convolution inference operation in a normal neural network, according to an implementation example. Specifically, [Fig.39] illustrates an example of a convolution inference operation for a convolution layer, and [Fig.40] illustrates an example flow of the convolution inference operation for the convolution layer. At 4001, the flow convolves each kernel (3x3x3 as shown in [Fig.39]) on the input data. At 4002, the flow multiplies each value and accumulates or sums the products. In the example of [Fig.39], an output matrix (3x3) can be generated for each kernel. At 4003, the flow sums each output matrix by a corresponding bias. Each kernel can have a different bias, which is spread across the kernel's output matrix (3x3 in [Fig.39]). [Fig.41] and 42 illustrate an example of a convolution inference operation for NN2.0, according to an implementation example. Specifically, [Fig.41] illustrates an example of a convolution inference operation for a convolution layer for NN2.0, and [Fig.42] illustrates an example flow of the inference of convolution for the convolution layer for NN2.0. In 4201, the flow scales each of the input data by a factor and each bias value by the same factor. The flow upscales each of the input data by multiplying the factor (e.g., 2) in cases where the layer is the input layer to the NN2.0. If the layer is not the input layer, the input data values are assumed to be already scaled, and the kernel weights are assumed to be trained for logarithmically quantized values to be used for shifting. In 4202, the flow convolves each kernel (2x2x3 in [Fig.41]) on the input data. An element-wise shift can be used for each value, and the results are accumulated. In some aspects, an output matrix (3x3 in [Fig.41]) is generated for each kernel.Weight values in kernels can have the format (+ / - to determine the sign of the weight) (+ / - for left / right shift, followed by how much to shift). For example, +(-5) indicates that the sign of the weight is negative, followed by a right shift by 5. This is equivalent to multiplying the input value by 25. In 4203, the stream sums each output matrix by a corresponding bias. Each kernel can have a respective bias, which can be broadcast across the kernel's entire output matrix (3x3 in [Fig.41]). Regarding batch normalization inference, batch normalization to d'euit : = p{ A- Mean can correspond to the following: BN ( x ) = r{ rarté ) +B. where y and B can be trainable parameters, while the mean and variance are constants and can be set during training. Epsilon ( €) is also a constant used for numerical stability and has a small value, such as, but not limited to, 1E-3. The mean, variance, and epsilon are all diffused. The mean and variance have a per-channel value (diffused across the height / width of each channel), while epsilon is a diffused value across all dimensions. In some cases, element-wise operations according to the batch normalization equation can be used to calculate the axon using the input data (x). [Fig. 43A], 43B, and 44 illustrate an example of batch normalization inference, according to an example implementation. Specifically, [Fig. 43A] illustrates converted batch normalization equations for NN2.0, [Fig. 43B] illustrates batch normalization inference for NN2.0, and [Fig. 44] illustrates an example batch normalization inference flow for NN2.0. The batch normalization equation of NN2.0 is converted as shown in [Fig. 43A]. Batch normalization for the final format of NN2.0 is represented by Equation 3 in [Fig. 43A]. In some cases, during training, it can be assumed that P in Equation 4 of [Fig. 43A] and B in Equation 4 of [Fig. 43A] are optimized, where P is quantized logarithmically, and P and B are defined and ready for inference. At 4401, the stream element-wise shifts the input data based on the logarithmically quantized weight (p) values, as shown in [Fig. 43B]. At 4402, the stream element-wise adds the bias. Since this is a batch normalization layer, it is unlikely to be the input layer, so the input data is assumed to be scaled. The bias may also be scaled by the same factor as the input data. At 4403, the stream computes the axon. [Fig.45] and 46 illustrate an example of RNN inference in a normal neural network, according to an example implementation. Specifically, [Fig.45] illustrates an example of RNN inference, and [Fig.46] illustrates an example of RNN inference flow. In 4601, the flow multiplies a first data from [Fig.45] with Weight (2x2). In 4602, the flow accumulates all the products of the first data and the weights. In 4603, for the first iteration, the flow multiplies a null grid (state_init) having the same shape as the data (1x2) by Hidden (2x2). In 4604, the flow accumulates all the products of the null grid. In 4605, the flow records the sum of the outputs of 4602 and 4604 and will be used in the next or a later iteration. In 4606, the stream multiplies a second data from [Fig.45] by Weight 2x2). In 4607, the stream accumulates all the products of the second data and the weight. In 4608, the stream multiplies the output of 4605 by Cachée (2x2).At 4609, the stream accumulates all the products of the recorded output. At 4610, if the data is not fully processed at 4609, then the process from 4605 to 4609 repeats until the data is fully processed. [Fig.47] and 48 illustrate an example of RNN inference for NN2.0, according to an example implementation. Specifically, [Fig.47] illustrates an example of RNN inference for NN2.0, and [Fig.48] illustrates an example flow of RNN inference for NN2.0. In 4801, the flow multiplies and accumulates a null grid (init_state) by hidden (2x2) using the shift. The resulting vector is stored (sorl A) as shown in [Fig.47]. In 4802, the flow multiplies and accumulates a first data (data A) by weight (2x2) using the shift. Weight (2x2) and hidden (2x2) are both dense layers. The resulting vector is stored (sor2 A) as shown in [Fig.47]. At 4803, the flux adds the vector outputs of 4801 and 4802 together. The resulting vector is stored (sor3 A) as shown in [Fig.47]. At 4804, the (lux) multiplies and accumulates the vector output of 4803 by hidden (2x2) using the offset.The resulting vector is stored (sorl B) as shown in [Fig.47]. At 4805, the stream multiplies and accumulates a second data (data B) by weight (2x2) using the offset. The resulting vector is stored (sor2 B) as shown in [Fig.47]. At 4806, if the data is not fully processed at 4805, then the process from 4802 to 4805 is repeated. until the data is fully processed. In some cases, three types of rectified linear unit (relu) activation functions are commonly used, and may include: ReLU, LeakyReLU, or Parametric ReLU (PreLU). ReLU can be: ReLU(x) = (x)+ = max(0,x) LeakyReLU may correspond to the following: LeakyReLU(x) = max(0,x) + negative_slope * min(0,x), where six >0 LeakyRELU(x) = [* negative_slope *x. otherwise PReLU can correspond to the following: PReLU(x) = max(0,x) + à * min(0,x), where six > 0 PReLU(x) = | * ax, otherwise All three functions are configured to accept an input, typically an axon tensor computed through a layer of a neural network, and apply a function to compute the output. Each input value in the axon tensor behaves independently depending on its value. For example, if the input value is greater than zero (0), all three functions work the same way, so that output = input. However, if the input value is less than zero (0), the functions work differently. In the case of ReLU, output = 0 if the input value < 0. In the case of LeakyReLU, output = negative_slope * input, where negative_slope is set at the beginning of training (usually 0.3) and is fixed throughout training. In the case of PReLU, output = a * input, where a is trainable and optimized during training. The a has one value per PReLU layer and is broadcast in all dimensions. In some cases, such as when there is more than one PReLU in the network, each PReLU will have a trained and optimized a. [Fig. 49] illustrates an example plot of each of the three functions, according to an example implementation. All three activation functions infer the same as their standard inferences if the input value is greater than 0, so that output = input. If the input value is less than zero (0), the NN2.0 ReLU inference can have output = 0, as shown by the short dashed line in [Fig. 49]. The NN2.0 ReLU inference can be the same as the standard ReLU when the input value is less than zero (0). The LeakyReLU NN2.0 inference for negative input values is modified so that the negative_slope is logarithmically quantized (having a default value of 0.25 = 2, as shown by the long dashed line cn [Fig. 49]). Logarithmic quantization is performed to use the offset (instead of multiplication) to calculate the outputs. The slope_negative value is set before training begins, and trainable parameters in other layers are trained and optimized accordingly. NN2.0 PReLU inference for negative input values is also different in that the trainable parameter (a = 0.5 = 2-1, as indicated by the dotted line in [Fig. 49]) is logarithmically quantized during training, allowing the offset to be used to calculate the output values. [Fig.50] and [Fig.51] illustrate an example of how to transform an object detection model such as YOLO into a logarithmically quantized NN2.0 model, according to an example implementation. A typical YOLO architecture might include a 5001 frame, a 5002 neck, and a 5003 head. The frame might include CSPDarknet53 Tiny, while the neck and head comprise convolution blocks. An input layer might be scaled by a factor of 2” (e.g., 2 ) for offsetting purposes. The biases for the convolution and batch normalization layers might also be scaled by the same 2" factor (e.g., 2?*) used to scale the input layer. The outputs can be downscaled by the same 2* factor used to scale the input layer and biases for the convolution and batch normalization layers. [Fig.51] illustrates an example of which YOLO operations / layers to logarithmically quantize to transform the model into an NN2.0 model. The input to the framework 5101 is scaled by a factor of 2" for shifting purposes. For example, the factor may be 2, but the disclosure is not intended to be limited to the example 2%, so the factor may be a different value. The framework 5101, neck 5102, and / or head 5103 may include a plurality of layers (e.g., neural network layers) that process the data. For example, some of the layers may include convolution layers, batch normalization layers, or LeakyReLU layers. Operations / layers that use multiplication and / or addition such as the convolution layers, batch normalization layers, and LeakyReLU layers are logarithmically quantized to transform the model into an NN2.0 model.Other layers within the skeleton, neck, and / or head are not logarithmically quantized because these other layers do not use multiplication and / or addition operations. For example, some of the other layers may include concatenation, upsampling, or zero-padding layers that do not involve multiplication to perform their respective operations, so the concatenation, upsampling, or zero-padding layers are not logarithmically quantized. However, in some cases, other layers that do not use multiplication and / or addition operations may be logarithmically quantized. mically. Layers that use multiplication and / or addition operations, such as, but not limited to, convolution layers, dense layers, RNN, batch normalization, or Leaky ReLU are usually logarithmically quantized to transform the model into an NN2.0 model. The head outputs can be downscaled by the same factor used to scale the input to generate the same output values as the normal model. For example, the head outputs can be downscaled by the factor 224. [Fig.52A] and 52B illustrate examples of how to transform a face detection model such as an MTCNN into a logarithmically quantized NN2.0 model, according to an example implementation. Specifically, [Fig.52A] illustrates a typical MTCNN model architecture, while [Fig.52B] illustrates MTCNN model layers that are logarithmically quantized to transform the model into an NN2.0 model. [Fig.52A] includes example architectures of PNet, RNet, and ONet and identifies the layers within each architecture that can be logarithmically quantized. For example, the convolution layers and PReLU layers of PNet in [Fig.52A] can be log-quantized, while the convolution layers, PReLU layers, and dense layers of RNet and ONet in [Fig.52A] can be log-quantized. With reference to [Fig.52B], the architecture of PNet, RNet, and ONet under NN2.0 includes the scaling layers for input and output, as well as the logarithmically quantized layers to transform the model in [Fig.52A] into an NN2.0 model. [Fig. 53A] and 53B illustrate examples of how to transform a face recognition model such as a VGGFace into a logarithmically quantized NN2.0 model, according to an example implementation. Specifically, [Fig. 53A] illustrates a typical VGGFace model architecture, while [Fig. 53B] illustrates VGGFace model layers that are logarithmically quantized to transform the model into an NN2.0 model. [Fig. 53A] includes example architectures of ResNet50 and ResBlock and identifies the layers within each architecture that can be logarithmically quantized. For example, the convolution layers, batch normalization layers, and stacking layers comprising the ResBlock and ResBlock convolution layers in [Fig. 53A] can be logarithmically quantized. Referring to [Fig.53B], the architecture of ResNet50 and ResBlock under NN2.0 includes scaling layers for input and output, as well as logarithmically quantized layers to transform the model in [Fig.53A] into an NN2.0 model. [Fig.54A] and 54B illustrate an example of how to transform an autoencoder model into a logarithmically quantized NN2.0 model, according to an example implementation. Specifically, [Fig.54A] illustrates an architecture typical of an autoencoder model, while [Fig.54B] illustrates autoencoder model layers that are logarithmically quantized to transform the model into an NN2.0 model. [Fig.54A] includes an example of an autoencoder layer structure and identifies the layers that can be logarithmically quantized. For example, the dense layers within an encoder and decoder in [Fig.54A] can be logarithmically quantized. With reference to [Fig.54B], the autoencoder layers under NN2.0 include scaling layers for the input and output, as well as the logarithmically quantized layers to transform the model in [Fig.54A] into an NN2.0 model. [Fig.55A] and 55B illustrate an example of how to transform a dense neural network model into a logarithmically quantized NN2.0 model, according to an example implementation. Specifically, [Fig.5SA] illustrates a typical architecture of a dense neural network model, while [Fig.55B] illustrates dense neural network model layers that are logarithmically quantized to transform the model into an NN2.0 model. [Fig.55A] includes an example of a dense neural network model layer structure and identifies the layers that can be logarithmically quantized. For example, the dense layers within the model architecture of [Fig.55A] can be logarithmically quantized. Referring to [Fig.55B], the model layers under NN2.0 include scaling layers for input and output, as well as the logarithmically quantized layers to transform the model in [Fig.55A] into a NN2.0 model. . [Fig. 56] illustrates an example of a typical binary multiplication occurring in hardware, according to an example implementation. The example multiplication occurring in hardware may use binary numbers. For example, as shown in [Fig. 56], a data 5601 may have a value of 6, and a parameter 5602 may have a value of 3. Both data 5601 and parameter 5602 are 16-bit data, so the 16-bit parameter data will come in and be multiplied by a 16x16 multiplier using a multiplier 5603 which will generate a 32-bit number 5604. The 32-bit number may be truncated using a truncation operation 5605 to produce a 16-bit number 5606 if desired. The 16-bit number 5606 will have a value of 18. [Fig.57] and 58 illustrate an example of a shift operation for NN2.58, according to an implementation example. Specifically, [Fig.57] illustrates an example of the shift operation for NN2.0, and [Fig.58] illustrates an example flow of the shift operation for NN2.0. In 5801, the stream scales the data by a data scaling factor. In the example of [Fig.57], the input data 5701 may have a value of 6 and the input data is scaled by a scaling factor of 2!°, The data scaling factor may produce scaled data. Other data scaling factors may be used, and the disclosure is not intended to be limited to the examples provided herein. The input data 5701 is scaled by multiplying the input data 5701 by the data scaling factor of 2!°, which gives the scaled data a value of 6.144, The 16-bit binary representation of the scaled data is 0001100000000000. At 5802, the stream shifts the scaled data based on a shift instruction derived from the logarithmically quantized parameter. In the example in [Fig.57], parameter 5702 has a value of 3, and parameter 5702 is logarithmically quantized to generate a shift instruction to shift the scaled data. Parameter 5702 is logarithmically quantized, where the method for logarithmically quantizing the value +3 is as follows: quantif-log(+3) => +2swrndi (og2(3)) — 4 Rounded (+1.5649) 49642) — 44, The shifting in 5802 is conducted in accordance with shift instructions that are provided to the shifter 5709. The shift instructions may include one or more of the sign bit 5704, the shift direction 5705, and the shift magnitude 5706. The shift instruction 5703 derived from a logarithmically quantized parameter is presented as 6-bit data, where a sign bit 5704 is the most significant bit of the shift instruction 5703, a shift direction 5705 is the second most significant bit, and a shift magnitude 5706 are the remaining 4 bits of the shift instruction 5703. The sign bit 5704 having a value of 0 or 1 is based on the sign of the logarithmically quantized parameter. For example, sign bit 5704 having a value of 0 is indicative of the positive sign of the logarithmically quantized parameter. Sign bit 5704 having a value of 1 would be indicative of the negative sign of the logarithmically quantized parameter.In the example of [Fig.57], the parameter +3 has a positive sign, so the sign bit 5704 has a value of 0. The shift direction 5705 having a value of 0 or 1 is based on the sign of the exponent of the logarithmically quantized parameter. For example, the shift direction 5705 having a value of 0 is based on the exponent having a positive sign, which corresponds to a left shift direction. The shift direction 5705 having a value of 1 is based on the exponent having a negative sign, which corresponds to a right shift direction. In the example of [Fig.57], the exponent (+2) of the logarithmically quantized parameter has a positive sign, so the shift bit 5705 has a value of 0, which corresponds to a left shift direction. The magnitude of the 5706 shift is based on the magnitude of the exponent of the logarithmically quantized parameter. In the example in [Fig.57], the exponent has a magnitude of 2, so the magnitude of . shift 5706 is 2. Shift magnitude 5706 is composed of the last 4 bits of shift instruction 5703, so shift magnitude 5706 of 2 corresponds to 0010. With the determination of shift direction 5705 and shift magnitude 5706, the shift can be applied to the scaled data. The scaled data, shift direction, and shift magnitude are input to a shifter 5709. Shifter 5709 can be a 16-bit shifter as shown in this example because the scaled data is represented as 16-bit data. The shifter 5709 applies the shift operation based on the shift direction 5705 (left direction) and the shift magnitude 5706 (2), to generate a shifted value 5710 of 0110000000000000, which corresponds to 24.576. The mathematically equivalent operation, using multiplication, to the shift operation that has been shown is as follows.The scaled data has a value of 6.144 and the logarithmically quantified value of the +3 parameter is +4, and the product of 6.144 x 4 = 24.576. The shift operation for NN2.0 achieves the same result by shifting, and without a multiplication operation. At 5803, the flow performs an XOR operation of the data sign bit and the sign bit of the shift instruction to determine a sign bit of a shifted value. In the example in [Fig.57], the data sign bit 5707 has a value of 0 and the sign bit 5704 of the shift instruction has a value of 0. Both values are input into XOR 5708, and 0 XOR 0 gives 0, so the sign bit 5711, of the shifted value 5710, has a value of 0. At 5804, the stream sets a sign bit of the shifted value. The sign bit 5711 of the shifted value 5710 is based on the results of the XOR 5708. In the example in [Fig.57], the result of the XOR between sign bit 5704 and sign bit 5707 is 0, so sign bit 5711 is set to 0. [Fig.59] illustrates an example of a shift operation for NN2.0, according to an example implementation. The flow of the shift operation for NN2.0 in [Fig.59] is consistent with the flow in [Fig.58]. The example in [Fig.59] has a different parameter value than the parameter in the example in [Fig.57]. For example, parameter 5902 in [Fig.59] has a value of -0.122, which is logarithmically quantized as quantif-log(-0.122) = -2rounded 0og,(0.122) 5 Zamondi (3.035) 5 1269 = 0.125. Therefore, the sign bit 5904 has a value of 1, due to the sign of the logarithmically quantized parameter, and the shift direction 5905 has a value of 1, due to the sign of the exponent of the logarithmically quantized parameter. The shift magnitude is 3 due to the exponent number, which has a magnitude of 3. The shift magnitude 5906 is in binary form within the last 4 bits of the logarithmically quantized parameter 5903.The shift direction 5905, shift magnitude 5906 and scaled data 5901 are entered. into shifter 5909 to apply the shift amount and shift direction to the scaled data, resulting in a shifted value 5910 of -768. The shifted value 5910 has a negative sign due to the XOR of sign bit 5904 and sign bit 5907, resulting in a value of 1 for sign bit 5911. Sign bit 5911 having a value of 1 results in the shifted value 5910 having a negative sign, so the shifted value 5910 has a value of -768. The scaled data has a value of 6 x 2° = 6.144, and the logarithmically quantized parameter value has a value of -24* = -0.125. The product of the scaled data and the logarithmically quantified parameter is 6.144 x -0.125 = -768. The shifted value 5910 has a value of -768, obtained by using the shifter and not by using a multiplication. The shift operation for NN2.0 achieves the same result by shifting, and without a multiplication operation. [Fig.60] and [Fig.61] illustrate an example of a shift operation for NN2.0 using two's compliment data, according to an implementation example. Specifically, [Fig.60] illustrates an example of the shift operation for NN2.0 using two's compliment data, and [Fig.61] illustrates an example flow of the shift operation for NN2.0 using two's compliment data. At 6101, the stream scales the data by a data scaling factor. In the example of [Fig. 60], the input data 6001 may have a value of 6 and the input data is scaled by a scaling factor of 2". The data scaling factor may produce data that is represented as 16-bit data. Other data scaling factors may be used, and the disclosure is not intended to be limited to the examples provided herein. The input data 6001 is scaled by multiplying the input data 6001 by the data scaling factor of 2, resulting in the scaled data having a value of 6.144. The 16-bit scaled data represented as a binary number is 0001100000000000. At 6102, the stream performs an arithmetic shift of the scaled data based on a shift instruction. In the example in [Fig.60], parameter 6002 has a value of 3, and parameter 6002 is logarithmically quantized to produce the shift instruction to shift the scaled data. The parameter 6002 is logarithmically quantized, where the process of logarithmically quantizing the value +3 is as follows: quantif-log(+3) => +2rounded doe,G) = 4262) = +4, The shift instruction 6003 derived from a logarithmically quantized parameter is presented as 6-bit data, where a sign bit 6004 is the most significant bit of the shift instruction 6003, a shift direction 6005 is the second most significant bit, and a shift magnitude 6006 are the remaining 4 bits of the parameter logarithmically quantized. Sign bit 6004 having a value of 0 or 1 is based on the sign of the logarithmically quantized parameter. For example, sign bit 6004 having a value of 0 is indicative of the positive sign of the logarithmically quantized parameter. Sign bit 6004 having a value of 1 would be indicative of the negative sign of the logarithmically quantized parameter. In the example in [Fig.60], the +3 parameter has a positive sign, so sign bit 6004 has a value of 0. Shift direction 6005 having a value of 0 or 1 is based on the sign of the exponent of the logarithmically quantized parameter. For example, shift direction 6005 having a value of 0 is based on the exponent having a positive sign, which corresponds to a left shift direction. The shift direction 6005 having a value of 1 is based on the exponent having a negative sign, which corresponds to a right shift direction. In the example of [Fig.60], the exponent (2) of the logarithmically quantized parameter has a positive sign, so that the shift bit 6005 has a value of 0, which corresponds to a left shift direction. The magnitude of the shift 6006 is based on the magnitude of the exponent of the logarithmically quantized parameter. In the example of [Fig. 60], the exponent has a magnitude of 2, so the shift magnitude 6006 is 2. The shift magnitude 6006 is composed of the last 4 bits of the shift instruction data 6003, so the shift magnitude 6006 of 2 corresponds to 0010. With the determination of the shift direction 6005 and the shift magnitude 6006, the shift can be applied to the scaled data. The scaled data, shift direction, and shift magnitude are fed into a 6009 arithmetic shifter.The arithmetic shifter 6009 may be a 16-bit arithmetic shifter as shown in this example because the scaled data is represented as 16-bit data. The arithmetic shifter 6009 applies the shift operation based on the shift direction 6005 (left direction) and the shift magnitude 6006 (2), to generate a shifted value 6010 of 0110000000000000. . At 6103, the stream performs an XOR operation of the shifted data with a sign bit of the shift instruction. In the example of [Fig.60], the sign bit 6004 has a value of 0 which is fed into XOR 6011 with the shifted value 6010 (output of arithmetic shifter 6009). The result of the XOR operation between the sign bit 6004 and the shifted value 6010 gives the shifted value 6012. In the example of [Fig.60], since the sign bit 6004 has a value of 0, the shifted value 6012 is not changed from the shifted value 6010 as a result of the XOR operation between the sign bit 6004 and the shifted value 6010. At 6104, the stream increments a value of the XOR result by 1 if the sign bit of the shift instruction is 1. In the example in [Fig.60], the shifted value 6012 is input to an incrementer (e.g. +1 or 0), which is populated with the sign bit 6004. The sign bit 6004 of the shift instruction is 0, so the stream does not increment the shifted value 6012 of the XOR results and gives the shifted value 6013. [Fig.62] illustrates an example shift operation for NN2.0 using two's compliment data, according to an example implementation. The flow of the shift operation for NN2.0 in [Fig.62] is consistent with the flow in [Fig.61]. The example in [Fig.62] has a different shift instruction than the shift instruction in the example in [Fig.60]. For example, parameter 6202 in [Fig.62] has a value of -0.122, which is logarithmically quantized to produce the shift instruction to shift the scaled data. The parameter 6202 is logarithmically quantized, where the method of logarithmically quantifying the value -0.122 is as follows: quantif-log(-0.122) => -2amondilos,(0.122) = +2arondit3035) 263 = 0.125.The shift instruction derived from the logarithmically quantized parameter 6203 is presented as 6-bit data, where a sign bit 6204 is the most significant bit of the shift instruction 6203, a shift direction 6205 is the second most significant bit, and a shift magnitude 6206 are the remaining bits of the logarithmically quantized parameter 6203. The sign bit 6204 has a value of 1, due to the negative sign of the logarithmically quantized parameter, and the shift direction 6205 has a value of 1, due to the sign of the exponent of the logarithmically quantized parameter. The shift magnitude is 3 because of the exponent number, which has a magnitude of 3. The magnitude of the shift 6206 is based on the magnitude of the exponent of the logarithmically quantized parameter. In the example of [Fig.62], the exponent has a magnitude of 3, so the shift amplitude 6206 is 3.The shift magnitude 6206 is in binary form within the last 4 bits of the shift instruction 6203, so the shift magnitude 6206 of 3 corresponds to 0011. The shift direction, shift magnitude, and scaled data are input to the 16-bit arithmetic shifter 6209 to apply the shift magnitude and shift direction to the scaled data 6201, producing a shifted value 6210 of 0000001100000000. The shifted value 6210 and the sign bit 6204 of the shift instruction are input to XOR 6211. The result of the XOR operation between the sign bit 6204 and the shifted value 6210 results in the shifted value 6212. The output of the XOR result (e.g., the shifted value 6212) and the sign bit are input to an incrementer (e.g. +1 or 0). The incrementer can increment the shifted value 6212 by 1 if the sign bit of the shift instruction is 1. In the example in [Fig.62], the sign bit 6204 of the shift instruction is 1, so the shifted value 6212 is incremented by 1 due to the sign bit of the shift instruction having a value of 1. As a result, the shifted value 6212 is incremented to generate the shifted value . 6213 of 0000001100000000. The shifted value 6213 has a value of -768. The scaled data has a value of 6 x 2° = 6.144, and the logarithmically quantified parameter has a value of -24 = -0.125. The product of the scaled data and the logarithmically quantified parameter is 6.144 x -0.125 = -768. The shifted value 6212 has a value of -768, obtained by using the shifter and not by using multiplication. The shift operation for NN2.0 achieves the same result by shifting, and without a multiplication operation. [Fig. 63] and 64 illustrate an example of an accumulator / add operation for a NN2.0 where the add operation can be replaced by a shift operation, according to an example implementation. Specifically, [Fig. 63] illustrates an example of the accumulator / add operation for NN2.0, and [Fig. 64] illustrates an example flow of the accumulator / add operation for NN2.0. The accumulator operation for NN2.0 can use shift operations to perform an accumulation or addition of N numbers of signed magnitude data using two distinct sets of shifts, positive accumulation shifts for positive numbers and negative accumulation shifts for negative numbers. At 6401, the stream divides a magnitude portion of data into a plurality of segments. In the example of [Fig. 63], the magnitude portion of data 6301 is divided into six 5-bit segments specified as seg! — seg6. However, in some cases, the magnitude portion of data may be divided into a plurality of segments, and the description is not intended to be limited to six segments. The 30th bit may be reserved for future use, the 31st bit is a sign bit 6304, while the remaining bits include the six 5-bit segments and the reserved 30th bit. At 6402, the flow enters each segment into both the positive accumulator shifter and the negative accumulator shifter. In the example of [Fig.63], the first segment (seg1) of the first data string (data #1) is entered into the positive accumulator shifter 6302 and the negative accumulator shifter 6303. The other segments (seg2 - seg6) have the same positive accumulator and negative accumulator structure as the segment]. Alternatively, one can have an architecture in which all 6 segments share the same positive accumulator shifter and the same negative accumulator shifter with appropriate buffers to store the intermediate results of the shift operation for all segments. At 6403, the stream determines to perform a shift operation based on a sign bit. In the example in [Fig.63], sign bit 6304 is used by shifters 6302 and 6303 to determine the shift operation. For example, if sign bit 6304 has a value of 0, which corresponds to a positive number, then the positive accumulative shift operation will be performed. If sign bit 6304 has a value of 1, which corresponds to a negative number, then the negative accumulative shift operation will be performed. Each data (data #1, data #2, … data #N) has a corresponding sign bit 6304. At 6404, the stream shifts the data by a shift amount represented by the segment value. At the beginning of the operation, the shifter receives a constant | as input to the shifter. The shifter then receives the output of the shifter as input to the shifter for all subsequent operations. At 6405, the stream continues the process of 6401-6404 for each segment and data string, until all data has been processed. [Fig.65] and [Fig.66] illustrate an example of overflow processing for an add operation for NN2.0 using a shift operation, according to an implementation example. Specifically, [Fig.65] illustrates an example of the overflow processing for the add operation for NN2.0 using shifters, and [Fig.66] illustrates an example flow of the overflow processing for the add operation for NN2.0 using shifters. At 6601, the flow enters the first segment overflow signal (segl) from the shifter into an overflow counter. In the example of [Fig.65], the overflow signal from shifter 6501 is input to overflow counter 6502. At 6602, when the overflow counter seg1 reaches a maximum value, the flow enters an output of the overflow counter segl into a shifter seg2 as a shift amount to shift the data of seg2 according to the value of the overflow counter from the overflow counter segl. In the example of [Fig.65], the data of the overflow counter 6502 is input into the overflow seg| 6503, and when the segl overflow 6503 reaches a maximum value, the output of the seg1 overflow 6503 is received as an input by the shifter 6504. The shifter 6504 will use the input of the segl overflow 6503 as a shift magnitude to shift the seg2 data by a magnitude corresponding to an overflow counter value provided by the segl overflow 6503. At 6603, when the seg2 overflow counter reaches a maximum value, the flow enters an output of the seg2 overflow counter into a seg3 shifter as a shift amount to shift the data of seg3 based on the value of the overflow counter from the seg2 overflow counter. In the example of [Fig.65], the data from the 6505 overflow counter is input to the seg2 overflow 6506, and when the seg2 overflow 6506 reaches a maximum value, the output of the seg2 overflow 6506 is received as an input by a third shifter (not shown). The third shifter will use the input of the seg2 overflow 6506 as a shift amount to shift the data of the seg3 with an amplitude corresponding to an overflow counter value provided by the overflow of seg2 6503. At 6604, the stream determines whether all data segments have been processed. If not, then the process from 6601-6603 repeats until all data segments have been processed. [Fig. 67] and 68 illustrate an example of a segment assembly operation for NN2.0, according to an example implementation. Specifically, [Fig. 67] illustrates an example of the segment assembly operation for NN2.0, and [Fig. 68] illustrates an example flow of the segment assembly operation for NN2.0. The segment assembly operation can assemble the output of the accumulation operations of the 6 segments. In 6801, after the accumulation shift is performed, the flow converts the output data, which is a one-hot binary number, into a coded binary number. For example, the output data 6701-1 may comprise 32-bit one-hot data that is converted into a 5-bit coded binary number 6702-1. The output one-hot data of each of the 6 segments is converted into a 5-bit coded binary number. In the example of [Fig.67], the conversion of the first, second, fifth, and sixth segments is shown, while the conversion of the third and fourth segments is not shown. In 6802, the stream concatenates the segments into a 30-bit data 6703. The 6 segments are concatenated to form the 30-bit data, and their placement in the 30-bit data is ordered according to the segment numbering. For example, the first 5-bit binary number 6702-1 is placed at the position of bits numbered 0-4, followed by the second 5-bit binary number 6702-2, then the third, then the fourth, then the fifth 6702-5, and ends with the sixth 5-bit binary number 6702-6 at the end of the 30-bit data. At 6803, the stream concatenates a sign bit 6704 and a 305 bit 6705 to the 30-bit data 6703. The combination of the sign bit 6704, the 305 bit 6705, and the 6 segments that form the 30-bit data 6703 form a 32-bit data 6706.The example in [Fig.67] shows the formation of the 32-bit data 6706 which is for "accumulate + assembly". A similar procedure occurs for "accumulate - assembly", but is not shown here to reduce redundant explanations. At 6804, the stream performs segment assembly. As shown in [Fig.69], after the segment assembly procedure has been executed for "accumulate +" and "accumulate -", the data (6901, 6902) of "accumulate +" and "accumulate -" are input to an adder 6903 and are added together to form the final data. [Fig.70] and 71 illustrate an example of an accumulation / addition operation for a NN2.0 where the addition operation can be replaced by a shift operation, according to an example implementation. Specifically, [Fig.70] illustrates an example of the accumulation / addition operation for NN2.0, and [Fig.71] illustrates an example flow of the accumulation / addition operation for NN2.0. The accumulation operation for NN2.0 can use shift operations to perform accumulation or addition of N numbers of signed magnitude data using a set of shifters that can shift both right and left for each of the positive and negative data. At 7101, the stream divides a magnitude portion of data into a plurality of segments. In the example of [Fig. 70], the magnitude portion of data 7001 is divided into six 5-bit segments specified as seg! — seg6. However, in some cases, the magnitude portion of data may be divided into a plurality of segments, and the description is not intended to be limited to six segments. The 30th bit may be reserved for future use, the 31st bit is a sign bit 7003, while the remaining bits include the six 5-bit segments and the reserved 30th bit. At 7102, the stream enters each segment into a shifter. In the example of [Fig.70]. segments 7001 data are entered into a shifter 7002. The other segments (seg2-seg6) have the same shifter structure as segment1. Alternatively, one can have an architecture in which all 6 segments share the same shifter with appropriate buffers to store the intermediate results of the shift operation for all segments. At 7103, the stream determines to perform a shift operation based on a sign bit. In the example in |Fig.70], the sign bit 7003 is used by the shifter 7002 to determine the shift direction. For example, if the sign bit 7003 has a value of 0, then the data is shifted to the left. If the sign bit 7003 has a value of 1, then the data is shifted to the right. At 7104, the stream shifts the data by a shift amount represented by the segment value. At the beginning of the operation, the shifter receives a constant 1 as the shifter input. The shifter then receives the output of the shifter as the shifter input for all subsequent operations. At 7105, the flow continues the process from 7101-7104 until all input data is processed. [Fig. 72] illustrates an example of a general AI Processing Element (AIPE) architecture, according to an example implementation. The AIPE is configured to process several neural network operations, such as, but not limited to, convolution, dense layer, ReLU, leaky ReLU, max pooling, addition, and / or multiplication. The AIPE may include many different components, such as a shifter circuit 7201 that receives the data 7202 and the parameter 7203 as inputs. The AIPE may also include an adder circuit or shifter circuit 7204 which receives as input the output of the shifter circuit 7201. The AIPE may also include a register circuit such as a flip-flop 7205 which receives as input the output of the adder circuit or the shifter circuit 7204. The output of the register circuit such as the flip-flop 7205 is returned to the AIPE and is multiplexed with the data 7202 and the parameter 7203. As illustrated in [Fig.72], the AIPE may include at least one shifter circuit 7201 that is configured to accept a shiftable input 7206 derived from input data (M1, M2) for a neural network operation, accept a shift instruction 7207 derived from a corresponding logarithmically quantized parameter 7203 of a neural network or a constant value such as const 0 as shown in [Fig.72]; and shift the shiftable input in a leftward direction or a rightward direction in accordance with the shift instruction 7207 (e.g., as illustrated in [Fig.57] to 63) to form a shifted output 7208 (Mout) representative of a multiplication of the input data with the corresponding logarithmically quantized parameter of the neural network.Such a shifter circuit 7201 may be any shifter circuit known in the art, such as, but not limited to, a logarithmic shifter circuit or a barrel shifter circuit. As described herein, the input data may be scaled to form the shiftable input 7206 through streams as illustrated in [Fig. 37] and 38. Such streams may be executed by dedicated circuitry, by a computing device, or by any other desired implementation. In an exemplary implementation, as illustrated in [Fig. 57] to 62 based on the architecture of [Fig. 72], the shift instruction may include a shift direction (e.g., 5705, 5905, 6005, 6205) and a shift magnitude (e.g., 5706, 5906, 6006, 6206), the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized parameter (e.g., 5702, 5902, 6002, 6202), the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized parameter; wherein the shifter circuit shifts the shiftable input in the leftward direction or the rightward direction depending on the shift direction and shifts the shiftable input in the shift direction by a magnitude indicated by the shift amplitude as shown, e.g. at 5710, 5910, 6010 and 6210. Although example implementations use a shift instruction as derived from the logarithmically quantized parameter as described herein, the present disclosure is not limited thereto and other implementations are also possible. For example, the shift instruction may be derived from data as input to shift a scaled parameter (e.g., scaled from a floating-point parameter, an integer parameter, or the like) if desired. In such an example implementation, if logarithmically quantized data values are available, then the shift instruction can be similarly derived from the logarithmically quantized data value. For example, the shift amount can thus be derived from a magnitude of an exponent of the corresponding logarithmically quantized data value, and the shift direction can be derived from a sign of the exponent of the corresponding logarithmically quantized value to generate shift instructions for shifting a scaled parameter value. Such implementations are possible because the operation is equivalent to a multiplication between the data and parameter resulting from shifting a value by a shift instruction derived from a logarithmically quantized value. In an exemplary implementation based on the architecture of [Fig. 72] and the exemplary implementations of [Fig. 57] through 62, the AIPE may further involve a circuit such as an XOR circuit (e.g., 5708, 5908) or any equivalent thereof configured to admit a first sign bit (5707, 5907) of the shiftable input and a second sign bit (e.g., 5704, 5904) of the corresponding logarithmically quantized parameter to form a third sign bit (e.g., 5711, 5911) for the shifted output. In an exemplary implementation based on the architecture of [Fig.72] extended in the example of [Fig.73] and 74, and the exemplary implementations of [Fig.57] to 64, the AIPE may further comprise a first circuit such as an XOR circuit (e.g., 6011, 6211, 7311) or its equivalent configured to accept the shifted output (e.g., 6010, 6210, 7310) and a sign bit (e.g., 6004, 6204, 7306) of the corresponding one of the logarithmically quantized parameters to form the one's complement data (e.g., 7405, 7406); and a second circuit such as an incrementer / adder circuit (7204, 7302) configured to increment the one's complement data by the sign bit of the corresponding logarithmically quantized parameter to change the one's complement data to two's complement data (e.g., 7405, 7406) that is representative of multiplying the input data with the corresponding logarithmically quantized parameter. In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the examples of Figs. 73-82, the AIPE may include a circuit such as a multiplexer 7210 or any equivalent thereof, configured to accept the output of the neural network operation, wherein the circuit provides the shiftable input from the output (e.g., M2) of the neural network operation or from scaled input data (e.g., 7202, M1) generated from the input data for the neural network operation according to a signal input (s1) to the shifter circuit 7201. Such a circuit (e.g., the multiplexer 7210) may accept a control signal (s1) to control which of the circuit's inputs is provided to the shifter circuit 7201. In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the examples of Figs. 73-82, the AIPE may include a circuit such as a multiplexer 7211 configured to provide the shift instruction derived from the corresponding logarithmically quantized parameter of the neural network (e.g., K) or the constant value (e.g., const 0) according to a signal input (s2). In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the examples of Figs. 73-82, the AIPE may include an adder circuit 7204, 7302 coupled to the shifter circuit, the adder circuit 7204, 7302, 7608 configured to add based on the shifted output to form an output (e.g., Out, aout) for the neural network operation. Such an adder circuit 7204, 7302, 7608 may take the form of one or more shifters, an integer adder circuit, a floating point adder circuit, or any circuit equivalent thereto depending on the desired implementation. In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the examples of Figs. 73-82, the adder circuit 7204, 7302, 7608 is configured to add the shifted output to a corresponding one of a plurality of bias parameters 7305 of the trained neural network to form the output (aout) for the neural network operation. In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the exemplary implementations of [Fig. 62] through 72, the AIPE may include a further shifter circuit 7204; and a register circuit such as output flip-flops 7205 and / or a multiplexer 7209, or equivalents thereto coupled to the further shifter circuit 7204 that latches the output (Out) from the further shifter circuit. As illustrated, for example, in [Fig. 70], the further shifter circuit 7204 is configured to admit a sign bit S associated with the shifted output and each segment of the shifted output to shift a further shifter circuit input left or right based on the sign bit to form the output from the further shifter circuit. In an exemplary implementation based on the architecture of [Fig. 72] and as extended in the exemplary implementations of [Fig. 62] to 72, the AIPE may include a counter such as an overflow counter (e.g., 6502, 6505) configured to admit an overflow or underflow (e.g., 6503, 6506) from the other shifter circuit resulting from the shifter circuit shifting the input of the other shifter circuit; wherein the other shifter circuit is configured to admit the overflow or underflow from each segment to shift a subsequent segment left or right by an overflow or underflow magnitude as illustrated in [Fig. 65] and 70. Such a counter can be implemented according to the desired implementation with any circuit known in the art. In an exemplary implementation based on the architecture of [Fig. 72], the AIPE may include a 1-of-n to binary encoding circuit such as circuit 6710 or any equivalent thereof that performs the functions of [Fig. 67] and [Fig. 70]. The 1-of-n to binary encoding circuit is configured to admit the latched output to generate an encoded output, and concatenate the encoded output from all segments and a sign bit from the result of an overflow or underflow operation to form the output for the neural network operation (6701-6706). In an example implementation based on the architecture of [Fig. 72], the AIPE may include a positive accumulator shifter circuit 6302 including a second shifter circuit configured to admit each segment of the shifted output to shift the input of the positive accumulator shifter circuit to the left for a sign bit associated with the shift instruction indicating a positive sign; the second shifter circuit coupled to a first register circuit configured to latch the input of the shifted positive accumulator shifter circuit from the second shifter circuit as a first latched output, the first register circuit configured to provide the first latched output as an input of the positive accumulator shifter circuit for receipt of a signal indicating that the neural network operation is not complete;a negative accumulator shifter circuit 6303 comprising a third shifter circuit configured to admit each segment of the shifted output to shift the input of the negative accumulator shifter circuit to the left for the sign bit associated with the shift instruction indicating a negative sign; the third shifter circuit coupled to a second register circuit configured to latch the input of the negative accumulator shifter circuit shifted from the third shifter circuit as a second latched output, the second register circuit configured to provide the second latched output as an input of the negative accumulator shifter circuit for receipt of a signal indicating that the neural network operation is not complete;and an adder circuit 6903 configured to add based on the first latched output 6901 from the positive accumulator shifter circuit and the second latched output 6902 from the negative accumulator shifter circuit to form the output of the neural network operation for receiving the signal indicating that the neural network operation is complete. ; In an example implementation based on the architecture of [Fig.72] and extended in the example of [Fig.81], for the neural network operation to be a parametric ReLU operation, the shifter circuit 8107 is configured to provide the shiftable input as a shifted output without performing a shift for a bit of sign of the shiftable input which is positive. [Fig. 73] illustrates an example AIPE having an arithmetic shift architecture, according to an example implementation. The AIPE of [Fig. 73] uses an arithmetic shifter 7301 and an adder 7302 to process neural network operations, such as, but not limited to, convolution, dense layer, ReLU, parametric ReLU, batch normalization, max pooling, addition, and / or multiplication. The arithmetic shifter 7301 receives, as input, the data 7303 and the shift instruction 7304 derived from the logarithmic quantization parameter. The data 7303 may comprise 32-bit data based on a two's compliment, while the shift instruction 7304 may comprise 7-bit data. The arithmetic shifter 7301 may comprise a 32-bit arithmetic shifter. Arithmetic shifter 7301 shifts data 7303 based on shift instruction 7304.The output of arithmetic shifter 7301 passes through a circuit that transforms the output into two's compliment data and is then added to a bias 7305. The bias 7305 may include a 32-bit bias. Adder 7302 receives three inputs, the output of multiplexer (mux) M3 and the output of XOR 7311, and a carry input (Ci) from sign bit 7306 of shift instruction 7304. The adder adds the two inputs and the carry input to form the output, which goes into mux M4. The output of mux M4 is latched by flip-flop 7307. The output of flip-flop 7307 can then be fed back into mux M1 for another neural network operation, and the sign bit of the ffout of flip-flop 7307 can be used for OR circuit 7312 to control mux M2 to choose between the shift instruction 7304 or a constant 1. [Fig.74] illustrates an example of an AIPE operation using a shifter and an adder, according to an example implementation. AIPE uses the shift operation to replace the multiplication. For example, if data 7401 has a value of 12 and the shift instruction 7402, derived from the logarithmically quantified parameter, has a value of +2, the multiplication of the data and the shift instruction is 12 x (+2), which can be written as 12 x (+2!) where (+2+!) is the logarithmically quantified parameter. The sign of the parameter exponent is positive (+), which means the direction of the shift is to the left, and the magnitude of the exponent is 1, which means the magnitude of the shift is 1. Thus, data 12 is shifted to the left by 1. Shifting data 12 to the left by 1 gives 24, as shown in 7403 in [Fig.74].In another example, data 7401 has a value of 12, while shift instruction 7402 has a value of +0.5. The multiplication of the data and the shift instruction is 12 x (+0.5), which can be written as 12 x (+2") where (+27) is the logarithmically quantified parameter. The sign of the parameter's exponent is negative (-), which means that the . shift direction is to the right, and the magnitude of the exponent is 1, which means the magnitude of the shift is 1. Thus, data 12 is shifted to the right by 1. Shifting data 12 to the right by 1 gives 6, as shown in 7404 in [Fig.74]. In another example, data 7401 has a value of 12 and the shift instruction 7402 has a value of -2, the multiplication of the data and the shift instruction is 12 x (-2), which can be written as 12 x (-2+!) where (-2#) is the logarithmically quantified parameter. The sign of the parameter's exponent is positive (+), which means the shift direction is to the left, and the magnitude of the exponent is 1, which means the magnitude of the shift is 1. Thus, data 12 is shifted to the left by 1.However, the base of the parameter has a negative value, as such the shifted value encounters a two's compliment procedure to result in -24, as shown at 7405 of [Fig.74]. In another example, data 7401 has a value of 12 and shift instruction 7402 has a value of -0.5. The multiplication of the data and the shift instruction is 12 x (-0.5), which can be written as 12 x (-0.5"!) where (-0.5-!) is the logarithmically quantified parameter. The sign of the parameter exponent is negative (-), meaning the direction of the shift is to the right, and the magnitude of the exponent is 1, meaning the magnitude of the shift is 1. Thus, the data 12 is shifted to the right by 1. However, the base of the parameter has a negative value, as such the shifted value encounters a two's compliment procedure to end up as -6, as shown at 7406 of [Fig.74]. . [Fig. 75] illustrates an example of an AIPE operation using a shifter and an adder, according to an example implementation. AIPE uses the shift operation to replace the multiplication. For example, if data 7501 has a value of -12 and the shift instruction 7502, derived from the logarithmically quantified parameter, has a value of +2, the multiplication of the data and the shift instruction is -12 x (+2), which can be written as -12 x (+2*!) where (+2!) is the logarithmically quantified parameter. The sign of the parameter exponent is positive (+), which means the direction of the shift is to the left, and the magnitude of the exponent is 1, which means the magnitude of the shift is 1. Thus, data - 12 is shifted to the left by 1. Shifting data -12 to the left by 1 gives -24, as shown in 7503 in [Fig.75].In another example, data 7501 has a value of -12, while shift instruction 7502 has a value of +0.5. The multiplication of the data and the shift instruction is -12 x (+0.5), which can be written as -12 x (+2-!) where (+2-!) is the logarithmically quantified parameter. The sign of the parameter's exponent is negative (-), meaning the direction of the shift is to the right, and the magnitude of the exponent is 1, meaning the magnitude of the shift is 1. Thus, data -12 is shifted to the right. of 1. Shifting data -12 to the right by 1 gives -6, as shown at 7504 in [Fig.75]. In another example, data 7501 has a value of -12 and shift instruction 7502 has a value of -2, the multiplication of the data and the shift instruction is -12 x (-2), which can be written as -12 x (-2#) where (-2H) is the logarithmically quantified parameter. The sign of the parameter exponent is positive (+), meaning the direction of the shift is to the left, and the magnitude of the exponent is 1, meaning the magnitude of the shift is 1. Thus, data -12 is shifted to the left by 1. However, the base of the parameter has a negative value, as such the shifted value encounters a two's compliment procedure to result in +24, as shown at 7505 of [Fig.75]. In another example, data 7501 has a value of -12 and shift instruction 7502 has a value of -0.5.The multiplication of the data and the shift instruction is -12 x (-0.5), which can be written as -12 x (-0.5"!) where (-0.5-) is the logarithmically quantified parameter. The sign of the parameter exponent is negative (-), meaning the direction of the shift is to the right, and the magnitude of the exponent is 1. meaning the magnitude of the shift is 1. Thus, the data -12 is shifted to the right by 1. However, the base of the parameter has a negative value, as such the shifted value encounters a two's compliment procedure to end up as -6, as shown at 7506 of [Fig.75]. . [Fig. 76], 77 and 78 illustrate an example of an AIPE performing a convolution operation, according to an example implementation. Specifically, [Fig. 76] illustrates an example of the AIPE architecture configured to perform the convolution operation, [Fig. 77] illustrates an example flow of an initial cycle of the convolution operation, and [Fig. 78] illustrates an example flow of subsequent cycles of the convolution operation. The AIPE may perform the convolution operation using an arithmetic shifter. At 7701, for the initial cycle of the convolution operation, the stream loads data 7601 and shift instruction 7602 derived from logarithmic quantization of the corresponding parameter. Data 7601 may include a plurality of data values (X1, X2, .. X9) as an example. Shift instruction SH 7602 may be derived from parameter values (K1, K2, … K9) to form shift instructions (SH1, SH2, … SH9) corresponding to each of these parameter values. In the example of [Fig. 76], data 7601 and shift instruction 7602 have 9 values, but the disclosure is not intended to be limited to the examples disclosed herein. Data 7601 and shift instruction 7602 may have one or more values. In the initial cycle of the convolution operation, the stream loads X1 into data 7601 and SHI into shift instruction 7602. At 7702, the flow sets a control bit for the data mux M1 and a control bit for the parameter mux M2. Control bit 7603 for data 7601 can be set to 0. Control bit 7604 for parameter can be set to 1. At 7703, the stream shifts the data by the shift instruction. The data 7601 and the shift instruction 7602, derived from the logarithmically quantized parameter, are input to an arithmetic shifter 7605, and the arithmetic shifter 7605 shifts the data 7601 by the shift amount based on the shift instruction 7602. Then, the output of the arithmetic shifter 7605 is converted to two's complement data. The output of the arithmetic shifter 7605 is input to an adder 7608. At this point, the output of the arithmetic shifter 7605 includes the value (X1*K1) of the first cycle of the convolution process. However, the value of the first cycle of the convolution process is obtained by using the arithmetic shifter 7605, not by using a multiplication operation. The convolution process is the sum of the product of each data and parameter (X1*K1 + X2*K2 + … + X9*K9). At 7704, the stream loads a bias with a bias value, and sets a control bit for the bias mux M2. Bias 7606 is loaded with the bias value, and bias control bit 7607 is set to 1. Bias 7606 loaded with the bias value is fed into adder 7608. At 7705, the stream processes the shifted data and bias via the adder. The output of the arithmetic shifter 7605 or the shifted data is added to the bias 7606 by the adder 7608. In the first cycle of the convolution process, the bias is added. In 7706, the stream captures the output of the adder. The output of the 7608 adder is fed to a 7610 flip-flop and is captured. At 7801, for subsequent cycles of the convolution operation, the stream loads the data and the shift instruction derived from the logarithmic quantization parameter. For example, after the initial cycle, the stream loads the data 7601 with X2 and the shift instruction 7602 with SH2 for the second cycle. In subsequent cycles, the output of the previous cycle is returned to the bias mux M3 for the subsequent cycle. For example, in the second cycle, the captured output of the first cycle adder is sent by flip-flop 7610 to the bias mux M3 for the input of adder 7608. In 7802, the flow sets the control bit for the data mux and the control bit for the parameter mux. The control bit 7603 for the data 7601 can be set to 0. The control bit 7604 for the parameter can also be set to 1. In 7803, the stream shifts the data by a shift instruction. The data 7601 and the shift instruction 7602 derived from the quantized parameter logarith- The data of the subsequent cycle are fed into an arithmetic shifter 7605, and the arithmetic shifter 7605 shifts the data 7601 by the shift amount based on the shift instruction 7602. Then, the output of the arithmetic shifter 7605 is converted to two's complement. The output of the arithmetic shifter 7605 is fed into an adder 7608. At this point, the output of the arithmetic shifter 7605 includes the value (X2*K2) of the second cycle of the convolution process. However, the value of the second and subsequent cycles of the convolution process is obtained using the arithmetic shifter 7605, not using a multiplication operation. At 7804, the flow sets a control bit for the bias mux. In the second cycle (and in later cycles), the bias control bit 7607 is set to 0 so that the bias mux M3 selects which output of the previous operation is returned. At 7805, the flow processes the shifted data and the output of the bias mux through the adder. The output of the arithmetic shifter 7605 or the shifted data is added to the output of the bias mux by the adder 7608. However, in the second and later cycles of the convolution process, the bias control bit 7609 being set to 0 allows the feedback from the flip-flop 7610 (the output of the adder from the previous cycle) to pass through the multiplexer M4. Thus, at this point in the second cycle, the output of the adder from the first cycle is added to the output of the arithmetic shifter 7605 from the second cycle to have the sum of the product of the data and the shift instruction for the first and second cycles of the convolution process (b + X1*SH1 + X2*SH2). In 7806, the stream captures the output of the adder. The output of the 7608 adder is fed to a 7610 flip-flop and is captured. At 7807, the flow continues the process of 7801-7806 for each data and shift instruction, until all data and shift instructions have been processed. [Fig.79] and [Fig.80] illustrate an example of an AIPE performing a batch normalization operation, according to an example implementation. Specifically, [Fig.79] illustrates an example of the AIPE architecture configured to perform the batch normalization operation, and [Fig.80] illustrates an example flow of the AIPE performing the batch normalization operation. The AIPE can perform the batch normalization operation using an arithmetic shifter. In the example of [Fig.79], the data = X, the parameter = y, B, and the batch normalization can correspond to: Xn norm_lot = 12 8) -f norm_lot= 5 +>X-5t=n-8 norm_lot=aX+bwhere to = Tr: Ubh= -5rsn-8 At 8001, the stream loads the data and the logarithmically quantized parameter. The data 7901 and the shift instruction 7902 derived from the logarithmically quantized parameter are loaded, while the output of the previous neural network operation is also available and multiplexed with the input data 7901. The stream can also load the bias. In the example of Fig. 79, the 7 — on can be logarithmically quantized and loaded into SH of the shift instruction 7902, and b = - rrzn - 8 can be loaded into D3 of bias 7904. The data and the logarithmically quantized parameter are fed into an arithmetic adder 7907. In 8002, the flow sets a control bit for the data mux and a control bit for the parameter mux. The control bit 7905 for the data mux 7901 can be set to 0 if the loaded data 7901 is used, and set to 1 if the output of the previous neural network operation is used. The control bit 7906 for the parameter can also be set to 1. In 8003, the stream shifts the data by the shift instruction. The data 7901 multiplexed with the feedback from the flip-flop 7903 and the shift instruction 7902, derived from the logarithmically quantized parameter, are fed into the arithmetic shifter 7907. The arithmetic shifter 7907 shifts the data by the shift instruction based on the logarithmically quantized parameter. Then, the output of the arithmetic shifter 7907 is converted to two's complement. The output of the arithmetic shifter 7907 is fed into an adder 7908. In 8004, the flow sets a control bit for the bias mux. The bias control bit 7909 can be set to 1. Setting the bias sign bit 7909 to 1 allows the bias loaded value in D3 to be provided to the adder 7908. In 8005, the stream processes the shifted data and bias through the adder. The output of arithmetic shifter 7907 or the shifted data is added to bias 7904 by adder 7908 to complete the batch normalization operation. The output of adder 7908 is sent to flip-flop 7903. In 8006, the flow sets an output control bit. Output control bit 7910 can be set to 1. Output control bit 7910 being set to | allows the output of adder 7908 to be sent to the flip-flop for capture. In 8007, the stream captures the output of the adder. The output of adder 7908 is captured by flip-flop 7903 based, in part, on output control bit 7910 being set to 1. [Fig.81] and 82 illustrate an example of an AIPE performing an operation of Parametric ReLU, according to an example implementation. Specifically, [Fig.81] illustrates an example of the AIPE architecture configured to perform the Parametric ReLU operation, and [Fig.82] illustrates an example of an AIPE flow performing the Parametric ReLU operation. AIPE can perform the Parametric ReLU operation using an arithmetic shifter. In the example of [Fig.81], data = X, logarithmically quantized parameter = a. The Parametric ReLU function is Y = X, if X>0, or Y = a*X if X<0. At 8201, the stream loads the data and the logarithmically quantized parameter, and the feedback from the previous neural network operation is also available as D2 which enters the data mux M1. The data 8101 and the shift instruction 8102, derived from the logarithmically quantized parameter, are loaded, while the output of the previous neural network operation in flip-flop 8103 is returned to the AIPE and multiplexed with the data 8101. The stream can also load the bias. The bias 8104 can be loaded with the constant 0 at D3 for this example. At 8202, the flow sets a control bit for the data mux and a control bit for the parameter mux. Control bit 8105 for data 8101 can be set to 1. Control bit 8106 for shift instruction 8102 can be set to 1. Control bit 8105 being set to 1 allows the feedback from flip-flop 8103 to be selected as the input to the shifter. Control bit 8106 being set to 1 allows the shift instruction 8102 to be selected as the input to arithmetic shifter 8107. At 8204, the stream shifts the data by a shift instruction. The arithmetic shifter 8107 shifts the data 8101 by the shift instruction 8102 based on the logarithmically quantized parameter. Then, the output of the arithmetic shifter 8107 is converted to two's complement. The output of the arithmetic shifter 8107 is fed into an adder 8108. At 8205, the flow sets a bias control bit. The bias control bit 8109 can be set to 1. Setting the bias control bit 8109 to 1 allows the bias loaded value in D3 to be provided to the adder 8108. In 8206, the stream processes the shifted data and bias through the adder. The output of the arithmetic shifter 8107 or the shifted data is added to the bias 8104 by the adder 8108 to complete the Parametric ReLU operation. The output of the adder 8108 is sent to the flip-flop 8103. In 8207, the flow sets an adder mux control bit. The adder mux control bit 8110 can be set to 1. Setting the adder mux control bit 8110 to 1 allows the output of adder 8108 to pass through a multiplexer associated with adder 8108 and be fed into flip-flop 8103. In 8208, the stream captures the output of the adder. The output of the 8108 adder passes through the multiplexer because the adder mux control bit is set to 1, so the 8103 flip-flop is allowed to receive and capture the output of the 8108 adder. The sign bit 8111 of the 8103 flip-flop can be fed into a WHERE circuit for comparison with the 8106 control bit. [Fig. 83] and 84 illustrate an example of an AIPE performing an addition operation, in accordance with an example implementation. Specifically, [Fig. 83] illustrates an example of the AIPE architecture configured to perform the addition operation, and [Fig. 84] illustrates an example flow of the AIPE performing the addition operation. In the example of [Fig. 83], the data may include a first input comprising X1-X9 and a second input comprising Y1-Y9. The addition operation may add the first and second inputs such that the addition operation = X1+Y1, X2+Y2, … X9+Y9. At 8401, the stream loads data and bias. 8301 data can be loaded with X1 at D1, while 8306 bias can be loaded with Y1 at D3. At 8402, the stream sets a control bit for the data mux and a parameter mux. Control bit 8303 for data 8301 can be set to 0. Control bit 8304 for parameter 8302 can also be set to 0. Control bit 8303 being set to 0 allows data 8301 (D1) to be fed into arithmetic shifter 8305. Control bit 8304 being set to 0, the constant O is fed into arithmetic shifter 8305. At 8403, the stream shifts the data by a shift instruction. Data 8301 and parameter 8302 are fed into arithmetic shifter 8305. Arithmetic shifter 8305 shifts the data by the shift amount based on parameter 8302 which is the constant 0. Therefore, the output of the shifter is the same as the input data 8301 since the shifter has shifted the data by 0, which is equivalent to no shift. The output of arithmetic shifter 8305 is fed into an adder 8308. At 8404, the flow sets a bias mux control bit. The bias mux control bit 8307 can be set to 1. The bias mux control bit 8307 being set to 1 can allow the bias 8306 at D3 to be provided to the adder 8308. In 8405, the (lux processes the shifted data and bias through the adder. The output of the arithmetic shifter 8305 or the shifted data is added to the bias 8306 by the adder 8308 to perform the addition operation. The output of the adder 8308 is sent to the flip-flop 8310. In 8406, the stream sets an adder mux control bit. The 8309 adder mux control bit can be set to 1. The adder mux control bit With 8309 set to 1, the output of adder 8308 can be supplied to flip-flop 8310. At 8407, the stream captures the output of the adder. The output of adder 8308 is supplied to flip-flop 8310, partly because adder mux control bit 8309 is set to 1. Flip-flop 8310 captures the output of adder 8308 at 8408. At 8409, the flow continues the process of 8401-8408 for the remaining data, until all data has been processed. [Fig. 85] illustrates an example of a neural network grid, in accordance with an example implementation. In the example of [Fig. 85], the neural network grid includes a plurality of AI processing elements (AIPEs) where data and logarithmically quantized parameters (kernels) are input to the AIPEs to perform the various operations, as described herein. The AIPE architecture is configured to use shifters and logic gates. Examples described herein include 32-bit data with a 7-bit logarithmically quantized parameter, where the data can be 1 bit to N bits and the logarithmically quantized parameter can be 1 bit to M bits, where N and M are any positive integer. Some examples include a 32-bit shifter; however, the number of shifters can be greater than one and can vary from one shifter to O number of shifters where O is a positive integer.In some cases, the architecture includes 128-bit data, a 9-bit logarithmically quantized parameter, and 7 shifters connected in series—one after the other. Moreover, the logic gates shown here are a typical set of logic gates that may change depending on a certain architecture. In some cases, the AIPE architecture may use shifters, adders, and / or logic gates. Examples described here include 32-bit data with a 7-bit logarithmically quantized parameter, the data may be 1 to N bits, and the logarithmically quantized parameter may be 1 to M bits, where N and M are any positive integer. Some examples include a 32-bit shifter and a 32-bit two-input adder; however, the number of shifters and adders may be greater than one and may vary from one shifter to O shifters and one adder to P adders where O and P are a positive integer. In some cases, the architecture includes 128-bit data, a 9-bit parameter, and 2 serially connected shifters, and 2 serially connected adders—one after the other. [Fig.86A], 86B, 86C and 86D illustrate examples of AIPE structures dedicated to each particular neural network operation, according to an example implementation. Specifically, [Fig.86A] illustrates an example of an AIPE structure configured to perform a convolution operation, [Fig.86B] illustrates an example of an AIPE structure configured to perform a normalization operation. batch normalization, [Fig.86C] illustrates an example of an AIPE structure configured to perform a pooling operation, and [Fig.86D] illustrates an example of an AIPE structure configured to perform a Parametric ReLU operation. The AIPE structure comprises four different circuits, where each circuit is dedicated to performing the convolution operation, the batch normalization operation, the pooling operation, and the Parametric ReLU operation. In some cases, the AIPE structure may comprise more or less than four different circuits, and is not intended to be limited to the examples described herein. For example, the AIPE structure may comprise multiple circuits where each circuit is dedicated to performing a respective neural network operation. The circuit of [Fig.86A], in order to perform the convolution operation, receives data as input and is stored in a register. The circuit also receives the kernel, which is a shift instruction derived from the logarithmically quantized parameter, and is also stored. Then, the first shift operation is performed by the shifter, based on the shift instruction, and the output of the shifter is stored. After shifting the data, the output is added with the return from the output of the register which receives the output of the shifter from the previous operation. In the initial cycle, the return has zeros, but in later cycles, the output of the previous cycle is added to the output of the next cycle. This combined output is then multiplexed and supplied to a register as the shifted output. The circuit of [Fig.86B], in order to perform the batch normalization operation, receives data as input and is stored in a register. The circuit also receives the kernel, which is a shift instruction derived from the logarithmically quantized parameter, and is also stored. Then, the first shift operation is performed by the shifter, based on the shift instruction, and the output of the shifter is stored. After shifting the data, the data is added by an adder which receives a bias. The output of the added shifted data and the bias is provided to a register as output data. The circuit of [Fig.86C], in order to perform the grouping operation, receives input data and is stored in a register. The data is supplied to a comparator which compares the input data as well as the output data. If the result of the comparison indicates that the output data is greater than the input data, then the output data is selected. If the result of the comparison indicates that the input data is greater than the output data, then the input data is selected. The input data is supplied to a multiplexer which receives a signal bit from the comparator which indicates the result of the comparison. The multiplexer feeds a second register, and the output of the second register is fed back into the multiplexer, so that the signal bit from the comparator indicates which data from the multiplexer should be fed into the second register. The output of the second register is returned to the comparator to allow the comparator to perform the comparison. The output of the second register is the data output. The circuit in [Fig.86D], in order to perform the Parametric ReLU operation, receives data as input and is stored in a register. The data is supplied to a shifter, a comparator and a multiplexer. The circuit also receives the shift instruction derived from the logarithmically quantized ReLU parameter which is supplied to the shifter. The first shift operation is performed by the shifter, based on the shift instruction, and the output from the shifter is supplied to the multiplexer. The comparator compares the original input data and the output of the shifter (shifted data). If the result of the comparison indicates that the shifted data is greater than the original input data, then the shifted data is selected. If the result of the comparison indicates that the original input data is greater than the shifted data, then the original input data is selected.The comparator provides an instruction to the multiplexer as to which data to choose, the original input data or the shifted data. The multiplexer then provides the original input data or the shifted data, based on the instruction from the comparator, to a register. The output of the register is the output of the ReLU operation. [Fig. 87] illustrates an example grid using the AIPE structures, in accordance with an example implementation. The grid structure may include a plurality of AIPE structures, where the grid structure is configured to perform the neural network operations. The grid structure includes a grid of AIPE structures that perform the convolution operations. The grid of AIPE structures that perform convolution may include 16x16x16 AIPEs as an example. The grid structure includes a grid of AIPE structures that perform the batch normalization operations. The grid of AIPE structures that perform the batch normalization may include a 16x1x16 AIPE as an example. The grid structure includes a grid of AIPE structures that perform the Parametric ReLU operations.The grid of AIPE structures that perform the Parametric ReLU operation may include a 16x1x16 AIPE as an example. The grid structure includes a grid of AIPE structures that perform the grouping operations. The grid of AIPE structures that perform the grouping operations may include 16x1x16 AIPE as an example. The respective outputs of the grids are provided to a multiplexer, where the output of the multiplexer is provided to an output buffer. The grid receives an input from an input buffer and receives the shift instruction derived from the logarith-quantized parameter. mically, from the kernel buffer. Both the input buffer and the kernel buffer can receive input from an AXI 1 to 2 demultiplexer. The demultiplexer receives an AXI read input. Thus, as illustrated in [Fig. 86A] to 87, variations of the implementation examples described herein may be modified to provide dedicated circuitry to be directed to specific neural network operations. A system may be composed of dedicated circuitry, such as a first circuit facilitating convolution by shifter circuit as illustrated in [Fig. 86A], a second circuit facilitating convolution by shifter circuit as illustrated in [Fig. 86B], a third circuit facilitating max pooling by comparator as illustrated in [Fig. 86C], and a fourth circuit facilitating parametric ReLU as illustrated in [Fig. 86D]. Such circuitry may be used in any combination or as standalone functions, and may also be used in conjunction with the AIPE circuitry as described herein to facilitate desired implementations. [Fig. 88] illustrates an exemplary computing environment with an exemplary computing device suitable for use in certain exemplary implementations, such as an apparatus for generating and / or logarithmically quantizing parameters, training AI / NN networks, or for executing the exemplary implementations described herein in algorithmic form. The computing device 8805 in the computing environment 8800 may include one or more processing units, cores or processors 8810, memory 8815 (e.g., RAM, ROM, and / or the like), internal storage 8820 (e.g., magnetic, optical, solid state storage, and / or organic), and / or the I / O interface 8825, each of which may be coupled onto a communication mechanism or bus 8830 for communicating information or integrated into the computing device 8805.The 8825 I / O interface is also configured to receive images from cameras or provide images to projectors or displays, depending on the desired implementation. The computing device 8805 may be communicatively coupled to the input / user interface 8835 and the output device / interface 8840. One or both of the input / user interface 8835 and the output device / interface 8840 may be a wired or wireless interface and may be detachable. The input / user interface 8835 may include any device, component, sensor, or interface, physical or virtual, that can be used to provide input (e.g., buttons, a touchscreen interface, a keyboard, a pointing / cursor control, a microphone, a camera, braille, a motion sensor, an optical reader, and / or the like). The output device / interface 8840 may include a display, a television, a monitor, a printer, a speaker, braille, or the like. In some In example implementations, the input / user interface 8835 and the output device / interface 8840 may be embedded with, or physically coupled to, the computing device 8805. In other example implementations, other computing devices may function as or provide the functions of the input / user interface 8835 and the output device / interface 8840 for a computing device 8805. Examples of computing device 8805 may include, but are not limited to, highly mobile devices (e.g., smartphones, devices in vehicles and other machines, devices carried by humans and animals, etc.), mobile devices (e.g., tablets, laptops, personal computers, portable televisions, radios, etc.), and devices not designed for mobility (e.g., desktop computers, other computers, information kiosks, televisions with one or more processor(s) embedded and / or coupled thereto, radio, etc.). The computing device 8805 may be communicatively coupled (e.g., via the I / O interface 8825) to the external storage 8845 and the network 8850 to communicate with any plurality of networked components, devices, and systems, including one or more computing devices of the same or different configuration. The computing device 8805 or any connected computing device may operate as, provide services of, or be designated as a server, client, thin server, general machine, special purpose machine, or other designation. The 8825 I / O interface may include, but is not limited to, wired and / or wireless interfaces using any communication or I / O protocol or standard (e.g., Ethernet, 802.11x, Universal System Bus, WiMax, modem, a cellular network protocol, and the like) to communicate information to and / or from at least all connected components, devices, and networks in the 8800 computing environment. The 8850 network may be any network or combination of networks (e.g., the Internet, a local area network, a wide area network, a telephone network, a cellular network, a satellite network, etc.). The computing device 8805 may use and / or communicate using computer-usable or computer-readable media, including ephemeral media and non-ephemeral media. Ephemeral media include transmission media (e.g., wire rope, optical fiber), signals, carrier waves, etc. Non-ephemeral media include magnetic media (e.g., disks and tapes), optical media (e.g., CD-ROMs, digital video discs, Blu-ray discs), solid-state media (e.g., RAM, ROM, flash memory, solid-state storage), and other non-volatile storage or memory. The 8805 computing device may be used to implement Computer-executable techniques, methods, applications, processes, or instructions in certain example computing environments. Computer-executable instructions may be retrieved from ephemeral media, and stored on and retrieved from non-ephemeral media. The executable instructions may be from one or more of any programming, scripting, and machine language (e.g., C, C++, C#, Java, Visual Basic, Python, Perl, JavaScript, and others). The 8810 processor(s) may run under any operating system (OS) (not shown), in a native or virtual environment. One or more applications may be deployed, including the logical unit 8860, the application programming interface (API) unit 8865, the input unit 8870, the output unit 8875, and the inter-unit communication mechanism 8895 for the various units to communicate with each other, with the OS, and with other applications (not shown). The units and elements described may vary in design, function, configuration, or implementation and are not limited to the descriptions provided. The 8810 processor(s) may be in the form of hardware processors such as central processing units (CPUs) or in the form of a combination of hardware and software units. In some example implementations, when information or an execution instruction is received by the PLC unit 8865, it may be communicated to one or more other units (e.g., logic unit 8860, input unit 8870, output unit 8875). In some cases, the logic unit 8860 may be configured to control the flow of information among the units and direct the services provided by the PLC unit 8865, the input unit 8870, the output unit 8875, in some example implementations described above. For example, the flow of one or more processes or implementations may be controlled by logic unit 8860 alone or in conjunction with PLC unit 8865. Input unit 8870 may be configured to obtain input for the calculations described in the example implementations, and output unit 8875 may be configured to provide output based on the calculations described in the example implementations. Depending on the desired implementation, the 8810 processor(s) may be configured to convert data values or parameters of an AI / neural network model into logarithmically quantized data values or logarithmically quantized values to be provided to a memory of a system as illustrated in [Fig. 89]. The logarithmically quantized data values or logarithmically quantized parameters may then be used by a controller of the system of [Fig. 89] to be converted into shift instructions to shift the parameters or values of peer data to facilitate a neural network or AI operation. In such example implementations, the processor(s) 8810 may be configured to perform the processes as illustrated in [Fig. 9A] and 9B to conduct training of the machine learning algorithm and result in logarithmically quantized parameters, which may be stored in memory for use by a controller. In other example implementations, the processor(s) 8810 may also be configured to perform a method or process to convert input data into logarithmically quantized data to be provided in AIPEs. [Fig. 89] illustrates an exemplary system for controlling an AIPE, in accordance with an exemplary implementation. In an exemplary implementation, controller 8900 may control one or more AIPEs 8901 as described herein via control signals (e.g., s1, s2, s3, s4 as illustrated in [Fig. 72] to 85) to perform the desired neural network operation. Controller 8900 is configured with controller logic that may be implemented as any logic circuit or any type of hardware controller known in the art, such as a memory controller, a central processing unit, and so on, in accordance with the desired implementation. In exemplary implementations, controller 8900 may retrieve logarithmically quantized parameters from memory 8902 and convert them to shift instructions involving the sign bit, the shift direction, and the shift instruction derived from the logarithmically quantized parameter.Such shift instructions and control signals may be provided from the controller 8900 to the AIPE(s) 8901. Depending on the desired implementation, the input data may be provided directly to the AIPE(s) 8901 by any input interface 8903 in accordance with the desired implementation (e.g., a data stream as processed by a transformation circuit configured to upscale the data stream by a factor of 2*, an input preprocessing circuit, an FPGA, a hardware processor, etc.), or may also be provided by the controller 8900 as retrieved from memory 8902. The output of the AIPE(s) 8901 may be processed by an output interface 8904 that may present the output of the neural network operation to any desired device or hardware in accordance with the desired implementation.The output interface 8904 may be implemented as any hardware (e.g., FPGA, hardware, dedicated circuit) in accordance with the desired implementation. Further, any or all of the controller 8900, the AIPE(s) 8901, the memory 8902, the input interface 8903, and / or the output interface 8904 may be implemented as one or more hardware processor(s) or FPGA(s) in accordance with the desired implementation. The 8902 memory may be any form of physical memory in accordance with the desired implementation, such as, but not limited to, double data rate synchronous dynamic random-access memory (DDR SDRAM), magnetic random access memory (MRAM), and so on. In an exemplary implementation, if the data is logarithmically quantized and stored in memory 8902, then the data may be used to derive the shift instruction for shifting neural network parameters as retrieved from memory 8902 instead of using logarithmically quantized neural network parameters to derive the shift instruction. Deriving the shift instruction from logarithmically quantized data may be conducted in a manner similar to that of the logarithmically quantized parameter. In example implementations, there may be a system as illustrated in [Fig. 89] in which a memory 8902 may be configured to store a trained neural network represented by one or more logarithmically quantized parameter values associated with one or more neural network layers, each of the one or more neural network layers representing a corresponding neural network operation to be performed. Such a system may involve one or more hardware elements (e.g., AIPE 8901 as described herein, hardware processors, FPGAs, etc.) configured to shift or add shiftable input data; and controller logic (e.g., as implemented as an 8900 controller, as a hardware processor, as logic circuits, etc.) configured to control the one or more hardware elements (e.g., via control signals sl, s2, s3, s4, etc.) for, for each of the one or more neural network layers read from the memory, shifting the shiftable input data left or right based on a shift instruction derived from the corresponding logarithmically quantized parameter values to form shifted data; and adding or shifting the formed shifted data (e.g., via an adder circuit or a shifter circuit as described herein), depending on the corresponding neural network operation to be performed. Depending on the desired implementation, the system may further involve a data scaling device configured to scale input data to form shiftable input data. Such a data converter may be implemented in hardware (e.g., via dedicated circuit logic, a hardware processor, etc.) or in software in accordance with the desired implementation. Such a data scaling device may be configured to scale bias parameters from one or more neural network layers read from the memory 8902 to add them to shifted data via an adder or shifter circuit, or scale the input data (e.g., by a factor of 2* to form shiftable input data, where x is an integer). As illustrated in the example implementations described herein, the AIPE 8901 or equivalent hardware elements thereof may involve one or more shifter circuits (e.g., barrel shifter circuits, logarithmic shifter circuits, arithmetic shifter circuits, etc.) configured to perform the shifting. It may further involve one or more adder circuits (e.g., arithmetic adder circuits, integer adder circuits, etc.) configured to perform the addition as described herein. If desired, the addition operations may involve one or more shifter circuits configured to perform the addition as described herein (e.g., via segments, positive / negative accumulators, etc.). The controller 8900 may be configured to generate a shift instruction to be provided to the AIPE(s) 8901 or equivalent hardware elements. Such a shift instruction may involve a shift direction and a shift magnitude to command / direct the AIPE(s) or equivalent hardware elements to shift the shiftable input data left or right. As described herein (e.g., as illustrated in [Fig. 59] to 62), the shift magnitude may be derived from a magnitude of an exponent of the corresponding logarithmically quantized weight parameter (e.g., 2? has a magnitude of 2, making the shift magnitude 2), and the shift direction may be derived from a sign of the exponent of the corresponding logarithmically quantized weight parameter (e.g., 2? has a positive sign, thus indicating a left shift). Depending on the desired implementation, the AIPE(s) 8901 or equivalent hardware may be configured to provide a sign bit for the shifted data formed based on a sign bit of the corresponding logarithmically quantized weight parameter and a sign bit of the input data as shown in [Fig. 60] or 62. The shift instruction may include the sign bit of the corresponding logarithmically quantized weight parameter for use in an XOR circuit or for two's complement purposes depending on the desired implementation. As described herein in the various implementation examples, the computing environment of [Fig. 88] and / or the system of [Fig. 89] may be configured to execute a method or computer instructions for processing a neural network operation, which may include multiplying input data with a corresponding logarithmically quantized parameter associated with the operation for a neural network (e.g., to facilitate a convolution, a batch norm, etc.). Such computer methods and instructions for multiplication may involve admitting a shiftable input derived from the input data (e.g., scaling by a factor); shifting the shiftable input in a direction toward the left or a right direction according to a shift instruction derived from the corresponding logarithmically quantized parameter to generate an output representative of multiplying the input data with the corresponding logarithmically quantized parameter for the neural network operation as described herein. As described herein, the shift instruction associated with the corresponding logarithmically quantized parameter may involve a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized parameter; wherein shifting the shiftable input involves shifting the shiftable input in the left direction or right direction according to the shift direction and by a magnitude indicated by the shift magnitude.Although the following is described with respect to the systems illustrated in [Fig. 88] and 89, other implementations for facilitating the methods or computer instructions are also possible, and the present disclosure is not limited thereto. For example, the method may be executed by a field-programmable gate array (FPGA), by an integrated circuit (e.g., ASIC), or by one or more hardware processors. As described herein in the computing environment of [Fig.88] and / or a system as described in [Fig.89], there may be a method or computer instructions for processing an operation for a neural network, which may involve admitting shiftable input data derived from input data of the operation for the neural network; admitting an input associated with a corresponding logarithmically quantized weight parameter for the input data of the operation for the neural network, the input involving a shift direction and a shift magnitude, the shift magnitude derived from a magnitude of an exponent of the corresponding logarithmically quantized weight parameter, the shift direction derived from a sign of the exponent of the corresponding logarithmically quantized weight parameter; and shifting the shiftable input data according to the input associated with the corresponding logarithmically quantized weight parameter to generate an output for processing the operation for the neural network. As illustrated in example implementations described herein, the methods and computer instructions may involve determining a sign bit of the output of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation based on the corresponding logarithmically quantized parameter sign bit and a sign bit of the input data (e.g., via an XOR circuit or equivalent function in software or circuitry). As illustrated in example implementations described herein, the methods and ins- Multiplication computer instructions may involve, for a sign bit of the corresponding logarithmically quantized parameter being negative, converting the output of multiplying the input data with the corresponding logarithmically quantized parameter for the neural network operation into one's complement data; incrementing the one's complement data to form two's complement data as the output of multiplying the input data with the corresponding logarithmically quantized parameter for the neural network operation. As illustrated in example implementations described herein, the methods and computer instructions may involve adding a value associated with the neural network operation to the output generated from multiplying the input data with the corresponding logarithmically quantized parameter to form an output for processing the neural network operation. Such addition may be conducted by an adder circuit (e.g., an integer adder circuit or a floating-point adder circuit), or by one or more shifter circuits (e.g., barrel shifter circuits, logarithmic shifter circuits, etc.) depending on the desired implementation. Such shifter circuit(s) may be the same as or distinct from the one or more shifter circuits that handle the shifting depending on the desired implementation.The value associated with the neural network operation can be a bias parameter, but is not limited to it. As described herein in example implementations, the computer methods and instructions may involve, for the neural network that is a convolution operation, the input data involves a plurality of input elements for the convolution operation; the shiftable input involves a plurality of shiftable input elements, each of which corresponds to one of the plurality of input elements to be multiplied by the corresponding logarithmically quantized parameter from a plurality of logarithmically quantized parameters;the output of multiplying the input data with the corresponding logarithmically quantized parameter for the neural network operation involves a plurality of shiftable outputs, each of the plurality of shiftable outputs corresponding to a shift of each of the shiftable input elements according to the input associated with the corresponding one of the plurality of logarithmically quantized parameters; wherein the plurality of shiftable outputs are summed by addition operations or shift operations.; As described herein in example implementations, the computer methods and instructions may involve, for the neural network operation that is a parametric ReLU operation, shifting the shiftable input according to the shift instruction to generate the output of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation is done only when a sign bit of the input data is negative, and the shiftable input is provided as the output of the multiplication of the input data with the corresponding logarithmically quantized parameter for the neural network operation without shifting for when the sign bit of the input data is positive. Portions of the detailed description are presented in terms of algorithms and symbolic representations of operations within a computer. These algorithmic descriptions and symbolic representations are the means used by those skilled in the art to communicate the essence of their innovations to others in the art. An algorithm is a series of defined steps leading to a desired result or end state. In implementation examples, the steps performed require physical manipulations of tangible quantities to achieve a tangible result. Unless otherwise specifically indicated, as evident from the discussion, it is noted that throughout the specification, discussions using terms such as "processing," "computation," "determination," "display," or the like may include the actions and processes of a computer system or other information processing device that manipulates and transforms data represented as physical (electronic) quantities in the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other information storage, transmission, or display devices. Example implementations may also relate to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the required purposes, or it may include one or more general-purpose computers selectively activated or reconfigured by one or more computer programs. These computer programs may be stored on a computer-readable medium, such as a computer-readable storage medium or a computer-readable signal medium. A computer-readable storage medium may involve tangible media such as, but not limited to, optical disks, magnetic disks, read-only memories, random access memories, solid-state devices and drives, or any other type of tangible or non-ephemeral medium suitable for storing electronic information.A computer-readable signal medium may include media such as carrier waves. The algorithms and displays presented herein are not inherently tied to any particular computer or other device. Computer programs may involve pure software implementations that involve . instructions that perform the operations of the desired implementation. Various generic systems may be used with programs and modules according to the examples detailed herein, or it may be convenient to construct more specialized apparatus to perform the desired method steps. Furthermore, the implementation examples are not described with reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the techniques of the implementation examples as described herein. The instructions of the programming language(s) may be executed by one or more processing devices, e.g., central processing units (CPUs), processors, or controllers. As is known in the art, the operations described above may be performed by hardware, software, or some combination of software and hardware. Various aspects of the exemplary implementations may be implemented using logic circuits and devices (hardware), while other aspects may be implemented using instructions stored on a machine-readable medium (software), which, if executed by a processor, would cause the processor to perform a method for performing implementations of the present application. Further, some exemplary implementations of the present application may be performed solely by hardware, while other exemplary implementations may be performed solely by software. In addition, the various functions described may be performed in a single unit, or may be distributed across a plurality of components in any number of ways.When executed by software, the methods may be executed by a processor, such as a general-purpose computer, based on instructions stored on a computer-readable medium. If desired, the instructions may be stored on the medium in a compressed and / or encrypted format. Additionally, other implementations of the present application will become apparent to those skilled in the art upon consideration of the description and practice of the techniques of the present application. Various aspects and / or components of the described implementation examples may be used alone or in any combination. It is intended that the description and implementation examples be considered exemplary only, with the true scope and spirit of the present application being indicated by the following claims.

Claims

Demands

1. Artificial intelligence processing element (AIPE), the AIPE including: * a circuit shifter configured for: - admit a shiftable input derived from input data for a neural network operation; - allow a shift instruction derived from a quantized parameter logarithmically corresponding of a neural network or a value constant; and - shift the shiftable input in a direction to the left or a direction to the right in accordance with the offset instruction for to form a staggered output representative of a multiplication of the input data with the logarithmically quantified parameter cor- neural network responder.

2. AIPE according to claim 1, wherein the shift instruction includes a direction of offset and an amplitude of offset, the shift amplitude derived from a magnitude of an exponent of the corresponding logarithmically quantified parameter, the direction of offset derived from the sign of the exponent of the quantized parameter logarith- correspondingly; in which the shifter circuit shifts the shiftable input in the direction to the left or to the right depending on the direction of the offset and shifts the shiftable input in the direction of the shift by an amplitude indicated by the amplitude of the offset.

3. AIPE according to claim 1, further comprising a configured circuit to admit a first sign bit for the shiftable input and a second bit of sign of the logarithmically quantified parameter cor- responding to form a third sign bit for the shifted output.

4. AIPE according to claim 1, further comprising a first circuit configured to allow the offset output and a sign bit of the one that corresponds among the logarithmically quantified parameters for form one's complement data for when the sign bit of the Logarithmically quantified parameters are indicative of a sign negative; and a second circuit configured to increment the data of one's complement by the sign bit of the quantized logarith parameter mically corresponding to change the offset output into data of complement to two which are representative of the multiplication of input data with the logarithmically quantified parameter cor- respondent

5. AIPE according to claim 1, wherein the shift circuit is a logarithmic shifter circuit or barrel shifter circuit.

6. AIPE according to claim 1, further comprising a configured circuit to admit the output of the neural network operation, in which the circuit provides the shiftable input from the output of the operation of neural network or from scaled input data generated from the input data for the network operation neuronal according to a signal input in the shifter circuit.

7. AIPE according to claim 1, further comprising a configured circuit to provide the shift instruction derived from the quantized parameter lo- arithmically corresponding of the neural network or the value constant according to a signal input.

8. AIPE according to claim 1, further comprising an additional circuit- tionor coupled to the shifter circuit, the adder circuit being configured to add based on the shifted output in order to form an output for the neural network operation.

9. AIPE according to claim 8, wherein the adder circuit is a Integer adder circuit.

10. AIPE according to claim 8, wherein the adder circuit is configured to sum the offset output with a cor- parameter responding to a plurality of bias parameters of the neural network to form the output for the neural network operation.

11. AIPE according to claim 1, further comprising: another offset circuit; and a register circuit coupled to the other shifter circuit which locks the output from the other circuit shifter; in which the other shifter circuit is configured to admit a bit of sign associated with the offset output and each segment of the offset output to shift another circuit input to the left or towards the right side depending on the sign bit to form the output from the other circuit shifter; in which the register circuit is configured to provide the output ver- rusted from the other circuit shifter as the input of the other circuit shifter to the other circuit, shifter for receiving an indicator signal of the non-completion of the neural network operation and provide the output locked as output for the neural network operation for the reception of the signal indicating the completion of the network operation neuronal.

12. AIPE according to claim 11, wherein each segment has a size of a binary logarithm of the width of the input of the other circuit offsetter.

13. AIPE according to claim 11, further comprising a counter configured to allow an overrun or underrun from the other offset circuit resulting from the offset of the other offset circuit entered via the shifter circuit; in which the other shifter circuit is configured to admit the de- passing or weighing each segment to offset a next segment to the left or right by an amplitude of the de- passage or weighing.

14. AIPE according to claim 11, further comprising a circuit of 1-out-of-n encoding to binary configured to admit output ver- rusted in order to generate an encoded output, and concatenate the encoded output from all segments and a sign bit from the result of a overtaking or weighting operation to form the exit for neural network operation.

15. AIPE according to claim 1, further comprising: a positive accumulation shift circuit comprising a second offset circuit configured to admit each segment of the output offset to offset the input of the positive accumulation offset circuit to the left for a sign bit associated with the shift instruction indicating a positive sign; the second circuit shifter coupled to a first register circuit configured to lock the circuit input offset positive accumulation shifter from the second circuit shifter as the first locked output, the first circuit of register being configured to provide the first locked output in as long as the input of the positive accumulation shift circuit for the reception of a signal indicating that the neural network operation is not not finished; a negative accumulation shift circuit comprising a third offset circuit configured to admit each segment of the output offset to offset the input of the negative accumulation offset circuit to the left for the sign bit associated with the shift instruction indicating a negative sign; the third circuit shifter coupled to a second register circuit configured to lock the circuit input negative accumulation offset from the originating from the third circuit shifter as second locked output, the second register circuit being configured to provide the second output locked as input to the accumulation shifter circuit negative for the reception of a signal indicating that the operation of neural network is not finished; And an adding circuit configured to add based on the first locked output from the accumulator shifter circuit positive and the second locked output of the accumulator shifter circuit negative emulator to form the output of the neural network operation for receiving the signal indicating that the neural network is operating is finished.

16. AIPE according to claim 15, further comprising: a first counter configured to allow an initial overrun of the circuit shifter with positive accumulation resulting from the shift of the input of the positive accumulation shift circuit, in which the The second circuit shifter is configured to admit the first de- passing each segment to shift a subsequent segment towards the left by an amplitude of the first overshoot; and a second counter configured to admit a second de- switching of the circuit shifter to negative accumulation resulting from the offset of the input of the negative accumulation shifter circuit, in which the third circuit shifter is configured to admit the second overshoot of each segment to shift a segment following to the left by an amplitude of the second overshoot.

17. AIPE according to claim 15, further comprising: a first 1-of-n to binary coding circuit configured for admit the first locked output to generate a first output encoded, and concatenate the first encoded output from all segments and a positive bit to form a first input of the addi- circuit tioner; a second 1-of-n-to-binary coding circuit configured for admit the second locked output to generate a second encoded output, and concatenate the second encoded output from all the segments and a negative sign bit to form a second input of adder circuit; in which the adding circuit performs the addition based on the first output locked and second output locked by adding the first input of the adder circuit with the second input of adder circuit to form the output for the network operation neuronal.

18. AIPE according to claim 1, wherein the input data are scaling to form the offset entry.

19. AIPE according to claim 1, further comprising: a register circuit configured to lock the offset output; in which for the reception of an indicative control signal of a addition operation: the shift circuit is configured to admit each segment of the offset input to shift the offset output to the left or right based on a sign bit associated with the shifted output to form a another offset output representing an addition operation of the output staggered and from the staggered entrance.

20. AIPE according to claim 1, wherein, in order that the operation of neural network, or a parametric ReLU operation, the circuit The shifter is configured to provide the shiftable input as an output. shifted without performing a shift for one sign bit of the input offset which is positive.

21. A method implemented by a computer entity to process an in- artificial intelligence, including the steps of: admission of a shiftable input derived from input data for a neural network operation; admission of a shift instruction derived from a parameter logarithmically quantified corresponding of a neural network or of a constant value; and offset of the shiftable input in a direction to the left or a direction to the right in accordance with the offset instruction for to form a staggered output representative of a multiplication of the input data with the logarithmically quantified parameter cor- neural network responder.