AMBIENT LIGHT SENSOR

Abstract

According to one aspect, an ambient light sensor is proposed comprising: - a photodiode (PHD) configured to generate an electrical signal based on ambient light, - a capacitive feedback transimpedance amplifier (CTIA) connected at the input of the photodiode (PHD) to receive a signal generated by the photodiode and to generate at the output an amplified signal from the signal generated by the photodiode (PHD), - a self-zero switch (AZS) at the input of the capacitive feedback transimpedance amplifier, and - a control circuit (CC) comprising a trigger circuit (CA) configured to: ○ receive an initial control logic signal (AZB_X) with a positive or zero voltage, then ○ generate, from this initial control logic signal, a matched control logic signal (AZ_SHIFT) having a first positive voltage level and a second negative voltage level to control the self-zero switch (AZS). Figure for the abstract: Fig 1

Description

Title of the invention: AMBIENT LIGHT SENSOR

[0001] Some embodiments relate to ambient light sensors.

[0002] An ambient light sensor is a photodetector configured to detect an amount of ambient light around that sensor.

[0003] Such an ambient light sensor can be integrated into smartphones or laptops, for example. In particular, the ambient light sensor can be used to adjust the screen brightness of a smartphone or laptop according to the ambient light.

[0004] An ambient light sensor generally includes a photodiode configured to generate an electrical signal dependent on the ambient light around that photodiode.

[0005] This electrical signal is then amplified by an amplifier of the ambient light sensor before being processed.

[0006] To amplify the electrical signal generated by the photodiode, it is possible to use a capacitive feedback transimpedance amplifier (also known by the acronym "CTIA" from the English "capacitive transimpedance amplifier").

[0007] Such an amplifier comprises an operational amplifier with a capacitive element in loop.

[0008] In particular, the operational amplifier may have a first inverting input connected to the photodiode, and a non-inverting input connected to a cold point, in particular ground. The operational amplifier also includes an output configured to deliver an amplified signal from the electrical signal delivered by the photodiode.

[0009] The output of the operational amplifier is connected to a first terminal of the capacitive element, and a second terminal of the capacitive element is connected to the inverting input of the operational amplifier.

[0010] Furthermore, it is preferable to use an auto-zero switch (in English "auto-zero switch" or "AZ switch") between the inverting input and the non-inverting input of the operational amplifier.

[0011] In particular, the auto-zero switch makes it possible to eliminate an input voltage offset of the amplifier.

[0012] The self-zero switch can be an NMOS transistor.

[0013] Furthermore, it is important to reduce information loss through the capacitive element during the integration time of the transimpedance amplifier.

[0014] Indeed, because the electrical signals that can be generated by the photodiode have a low intensity, on the order of picoamperes to nanoamperes, the losses can lead to significant errors in the measurement of ambient light.

[0015] It is notably possible to use a low-loss self-zeroing switch with a high threshold voltage. However, manufacturing such a low-loss self-zeroing switch requires the use of an additional mask. Thus, such a solution is complex and expensive to implement.

[0016] There is therefore a need to propose a simple and inexpensive solution to reduce the switching losses between the inputs of the capacitive feedback transimpedance amplifier.

[0017] According to one aspect, an ambient light sensor is proposed comprising: - a photodiode configured to generate an electrical signal based on ambient light, - a capacitive feedback transimpedance amplifier connected at the input to the photodiode to receive a signal generated by the photodiode and to generate at the output an amplified signal from the signal generated by the photodiode, - an auto-zero switch at the input of the capacitive feedback transimpedance amplifier, and - a control circuit including a priming circuit configured to: O receive an initial logic control signal at positive or zero voltage, then O generate, from this initial logic control signal, a suitable logic control signal having a first positive voltage level and a second negative voltage level to control the auto-zero switch.

[0018] The ability to control the auto-zero switch with a negative voltage during the integration time makes it possible to reduce losses.

[0019] Such an ambient light sensor therefore makes it possible to reduce the errors in measuring ambient light.

[0020] Furthermore, such an ambient light sensor does not require the use of a self-zeroing transistor with a high threshold voltage. This avoids the need for an additional mask in the manufacture of the self-zeroing transistor.

[0021] The priming circuit therefore allows the use of an inexpensive self-zeroing transistor.

[0022] In an advantageous embodiment, the priming circuit comprises: - an inverter gate configured to receive the initial logic control signal, - a capacitive element having a first terminal connected to an output of the inverter gate, - a first PFET-type transistor having a gate configured to receive the initial logic control signal, a drain connected to the second terminal of the capacitive element and a source configured to receive a common-mode voltage, - an output connected to the second terminal of the capacitive element and to the drain of the first transistor and configured to deliver the appropriate logic control signal to the auto-zero switch.

[0023] Preferably, the initial control logic signal has a first level at 1.8V and a second level at 0V, and the adapted control logic signal has a first positive level at 0.9V when the initial control logic signal is at 0V, and a second negative level at -0.9V, when the initial control logic signal is at 1.8V.

[0024] Advantageously, the priming circuit further comprises: - a second NFET-type transistor having a source connected to the second terminal of the capacitive element, a gate configured to receive the initial logic control signal, and a drain connected to the output of the priming circuit, - a PFET type transistor having a source connected to the output of the inverter gate, a gate configured to receive the initial logic control signal and a drain connected to the output of the priming circuit.

[0025] Thus, the second terminal of the capacitive element is connected to the output via the second transistor.

[0026] Preferably, the initial control logic signal has a first level at 1.8V and a second level at 0V, and the adapted control logic signal has a first positive level at 1.8V when the initial control logic signal is at 0V, and a second negative level at -0.9V, when the initial control logic signal is at 1.8V.

[0027] In an advantageous embodiment, the capacitive feedback transimpedance amplifier includes an operational amplifier having an inverting input connected to the photodiode and a non-inverting input connected to a cold point, the auto-zero switch having a first terminal connected to the inverting input of this operational amplifier and a second terminal connected to the non-inverting input of this operational amplifier.

[0028] Preferably, the capacitive feedback transimpedance amplifier includes a capacitive element having a first terminal connected to an output of the operational amplifier, and a second terminal connected to the inverting input of the operational amplifier.

[0029] According to another aspect, a device comprising an ambient light sensor as described above is proposed.

[0030] Other advantages and features of the invention will become apparent upon examination of the detailed description of implementation and embodiments, which are by no means limiting, and the accompanying drawings in which:

[0031] [Fig.1]

[0032] [Fig.2]

[0033] [Fig.3]

[0034] [Fig.4]

[0035] [Fig.5]

[0036] [Fig.6] schematically illustrate methods of embodiment and implementation of the invention.

[0037] The ALS ambient light sensor includes a PHD photodiode.

[0038] The PHD photodiode is configured to generate an SPHD electrical signal as a function of the ambient light around the ALS sensor.

[0039] The ALS ambient light sensor includes a CTIA capacitive transimpedance amplifier.

[0040] The CTIA capacitive feedback transimpedance amplifier includes an operational amplifier op-amp.

[0041] The operational amplifier op-amp has an inverting input connected to the photodiode PHD. In this way, the inverting input of the operational amplifier op-amp is configured to receive the electrical signal SPHD generated by the photodiode PHD.

[0042] The operational amplifier op-amp also has a non-inverting input connected to a cold point, in particular to a GND ground.

[0043] The operational amplifier op has an output configured to deliver an amplified SAMP signal from the SPHD signal generated by the photodiode.

[0044] The CTIA amplifier includes a first capacitive element CAP1 that provides feedback to the operational amplifier AOP. In particular, the second capacitive element CAP1 has a first terminal connected to the output of the operational amplifier AOP, and a second terminal connected to the inverting input of the operational amplifier.

[0045] The CTIA amplifier also includes a second capacitive element CAP2 that provides feedback to the operational amplifier (op-amp). In particular, the second capacitive element CAP2 has a first terminal connected to the output of the operational amplifier (op-amp), and a second terminal connected to the inverting input of the operational amplifier.

[0046] More specifically, the second terminal of the second capacitive element CAP2 is connected to the inverting input of the amplifier via at least one MO switch. Each MO switch can be implemented by an NMOS transistor.

[0047] The second capacitive element CAP2 has a capacitance equal to the capacitance of the first capacitive element CAP1.

[0048] The MO switch is configured to be controlled by an SCOM control signal having a low level of -0.9V and a high level of 1.8V.

[0049] Thus, the second capacitive element CAP1 allows the gain of the CTIA amplifier to be divided by two when the MO switch is closed.

[0050] The ambient light sensor also includes an AZS auto-zero switch. This AZS auto-zero switch has a first terminal connected to the inverting input of the op-amp, and a second terminal connected to the non-inverting input of the op-amp. This AZS auto-zero switch can, for example, be implemented using an NMOS transistor.

[0051] The auto-zero switch AZS makes it possible to eliminate an input offset voltage of the operational amplifier AOP.

[0052] The ambient light sensor ALS includes a DC control circuit to control the auto-zero switch AZS.

[0053] The CC control circuit includes an initial control signal generator GEN. This GEN is configured to generate an inverted initial control logic signal AZB_X.

[0054] The initial AZB_X reverse control signal can, for example, vary between 0V and 1.8V.

[0055] In order to adapt the initial AZB_X control signal to reduce the losses of the auto-zero switch AZS, the DC control circuit includes a AC bootstrap circuit.

[0056] The AC priming circuit is thus configured to control the auto-zero switch AZS with a suitable logic control signal AZ_SHIFT.

[0057] Figure 2 represents a first embodiment of such a priming circuit CAL

[0058] The CAI initiation circuit comprises an INV1 inverter gate, a CAPA1 capacitive element, and a MIL transistor

[0059] The CAI priming circuit is configured to receive as input the initial AZB_X inverted control signal. As shown in [Fig. 3], the initial AZB_X inverted control signal can, for example, vary between 0V and 1.8V.

[0060] The INV1 inverter gate has an input configured to receive the initial AZB_X inverted control signal.

[0061] The INV1 inverter gate allows the initial AZB_X signal to be inverted. Thus, the INV1 inverter gate allows an INB signal to be obtained with a voltage of 1.8V when the AZB_X signal is at 0V, and a voltage of 0V when the AZB_X signal is at 1.8V.

[0062] The capacitive element CAPA1 has a first terminal connected to the output of the inverter gate INV 1 and a second terminal connected to a drain of the transistor MIL

[0063] The capacitive element CAPA1, for example, has a capacitance between 100F and 1pF.

[0064] The capacitive element CAPA1 allows a negative voltage to be obtained at its second terminal. In particular, this voltage is equal to -0.9V.

[0065] The Mil transistor is a PFET type transistor (P-channel MOSFET transistor).

[0066] The Mil transistor has a drain connected to the second terminal of the capacitive element CAPA1, a gate configured to receive the initial inverted control signal AZB_X and a source configured to receive a common mode voltage VCM.

[0067] For example, the common mode VCM voltage is equal to 0.9V.

[0068] The Mil transistor is conducting when the AZB_X signal is at 0V. Thus, the Mil transistor makes it possible to obtain an AZ_SHIFT signal at the output of the CAI priming circuit having a voltage equal to the VCM voltage, i.e. 0.9V, when the AZB_X signal is at 0V.

[0069] Thus, the voltage of the AZ_SHIFT signal at the output of the CAI priming circuit is between -0.9V and 0.9V. In particular, the output voltage is 0.9V when the voltage of the AZB_X signal is 0V, and is -0.9V when the voltage of the AZB_X signal is 1.8V.

[0070] The negative voltage of the AZ_SHIFT signal allows a negative gate-source voltage to be obtained on the AZS auto-zero switch. This reduces the losses of the auto-zero switch, particularly during the integration time.

[0071] Fig. 4 represents a second embodiment of the CA2 initiation circuit.

[0072] The CA2 initiation circuit includes an inverter gate INV2, a capacitive element CAPA2, a first transistor M21, a second transistor M22 and a third transistor M23.

[0073] The CA2 priming circuit is configured to receive as input the initial AZB_X reverse control signal.

[0074] The INV2 inverter gate has an input configured to receive the AZB_X signal and an output configured to deliver an INB signal inverted with respect to the AZB_X signal. Thus, as shown in [Fig.4], the INB signal can be at 1.8V when the AZB_X signal is at 0V, and at 0V when the AZB_X signal is at 1.8V.

[0075] The capacitive element CAPA2 comprises a first terminal connected to the output of the inverter gate INV2, and a second terminal connected to a drain of the first transistor M21 and to a source of the second transistor M22.

[0076] The capacitive element CAPA2 makes it possible to obtain a voltage of -0.9V at the second terminal of the capacitive element CAPA2 when the voltage of the signal IN is at 1.8V.

[0077] The first transistor M21 is a PFET type transistor.

[0078] The first transistor M21 has a drain connected to the second terminal of the capacitive element, a gate configured to receive the AZB_X signal, and a source configured to receive the common-mode VCM voltage.

[0079] For example, the common mode VCM voltage is equal to 0.9V.

[0080] Transistor M21 is conducting when the AZB_X signal is at 0V. Thus, transistor M21 makes it possible to obtain a voltage at the drain of this transistor M21 equal to the VCM voltage, i.e. 0.9V, when the AZB_X signal is at 0V.

[0081] Thus, the NET signal at the drain of transistor M21 has a voltage between -0.9V and 0.9V. In particular, this voltage is 0.9V when the voltage of the AZB_X signal is 0, and is -0.9V when the voltage of the AZB_X signal is 1.8V.

[0082] The second transistor M22 is an NFET type transistor (N-channel MOSFET transistor).

[0083] The second transistor M22 has a source connected to the drain of the first transistor M21 and to the second terminal of the capacitive element CAPA2.

[0084] The second transistor M22 also has a gate configured to receive the AZB_X signal, and a drain connected to an OUT output configured to deliver a suitable AZ_SHIFT control signal.

[0085] The second transistor M22 is conducting when the AZB_X signal is at 1.8V. Thus, transistor M21 makes it possible to obtain a voltage of the adapted AZ_SHIFT control signal at the output of the CA2 priming circuit equal to -0.9V when the AZB_X signal is at 1.8V.

[0086] The M23 transistor is a PFET type transistor.

[0087] The third transistor M23 has a source connected to the output of the inverter gate, a gate configured to receive the IN signal, and a drain connected to the OUT output.

[0088] The third transistor M23 is conducting when the AZB_X signal is at 0V. Thus, transistor M21 makes it possible to obtain a voltage of the adapted AZ_SHIFT control signal at the output of the CA2 priming circuit equal to 1.8V when the AZB_X signal is at 0V.

[0089] Thus, the voltage of the matched AZ_SHIFT control signal at the output of the priming circuit is between -0.9V and 1.8V. In particular, the voltage of the matched AZ_SHIFT control signal at the output of the priming circuit is 1.8V when the voltage of the AZB_X signal is 0V, and is -0.9V when the voltage of the AZB_X signal is 1.8V.

[0090] Such a voltage makes it possible to obtain a negative gate-source voltage on the auto-zero switch AZS. This makes it possible to reduce the losses of the auto-zero switch, particularly during the integration time.

[0091] In addition, applying a voltage of 1.8V for the control of the AZS auto-zero switch allows for better operation of this AZS auto-zero switch.

[0092] Figure 6 illustrates an APP device comprising an ambient light sensor as described previously. For example, the device could be a smartphone or a laptop.

Claims

1. Demands Ambient light sensor including: - a photodiode (PHD) configured to generate an electrical signal based on ambient light, - a capacitive feedback transimpedance amplifier (CTIA) connected at the input to the photodiode (PHD) to receive a signal generated by the photodiode and to generate at the output an amplified signal from the signal generated by the photodiode (PHD), the capacitive feedback transimpedance amplifier (CTIA) comprising an operational amplifier (op-amp) having an inverting input connected to the photodiode (PHD) and a non-inverting input connected to ground (GND), - a self-zeroing switch (AZS) at the input of the capacitive feedback transimpedance amplifier, the self-zeroing switch (AZS) having a first terminal connected to the inverting input of this operational amplifier and a second terminal connected to the non-inverting input of this operational amplifier, the self-zeroing switch being an NMOS transistor, and - a control circuit (CC) including a starting circuit (CA) configured for: To receive an initial logic control signal (AZB_X) with positive or zero voltage, then To generate, from this initial logic control signal, a suitable logic control signal (AZ_SHIFT) having a first positive voltage level and a second negative voltage level to control a gate of the self-zero switch (AZS), and in which the trigger circuit (CA) includes: - an inverter gate (INV1, INV2) configured to receive the initial logic control signal (AZB_X), - a capacitive element (CAPA1, CAPA2) with a first terminal connected to an output of the inverter gate, - a first PFET-type transistor (Mil, M21) having a gate configured to receive the initial logic control signal, a drain connected to the second terminal of the capacitive element (CAPA1, CAPA2) and a source configured to receive a common-mode voltage, - an output (OUT) connected to the second terminal of the capacitive element (CAPA1, CAPA2) and to the drain of the first transistor (Mil, M21) and configured to deliver the adapted control logic signal (AZ_SHIFT) to the auto-zero switch (AZS).

2. Sensor according to claim 1, wherein the initial control logic signal (AZB_X) has a first level at 1.8V and a second level at 0V, and the adapted control logic signal (AZ_SHIFT) has a first positive level at 0.9V when the initial control logic signal (AB_X) is at 0V, and a second negative level at -0.9V, when the initial control logic signal (AZB_X) is at 1.8V.

3. Sensor according to claim 1, wherein the trigger circuit (TC) further comprises: - a second NFET-type transistor (M22) having a source connected to the second terminal of the capacitive element, a gate configured to receive the initial logic control signal and a drain connected to the output of the trigger circuit, such that the output of the trigger circuit is connected to the second terminal of the capacitive element and to the drain of the first transistor via the second transistor, - a PFET-type transistor (M23) having a source connected to the output of the inverter gate, a gate configured to receive the initial logic control signal and a drain connected to the output of the trigger circuit.

4. Sensor according to claim 3, wherein the initial control logic signal (AZB_X) has a first level at 1.8V and a second level at 0V, and the adapted control logic signal (AZ_SHIFT) has a first positive level at 1.8V when the initial control logic signal (AB_X) is at 0V, and a second negative level at -0.9V, when the initial control logic signal (AZB_X) is at 1.8V.

5. Sensor according to any one of claims 1 to 4, wherein the capacitive feedback transimpedance amplifier (CTIA) comprises a capacitive element (CAP2) having a first terminal connected to an output of the operational amplifier (op-amp), and a second terminal connected to the inverting input of the operational amplifier (op-amp).

6. Device comprising an ambient light sensor (ALS) according to any one of claims 1 to 5.

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