CIRCUIT DE COMMUTATION COMPACT DOTE DE TRANSISTORS A HETEROJONCTION

Abstract

A switching circuit forming a bidirectional switch between a first node (NA) and a second node (NB) and resting on a substrate, the circuit comprising: - a first branch (47A) with a first diode (41) in series with a first field-effect heterojunction transistor (T1), - a second branch (47B) with a second field-effect heterojunction transistor (T2) in series with a second diode (42), the first branch (47A) and the second branch (47B) being mounted in parallel with each other and such that the first diode (41) and the second diode (42) are arranged in antiparallel or anti-series with respect to each other, the first transistor (T1), the second transistor (T2) each being provided with a control gate (G1, G2) opposite a heterojunction band forming an active region (40) in which an electron gas is capable of being formed,the first diode (41) being a Schottky diode with a metallic electrode (43) in contact with the heterojunction band, the second diode (42) being a Schottky diode with a metallic electrode (45) in contact with the heterojunction band, the first diode (41), the first transistor (T1), the second diode (42), the second transistor (T2) sharing the same active region (figure 5).

Description

Title of the invention: COMPACT SWITCHING CIRCUIT EQUIPPED WITH HETERO JUNCTION TRANSISTORS Technical field

[0001] The present application relates to the field of switching circuits, in particular power switching circuits intended to carry out voltage and / or current switching, and comprising at least one bidirectional operation in voltage or current or in voltage and current.

[0002] It relates in particular to the production of an improved switching circuit capable of operating as a 4-quadrant switch and capable of being used in particular for energy conversion, in particular in a range between several milliwatts and several tens of watts. STATE OF THE PRIOR ART

[0003] To achieve a bidirectional switch function also called 4-quadrant various arrangements exist.

[0004] It is known in particular to provide a circuit branch in which the following are associated: - a FET transistor (for “Field-Effect Transistor”) and a diode connected in series, or, - an IGBT transistor (for "Insulated Gate Bipolar Transistor") and a diode connected in series or a GTO thyristor (from the English "Gate Turn-Off Thyristor") and a diode connected in series, or even - an IGCT thyristor (for “Integrated Gate Commutated Thyristor”).

[0005] Such a branch makes it possible to perform a bidirectional voltage switch function and a unidirectional current switch function. To perform the bidirectional current switch function, two such branches are therefore associated in anti-parallel.

[0006] Thus a basic bidirectional switch cell Ci is illustrated in [Fig.l] and is here formed of two branches 7a, 7b arranged head to tail and each provided with a switch element preventing the passage of current under certain conditions (self-blocking or controlled blocking) and allowing this passage the rest of the time (self-priming and controlled primer).

[0007] We therefore obtain a bidirectional component in voltage and current, of which an ideal current-voltage characteristic is represented schematically in [Fig.2], in an orthogonal reference frame defining four quadrants Q1 (positive voltage positive current), Q2 (negative voltage positive current), Q3 (negative voltage positive current negative), Q4 (positive voltage negative current). For this component, also called a 4-quadrant switch, self-switching occurs here in quadrants Q2 and Q4, with, respectively, on the one hand, spontaneous blocking at zero current and spontaneous ignition at zero voltage, and on the other hand, spontaneous blocking at zero current and spontaneous ignition at zero voltage.

[0008] Document FR3°028°666°Al provides a particular bidirectional switch structure formed of 4 hetero-junction field effect transistors (or HEMT for “High-Electron-Mobility Transistor”, i.e. “high electron mobility transistor”) distributed in two branches, two transistors T[2, T2i being mounted as a diode, the other two Tu, T22 following a conventional assembly.

[0009] Such a structure is particularly suitable for power applications, since it is formed of transistors having a high breakdown voltage, with reduced conduction resistance and a potentially high current density.

[0010] As can be seen in [Fig.3B], the structure is formed in two active zones 15A, 15B distinct and spaced from each other, each of the active zones being formed of a stack of semiconductor layers respectively based on GaN and based on AlGaN forming a hetero-junction. Each branch of the switching structure is thus formed by an active zone 15A, 15B in which a 2D gas of electrons is produced. The two active zones are here typically separated from each other by means of an insulating zone 13 for example in the form of a trench.

[0011] A disadvantage of such a structure is its size, the latter occupying a total surface area equal to that of two individual active zones to which is added the insulation zone between the two active zones.

[0012] Furthermore, the use of diode-mounted transistors implies a trigger voltage Vf equal to the threshold voltage Vth of the transistor, which leads to losses in the on state.

[0013] The problem therefore arises of finding a new switching structure which is improved with respect to the drawbacks mentioned above. Statement of the invention

[0014] According to one aspect, the present invention relates to a switching circuit forming a bidirectional switch between a first node and a second node and resting on a substrate, the substrate being covered with a heterojunction strip forming an active zone in which an electron gas is capable of being formed, said circuit being provided with: - a first branch formed, between one end connected to the first node and another end connected to the second node: a first diode in series with a first field effect heterojunction transistor, - a second branch formed, between an end connected to the first node and a other end connected to the second node: of a second heterojunction field effect transistor in series with a second diode, the first branch and the second branch being connected in parallel with each other and so that the first diode and the second diode are arranged in anti-series or anti-parallel with respect to each other, the first transistor, the second transistor each being provided with a control gate facing a heterojunction strip forming an active zone in which an electron gas is capable of being formed, the first diode being a Schottky diode provided with a metal electrode called "first metal electrode" in contact with said heterojunction strip, the second diode being a Schottky diode provided with a metal electrode called "second metal electrode" in contact with said heterojunction strip, the first diode, the first transistor, the second diode, the second transistor sharing said same active zone.

[0015] Here, a diode and a transistor are advantageously combined in series, mounted in anti-series or anti-parallel, and Schottky diodes are used, the semiconductor zone of which is shared with that of the transistor.

[0016] Advantageously, the drain of the first transistor and the drain of the second transistor can be connected to each other. In this case, the transistors are in anti-series.

[0017] Thus the first diode, the first transistor, the second diode, the second transistor are respectively arranged so that when the first branch is turned on a first current is able to flow in said strip between the first metal electrode and a first conduction electrode of the first transistor, when the second branch is turned on a second current is able to flow in said same heterojunction strip between the second metal electrode and a first conduction electrode of the second transistor.

[0018] Compared to a circuit as implemented according to the prior art, losses in the on state are limited and only a single active zone is used to produce the two switching branches. This thus makes it possible to gain in compactness by a factor of two on the surface occupied on a substrate on which the circuit rests. This represents an advantage in terms of chip manufacturing cost and packaging.

[0019] According to a first possible arrangement, the switching circuit comprises, opposite the active zone in this order, and in a first direction x parallel to a main plane of the substrate: a first conduction electrode of the first transistor, a second conduction electrode of the first transistor, said first metal electrode belonging to the first diode, a first conduction electrode of the second transistor, a second conduction electrode of the second transistor, the second metal electrode belonging to the second diode.

[0020] Advantageously, the first metal electrode and the second metal electrode extend parallel to a second direction, orthogonal to the first direction, and have respective lengths measured parallel to the second direction greater than or equal to a width of the active zone measured in the second direction.

[0021] According to a second possible arrangement, the switching circuit may comprise, opposite the active zone in a first direction parallel to a main plane of the substrate: a first conduction electrode of the second transistor, the control gate of the second transistor, the first metal electrode, the second metal electrode, the control gate of the first transistor, a first conduction electrode of the first transistor, the first metal electrode and the second metal electrode being arranged between the control gate of the second transistor and the control gate of the first transistor.

[0022] Advantageously, the first transistor and the second transistor comprise a second conduction electrode, the second conduction electrode being common to the first transistor and to the second transistor, said second common conduction electrode being arranged between the first metal electrode and the second metal electrode.

[0023] Advantageously, the first metal electrode and the second metal electrode extend parallel to a second direction, orthogonal to the first direction, and have respective lengths measured parallel to the second direction less than a width of the active zone measured in the second direction, so that in the second direction a portion of the active zone located in the extension of the first metal electrode is not covered by the first metal electrode and so that in the second direction another portion of the active zone located in the extension of the second metal electrode is not covered by the second metal electrode.

[0024] According to a particular embodiment, the first transistor and / or the second transistor has a first conduction electrode, typically a source electrode, and a second conduction electrode, typically a drain electrode, each formed from an ohmic contact.

[0025] According to a third possible arrangement, the switching circuit may comprise, opposite the active zone in a first direction x parallel to a main plane of the substrate, a first region and a second region juxtaposed to the first region: the first branch and the second branch, distributed respectively in the first region and in the second region, - the first branch comprising, on a first axis parallel to the second direction and making a non-zero angle with the first direction and in particular orthogonal to the first direction: the first metal electrode, the control gate of the first transistor, a first conduction electrode of the first transistor, - the second branch comprising on a second axis parallel or substantially parallel to the first axis: a first conduction electrode of the second transistor, the control gate of the second transistor, the second metal electrode,

[0026] the first metal electrode and the second metal electrode being distributed on a third given axis making a non-zero angle with the first axis and the second axis, the control gate of the first transistor and the control gate of the second transistor being distributed on a fourth axis making a non-zero angle with the first axis (A1), the second axis (A2), and said third axis.

[0027] By "substantially parallel" is meant here those which make an angle of less than 10° with respect to each other.

[0028] Advantageously, the first transistor and / or the second transistor comprises a control gate which partially surrounds the first conduction electrode.

[0029] According to a particular embodiment, the first transistor and the second transistor each comprise a first conduction electrode comprising a metal zone in contact with said heterojunction strip, and in which the first transistor and the second transistor comprise a second conduction electrode constituted by a zone of said heterojunction strip.

[0030] Advantageously, the heterojunction band is surrounded by a structure configured to prevent diffusion of the 2D gas around said heterojunction band such as an insulating zone or a doped zone, in particular doped with Argon.

[0031] According to an advantageous embodiment, the first transistor and the second transistor are high electron mobility transistors HEMT, said heterojunction strip being formed of a first semiconductor layer, in particular based on AlGaN, stacked on a second semiconductor layer, in particular made of GaN.

[0032] The present invention also relates to a power electronic device comprising a converter, in particular AC / DC or DC / AC or AC / AC, provided with a plurality of switching cells, each switching cell being provided with a switching circuit as defined above. Brief description of the drawings

[0033] The present invention will be better understood on reading the description of exemplary embodiments given, for purely indicative and non-limiting purposes, by making reference to the attached drawings in which:

[0034] [Fig. 1] serves to illustrate an electrical diagram of an integrated switching circuit whose cells form a bidirectional switch;

[0035] [Fig.2] serves to illustrate an ideal current-voltage characteristic of a switch 4-quadrants;

[0036] [Fig.3A][Fig.3B] are used to illustrate a prior art integrated switching circuit forming a 4-quadrant switch suitable for power applications and produced from four HEMT transistors, two of which are diode-mounted to form two separate circuit branches produced in two separate active zones isolated from each other;

[0037] [Fig.4] serves to illustrate a switching circuit implemented according to the present invention with heterojunction transistors and Schottky diodes to form two switching branches this time in a single active zone;

[0038] [Fig.5] serves to illustrate a top view of a first embodiment of a switching circuit structure according to the invention;

[0039] [Fig.6] serves to illustrate a partial sectional view of the first embodiment of the switching circuit structure according to the invention;

[0040] [Fig.7A] [Fig.7B] [Fig.7C][Fig.7D] [Fig.7E] [Fig.7F] [Fig.7G] [Fig.7H][Fig.7I] are partial cross-sectional views of a portion of the switching integrated circuit at different stages of an exemplary manufacturing process;

[0041] [Fig.8] serves to illustrate a switching circuit structure implemented according to a second embodiment of the present invention;

[0042] [Fig.9] serves to illustrate a partial sectional view of the circuit structure of com mutation following the second embodiment;

[0043] [Fig. 10] serves to illustrate a switching circuit structure implemented according to a third embodiment of the present invention;

[0044] [Fig. 11] serves to illustrate a switching circuit structure implemented according to a fourth embodiment of the present invention;

[0045] [Fig. 12A][Fig. 12B] are partial sectional views of a portion of an exemplary switching integrated circuit according to the fourth embodiment of the present invention;

[0046] [Fig. 13] serves to illustrate a bidirectional AC / AC matrix converter in voltage and current, the elementary cells of which are each formed from a switching circuit and implemented according to the present invention;

[0047] [Fig. 14] serves to illustrate an AC / DC matrix converter whose elementary cells are each formed from a switching circuit implemented according to the present invention;

[0048] [Fig. 15] is used to illustrate a DC / AC matrix converter whose cells are each formed from a bidirectional voltage and current switching circuit and implemented according to the present invention;

[0049] Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the transition from one figure to another.

[0050] The different parts represented in the figures are not necessarily on a uniform scale, in order to make the figures more readable.

[0051] DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS

[0052] [Fig.4] is a schematic illustration of a switching circuit Cio as implemented according to the invention and configured to operate as a 4-quadrant, bidirectional voltage and current switch.

[0053] The switching circuit Cio is provided with two nodes NA, NB and comprises, between these nodes NA, NB, a first branch 47A, one end of which is connected to the first node NA and another end of which is connected to the second node NB. A second branch 47B of the circuit placed in parallel with the first branch is also provided with one end connected to the first node NA and another end connected to the second node NB.

[0054] The circuit Cio comprises a first transistor Ti and a second transistor T2, each of the field effect heterojunction type, in particular high mobility, advantageously high electron mobility (HEMT), as well as a first diode 41, and a second diode 42, in particular Schottky type diodes each provided with a metal electrode in contact with a heterojunction strip (not shown in [Fig. 4]). The heterojunction strip is typically provided with two joined semiconductor layers, in particular stacked and based on different gap materials. The heterojunction can be produced for example by means of an AlGaN / GaN stack.

[0055] More precisely, the first branch 47A includes the first diode 41 in series with the first transistor TH while the second branch 47B, parallel to the first branch 47A, includes the second transistor T2 in series with the second diode 42. The diodes 41, 42 are connected in anti-series with respect to each other. Thus, when the first diode 41 is conducting, a current from the first node NA is likely to flow through the first diode 41, while when the second diode 42 is conducting, a current from the second node NB is likely to flow through the second diode 42.

[0056] The first node NA is connected to a first conduction electrode, here source S2 of the second transistor T2 and to an anode 43, of the first Schottky diode 41, while the second node NB is connected to a first conduction electrode, here source SI of the first transistor Ti and to an anode 45, of the second Schottky diode 42. The first transistor Ti and the second transistor T2 can be each provided with a second conduction electrode D1, D2, here drain, the second conduction electrodes D1 and D2 being connected to another electrode, here the cathode, respectively of the first diode 41 and the second diode 42.

[0057] The first transistor Ti and the second transistor T2 are also each provided with a control gate Gh G2 to enable the conduction state of the transistors Ti and T2 to be controlled. The control potentials applied respectively to the transistors determine whether they are in an on or off state and the selective establishment of a current between the conduction electrodes. The gates can be controlled independently of each other by means of a control circuit (not shown) connected to these control gates Gl, G2. The control voltages of the gates are applied respectively with respect to the electrodes SI and S2. When it is considered that the connection between the drain electrodes Dl and D2 is optional, the diodes are in anti-parallel with respect to each other.

[0058] An alternative configuration without providing a specific conductive track on the active area to connect the drain electrodes together is possible. Such a circuit makes it possible to form a power switch with bidirectional operation in current and / or voltage with reduced conduction losses.

[0059] The use of heterojunction transistors Ti, T2 makes the switching circuit particularly suitable for power applications, since these transistors Tb T2 have a high breakdown voltage, with reduced conduction resistance and potentially high current density.

[0060] The switching circuit here has the particularity of having the first transistor Ti, the second transistor T2, the first diode 41, the second diode 42 which are formed from the same heterojunction strip in which an electron gas is likely to extend. Thus, it is planned to produce the two branches 47A, 47B of the circuit in a single heterojunction strip forming a single active zone. This is possible because a portion of the diodes is produced in the stack of semiconductor layers forming the heterojunction.

[0061] This allows a significant gain in compactness, which promotes integration density. A surface gain of a factor of 2 can in particular be obtained compared to a structure such as presented previously in connection with [Fig.3B], and a factor of 3 can be obtained compared to a circuit formed of four discrete components. In addition to the space saving, such a configuration makes the circuit manufacturing process less expensive.

[0062] [Fig. 5] gives a top view of a first example of topography of such a switching circuit, with an active zone 40, in which an electron gas is likely to be formed, represented here schematically by a broken line frame.

[0063] The first transistor Ti and the second transistor T2, as well as the first Schottky diode and the second Schottky diode are arranged along the same heterojunction strip, which may have an elongated shape, and intended to form the active zone 40. The heterojunction strip is produced on a substrate which is not shown in this figure but of which a main plane extends parallel to the plane [O; x; y] of the orthogonal reference frame [O; x; y; z] given in [Fig.5].

[0064] In the particular embodiment illustrated, the active zone 40 has a rectangular or substantially rectangular shape with a first dimension (not referenced), in particular its length measured parallel to a first direction along the x axis of the orthogonal reference frame [O; x; y; z], and a second dimension yl, in particular its width, measured parallel to a second direction along the y axis of the orthogonal reference frame [O; x; y; z].

[0065] The arrangement is here provided so that the circuit comprises in the first direction: a first conduction electrode of the first transistor Ti, here its source SI, the control gate Gl of the first transistor Tb a second conduction electrode of the first transistor Ti, here its drain Dl, a metal electrode 43 of the first diode 41, a first conduction electrode of the second transistor T2, here its source S2, the control gate G2 of the second transistor T2j a second conduction electrode of the second transistor T2, here its drain D2, a metal electrode 45 of the first diode 4L

[0066] Advantageously, the electrodes S1, G1, D1, 43, S2, G2, D2, 45 are arranged parallel to each other and extend orthogonally to the first direction, in other words are directed in the direction of the width of the heterojunction strip.

[0067] In this embodiment, the arrangement of the electrodes S1, G1, D1, S2, G2, D2, S3, S4, G2, D2, S5 is such that they cover the active zone 40 over its entire width y1. Thus, the first metal electrode 43 and the second metal electrode 45 form metal strips which extend parallel to the second direction y and have respective lengths which may be greater than or equal to the width y1 of the active zone 40.

[0068] To delimit the active zone 40, the heterojunction band may be surrounded by a structure 51 configured to prevent the presence of the 2D gas around said heterojunction band, for example an insulating zone or a doped zone, for example an Argon-doped zone and formed in the stack of materials of different Gaps in which the heterojunction band is produced.

[0069] Here, advantageously, for each transistor Ti, T2, a distance x2, x'2 (dimensions measured parallel to the first direction x) between its gate Gl, G2 and its source SI, S2 is provided, sufficient to support the gate bias voltage between the gate and the source. A distance x4 (dimension measured parallel to the first direction x) between its gate Gl, G2 and its drain Dl, D2 is preferably provided sufficient to support the bias voltage between drain and gate. In the particular embodiment illustrated, x2 is less than x4.

[0070] A distance x3 (dimension measured parallel to the first direction x) is also preferably provided between the metal electrode 43, 45 of each of the Schottky diodes 41, 42 and the drain D1, D2 of the given transistor with which this diode is connected in series, equal to the distance x4 sufficient to withstand the voltage between the Schottky contact and the drain. In the particular embodiment illustrated, x3 is equal to x4.

[0071] The table below gives examples of values ​​of these dimensions x2, x3, x4, and that of the electrodes and the active zone for the arrangement of [Fig.5], Xschot, XD1, XG1, XS1, XD2, XG2, XS2 corresponding to the respective widths (dimensions measured parallel to the first direction x) of the electrodes 41 and 45, D1, Gl, SI, D2, G2, S2, and this to support a voltage of the order of 650 V and a current of the order of 50 mA. [Table 1]

[0072] ___________________________________________ Example of dimensions for the arrangement of Figure 5 Unit: X2 0 5 x3 10 x4 10 Xschot 1 XD1 1 XG1 0.5' XS1 1 XD2 1 XG2 0.5 XS2 1 Total x 48 y1 500 Total y 500 In Figure 6, a sectional view of a part of the switching circuit is given. The second transistor T2 provided with its electrodes D2, G2, S2, the first diode 41 whose metal electrode 43 is located between the first transistor, in particular its drain DI, and the second transistor T2, in particular its source S2, are shown. The source, the gate of the first transistor Ti, as well as the metal electrode of the second diode, are not shown here. The two circuit branches are therefore made from the same heterojunction strip 62 in which a layer of electron gas 2Deg is shown schematically by a dotted line. The heterojunction strip 62 rests on a substrate 60 which may be semiconducting, for example made of silicon or GaN or another type of material. A sapphire substrate (A12O3) may be used in particular.

[0073] The source and drain electrodes of the transistors T2 are typically in the form of ohmic contacts 65 formed of a zone 65A of metal in contact with a semiconductor region 65B of the heterojunction strip 62 in which metal has diffused. As an alternative to metal diffusion, the semiconductor region 65B of the source or drain electrodes may be a doped zone produced by ion implantation.

[0074] The metal electrode 43 of each diode 41 forms a Schottky contact 64 with a semiconductor region 64B of the heterojunction strip 62. The semiconductor regions 64B, 65B are in particular zones of an upper semiconductor layer 612 of a stack forming the heterojunction. This upper semiconductor layer 612 is typically a so-called barrier layer, formed from a ternary alloy of a nitride of a type III element such as, for example, AIGaN.

[0075] In the particular embodiment illustrated in [Fig. 6], the metal electrode 43 (resp. 45) of each Schottky diode 41 (resp. 42) is connected to a conduction electrode, in particular the source S2 of the transistor T2 of the other branch by means of a metal connection zone 67 formed in a first metal level Mi of connections. This metal connection zone 67 is here more precisely in contact with the metal zone of the source electrode and can also be connected to a field plate electrode 69 placed opposite a portion of the gate of the transistor T2 (resp. Ti). Such a field plate can make it possible to avoid an electric field peak at the foot of an insulating zone 66B serving as a gate dielectric.

[0076] In this particular embodiment, the control gates G1, G2 form a gate contact 66 in the form of a MIS (For “Metal Insulating Semiconductor”) type structure comprising a metal zone 66A resting on an insulating zone 66B in contact with a semiconductor zone 66C of the heterojunction strip. The stack of the metal zone 66A and the insulating zone 66B is here arranged in a trench whose bottom is located in the heterojunction strip, in particular in a lower semiconductor layer 611 forming with said upper semiconductor layer 612 the heterojunction.

[0077] The lower semiconductor layer 612 may be provided in a binary alloy of a nitride of a type III element, for example GaN. Thus, the gate Gl, G2 extends in this example below the level in which the electron gas layer 2Deg, the latter being typically located at the interface between the lower semiconductor layer 611 and the upper semiconductor layer 612.

[0078] Alternatively, other gate configurations with or without a trench may be provided. Among other arrangements, a gate disposed directly on the barrier layer, a gate disposed on a doped layer resting on the barrier layer, a gate arranged on an implanted area of ​​the barrier layer may also be provided.

[0079] It is preferably provided to dimension each portion of Schottky diode 41 (resp. 42) in the heterojunction strip 62 with a first minimum distance L i greater than a given threshold between a zone of the metal electrode 43 (resp. 45) in contact with the heterojunction strip and a drain zone DI (resp. D2) of the transistor Ti (resp. T2) with which this diode 41 is arranged in series. Such a distance is dependent and in particular proportional to a desired voltage withstand for the structure.

[0080] Similarly, the dimensioning of each transistor T2 (resp. TJ) is preferably chosen with a second minimum distance L2 greater than a given threshold between a region of the heterojunction band against which its gate G2 (resp. Gl) is formed and its drain D2 (resp. Dl). Such a distance is also dependent and in particular proportional to a desired voltage resistance for the structure.

[0081] For example, in a case where it is desired to obtain a bidirectional voltage withstand of the order of 650V, the first distance Li can be provided, for example, of at least 10 pm. The second distance L2 can, for its part, be provided, for example, of at least 10 pm. These distances Lh L2 depend on the constitution of the heterojunction band and in particular on the large gap material forming this heterojunction. In the case, for example, where this large gap material is GaN, these values ​​can be determined by considering a withstand before breakdown of the order of 3 MV / cm and typically by providing a margin in order to avoid an electric field greater than 0.3 MV / cm.

[0082] Although a particular case of a heterojunction transistor of the AIGaN / GaN type has been mentioned previously, other structures with different heterojunctions, for example such as GaAIAs / GaAs, or GaAIAs(N+) / InGaAs(nd) / GaAs, can also be envisaged.

[0083] An example of a sequence of steps of a method for manufacturing a switching circuit of the type described previously will now be illustrated in connection with FIGS. 7A to 71.

[0084] A possible starting material of the method is a substrate 700, which may be semiconducting, for example made of silicon with a thickness of, for example, the order of 1 mm. The substrate 700 is coated with a first semiconducting layer 702, in particular based on a wide bandgap semiconductor and of type III / V, for example such as GaN. The first semiconducting layer 702 is itself coated with a second semiconducting layer 704 which may be formed by epitaxy and in particular based on a direct gap material such as, for example, aluminum-gallium nitride (AlxGabxN). This layer 704 forms a heterojunction with the first semiconducting layer 702 and an electron gas layer is intrinsically formed at the interface between these two layers 702, 704.

[0085] As illustrated in [Fig.7A], a first passivation layer 706 can then be deposited on the second semiconductor layer 704. This first passivation layer 706 is made of an insulating material such as, for example, silicon nitride.

[0086] In the embodiment illustrated in [Fig.7B], the first dielectric passivation layer 706 is then coated with other passivation layers so as to form an alternation of layers 706, 710 made of an insulating material, for example silicon nitride, and layers 708, 712 made of another insulating material such as, for example, silicon oxide.

[0087] One or more steps of etching the passivation layers 706, 708, 710, 712 can then be implemented to form openings including a first opening 715 giving access to the second semiconductor layer 704 and a second opening 717 made through the second semiconductor layer 704 and revealing the first semiconductor layer 702. In the particular embodiment illustrated in [Fig.7B], the production of the first opening 715 comprises the removal of an upper portion of the second semiconductor layer 704.

[0088] According to a particular embodiment, to produce the first opening 715, a thickness of the order of 10 nm can be removed from a semiconductor layer 706 of AlGaN with a thickness of the order of 25 nm. According to this same example, to produce the second opening 717, a thickness of the order of 80 nm can be removed from a semiconductor layer 702 of GaN with a thickness of the order of 4 pm.

[0089] Next, a dielectric layer 721 is formed in the openings, and in particular in the first opening 715 and the second opening 717. This dielectric layer 721 is, for example, based on Al2O3 and has a thickness of around 30 nm and can be formed by the ALD technique (for “Atomic Layer Deposition”).

[0090] Then ([Fig.7C]), a metal layer 723 is deposited. This metal layer 723 is for example based on TiN and has a thickness of the order of 60 nm and can be formed by PVD technique (for “Physical Vapor Deposition”).

[0091] At least one orifice 725 is then produced ([Fig.7D]) at the level of the stack located in the first opening 715 in order to reveal the first semiconductor layer 704. Such an orifice 725 is typically produced by photolithography and etching, for example using plasma (dry etching).

[0092] Then ([Fig.7E]), one or more metal layers are deposited. Typically, a stack of a thin metal layer 731, for example based on TiN of 60 nm and at least one other metal layer 733, for example tungsten with a thickness of the order of 300 nm, is produced in order to produce a Schottky type contact in the orifice 725. These metal layers 731, 733 can also be used to fill the second opening 725.

[0093] One or more patterns are then formed by etching the stack of layers 721, 723, 731, 733 so as to define electrodes. In [Fig.7F], a gate electrode G1 of the first transistor Ti and a metal electrode 43 of the first diode 41 are shown.

[0094] The electrodes can then be covered with an insulating layer 742 ([Fig.7G]). The insulating layer 742 is made for example of SiO2. A PECVD technique for (“Plasma-Enhanced Chemical Vapor Deposition” or plasma-assisted chemical vapor deposition) can be used to achieve a thickness for example of the order of 150 nm.

[0095] One or more connection elements 761, 762, 763 can then be defined, some of which 761, 763 are in contact with the first semiconductor layer 702 ( [Fig.7H]). For this purpose, holes 751, 753 are first made, revealing the first semiconductor layer 702. The production of such holes 751, 753 can comprise one or more dry etching steps. Then, one or more metallic materials are deposited. For example, a layer is first formed, then a barrier layer such as a 60nm TiN layer using a deposition process which can be of the PVD (Physical Vapor Deposition) type, then a layer of aluminum and copper alloy Al:Cu of the order of 200 nm.

[0096] Another insulating layer 771 is then formed, followed by a first metallic interconnection level 773 ([Fig.71]). For this purpose, one or more metallic materials are deposited. For example, a layer of Ti of the order of 20 nm is first formed, then a layer of TiN of the order of 20 nm and aluminum. The deposition can be completed, for example, by a layer of copper of the order of 1.4 pm, Ti of the order of 20 nm, and TiN of the order of 40 nm. Such metallic layers can be formed for example by PVD.

[0097] According to an alternative embodiment of the structure described above, in order to further limit the size of the transistors Tb T2, it is possible to provide, as in the example embodiment illustrated in [Fig. 8], an arrangement with a drain electrode D[2 common to the first transistor Ti and to the second transistor T2. It is thus possible to combine the drain electrodes into a single ohmic contact and avoid using an additional metal connection above.

[0098] In the illustrated embodiment, the metal electrodes 43, 45 of the diodes 41, 42 also advantageously have a shorter length than the other electrodes and in particular than the common drain electrode D[2. The metal electrodes 43, 45 thus extend opposite only a portion of the width yl of the active zone 40. A portion 81 of the active zone 40 located in the extension of the first metal electrode 43 and which extends in the second direction y, is not covered by the first metal electrode 43. Similarly, another portion 82 of the active zone 40 located in the extension of the second metal electrode 45 and which extends in the second direction y is not covered by the second metal electrode 45.Such an arrangement allows for better compactness, the portions 81, 82 of the active zone serving in this case as channel regions respectively of the second transistor T2 and of the first transistor T1. The two channel regions are here offset relative to each other.

[0099] The table below gives examples of values ​​of certain dimensions of this arrangement, with in particular xn: a distance measured parallel to the first direction x between the common drain electrode Dn and the first and / or second metal electrode 43, 45, xn: a distance measured parallel to the first direction x between the control gate G1 (resp. G2) and the metal electrode of the diode D2 belonging to the opposite branch, y2 the length of the portions 81, 82 located in the respective extension of the metal electrodes and measured parallel to the second direction y, Xschot, XD1, XG1, XS1, XD2, XG2, XS2 corresponding in the case of a circuit supporting a voltage of the order of 650 V and a current of the order of 50 mA.

[0100] [Table 2] Arrangement of Figure 8 Unit: pm »2 10 Xl3 10 Xschott XD1 0 XG1 0.5 XS1 XD2 0 0.5 In [Fig.9], a partial sectional view (along a section plane parallel to the plane [O; x; z]) of this same switching circuit is given. Only a part of the first transistor and the second diode 43 are shown, but the two branches have similar structures. The source electrode SI of the first transistor Ti is in the form of an ohmic contact 65, the gate G1 forming a structure 66 MIS and the metal electrode of the second metal diode 45 forming a Schottky contact 64. The metal electrode 45 of the second Schottky diode 42 is connected here to a field plate electrode 99 via a metal connection zone 97 formed in a first metal level Mi of connections.

[0101] A variant of the embodiment described previously in connection with [Fig. 10], provides an arrangement without a metal drain electrode or without a metal zone to form the drain electrode of the transistors Tb T2. The drains of the transistors Tb T2 of the transistors are then formed respectively in zones 101, 102 of the heterojunction strip, which again makes it possible to gain in compactness of the circuit.

[0102] Another example of arrangement of the switching circuit is given in [Fig.l 1]. The circuit this time comprises, opposite the active zone 40 in a first direction parallel to the axis x of the reference [O; x; y; z] and to the main plane of the substrate, all of the elements forming the first branch located in a first region 110a of the active zone 40, and all of the elements forming the second branch located in a second region 110b of said active zone 40 juxtaposed with the first region 110.

[0103] The first branch comprises, on a given axis Al along a second direction making a non-zero angle with the first direction and in particular orthogonal to the first direction: the first metal electrode 43, the control gate G1 of the first transistor Ti, the source electrode SI of the first transistor Ti.

[0104] The second branch comprises, on an axis A2 which may be parallel to the first axis A1 and to the second direction making a non-zero angle with the first direction and in particular orthogonal to the first direction: the source electrode S2 of the second transistor T2, the control gate G2 of the second transistor T2, the second metal electrode 45. In this configuration the drain contacts are eliminated. Thus, it is not necessary here to provide a specific additional track or ohmic contact to make the drain electrodes. The drain electrode is then only made up of a portion of the semiconductor stack forming the heterojunction strip.

[0105] The metal electrode 43 of the first diode and the metal electrode 45 of the second diode are distributed on an axis A4 making a non-zero angle with the axes Al and A2, while the control gate G1 of the first transistor Ti and the control gate G2 of the second transistor T2 are distributed on an axis A3 making a non-zero angle with the axes Al, A2, A3.

[0106] When the first branch 47a is conducting (i.e. when the first diode 41 and the first transistor Ti are conducting) a current h oriented along the axis Al is likely to flow between a part of the heterojunction strip located opposite the first metal electrode 43 and a part of the heterojunction strip located opposite the source electrode SI of the first transistor TL

[0107] When the second branch 47b is conducting (i.e. when the second diode 42 and the first transistor T2 are conducting) a current I2 oriented along the axis A2 is likely to flow between a part of the heterojunction strip located opposite the second metal electrode 45 and a part of the heterojunction strip located opposite the source electrode S2 of the second transistor T2. The currents L and I2 thus flow in the heterojunction strip in the same direction but in opposite directions to each other.

[0108] Advantageously, the control grids G1 and G2 partially surround respectively the source electrode SI of the first transistor Ti and the source electrode S2 of the second transistor T2. The gates Gl, G2 are therefore here not formed from a rectilinear zone but from portions which extend in different directions from each other. In the embodiment illustrated in [Fig.11], the gates Gl, G2 have a 'U' shape around the source electrodes SI, S2. In particular, the gates Gl, G2 have a portion 111 which extends in a first direction, here parallel to that corresponding to the length of the active zone and portions 112, 113 which extend in a first direction, here parallel to that x in which the length of the active zone is measured. The configuration of the gates Gl, G2 makes it possible to achieve adjustable insulation between the different components forming the two branches of the circuit.Such an embodiment is particularly suitable for applications operating in lower current ranges than those of the embodiments described previously. In the particular embodiment shown, the 'U'-shaped grids G1, G2 are arranged head to tail with respect to each other.

[0109] A given distance x2i (dimension measured parallel to the x direction) is provided between each gate Gl, G2 of transistor Tb T2 and the metal electrode 45, 43 of the other branch. A distance y3 (dimension measured parallel to the y direction) can also be provided between the metal electrode 43, 45 of each of the Schottky diodes 41, 42 and the gate of the transistor Tb T2 of the branch in which this diode is arranged. A distance d > y3 can also be provided between the two metal electrodes 43, 45 of the Schottky diodes 41, 42.

[0110] The table below gives examples of values ​​of these dimensions and that of the electrodes and the active zone for the arrangement of [Fig. 11] to support a voltage of the order of 650 V and a current of the order of 50 mA. [YES] [Table 3] Dimensions of the exemption from the realization of figure 11 Unit: pm x1 05 x21 =x2 0.5 Xschott 500 XG1 0.5 XS1 500 Total x 1002.5 yi 1 +0.5+05+10+1 y2Q—y2 1 y3 10 Total y 24 Total Surface 24060 Figures 12A-12B give sectional views, respectively along a section plane parallel to the plane [O; x; y] of the orthogonal reference frame [O; x; y; z] and a section plane parallel to the plane [O; y; z] of the configuration example previously given.

[0112] The metal electrodes 43, 45 respectively of the first diode, of the second diode again form Schottky contacts 64, while the gates G1, G2 form a structure 66 of the MIS type. The first conduction electrode, here the source S1, S2 of the transistors T1, T2 is again in the form of an ohmic contact 65.

[0113] The metal electrodes 43, 45 and source electrodes are here coated with connection pads formed in a first level of metal Mb

[0114] One or other of the structures described previously in connection with figures 5, 8, 10, 11 can be repeated several times on the same heterojunction strip to form a switching circuit.

[0115] Although the embodiments of the switching circuit have been described with high electron mobility heterojunction field effect transistors Tb T2, it is possible, as a variant of one or other of the embodiments presented previously, to provide for the integration therein of high electron mobility heterojunction field effect transistors. of holes.

[0116] A bidirectional switching circuit can also be used as a power switch in a power electronic device and in particular in a matrix converter.

[0117] For example, as illustrated in [Fig. 13], an AC / AC matrix converter is formed from a matrix of cells 130, in this example a 3*3 matrix each provided with at least one switching circuit CIO whose principle diagram has been presented in [Fig. 4] and implemented according to one or other of the embodiments described previously.

[0118] According to another example of application given in [Fig. 14], an AC / AC matrix converter comprises a plurality of cells 140, each formed of at least one switching circuit CIO.

[0119] A third example of application this time concerns a DC / AC type converter and whose cells 150 each integrate at least one switching circuit Cio described above.

Claims

Claims

1. Switching circuit (Cio) forming a bidirectional switch between a first node (NA) and a second node (NB) and resting on a substrate (60), the substrate being covered with a heterojunction strip (62) forming an active zone (40) in which an electron gas is capable of being formed, said circuit being provided with: - a first branch (47A) formed, between one end connected to the first node (NA) and another end connected to the second node (NB): a first diode (41) in series with a first field effect heterojunction transistor (Ti), - a second branch (47B) formed, between one end connected to the first node (NA) and another end connected to the second node (NB): a second field effect heterojunction transistor (T2) in series with a second diode (42), the first branch (47A) and the second branch (47B) being connected in parallel with each other and so that the first diode (41) and the second diode (42) are arranged in anti-series or anti-parallel with respect to each other, the first transistor (Ti), the second transistor (T2) each being provided with a control gate (Gl, G2) facing said heterojunction strip (62), the first diode (41) being a Schottky diode provided with a metal electrode called the first metal electrode (43) in contact with said heterojunction strip (62),the second diode (42) being a Schottky diode provided with a metal electrode called second metal electrode (45) in contact with said heterojunction strip (62), the first diode (41), the first transistor (Ti), the second diode (42), the second transistor (T2) sharing said same active area (40), wherein, said circuit comprises, opposite the active area (40) in a first direction (x) parallel to a main plane of the substrate: a first conduction electrode (S2) of the second transistor (T2), the control gate (G2) of the second transistor (T2), the first metal electrode (43), the second metal electrode (45), the control gate (G1) of the first transistor (TJ, a first conduction electrode (SI) of the first transistor (Ti), the first metal electrode (43) and the second metal electrode (45) being arranged between the control gate (G2) of the second transistor and the control gate (G1) of the first transistor, wherein the first metal electrode (43) and the second metal electrode (45) extend parallel to a second direction, orthogonal to the first direction, and have respective lengths measured parallel to the second direction less than a width (yl) of the active zone (40) measured in the second direction, such that in the second direction a portion (81) of the active zone (40) located in the extension of the first metal electrode (43') is not covered by the first metal electrode and such that in the second direction another portion (82) of the active zone located in the extension of the second metal electrode is not covered by the second metal electrode, said portions (81, 82) not covered by the metal electrodes (43, 45) respectively forming a channel region for the first transistor and the second transistor.

2. Switching circuit according to claim 1, wherein said circuit (Cio) comprises, opposite the active zone (40) in this order, and in a first direction (x) parallel to a main plane of the substrate: a first conduction electrode (SI) of the first transistor (Ti), the control gate (Gl) of the first transistor (Tl), a second conduction electrode (Dl) of the first transistor (Ti), the first metal electrode (43), a first conduction electrode (S2) of the second transistor (T2), the control gate (G2) of the second transistor (T2), a second conduction electrode (D2) of the second transistor, the second metal electrode (45).

3. A switching circuit according to claim 2, wherein the first metal electrode (43) and the second metal electrode (45) extend parallel to a second direction, orthogonal to the first direction, and have respective lengths measured parallel to the second direction greater than or equal to a width of the active area (40) measured in the second direction.

4. A switching circuit according to claim 1, wherein the first transistor (TJ) and the second transistor (T2) comprise a second conduction electrode (D[2), the second conduction electrode being common to the first transistor (Ti) and the second transistor (T2), said second common conduction electrode (D[2) being arranged between the first metal electrode (43) and the second metal electrode (45).

5. Switching circuit according to one of claims 1 to 4, the first transistor (TJ and / or the second transistor (T2) having a first conduction electrode (SI, S2) and a second conduction electrode (Dl, D2) formed by an ohmic contact.

6. Switching circuit according to claim 1, wherein the first transistor and the second transistor each comprise a first conduction electrode (SI, S2) comprising a metal zone (65A) in contact with said heterojunction strip, and wherein the first transistor and the second transistor comprise a second conduction electrode (Dl, D2) constituted by a zone (101, 102) of said heterojunction strip.

7. Switching circuit according to one of claims 1 to 6, wherein said heterojunction strip (60) is surrounded by a structure (61) configured to prevent diffusion of the 2D gas around said heterojunction strip such as an insulating zone or a doped zone, in particular doped with Argon.

8. Switching circuit according to one of claims 1 to 7, wherein said first and second transistors (T1, T2) are high electron mobility transistors (HEMT), said heterojunction strip being formed of a first semiconductor layer (612, 704) in particular based on AlGaN stacked on a second semiconductor layer (611, 702), in particular made of GaN.

9. Power electronic device comprising a converter, provided with a plurality of switching cells (130, 140, 150), each switching cell being provided with a switching circuit (Cio) according to one of claims 1 to 8.

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