Transistor control device and control method

Abstract

Title: Transistor control device and control method The invention relates to a transistor control device (1) FDSOI comprising: - A plurality of first boxes (21, 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h) having a first type of conductivity (P), each first box (21) being associated with a group of transistors (20), - At least one second box (22, 22a, 22b, 22c, 22d) having a second type of conductivity (N), formed under and around the first boxes (21), - A biasing circuit configured to apply at least one first bias voltage V1 to the first boxes (21), and at least one second bias voltage V2 to at least one second box (22). Advantageously, all the transistors (20) have the second type of conductivity (N). The invention also relates to a method for controlling the aforementioned device. Figure for the abstract: Fig. 1

Description

Title of the invention: Transistor driving device and driving method Technical field

[0001] The present invention relates, in general, to a driving device comprising a plurality of transistors having the same type of conductivity, and more particularly, transistors of the same type on a fully depleted semiconductor-on-insulator substrate. The present invention also relates to a method for driving this transistor driving device. An advantageous application of this transistor driving device relates to resistive memory circuits of the RRAM type (acronym for "Resistive Random Access Memories"). STATE OF THE ART

[0002] Resistive memories, in particular resistive memories of the OxRAM type (acronym for "Oxide-Based Random Access Memories") are currently being developed for non-volatile applications, with the aim of replacing Flash type memories. They have the particular advantage of being integrable with the BEOL (Back-End Of Line) process of CMOS technology (acronym for "Complementary Metal-Oxide-Semiconductor" technology based on "Complementary Metal-Oxide-Semiconductor" transistors).

[0003] Resistive memories typically comprise a multitude of memory cells arranged in the form of a matrix. In a so-called “1T1R” configuration, each memory cell (also called a memory point) comprises a resistive memory element (“IR”) associated with a selection transistor (“1T”).

[0004] The resistive memory element can reversibly switch between two resistance states, which correspond to logic values ​​"0" and "1" used to encode a bit of information.

[0005] The information is written into the memory cell by switching the resistive memory element from a highly resistive state (or “HRS” for “High Resistance State”) to a weakly resistive state (“LRS” for “Low Resistance State”). Conversely, to erase the information from the memory cell, the resistive memory element is switched from the weakly resistive state to the highly resistive state.

[0006] In some cases, more than two resistance states can be generated, which makes it possible to store several bits of information in a single memory cell. These are called multi-level cells (MLCs) (acronym for “Multi Level Cells”).

[0007] The writing and erasing of these MLC multilevel cells can be achieved by finely controlling, in an analog manner, the voltage applied to the different connections of the memory cell. These connections are known as "bitline" BL (connection to the resistive element), "sourceline" SL (connection to the source of the selection transistor), "wordline" WL (connection to the gate of the selection transistor). Other known writing and erasing solutions consist of varying the duration of the so-called SET / RESET switching operations (switching from HRS to LRS / switching from LRS to HRS, respectively), typically by adjusting the width of the applied voltage pulses. This "analog" management of writing and erasing nevertheless requires new circuits for generating or regulating analog voltages and currents and / or a significant modification of the existing circuits.

[0008] Furthermore, the size of a 1T1R memory cell is mainly dictated by the surface area of ​​the substrate occupied by the selection transistor, rather than by the dimensions of the memory element, the latter being located at the metallization level (BEOL). To increase the density of resistive memories, it is therefore necessary to reduce the surface area occupied by the selection transistor of each memory cell. This reduction is typically carried out at the expense of the current that the selection transistor is capable of delivering. The programming window of the memory cell is therefore reduced. One solution consists of applying a bias to the rear face of the transistor (a technique called BB for "back-biasing" in English), which makes it possible to dynamically modulate the threshold voltage of the transistor and therefore its capacity to supply current.Forward back bias (or FBB) of the selection transistor generally reduces the threshold voltage and increases the on-current, for example during a memory cell write operation. Reverse back bias (or RBB) of the selection transistor typically limits current leakage, for example during a memory cell read operation. Different architectures implementing RBB bias have been developed. The document "Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)" describes a memory cell architecture based on complementary transistors on a fully depleted silicon-on-insulator (FDSOI) substrate.The implementation of BB polarization remains limited and partly ineffective in this type of architecture. Memory cells in particular exhibit inhomogeneous performance with this type of architecture.

[0009] There is therefore a need to increase the passing current while limiting the current leaks, homogeneously for all memory cells, and thus allow MLC programming and / or a reduction in the size of the memory cells.

[0010] An objective of the present invention is to meet this need, and to at least partially overcome the drawbacks mentioned above.

[0011] Other objects, features and advantages of the present invention will become apparent from the following description and accompanying drawings. It is understood that other advantages may be incorporated. SUMMARY

[0012] To achieve this objective, according to a first aspect, a transistor control device is provided comprising: - A substrate based on a semiconductor material, having a first type of conductivity, - An insulating layer based on a dielectric material on said substrate, - A layer based on the semiconductor material, called the active layer, located on the insulating layer, - A plurality of transistors each comprising a channel formed in the active layer and configured to be completely depleted, - A plurality of first wells formed in the substrate and having the first type of conductivity, each first well being associated with and arranged under a group of transistors of the plurality of transistors, - At least one second box having a second type of conductivity, formed in the substrate under and around the first boxes, so as to insulate the first boxes from each other and from the substrate, - A bias circuit configured to apply at least a first bias voltage VI to the first wells, and at least a second bias voltage V2 to the at least one second well.

[0013] Advantageously, all of the transistors of the plurality of transistors have the second type of conductivity.

[0014] Thus, unlike the known transistor architecture disclosed in the document “Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)”, the device according to the present invention only comprises transistors having a single type of conductivity, typically an N-type conductivity. This makes it possible to increase the performance of all the transistors by applying, for example, a single first bias voltage in the FBB “forward reverse bias” configuration via the bias circuit. On the contrary, in the known architecture comprising complementary transistors of N-type and P-type transistors, by polarizing all the transistors in FBB with a single potential, some will be accelerated and others slowed down, which limits the overall performance gain. To partially overcome this drawback, a solution proposed by the document "Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications embedding 16MB Phase Change Memory, F. Arnaud et al, IEDM18-424 (2018)" consists of using transistors and wells associated with these transistors having the same type of conductivity, according to an architecture known as "flip well". On the contrary, in the device according to the present invention, the transistors and their associated wells have two different types of conductivity.

[0015] The device according to the present invention also makes it possible to limit the current leaks of all the transistors by applying a first bias voltage in “reverse back bias” RBB configuration via the bias circuit.

[0016] Thus, the device according to the present invention makes it possible to obtain good homogeneity of the performances of the transistors. It allows operation of the transistors in FBB or in RBB with a single architecture, depending on the first bias voltage applied.

[0017] The use of at least one second voltage-controlled box allows dynamic isolation of the first boxes from each other. The range of possible values ​​for the first BB bias voltage can thus be extended. This ultimately allows the threshold voltages of the transistors to be modified more strongly or more significantly. In the case of a reduction in the threshold voltages, the performance of these transistors increases. The size of the transistors can thus be reduced. This also allows the current leakage of the transistors to be reduced in native BB, i.e. without FBB. The static consumption of the device is thus reduced.

[0018] Typically, the variation in potential of the second well does not modify the conductivity of the transistor(s) located on the first well(s). The second well makes it possible in particular to isolate the first wells from each other and from the substrate. The variation in the potential of the second well advantageously makes it possible to double the potential range of the first well.

[0019] According to another aspect, a method of driving the transistor driving device is provided, comprising: - Applying a first bias voltage VI to at least one first box of the plurality of first boxes, - Applying a second bias voltage V2 to the at least one second box surrounding said at least one first box.

[0020] Said applications of the first and second voltages VI, V2 are such that there is no there is no electrical conduction between said at least one first and second box. The second box thus acts as electrical insulation between the first boxes.

[0021] This dynamic isolation of the first boxes from each other, controlled via the bias circuit, advantageously makes it possible to extend the range of possible values ​​for the first bias voltage BB. This extended range of values ​​typically makes it possible to envisage MLC programming when the transistors are selection transistors associated with resistive elements and forming 1T1R memory cells with said resistive elements.

[0022] Other objects, features and advantages of the present invention will become apparent upon examination of the following description and the accompanying drawings. It is understood that other advantages may be incorporated. In particular, certain features and advantages of the control device may apply mutatis mutandis to the method of controlling this device, and vice versa. BRIEF DESCRIPTION OF THE FIGURES

[0023] The aims, objects, as well as the characteristics and advantages of the invention will emerge more clearly from the detailed description of embodiments thereof which are illustrated by the following accompanying drawings in which:

[0024] [Fig.l] [Fig.l] schematically illustrates in cross-section a transistor driving device, according to an embodiment of the present invention.

[0025] [Fig.2] [Fig.2] schematically illustrates in top view a transistor driving device, according to an embodiment of the present invention.

[0026] [Fig.3] [Fig.3] schematically illustrates in top view a transistor driving device, according to another embodiment of the present invention.

[0027] [Fig.4] [Fig.4] illustrates an electrical diagram of a memory cell, according to an embodiment of the present invention.

[0028] [Fig.5] [Fig.5] is a graph illustrating different resistance levels of the transistor (when it is on) obtained in the context of MLC programming, according to an embodiment of the present invention.

[0029] The drawings are given as examples and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate the understanding of the invention and are not necessarily on the scale of practical applications. In particular, on the schematic diagrams, the thicknesses of the different layers and portions, and the dimensions of the patterns are not representative of reality. DETAILED DESCRIPTION

[0030] Before commencing a detailed review of embodiments of the invention, are listed below are optional features that may be used in combination or alternatively:

[0031] According to one example, the at least one second box comprises a plurality of second boxes separated from each other by the substrate, each second box being associated with, and disposed under and around, a first box of the plurality of first boxes.

[0032] According to one example, the transistors are separated from each other by isolation trenches of a single type, typically shallow isolation trenches known by the acronym STI (meaning "Shallow Trench Isolation"). This makes it possible to simplify the design of the device, compared to a device using two types of isolation trenches, typically shallow isolation trenches STI and deep isolation trenches known by the acronym DTI (meaning "Deep Trench Isolation").

[0033] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R).

[0034] According to one example, all of the plurality of transistors are MOS transistors.

[0035] According to one example, the second type of conductivity is of type N. The selection transistors are thus preferably NMOS transistors.

[0036] According to one example, all the transistors are N-type MOS transistors, and the second bias voltage V2 is between 0V and 6V.

[0037] According to one example, the first bias voltage V1 is between -6V and +6V.

[0038] According to one example, the second bias voltage V2 is greater than or equal to the first bias voltage VI.

[0039] According to one example, the first bias voltage V1 is such that V2-6 <V1< V2.

[0040] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R), the method further comprising: - Applying a fixed control voltage to at least some of the selection transistors, so as to select certain memory cells associated with said selection transistors, and - Varying the first bias voltage VI of certain first boxes underlying said selected memory cells, according to at least three distinct bias values ​​so as to create at least three levels distinct resistances of the selection transistor for said selected memory cells.

[0041] According to one example, the transistors are selection transistors, the device further comprising a resistive element associated with each selection transistor and forming with said selection transistor a memory cell (1T1R), the method further comprising: - Fix the second bias voltage V2 of at least one second box, - Varying the first bias voltage VI of certain first wells underlying the selection transistors, according to at least three distinct bias values ​​so as to create at least three distinct resistance levels of the selection transistor for the memory cells associated with said first wells. The bias voltage V2 typically takes a fixed value, for example 0V, 3V, 6V, for a time typically corresponding to the duration of an elementary programming operation (for example the coding of a bit). This value can then evolve towards another fixed value, for another elementary programming operation for example.

[0042] Unless incompatibility exists, it is understood that all of the above optional features may be combined to form an embodiment that is not necessarily illustrated or described. Such an embodiment is obviously not excluded from the invention.

[0043] It is specified that, in the context of the present invention, the terms “on”, “overcomes”, “covers”, “underlying”, “facing” and their equivalents do not necessarily mean “in contact with”. Thus, for example, the deposition of a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it, or by being separated from it by at least one other layer or at least one other element.

[0044] A layer may also be composed of several sub-layers of the same material or of different materials.

[0045] A substrate, a stack, a layer, “based” on a material A, is understood to mean a substrate, a stack, a layer comprising this material A only or this material A and possibly other materials, for example alloying elements and / or doping elements. Thus, a silicon-based layer is understood to mean, for example, a Si, n-doped Si, p-doped Si, SiGe layer.

[0046] Several embodiments of the invention implementing successive steps The stages of the piloting process are described below. Unless explicitly stated, the adjective "successive" does not necessarily imply, even if this is generally preferred, that the stages follow one another immediately, as intermediate stages may separate them.

[0047] Furthermore, the term “step” means the carrying out of a part of the method, and can designate a set of sub-steps.

[0048] Furthermore, the term "step" does not necessarily mean that the actions carried out during a step are simultaneous or immediately successive. Certain actions of a first step may in particular be followed by actions linked to a different step, and other actions of the first step may be repeated subsequently. Thus, the term step does not necessarily mean unitary and inseparable actions in time and in the sequence of the phases of the process.

[0049] A preferably orthonormal reference frame, comprising the axes x, y, z is shown in the attached figures. When a single reference frame is shown on the same sheet of figures, this reference frame applies to all the figures in this sheet.

[0050] In the present patent application, the thickness of a layer is taken along a direction normal to the main extension plane of the layer. Thus, a layer typically has a thickness along z. The relative terms “on”, “overcomes”, “under”, “underlying”, “intercalated” refer to positions taken along the z direction.

[0051] The terms "vertical", "vertically" refer to a direction along z. The terms "horizontal", "horizontally", "lateral", "laterally" refer to a direction in the xy plane. Unless explicitly stated, thickness, height and depth are measured along z.

[0052] An element located "perpendicular to" or "in line with" another element means that these two elements are both located on the same line perpendicular to a plane in which a lower or upper face of a substrate mainly extends, that is to say on the same line oriented vertically in the figures.

[0053] In the following embodiments, the control device and the control method are illustrated in particular for the control of memory cells of the 1T1R type, typically comprising a transistor and a resistive element in series. The invention is not limited to memory cells. Any electronic device based on transistors of the same type can be implemented in the control device and / or the control method according to the present invention.

[0054] In the following embodiments, the first well(s) are preferably PWells. The second well(s) are preferably Deep NWells and / or NWells. The substrate is preferably of type P (Psub). The transistors are preferably NMOS. It is understood that the conductivity types can be inverted relative to each other, according to another embodiment of the present invention.

[0055] [Fig. 1] illustrates an embodiment of the transistor driving device.

[0056] The transistors 20 are here typically FDSOI type MOS transistors with rear gate, also called ultra-thin body and buried oxide transistors or UTBB (for “Ultra Thin Body and BOX” in English). This type of MOS transistor is manufactured from an SOI substrate successively comprising along z a silicon substrate 10, an electrically insulating layer 11 called buried, generally an oxide layer (or BOX layer, for “buried oxide layer” in English), and a thin layer 12 of monocrystalline silicon, also called active layer. The particularity of the UTBB FDSOI transistor is that the BOX layer 11 is extremely thin, typically with a thickness of less than 30 nm, which makes it possible to apply a bias to the rear face of the transistor 20. The thickness e^ of the thin layer 12 of monocrystalline silicon is typically less than 10 nm.

[0057] The transistors 20 have a channel 12c formed in the active layer 12, under the gate of the transistors 20. This channel 12c is configured to operate in a so-called “fully depleted” mode, in the blocked state of the transistor. The active layer 12 is typically intentionally undoped.

[0058] The transistors 20 of the device 1 all have the same type of conductivity, preferably an N-type conductivity (the majority charge carriers are electrons).

[0059] The device 1 also comprises at least one first well 21 having a conductivity type opposite to the conductivity type of the transistors 20. In this example, the well 21 is of type P. Such a P-type well can be called “PWell” according to the usual terminology. This first well 21 typically makes it possible to apply a bias VI to the rear face of the transistor(s) 20. This bias VI makes it possible to lower or increase the threshold voltage of the transistors 20, which can then deliver more or less current respectively. It is generally advantageous for the transistor to deliver more current in the on state, and less leakage current (in the off state).

[0060] The device 1 comprises a biasing circuit configured to apply this first biasing voltage VI to the first well 21, via a first contact 31.

[0061] In order to increase the bias voltage range VI, the device 1 comprises a second box 22 surrounding the first box VL. The second box 22 typically extends under the first box 21, and laterally borders the first box 21. The second box 22 is configured to electrically insulate the first box 21 from the substrate 10. The second box 22 has a conductivity type opposite to the conductivity type of the first well 21. In this example, the well 22 is of type N, like the transistors 20. Such an N-type well 22 may comprise a portion extending under the first well 21 called “Deep NWell” according to the usual terminology, and a portion laterally surrounding the first well 21 called “NWell”. The Deep NWell portion of the well 22 typically makes it possible to ensure deep insulation of the first well 21, typically with respect to the substrate 10. The NWell portion of the well 22 typically makes it possible to ensure lateral insulation of the first well 21, typically with respect to another adjacent first well 21. The second well 22 is typically formed by an NWell and a Deep NWell. In the following, the second box 22 is indifferently called “NWell” or “Deep NWell”, without this necessarily limiting it to one or other of the parts of said box.

[0062] A first diode 211 PN is thus formed between the first well 21 and the second well 22. A second diode 212 PN is thus formed between the substrate 10 and the second well 22.

[0063] Advantageously, a second bias voltage V2 can be applied to this second well 22 via a second contact 32 of the bias circuit. This second bias voltage V2 is typically between 0V and 6V, which makes it possible to keep the PN diode 212 in the blocking state. For a silicon-based PN diode 212, the current increases significantly above 6V (or below -6V for a reverse-biased diode), according to a typical Zener diode characteristic. The P-type substrate 10 is typically biased at 0V.

[0064] The bias voltage range V1 for keeping the PN diode 211 in the blocking state is advantageously increased by varying the second bias voltage V2. For diodes 211, 212 of substantially the same nature, the bias voltage range V1 is typically between -6V and +6V. For example, for V2 = 0V, the bias voltage VI may be between -6V and 0V. This corresponds to an RBB bias of the NMOS transistors 20. For V2 = 3V, the bias voltage VI may be between -3V and +3V. For V2 = 6V, the bias voltage V1 may be between 0V and +6V. This corresponds to an FBB polarization of the NMOS 20 transistors. The bias voltage range V1 allowing the NMOS 20 transistors to be biased on the rear face (BB) is thus significantly doubled by the addition of the Deep NWell 22 controlled by voltage V2.

[0065] The control of the second box 22 is preferably carried out so as to maintain the blocking state of the diodes 211, 212. According to one possibility, the bias voltages VI, V2 are applied via the bias circuit such that VI < V2.

[0066] As illustrated in [Fig.l], the device 1 may also comprise isolation trenches 23 on either side of the transistors 20 and the contacts 31, 32. These trenches isolation trenches 23 are preferably shallow isolation trenches called STI (for "Shallow Trench Isolation" in English). Preferably, the device 1 comprises only STI 23 between the transistors 20 and the contacts 31, 32. In particular and advantageously, the device 1 does not require the use of other types of isolation trenches, in particular deep isolation trenches called DTI (for "Deep Trench Isolation" in English), to extend the bias voltage range VI (bias BB). The trench isolation technology is thus simplified, and the associated cost remains low compared to technologies using two depths of STI and / or DTI.

[0067] [Fig.2] illustrates an embodiment in which eight first boxes 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h are isolated from each other by a second well 22. The first wells 21a, 21b, 21c, 21d, 21e, 21f, 21g, 21h are preferably PWells. The second well 22 is preferably a Deep NWell. The substrate 10 is preferably of type P.

[0068] For an RRAM or OxRAM type application, each of the first eight boxes may comprise a plurality of memory cells arranged in the form of lines. Each first box comprises, for example, 8 lines.

[0069] Each first well can be biased separately from the other first wells, via a dedicated biasing circuit. Thus, a first well 21 biased so as to apply a FBB back bias to the selection transistors typically corresponds to a memory cell programming operation (writing or erasing, SET / RESET). The memory cells formed on this first well are said to be “selected”.

[0070] The memory cells formed on a first well 21 biased so as to apply a RBB back bias to the selection transistors, are typically “unselected”, or selected in read only.

[0071] It is thus possible to program the memory cells of the lines formed on the box 21a, in FBB configuration over an extended range of values ​​VI, V2, while maintaining the memory cells of the lines formed on the boxes 21b, 21c, 21d, 21e, 21f, 21g, 21h in RBB configuration over an extended range of values ​​VI, V2.

[0072] This makes it possible, for example, to reduce the threshold voltage of the selection transistors (wordline connection) for writing or erasing, in FBB configuration. The threshold voltage of the selection transistors (wordline connection) for reading can also be reduced, in RBB configuration. The static consumption of the non-selected lines can also be reduced, in RBB configuration.

[0073] The extended value ranges in RBB (-6V to 0V) and in FBB (0V to +6V) advantageously make it possible to read and write several bits of information within a memory cell, as described in more detail below.

[0074] [Fig. 3] illustrates another embodiment in which the first boxes 21, 21a, 21b, 21c, 21d, are distributed in different second boxes 22, 22a, 22b, 22c, 22d. In this example, each first box 21 is associated with a second box 22. Other configurations are conceivable, for example four first boxes 21 distributed within two second boxes 22.

[0075] The second wells 22a, 22b, 22c, 22d are separated and isolated from each other by the substrate 10. The separation distance ds between two adjacent second wells 22a, 22b is of the order of a few microns, for example 3 μm. This makes it possible to polarize the second wells 22 independently. The possibilities of applying different FBB and RBB polarizations are increased. Thus, for example, the first well 21a PWell is polarized at -6V and the second well 22a Deep NWell is polarized at 0V. This makes it possible to generate an RBB polarization limiting or eliminating current leaks. The memory cells associated with the well 21a are not selected. The first well 21b PWell is for example polarized at +6V and the second well 22b Deep NWell is polarized at +6V. This allows the generation of an FBB bias reducing the threshold voltage of the selection transistors, for write or erase operations for example.The bias voltages V2 are thus applied independently of each other via the bias circuit. The versatility of the device 1 is increased. The biases VI, V2 of the first and second wells 21, 22 can vary dynamically depending on the memory accesses for example. The application of the bias voltages VI, V2 is typically controlled by the bias circuit of the device 1. The number of RBB and / or FBB bias configurations of the different memory cells is thus increased. The extended value ranges in RBB (-6V to 0V) and in FBB (0V to +6V) also make it possible to implement easy MLC programming of the memory cells.

[0076] [Fig.4] illustrates an electrical diagram of a memory cell mounted on a first PWell box isolated from the substrate by a second Deep NWell box, according to a principle of the invention.

[0077] Advantageously, the MLC programming of the memory cells can be implemented by controlling the back bias (BB) by the bias voltage VI, the range of values ​​of which is extended by varying V2. In particular, the control of the back bias BB makes it possible to control the threshold voltage of the transistor and therefore the resistance R between the source and the drain of the transistor (1T) which plays the role of a current limiter, in particular in a memory SET operation. If the resistance R of the transistor is reduced, the current passing increases. This makes it possible to reinforce the SET operation.

[0078] As illustrated in [Fig.5], the variation in bias voltage VI (BB) introduces a variation in the resistance R of the transistor and therefore of the resistive element of the RRAM memory. This makes it possible to access 3 or more RRAM resistance levels, each coding for separate bits of information. In the example shown, for 3 VI values ​​in the range -3V to +3V, with V2 set to +3V, 3 resistance levels RI, R2, R3 are obtained. By extending the range of VI values, for example between -6V and +6V, the number of resistance levels allowed increases.

[0079] The use of a voltage-controlled dual PWell / Deep NWell well for FDSOI NMOS transistors advantageously makes it possible to significantly modify the threshold voltages of these transistors. The overall energy efficiency is improved. Such a voltage-controlled dual well also makes it possible to envisage the implementation of MLC for memory cells based on a single type of transistor. The surface area occupied by these memory cells, each storing more than one bit of data, can thus be significantly reduced.

[0080] The invention is not limited to the embodiments previously described.

Claims

1. Claims Method for driving a transistor driving device (1), the device comprising: - A substrate (10) based on a semiconductor material, having a first type of conductivity (P), - An insulating layer (11) based on a dielectric material on said substrate (10), - A layer (12) based on the semiconductor material, called the active layer, located on the insulating layer (11), - A plurality of selection transistors (20) each comprising a channel (12c) formed in the active layer (12) and configured to be completely depleted, said selection transistors (20) having a second type of conductivity (N), the device (1) further comprising a resistive element (IR) associated with each selection transistor and forming with said selection transistor a memory cell (1T1R), - A plurality of first wells (21, 21a, 21b, 21c, 21d, 21e, 2If, 21g, 21h) formed in the substrate (10) and having the first conductivity type (P), each first well (21) being associated with and arranged under a group of transistors of the plurality of transistors (20), - At least one second box (22, 22a, 22b, 22c, 22d) having the second type of conductivity (N), formed in the substrate (10) under and around the first boxes (21), so as to insulate the first boxes (21) from each other and from the substrate (10), - A biasing circuit configured to apply at least a first bias voltage V1 to the first boxes (21), and at least a second bias voltage V2 to the at least one second box (22), said method comprising: - Applying a first bias voltage VI to at least one first box (21) of the plurality of first boxes, - Apply a second bias voltage V2 to the at least one second box (22) surrounding said at least one first well (21), Said applications of the first and second voltages VI, V2 being such that there is no electrical conduction between said at least one first and second well (21, 22), - Applying a fixed control voltage to at least some of the selection transistors, so as to select certain memory cells associated with said selection transistors, and - Varying the first bias voltage VI of certain first wells (21) underlying said selected memory cells, according to at least three distinct bias values ​​so as to create at least three distinct levels of resistance of the selection transistor (RI, R2, R3) for said selected memory cells.

2. Method according to the preceding claim in which all the selection transistors (20) are N-type MOS transistors, and in which the second bias voltage V2 is between 0V and 6V.

3. A method according to any preceding claim wherein the first bias voltage V1 is between -6V and +6V.

4. A method according to any preceding claim wherein the second bias voltage V2 is greater than or equal to the first bias voltage VI.

5. A method according to any preceding claim wherein the first bias voltage V1 is such that V2 - 6 < VI < V2.

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