Contact for electronic component

Abstract

Contact for electronic component This description relates to a method for manufacturing a contact (250) on a semiconducting region (124, 126) of an electronic component (200), said method comprising: - a step of forming a stack of layers adapted to be electrically conductive on the side walls and at the bottom of an orifice (251) passing through a dielectric region (142) of the electronic component, from a first surface (142A) of said dielectric region, the bottom of the orifice opening at the semiconducting region, said formation step comprising the formation of a layer (253) of polysilicon and a layer of a first metal in contact with the polysilicon layer, said first metal being chosen from the rare earth group, and being adapted to form with the polysilicon a metal silicide;then- a thermal annealing step adapted to react the first metal and the polysilicon, leading to the formation of a layer (256) of metal silicide comprising at least a portion extending in the longitudinal direction of the orifice. Figure for the abstract: Fig. 2G;

Description

Title of the invention: Contact for electronic component Technical field

[0001] The present description relates generally to electronic devices, and more particularly to semiconductor-based electronic components. Prior art

[0002] In an electronic device such as an integrated circuit, electronic components are generally connected to a first metal level of an interconnection part (known by the person skilled in the art by the acronym "BEOL", Back End Of Line). In particular, certain electronic components such as transistors, diodes, etc., comprise semiconductor regions electrically connected to the first metal level. Typically, a transistor, for example of the MOS type, comprises such drain, source and / or gate semiconductor regions. For these semiconductor regions, the electrical connection is generally provided by an electrically conductive pad, or contact, in direct contact on the one hand with the semiconductor region and on the other hand with the first metal level.

[0003] The lowest possible resistance of the electrical contact between the semiconductor region and the first metal level is generally sought.

[0004] This may be sought for applications in which one seeks to minimize the resistance of a transistor under voltage, known as "Ron", without this impacting other performance factors of the transistor, for example the off-voltage capacitance, known as "Coff" which one may also seek to minimize. In particular, this may be sought when it becomes difficult to act on the parameters of a transistor, for example on the channel or the gate to minimize both the Ron and the Coff.

[0005] Minimizing Ron and Coff is for example sought for electronic components used in RF (radio frequency) communication applications, for example for RF signal switching technologies (RF switch) and / or radio antenna front-end modules (FEM, Front-End Modules). Summary of the invention

[0006] There is a need for an electrical contact between a semiconductor region of an electronic component and a first metal level of an interconnection part, the resistance of which is as low as possible.

[0007] One embodiment overcomes all or part of the drawbacks of known electronic component contacts.

[0008] One embodiment provides a method of manufacturing a contact on a semiconductor region of an electronic component, said method comprising: - a step of forming a stack of layers adapted to be electrically conductive on the side walls and at the bottom of an orifice passing through a dielectric region of the electronic component in a longitudinal direction, the bottom of the orifice opening out at the level of the semiconductor region, said formation step being carried out from a first surface of said dielectric region and comprising the formation of a layer of polysilicon and a layer of a first metal in contact with the layer of polysilicon, said first metal being chosen from the group of rare earths, and being adapted to form a metal silicide with the polysilicon; then - a thermal annealing step adapted to react the first metal and the polysilicon, leading to the formation of a layer of metal silicide comprising at least one portion extending in the longitudinal direction of the orifice.

[0009] According to one embodiment, the electronic component comprises a silicide interface layer intended to form an interface between said semiconductor region and the contact, the bottom of the orifice opening onto said silicide interface layer.

[0010] According to one embodiment, the annealing step is carried out at a temperature between 500°C and 850°C, for example between 675°C and 850°C, and / or for a duration between 30 seconds and 5 minutes.

[0011] According to one embodiment, the polysilicon layer is formed on the side walls and at the bottom of the orifice, and the layer of the first metal is formed on the polysilicon layer.

[0012] According to a particular embodiment, the forming step further comprises the formation of a diffusion barrier layer, after the formation of the layer of the first metal, and on said layer of the first metal.

[0013] According to a particular embodiment, the forming step further comprises a step of filling the orifice leading to the formation of a filling layer of a second metal, said filling step being after the formation of the layer of the first metal, for example after the formation of the diffusion barrier layer.

[0014] According to one embodiment, the layer of the first metal is formed on the side walls and at the bottom of the orifice, before the layer of polysilicon.

[0015] According to a particular embodiment, the forming step further comprises the formation of a diffusion barrier layer before the layer of the first metal, and in contact with said layer of the first metal.

[0016] According to a particular embodiment, the training step further comprises the forming a bonding layer on the side walls and at the bottom of the orifice, before the layer of the first metal, and in contact with said layer of the first metal, or before the diffusion barrier layer, and in contact with said barrier layer.

[0017] According to a particular embodiment, the forming step comprises a step of etching, at least at the bottom of the orifice, a portion of the diffusion barrier layer and / or a portion of the bonding layer, the etching step being before the formation of the layer of the first metal.

[0018] According to a particular embodiment, the formation of the polysilicon layer corresponds to a filling of the orifice.

[0019] According to one embodiment, the method further comprises a step of planarizing the layers of the stack, adapted to make the contact flush with the first surface of the dielectric region, the planarization step comprising for example chemical-mechanical polishing.

[0020] One embodiment provides an electronic component comprising at least one contact on at least one semiconductor region of an electronic component, the contact being arranged in an orifice passing through a dielectric region of the electronic component in a longitudinal direction from a first surface of said dielectric region, the bottom of the orifice opening out at right angles to the semiconductor region, said contact comprising a layer of metal silicide comprising at least one portion extending in the longitudinal direction of the orifice.

[0021] According to one embodiment, the electronic component comprises a silicide interface layer between the semiconductor region and the contact, the bottom of the orifice opening onto said silicide interface layer.

[0022] According to one embodiment, the metal silicide layer has a U shape, comprising first and second portions extending in the longitudinal direction of the orifice, connected by a third portion at the bottom of the orifice.

[0023] According to one embodiment, a portion of the metal silicide layer, for example the third portion, is in direct contact with the semiconductor region or the silicide interface layer.

[0024] According to one embodiment, the electronic component comprises, for example, a MOS type transistor arranged in and on a substrate, the transistor comprising a gate semiconductor region covering a channel region located between a doped drain semiconductor region and a doped source semiconductor region, at least one contact being arranged on the drain semiconductor region, the source semiconductor region and / or the gate semiconductor region, a silicide interface layer being for example interposed between said semiconductor region and the contact.

[0025] According to one embodiment: - the first metal is chosen from: titanium, cobalt, platinum, nickel, tungsten; - the second metal is tungsten or copper; - the metal silicide is a titanium silicide, a cobalt silicide, or a nickel silicide; - the third metal is titanium, cobalt or nickel; and / or - the diffusion barrier layer comprises titanium nitride and / or a tantalum / tantalum nitride bilayer.

[0026] One embodiment provides an electronic device comprising at least one electronic component according to one embodiment.

[0027] According to one embodiment, said device is a radiofrequency signal switch. Brief description of the drawings

[0028] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0029] [Fig.1A] is a sectional view of an example of an electronic component;

[0030] [Fig.lB] schematically represents a sectional detail of a contact of an electronic component similar to the component of [Fig.lA];

[0031] [Fig.2A], [Fig.2B], [Fig.2C], [Fig.2D], [Fig.2E], and [Fig.2F] are sectional views showing steps of a method of manufacturing a contact according to one embodiment;

[0032] [Fig.2G] represents an electronic component in section comprising two contacts obtained by the manufacturing method of FIGS. 2A to 2F;

[0033] [Fig.3A], [Fig.3B], [Fig.3C], [Fig.3D], [Fig.3E] and [Fig.3F] are sectional views showing steps of a method of manufacturing a contact according to another embodiment;

[0034] [Fig.4A], [Fig.4B], [Fig.4C] and [Fig.4D] are sectional views showing steps of a method of manufacturing a contact according to another embodiment; and

[0035] [Fig.4E] represents an electronic component in section comprising two contacts obtained by the manufacturing method of FIGS. 4A to 4D. Description of the embodiments

[0036] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0037] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the manufacturing steps and the details of the elements of an electronic component (other than the contacts concerned by the embodiments), such as the drain, the source, the channel, and the gate for a MOS transistor, are not detailed, being achievable with the usual methods of manufacturing electronic components.

[0038] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0039] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to an electronic component in a normal position of use.

[0040] In the following description, when referring to the longitudinal direction of the orifice, it is to be understood the direction in which the orifice crosses the dielectric region, or, in other words, the direction corresponding to the depth of the orifice.

[0041] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0042] [Fig.lA] is a section of an example of electronic component 100. [Fig.lB] schematically represents and in section a detail of a contact of an electronic component similar to the component of [Fig.lB].

[0043] The electronic component shown comprises, or is, a MOS type transistor. The transistor is located in and on a substrate 120. The substrate is a semiconductor, preferably made of silicon. An insulating layer 110 is shown under the substrate, for example a layer known to those skilled in the art by the acronym "BOX" (buried oxide). For example, the substrate is a silicon film on the BOX, itself on another silicon substrate, according to SOI (Silicon On Insulator) technology.

[0044] The transistor comprises a gate region 132 covering a channel forming region 122 located between two doped semiconductor regions, respectively the drain 124 and the source 126. These semiconductor regions are connected to a first metal level 162 of an interconnection part 160 with electrically conductive pads, or contacts 150. In other words, a contact is connected, preferably connected, on the one hand with the semiconductor region and on the other hand with the first metal level. Although not shown, contact between the first metal level and the gate region can also be provided.

[0045] The gate region 132 is generally made of polysilicon (polycrystalline silicon). It may be flanked by an insulating side region or spacer 134. In addition, the gate region is generally isolated from the channel and / or the spacer by a gate oxide layer 136.

[0046] The transistor is preferably delimited by isolation trenches (not shown), typically of the surface isolation trench type, known to those skilled in the art by the English acronym "STI" (Shallow Trench Isolation). Such trenches may result from etching and filling, with an electrical insulator, the etched parts. The insulator is for example an oxide such as a silicon oxide.

[0047] Provision may be made to form a layer of metal silicide 140 (referred to as "silicide") at the interface between the semiconductor region 122, 124 and the contact 150. Such a layer of silicide makes it possible to significantly reduce the value of the electrical access resistance of the contact, i.e. the resistance between the semiconductor region and the contact. For example, as illustrated in [Fig.lA], the drain, source, or even gate regions may comprise parts of metal silicide opposite the contacts to make it possible to reduce the access resistance.

[0048] Furthermore, as illustrated in [Fig.lA], an etch stop layer 138, typically made of silicon nitride (SiN), for the future etching of the contact, can be arranged on the drain, source and gate regions, and in particular on the silicide layers. The etch stop layer is topped by a region made of a dielectric material 142, for example a dielectric material known to the person skilled in the art by the acronym "PMD" (Pre Metal Dielectric). According to one example, the PMD is more or less doped silicon dioxide (SiO2).

[0049] An example of a method for manufacturing a contact, comprising the prior formation of a metal silicide interface layer, is as follows, and is described using the numerical references of FIGS. 1A and 1B.

[0050] After annealing the semiconductor regions concerned, for example a source region and / or a drain region, carried out for example at 1030°C for a few seconds, the regions which must not be silicidated are protected with a specific mask, generally formed of a bilayer of silicon oxide and silicon nitride.

[0051] Then, a full-plate deposition of a cobalt / titanium nitride (Co / TiN) bilayer is carried out. A first rapid heat treatment (rapid annealing) is then carried out, typically at 530°C for a few seconds, so as to form cobalt mono-silicide (CoSi). Such rapid heat treatment is known to the person skilled in the art profession under the Anglo-Saxon acronym "RTP" (Rapid Thermal Processing).

[0052] The Co / TiN bilayer is then removed, and a densification annealing is carried out, typically at 830°C for a few seconds, which leads to the transformation of the cobalt mono silicide into cobalt disilicide (CoSi2) forming the silicide layer 140 on each semiconductor region, then a deposition of a stop layer 138 is carried out for the future etching of the contact, for example silicon nitride (SiN).

[0053] Then, a dielectric region 142 is formed using a dielectric material, for example a PMD, on the barrier layer 138.

[0054] A through-hole 151 is then etched in the dielectric region 142 so as to form the location of the future electrical contact. Preferably, the hole passes through the barrier layer 138 to the silicide layer 140 (CoSi2).

[0055] A layer of titanium (Ti) 152 is deposited on the side walls and at the bottom of the orifice (on the silicide layer), then a layer of titanium nitride (TiN) 154 forming a diffusion barrier layer. Then, the orifice is filled with a filling metal 156, for example tungsten (W).

[0056] A first metal level 162 of the interconnection portion 160 may then be formed on each contact, for example copper (Cu) or aluminum (Al) pads, said metal pads being insulated by a dielectric material 164, for example a silicon oxide containing carbon (SiOC), or a silicon phosphide known by the English abbreviation "PSG" (Phospho-Silicon Glass). An etch stop layer 166, for example a carbon and silicon nitride (SiCN), may be provided before forming the first metal level, in anticipation of the etching (of the metal or the dielectric depending on the method implemented) to form said first metal level in the dielectric material of the interconnection portion.

[0057] Concerning the contact 150 formed by this method, and in particular the interface between the silicided semiconductor region and the contact, it is noted that the layers 152, 154 respectively made of Ti and TiN are intercalated between the silicide layer and the tungsten, which increases the access resistance of the contact. Furthermore, by adding the resistance of the tungsten, the overall resistance of the contact between the silicided semiconductor region and the first metal level remains significant due to the stacking of resistances of the layers 152, 154, 156 respectively made of Ti, TiN and W.

[0058] The inventors propose a contact on a semiconductor region and a method for manufacturing such a contact making it possible to meet the improvement needs described above, and to overcome all or part of the drawbacks of the contacts described above. In particular, the inventors propose a contact and a method for manufacturing such a contact making it possible to reduce the access resistance, as well as the overall resistance of said contact.

[0059] Embodiments of contacts will be described below. The embodiments described are non-limiting and various variants will become apparent to those skilled in the art from the indications of the present description.

[0060] In the described embodiments, the contact is an electrical contact of an electronic component, for example a MOS type transistor such as that described in relation to Figures 1A and 1B. The contact is preferably formed on a silicided semiconductor region, that is to say surmounted by a silicide interface layer, for example a source region and / or a drain region, or even a gate region.

[0061] Furthermore, the starting structure of the described embodiments is a structure resulting from a method of manufacturing a through-orifice for the location of the future contact on the semiconductor region, with prior formation of a silicide interface layer on said semiconductor region. For example, the starting structure may be a structure resulting from a method similar to that described in relation to FIGS. 1A and 1B up to the step (inclusive) of etching the orifice in the dielectric region 142. The orifice 251 passes through the stop layer 138 to open onto the silicide interface layer 140.

[0062] In the embodiments shown, the longitudinal direction of the orifice corresponds substantially to the vertical.

[0063] Figures 2A to 2F are sectional views showing a method of manufacturing a contact 250 according to one embodiment.

[0064] [Fig.2A] represents the structure obtained after the deposition of a layer 253 of polysilicon on the initial structure, and in particular on the side walls 25 IC and at the bottom 251B of the orifice 251. This deposition can, for example, be carried out using a chemical vapor deposition technique, known by the English acronym "CVD" (Chemical Vapor Deposition), or by epitaxy. For example, the layer 253 has a uniform thickness of approximately 50 nanometers (nm).

[0065] [Fig.2B] represents the structure obtained after deposition of a layer 254 of titanium (Ti) (first metal) on layer 253 then of a layer 255 of titanium nitride (TiN) on layer 254. Thus, layer 254 of titanium is in contact with layer 253 of polysilicon. These deposits can, for example, be carried out using a CVD technique, or a physical vapor deposition technique, known by the English acronym "PVD" (Physical Vapor Deposition).

[0066] The TiN layer 255 forms a barrier layer, suitable for limiting, or even blocking, the diffusion of the filling metal (described below) into the Ti.

[0067] For example, the Ti layer 254 has a uniform thickness of about 35 nm, and the TiN layer 255 has a uniform thickness of about 15 nm.

[0068] Layers 253, 254, 255 generally include portions which extend beyond the exterior of the orifice 251 on the upper surface 142A (first surface) of the dielectric region 142.

[0069] [Fig.2C] represents the structure obtained at the end of a step of filling the orifice coated with layers 253, 254, 255 with a filling metal (second metal), for example tungsten (W). Alternatively to tungsten, the filling metal (second metal) can be copper.

[0070] This filling step can, for example, be carried out using a CVD technique or an atomic layer deposition technique (ALD, Atomic Layer Deposition).

[0071] This filling step leads to the formation of a layer 257 comprising a substantially vertical portion of filling metal in the orifice 251, in contact with the TiN layer 255. Furthermore, a substantially horizontal portion of the filling metal layer may cover the portions of the layers 253, 254, 255 which protrude outside the orifice 251.

[0072] [Fig.2D] represents the structure obtained at the end of a rapid heat treatment step (rapid annealing), to react the polysilicon of layer 253 with the titanium of layer 254, leading to the formation of a continuous layer 256 of titanium silicide (TiSi2) which extends between the unconsumed residue of layer 253 of polysilicon and layer 255 of TiN.

[0073] The treatment can, for example, be carried out at 675°C for 30 seconds and under nitrogen (N2).

[0074] The order of the filling and heat treatment steps may be reversed. In other words, the filling step may be provided after the heat treatment step.

[0075] [Fig.2E] represents the structure obtained at the end of a step of removing the portions of the layers 253, 254, 255, of the layer 257 of filling metal and of the layer 256 of titanium silicide, which extend above the orifice 251 and above the upper surface 142A of the dielectric region 142, so as to form a metal contact 250 flush with the upper surface 142A of the dielectric region 142. This removal step (planarization) can be carried out in a conventional manner by chemical-mechanical polishing, known by the English acronym "CMP" (Chemical Mechanical Polishing).

[0076] After this planarization step, the layer 256 of titanium silicide has a U shape, that is to say comprises first and second vertical portions 256A, 256B connected by a third horizontal portion 256C.

[0077] [Fig.2F] represents the structure obtained at the end of a step of forming a first level of metal 162 of the interconnection part 160, formed on the contact 250, a step which may be similar to that described in relation to FIGS. 1A and 1B.

[0078] Although the method is described for a single semiconductor region, the method can be implemented to make, preferably simultaneously, contacts on several semiconductor regions of an electronic component.

[0079] [Fig.2G] represents an electronic component 200 comprising two contacts 250 obtained by the manufacturing method of FIGS. 2A to 2F.

[0080] The electronic component 200 of [Fig.2G] differs from the electronic component of [Fig.1A] mainly by its contacts 250. Indeed, each of the contacts 250 of the electronic component 200 has a continuous layer of silicide 256 (TiSi2 in the embodiment shown) in the shape of a U, flush with the upper mouth 251A of the orifice 251 and extending practically to the bottom 251B of said orifice, to within the thickness of the layer 253 of polysilicon. The resistance of titanium silicide being approximately at least two times lower than that of tungsten, this continuous layer of silicide makes it possible to significantly reduce the access resistance, and the overall resistance, of the contact.

[0081] By adjusting the initial thickness of the polysilicon layer, in particular the polysilicon thickness at the bottom of the orifice, so that a major portion, or even all, of the polysilicon thickness at the bottom of the orifice is consumed at the end of the processing step to form the silicide, the silicide layer 256 can come closer to, or even in contact with, the silicide interface layer 140 on the semiconductor region 124, 126, which can further reduce the access resistance and the overall contact resistance.

[0082] The other elements of the electronic component 200 may be similar to those described in relation to FIGS. 1A and 1B.

[0083] Figures 3A to 3F are sectional views showing a method of manufacturing a contact 350 according to another embodiment.

[0084] [Fig.3A] represents the structure obtained after the deposition of a first layer 352 of Ti (third metal) on the initial structure, and in particular on the side walls 351C and at the bottom 351B of the orifice 351. This layer forms a bonding layer, allowing the bonding of the stack of layers described later on the dielectric region 142 in the orifice.

[0085] [Fig.3B] represents the structure obtained after the deposition of a layer 355 of TiN on the Ti bonding layer 352. This layer 355 of TiN forms a barrier layer suitable for limiting, or even blocking, the surface oxidation of the titanium, and thus preventing the formation of titanium oxide which could block the reaction between the titanium and the polysilicon described below.

[0086] [Fig.3C] represents the structure obtained after the deposition of a second layer 354 of Ti (layer of the first metal) on the barrier layer 355.

[0087] The deposits of these three layers can, for example, be carried out using a CVD technique or a PVD technique.

[0088] For example, the bonding layer 352 has a uniform thickness of approximately 15 nm, the barrier layer 355 has a uniform thickness of approximately 15 nm, and the first metal layer 354 has a uniform thickness of approximately 35 nm.

[0089] The layers 352, 355, 354 generally comprise portions which extend outside the orifice 351 onto the upper surface 142A (first surface) of the dielectric region 142.

[0090] [Fig.3D] represents the structure obtained at the end of a step of filling (filling) with polysilicon of the orifice coated with layers 352, 355, 354. The filling with polysilicon can be carried out using, for example, a CVD technique or epitaxy.

[0091] This filling step leads to the formation of a layer 353 of polysilicon having a substantially vertical portion in the orifice 351, in contact with the second layer 354 of Ti (layer of the first metal). Furthermore, a substantially horizontal portion of the layer 353 of polysilicon may cover the portions of the layers 352, 355, 354 which protrude outside the orifice 351.

[0092] [Fig.3E] represents the structure obtained at the end of a rapid heat treatment step (rapid annealing) allowing the polysilicon of layer 353 to react with the titanium of layer 354, leading to the formation of a continuous layer 356 of titanium silicide (TiSi2) which extends between the unconsumed residue of layer 353 of polysilicon and the barrier layer 355 of TiN.

[0093] The treatment can for example be carried out at 675°C for 30 seconds and under N2.

[0094] [Fig.3F] represents the structure obtained at the end of a step of removing the portions of layers 352, 355, 354, of polysilicon layer 353 and of titanium silicide layer 356 which extend above orifice 351 and above the upper surface 142A of dielectric region 142, so as to form a metal contact 350 flush with the upper surface 142A of dielectric region 142. This removal step (planarization) can be carried out conventionally by chemical mechanical polishing (CMP).

[0095] After this planarization step, the layer 356 of titanium silicide has a U shape, that is to say comprises first and second vertical portions 356A, 356B connected by a third horizontal portion 356C.

[0096] Similar to what is described in connection with [Fig.2F], a first metal level of the interconnection portion may be formed on the contact 350.

[0097] The embodiment of Figures 3A-3F can further reduce the access resistance compared to that of Figures 2A-2F.

[0098] Figures 4A to 4D are sectional views showing a manufacturing method of a contact 450 according to another embodiment.

[0099] We start with a structure similar to the structure of [Fig.3B], with a bonding layer 452 of Ti (third metal) and a barrier layer 455 of TiN, then we etch portions of layers 452, 455 located at the bottom 45IB of the orifice 451 and on the flat surfaces on either side of said orifice, for example by plasma etching so as to access the silicide interface layer 140. According to one example, the etching is anisotropic. [Fig.4A] represents the structure obtained at the end of this etching step.

[0100] [Fig.4B] represents the structure obtained after the deposition of a second layer 454 of Ti (layer of the first metal), similarly to the layer described in relation to [Fig.3C], except that, due to the etching, this second layer 454 of Ti comes to the bottom 451B of the orifice 451, in contact with the silicide interface layer 140 on the semiconductor region 124, and on the upper surface 142A of the dielectric region 142.

[0101] [Fig.4C] represents the structure obtained at the end of a step of filling the orifice 451 with polysilicon, leading to the formation of a layer 453 of polysilicon comprising a substantially vertical portion in the orifice 451 in contact with the second layer 454 of Ti. The filling is similar to that described in relation to [Fig.3D].

[0102] [Fig.4D] represents the structure obtained at the end of a rapid heat treatment step (rapid annealing) allowing the polysilicon of layer 453 to react with the titanium of layer 454, leading to the formation of a continuous layer 456 of titanium silicide (TiSi2) which extends substantially in a U shape, with first and second vertical portions 456A, 456B connected by a third horizontal portion 456C. This third horizontal portion 456C is in direct contact with the silicide interface layer 140 on the semiconductor region 124, which makes it possible to further reduce the access resistance of the contact.

[0103] The heat treatment may be similar to that described in relation to [Fig.3E].

[0104] Then, similarly to what is described in relation to [Fig.3F], a step of removing the portions of the layer 454, the polysilicon layer 453 and the titanium silicide layer 456 which extend above the orifice 451 and / or above the upper surface 142A of the dielectric region 142 is carried out, so as to form a metal contact 450 flush with the upper surface 142A of the dielectric region 142.

[0105] The embodiment of Figures 4A-4D can make it possible to further reduce the access resistance compared to that of Figures 3A-3F.

[0106] [Fig.4E] represents an electronic component 400 comprising two contacts 450 obtained by the manufacturing method of FIGS. 4A to 4D.

[0107] Each of the contacts 450 has a continuous layer 456 of silicide (TiSi2 in the embodiment shown) in the shape of a U, flush with the upper mouth 451A of the orifice 451 and extending to the bottom 451B of said orifice, in contact with the silicide interface layer 140 on the semiconductor region 124, 126. This makes it possible to achieve electrical continuity between the silicides, and thus to further reduce the access resistance of the contact, and the overall resistance of the contact up to the first metal level.

[0108] Figures 2A to 2F, 3A to 3F, 4A to 4D show a drain region 124, but this could be a source region and / or a gate region.

[0109] For the embodiments described, and more generally for a contact and a method of manufacturing a contact according to an embodiment, the first metal may, alternatively to titanium, be another rare earth element, for example cobalt (Co), or nickel (Ni) or platinum (Pt). The diffusion barrier layer may, alternatively to Ti / TiN, be a tantalum / tantalum nitride (Ta / TaN) bilayer, or any other layer or multilayer suitable for forming a diffusion barrier. The third metal, for the bonding layer may, alternatively to Ti, be tantalum (Ta) or Ni.

[0110] Depending on the first metal chosen, the silicide formed by the reaction with the polysilicon can be a titanium silicide, a cobalt silicide, or a nickel silicide.

[0111] In the embodiments described, the electronic component considered is a MOS transistor, but this is not limiting, the embodiments described being able to apply to another type of transistor or more broadly to any other electronic component comprising a semiconductor region intended to be electrically connected via a contact.

[0112] It is apparent from the description that the embodiments make it possible to reduce the overall resistance of the contact between the silicided semiconductor region on which it is formed and the first metal level.

[0113] Thus, for example, the embodiments make it possible to minimize the Ron of a transistor, without this impacting other performance factors of the transistor, for example without this impacting the Coff. Furthermore, this effect can be combined with other improvements to minimize the Ron and / or the Coff, for example with improvements made to the structure of the transistor itself.

[0114] The embodiments may find applications for electronic components used in RF (radio frequency) communication applications, for example for RF signal switching technologies (RF switch) and / or radio antenna front-end modules (FEM). In particular for RF switches, it is advantageous to reduce the access resistance of the contacts.

[0115] Various embodiments and variations have been described. The person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art.

[0116] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. Method for manufacturing a contact (350; 450) on a semiconductor region (124, 126) of an electronic component (300; 400), said method comprising: - a step of forming a stack of layers adapted to be electrically conductive on the side walls (35 IC; 45 IC) and at the bottom (351B; 451B) of an orifice (351; 451) passing through a dielectric region (142) of the electronic component in a longitudinal direction, the bottom of the orifice opening out at the level of the semiconductor region (124, 126), said forming step being carried out from a first surface (142A) of said dielectric region and comprising the formation of a layer (353; 453) of polysilicon and a layer (354; 454) of a first metal in contact with the polysilicon layer, said first metal being chosen from titanium, cobalt, platinum, nickel, tungsten, and being adapted to form a metal silicide with the polysilicon;then - a thermal annealing step adapted to react the first metal and the polysilicon, leading to the formation of a layer (356; 456) of metal silicide comprising at least one portion (356A, 356B; 456A, 456B) extending in the longitudinal direction of the orifice; wherein the layer (354; 454) of the first metal is formed on the side walls (35IC; 45IC) and at the bottom (35IB; 45IB) of the orifice (351; 451), before the layer (353; 453) of polysilicon.;

2. Method according to claim 1, in which the electronic component comprises a silicide interface layer (140) intended to form an interface between said semiconductor region and the contact (350; 450), the bottom (35IB; 45IB) of the orifice (351; 451) opening onto said silicide interface layer.

3. A method according to claim 1 or 2, wherein the annealing step is carried out at a temperature between 500°C and 850°C, for example between 675°C and 850°C, and / or for a time between 30 seconds and 5 minutes.

4. A method according to any one of claims 1 to 3, wherein the forming step further comprises forming a diffusion barrier layer (355; 455) before the layer (354; 454) of the first metal, and in contact with said layer of the first metal.

5. A method according to claim 3 or 4, wherein the forming step further comprises forming a bonding layer (352; 452) on the side walls (35IC; 45IC) and at the bottom (35IB; 45IB) of the orifice (351; 451), before the layer (354; 454) of the first metal, and in contact with said layer of the first metal, or before the diffusion barrier layer (355; 455), and in contact with said barrier layer.

6. Method according to claim 4 or 5, in which the forming step comprises a step of etching, at least at the bottom (45IB) of the orifice (451), a portion of the diffusion barrier layer (455) and / or a portion of the bonding layer (452), the etching step being before the formation of the layer (454) of the first metal.

7. Method according to any one of claims 1 to 6, in which the formation of the layer (353; 453) of polysilicon corresponds to a filling of the orifice (351; 451).

8. Method according to any one of claims 1 to 7, further comprising a step of planarizing the layers of the stack, adapted to make the contact (350; 450) flush with the first surface (142A) of the dielectric region (142), the planarization step comprising for example chemical-mechanical polishing.

9. Electronic component (300; 400) comprising at least one contact (350; 450) on at least one semiconductor region (124, 126) of an electronic component (300; 400), the contact being arranged in an orifice (351; 451) passing through a dielectric region (142) of the electronic component in a longitudinal direction from a first surface (142A) of said dielectric region, the bottom (351B; 451B) of the orifice opening out at right angles to the semiconductor region (124, 126), said contact comprising a layer (356; 456) of metal silicide comprising at least one portion (356A, 356B; 456A, 456B) extending in the longitudinal direction of the orifice, said contact further comprising a layer for filling the orifice, said filling layer being made of polysilicon and covering the metal silicide layer.

10. Electronic component (200; 300; 400) according to claim 9, comprising a silicide interface layer (140) between the semiconductor region (124, 126) and the contact (350; 450), the bottom (351B; 45IB) of the orifice (351; 451) opening onto said silicide interface layer.

11. An electronic component (400) according to claim 10, wherein a portion (456C) of the metal silicide layer (456) is in direct contact with the silicide interface layer (140).

12. An electronic component (300; 400) according to any one of claims 9 to 11, wherein the metal silicide layer (356; 456) has a U shape, comprising first (356A; 456A) and second (356B; 456B) portions extending in the longitudinal direction of the orifice, connected by a third portion (356C; 456C) at the bottom (35IB; 45IB) of the orifice.

13. An electronic component (300; 400) according to any one of claims 9 to 12, said electronic component comprising, for example being, a MOS type transistor disposed in and on a substrate (120), the transistor comprising a gate semiconductor region (132) covering a channel region (122) located between a drain doped semiconductor region (124) and a source doped semiconductor region (126), at least one contact (350; 450) being disposed on the drain semiconductor region, the source semiconductor region and / or the gate semiconductor region, a silicide interface layer (140) being for example interposed between said semiconductor region and the contact.

14. A method according to any one of claims 1 to 8, wherein the metal silicide is a titanium silicide, a cobalt silicide, or a nickel silicide.

15. Electronic device comprising at least one electronic component (200; 300; 400) according to any one of claims 9 to 13.

16. A device according to claim 15, said device being a radio frequency signal switch.

Images