Electrical connection and its manufacturing process
The described manufacturing process for electrical connections in electronic circuits addresses insulation and alignment challenges by using a silicon-conductive core and insulating sheath, ensuring reliable electrical isolation and reducing alignment constraints, thus enhancing manufacturing efficiency and reliability.
Patent Information
- Application Number
- FR2022004130
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-05-02
- Publication Date
- 2025-04-18
- Estimated Expiration
- 2042-05-02
AI Technical Summary
Existing electrical connections in electronic circuits, particularly those involving a silicon substrate with a back-end-of-line interconnection structure, face challenges in ensuring electrical insulation between conductive electrodes and the substrate while maintaining precise alignment during manufacturing processes.
A manufacturing process that includes forming a via with a silicon-conductive core and an insulating silicon oxide sheath, selectively exposing the core through chemo-mechanical polishing, and forming a conductive electrode in contact with the core, while using a self-aligned method to ensure electrical isolation and reduce alignment constraints.
The process achieves electrical insulation between the conductive electrode and the substrate, reducing alignment issues and ensuring reliable electrical connections without substrate contact, thereby improving manufacturing efficiency and reliability.
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Abstract
Description
Title of the invention: Electrical connection and method of manufacturing it Technical field
[0001] The present description relates generally to electronic circuits, and, more particularly, to electrical connections in electronic circuits. The present application also relates to a method of manufacturing an electronic circuit, and, more particularly, to an electrical connection in such a circuit. Prior art
[0002] Electronic circuits or devices are known comprising a silicon substrate having a first face, called the front face, coated with an interconnection structure commonly called a back end of line (BEOL) interconnection structure, and a second face, called the rear face, opposite and parallel to the first face.
[0003] When a conductive electrode is provided on the backside of the substrate, an electrical connection electrically connects the electrode to the interconnection structure covering the frontside.
[0004] However, these known electrical connections and their manufacturing methods have defects. Summary of the invention
[0005] There is a need to overcome all or part of the drawbacks of known electronic devices comprising an electrical connection as described above and known manufacturing methods for these electronic devices.
[0006] For example, there is a need to overcome all or part of the disadvantages of an electrical connection as described above that these known electronic devices comprise, and known methods of manufacturing such an electrical connection.
[0007] One embodiment overcomes all or part of the drawbacks of known electronic devices comprising an electrical connection as described above and known manufacturing methods for these electronic devices.
[0008] For example, one embodiment overcomes all or part of the drawbacks of an electrical connection as described above that these known electronic devices comprise, and known methods of manufacturing such an electrical connection.
[0009] One embodiment provides a manufacturing method comprising the following steps: providing a silicon substrate having a front face coated with an interconnect structure, a rear face opposite the front face, at least one via penetrating vertically into the substrate from the front face over a portion of the thickness of the substrate, said at least one via comprising a conductive silicon core and an insulating silicon oxide sheath which may comprise silicon nitride, the sheath covering the core and electrically insulating it from the substrate; etching, from the rear face, the substrate selectively with respect to the cladding so that a portion of said at least one via protrudes from the rear face; depositing an insulating layer of silicon oxide which may comprise silicon nitride on the rear face side over a thickness greater than a height of the portion of said at least one protruding via; performing chemical-mechanical polishing of the insulating layer until the conductive core of said at least one via is exposed, leaving in place a portion of the thickness of the insulating layer on the rear face; and forming a conductive electrode on the rear face side and in contact with the core of said at least one via.
[0010] According to one embodiment, the step of forming the electrode comprises the deposition of a conductive layer on the insulating layer and in contact with the core of said at least one via, and a step of removing a portion of the conductive layer while leaving said electrode in place.
[0011] According to one embodiment, the insulating layer is deposited on and in contact with the rear face of the substrate and the portion of said at least one protruding via.
[0012] According to one embodiment, the method further comprises, between the polishing step and the electrode formation step, a step of etching a portion of the core of said at least one via, the etching being carried out on the rear face side and being selective with respect to the cladding and the insulating layer.
[0013] According to one embodiment, the method further comprises, after the step of forming the electrode, a step of forming a quantum film resting on the insulating layer and the electrode.
[0014] According to one embodiment, the method further comprises: a step of providing an additional silicon substrate having a front face coated with an additional interconnection structure and a rear face opposite the front face of the additional substrate and intended to receive light; and a step of assembling the interconnection structure onto the additional interconnection structure.
[0015] According to one embodiment, the quantum film is configured to convert infrared light into electron-hole pairs and the electrode is made of a material transparent to infrared light, for example zinc oxide and / or indium-tin oxide.
[0016] According to one embodiment, the sheath of said at least one via is in contact with the core of said at least one via.
[0017] One embodiment provides a device comprising: a silicon semiconductor substrate comprising a front face and a back face opposite the front face; an interconnection structure covering the front face; an insulating layer of silicon oxide which may comprise silicon nitride, the insulating layer resting on the back side; at least one via comprising a conductive silicon core laterally covered with an insulating silicon oxide sheath which may comprise silicon nitride, said at least one via passing through the substrate from its front face, at least the sheath of said at least via passing through the insulating layer and being flush with a first face of the insulating layer opposite a second face of the insulating layer facing the substrate; and a conductive electrode resting on and in contact with the conductive core of said at least one via, on the side of the rear face of the substrate.
[0018] According to one embodiment, the device further comprises a quantum film resting on the insulating layer and the electrode.
[0019] According to one embodiment, the device further comprises an additional silicon substrate and an additional interconnection structure resting on a front face of the additional substrate, the interconnection structure being assembled on the additional interconnection structure and the additional substrate comprising a rear face opposite its front face and intended to receive light.
[0020] According to one embodiment, the quantum film is configured to convert infrared light into electron-hole pairs and the electrode is made of a material transparent to infrared light, for example zinc oxide and / or indium-tin oxide.
[0021] According to one embodiment, the sheath of said at least one via is in contact with the core of said at least one via. Brief description of the drawings
[0022] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:
[0023] [Fig.l] is a sectional view illustrating an example of an electronic device comprising an electrical connection as previously described;
[0024] [Fig.2] illustrates, by three sectional views A, B and C, steps of an example of a method of manufacturing an electrical connection of the device of [Fig.l];
[0025] [Fig.3] illustrates, by five sectional views A, B, C, D and E, stages of a method of carrying out a method of manufacturing an electrical connection of the device of [Fig.l];
[0026] [Fig.4] represents, by a sectional view, a step of a method of manufacturing the device of [Fig.1] according to one embodiment; and
[0027] [Fig.5] represents, by a sectional view, another step of a method of manufacturing the device of [Fig.l] according to one embodiment. Description of the embodiments
[0028] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.
[0029] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. In particular, the various known circuits comprising an electrical connection electrically connecting a conductive electrode arranged on the side of the rear face of the silicon substrate of the circuit and an end-of-line interconnection structure resting on the front face of the substrate have not been detailed, the described embodiments and variants being compatible with these known circuits.
[0030] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.
[0031] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures or to a ... in a normal position of use.
[0032] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.
[0033] [Fig.l] is a sectional view illustrating an example of an electronic device 1 comprising an electrical connection as described previously.
[0034] The device 1 comprises a first IR chip.
[0035] The IR chip comprises a silicon substrate SUB2 having a front face 100 and a rear face 102 opposite the front face 100.
[0036] The front face 100 is coated with an end-of-line interconnection structure BE0L2. Although this is not detailed in [Fig.l], the interconnection structure BE0L2 comprises portions of electrically conductive layers embedded in electrically insulating layers, and vias connecting the portions of electrically conductive layers to each other and / or to components, for example transistors (not shown), formed in and on the substrate SUB2 on the side of its face 100 and / or to electrical connection pads (not shown) formed on the side of a first face of the structure BEOL2 opposite a second face of the structure BEOL2 arranged opposite and on the side of the face 100 of the substrate SUB2.
[0037] The IR chip comprises an electrically conductive electrode 104 disposed on the side of the face 102 of the substrate SUB2. For example, the electrode 104 rests on the face 102.
[0038] In this example, the chip 104 comprises a quantum film QF covering the face 102 of the substrate SUB2, the film being in contact with the electrode 104. Although this is not shown in [Fig.l], an insulating layer is arranged between the film QF and the substrate SUB2 to electrically isolate them from each other.
[0039] The QF film is configured to convert received light in a given wavelength range into electron-hole pairs. For example, the QF film is configured to convert infrared light into electron-hole pairs, i.e., light having wavelengths, for example, between 780 nm and 1.5 pm.
[0040] The IR chip is for example an infrared light sensor configured to receive light 106 from its front face.
[0041] In the example of [Fig.l], the device 1 further comprises a second RGB chip.
[0042] The RGB chip comprises a silicon substrate SUBI having a front face 108 and a rear face 110 opposite the front face 108.
[0043] The front face 108 is coated with an end-of-line interconnection structure BEOL1 (in the orientation of [Fig.l], the substrate SUBI rests on the structure BEOL1). Although this is not detailed in [Fig.l], the interconnection structure BEOL1 comprises, like the interconnection structure BEOL2, portions of electrically conductive layers embedded in electrically insulating layers, and vias connecting the portions of electrically conductive layers to each other and / or to components, for example transistors (not shown), formed in and on the substrate SUBI on the side of its face 108 and / or to electrical connection pads (not shown) formed on the side of a first face of the structure BEOL1 opposite a second face of the structure BEOL1 arranged opposite and on the side of the face 108 of the substrate SUBI.
[0044] The RGB chip is, for example, a visible light sensor configured to receive light 106 from its backside 110. For example, the RGB chip is configured to convert visible light into an electron-hole pair, for example light having wavelengths between 400 nm and 650 nm.
[0045] Although not shown in [Fig.l], one or more anti-reflection layers and / or filters and / or lenses may rest on the face 110 of the substrate SUBI.
[0046] In the example of [Fig. 1], the RGB chip is mounted on, or assembled with, the IR chip. More particularly, in this example, the front face 100 of the substrate SUB2 is facing the front face 108 of the substrate SUB1. For example, the structure BEOL1 is mounted on, or assembled with, the structure BEOL2, for example so as to ensure an electrical connection between the IR and RGB chips. For example, the structure BEOL2 may comprise, on the side of its face facing the structure BEOL1, one or more anti-reflection layers and / or filters, for example configured to only allow infrared light to pass. For example, the face of the structure BEOL1 facing the structure BEOL2 is in contact with the face of the structure BEOL2 facing the structure BEOL1.For example, the BEOL2 structure may comprise, on the side of its face facing the BEOL1 structure, a bonding layer, for example made of silicon oxide, in contact with the BEOL1 structure, and / or the BEOL1 structure may comprise, on the side of its face facing the BEOL2 structure, a bonding layer, for example made of silicon oxide, in contact with the BEOL2 structure.
[0047] In the example of [Fig.l], the light 106 received by the device 1 on the side of the rear face 110 of the substrate SUBI comprises wavelengths in the visible range and wavelengths in the infrared range. The light 106 first reaches the substrate SUBI where the visible light is converted into electron-hole pairs. A portion of the light 106 which is not converted into electron-hole pairs in the substrate SUBI and which comprises wavelengths in the infrared range then passes through the substrate SUBI, the structures BEOL1 and BEOL2 and the substrate SUB2 before reaching the QF film where the infrared light is converted into electron-hole pairs.
[0048] The IR chip comprises an electrical connection 112 passing through the substrate SUB2 from its face 100 to the electrode 104. The connection 112 makes it possible to electrically connect the electrode 104 to the structure BEOL2.
[0049] Although not illustrated in [Fig.l], the IR chip may include a plurality of connections 112, for example each connected to a corresponding electrode 104.
[0050] A problem of the device 1, and, more particularly, of the connection 112, is to ensure the electrical connection between the electrode 104 and the connection 112, while ensuring that the electrode 104 and the connection 112 are electrically isolated from the substrate SUB2, for example as is apparent from the example of the manufacturing method illustrated by [Fig.2].
[0051] [Fig.2] illustrates, by three sectional views A, B and C, steps of an example of a method of manufacturing the electrical connection 112 of the device 1 of [Fig.l].
[0052] At a step illustrated by view A of [Fig.2], a via 200 has been formed in the SUB2 substrate.
[0053] The via 200 penetrates the substrate SUB2 from its front face 100. The via 200 penetrates the substrate SUB2 over only a portion of its thickness. In other words, the via 200 does not pass through the substrate SUB2. The via 200 penetrates vertically into the substrate SUB2, that is to say in a direction orthogonal to the plane of the faces 100 and 102 of the substrate SUB2.
[0054] The via 200 is intended to form the electrical connection 112 of the IR chip ([Fig.l]). The via 200 comprises a core 201 and a sheath 202. The core 201 is electrically conductive.
[0055] The sheath 202 is electrically insulating. The sheath 202 covers the core 201 and electrically insulates it from the substrate SUB2, i.e., from the silicon of the substrate SUB2. For example, the sheath 202 entirely covers the vertical (or lateral) walls of the core 201, and entirely one end of the core 201 opposite the face 100, i.e., the end of the core 201 arranged on the side of the face 102. Thus, no part of the core 201 is in contact with the substrate SUB2. Preferably, the sheath 202 is in contact with the core 201, for example with the entirety of the lateral walls of the core 201 and of the end of the core 201 furthest from the face 100.More preferably, the sheath comprises two main surfaces substantially parallel to each other, a first main surface of the sheath 202 facing the core 201 and being entirely in contact with the core 201, and a second main surface of the sheath 202 facing the substrate SUB2 and being entirely in contact with the substrate SUB2. In other words, the sheath 202 is interposed between the substrate SUB2 and the core 201 with which it is in contact.
[0056] By way of example, the via 200 is formed by etching a trench in the substrate SUB2 from the face 100 of the substrate and over only a portion of the thickness of the substrate SUB2, by forming the cladding 202 on the walls and the bottom of the trench, then by filling the trench with an electrically conductive material forming the core 201 of the via 200.
[0057] Although this is not illustrated in view A of [Fig.2], during the step of forming the via 200, the face 102 of the substrate SUB2 may rest on and in contact with a handle, i.e. a support layer.
[0058] Furthermore, in the step of view A of [Fig.l], the BEOL2 structure has been formed on the face 100 of the substrate SUB2, the formation of such a BEOL2 structure, for example by successive steps of deposition and etching of conductive and insulating layers, being within the reach of the person skilled in the art.
[0059] In a following step illustrated by view B of [Fig.2], the substrate SUB2 has been thinned, for example by chemical-mechanical polishing, from its rear face 102, until the core 201 of the via 200 is exposed, that is to say until the portion of the sheath 202 which covered the end of the core 201 on the side of the rear face 102 of the substrate SUB2. Thus, the via 200 is flush with the rear face 102 of the substrate SUB2.
[0060] Although this is not illustrated in [Fig.2], when in the step of view A of [Fig.2] the substrate SUB2 rests on a handle on the side of its face 102, this handle is removed prior to the step of thinning the substrate SUB2 or during the thinning step.
[0061] The step of thinning the substrate SUB2 is followed by a step of forming an insulating layer 204 on and in contact with the face 102 of the substrate SUB2. The layer 204 is formed as a full plate, that is to say that it entirely covers the face 102 and the part of the via 200 flush with the face 102. An opening 206 has then been formed through the layer 204, so as to expose the part of the via 200 flush with the face 102.
[0062] The formation of the opening 206 is implemented by forming an etching mask (not shown in [Fig. 2]) on the layer 204, the mask comprising a through opening at the location where it is desired to form the opening 206. However, as is well known to those skilled in the art, the alignment of the etching mask with the via 200 is complex to implement, and, due to an alignment defect, the opening 206 formed by the etching mask can then open not only onto the via 200, but also onto the substrate SUB2 as illustrated in view B of [Fig. 2].
[0063] As a result, in a following step illustrated by view C of [Fig.2], the electrode 104 formed in the opening 206 to be in contact with the core 201 of the via 200 forming the connection 112 ([Fig.l]) is also in contact with the substrate SUB2. However, the contact of the electrode 104 with the substrate SUB2 poses a problem, the latter then not being electrically isolated from each other.
[0064] [Fig. 3] illustrates, by five sectional views A, B, C, D and E, steps of an embodiment of a method for manufacturing an electrical connection 112 of the device of [Fig. 1],
[0065] View A of [Fig.3] illustrates a step of this embodiment of the manufacturing process.
[0066] In the embodiments described, for example the embodiment illustrated by [Fig. 3], the conductive core 201 of the via 200 is made of silicon, for example doped polycrystalline silicon, and the insulating sheath 202 of the via 200 is made of silicon oxide and may comprise silicon nitride. For example, the sheath 202 may comprise any stoichiometry of silicon, nitrogen and oxygen. For example, the sheath 202 comprises a layer of silicon oxide and may comprise a layer of silicon nitride. For example, the sheath 202 comprises a layer of thermal silicon oxide formed from the silicon of the substrate SUB2 constituting the walls and the bottom of the trench in which the via 200 is formed, and / or a layer of silicon oxide deposited re covering the walls and bottom of the trench and may comprise a layer of silicon nitride covering the walls and bottom of the trench. Preferably, the cladding 202 comprises only silicon oxide.
[0067] View A of [Fig.3] illustrates the IR chip at a stage following the stage described in relation to view A of [Fig.2].
[0068] In the step of view A of [Fig. 3], the substrate SUB2 has been etched from its face 102, selectively relative to the cladding 201 of the via 200. In other words, a portion of the thickness of the substrate SUB2 has been removed from the side of the face 102, by etching the silicon of the substrate SUB2 selectively relative to the silicon oxide of the cladding 202. This etching of the silicon of the substrate SUB2 may also be selective relative to the silicon nitride, for example when the cladding 202 comprises it. However, when the cladding 202 comprises a layer of silicon nitride and a layer of silicon oxide separating the layer of silicon nitride from the substrate SUB2, the etching of the silicon of the substrate SUB2 may not be selective relative to the silicon nitride.
[0069] Although this is not illustrated in [Fig. 2], when in the step of view A of [Fig. 2] the substrate SUB2 rests on a handle on the side of its face 102, this handle is removed before or simultaneously with the step of selective etching of the substrate SUB2. Furthermore, although this is not illustrated in [Fig. 3], the substrate SUB2 may rest on a handle on the side of its face 100 during the implementation of the step of selective etching of the substrate SUB2.
[0070] The etching is carried out so as to expose a portion of the via 200, and, more precisely, so that a portion of the via 200 is projecting relative to the face 102 of the substrate SUB2, or, in other words, protrudes above the face 102. For example, the portion of the via 200 projecting from the face 102 comprises a portion of the core 201 and a portion of the cladding 202 covering the core 201. For example, the thickness of the silicon removed during the etching is greater than the thickness of a portion of the substrate SUB2 extending from the via 200 to the face 102 before the etching. For example, the height of the portion of the projecting via 200, measured from the face 102 of the substrate SUB2, is greater than or equal to the thickness of the cladding 202.
[0071] Because the etching of the substrate SUB2 is selective with respect to the cladding 202, for the entire part of the via 200 projecting from the face 102, the cladding 202 covers the core 201.
[0072] In a following step illustrated by view B of [Fig.3], an insulating layer 300 has been deposited on the side of the rear face 102 of the substrate SUB2.
[0073] The insulating layer 300 is made of silicon oxide and may comprise silicon nitride. For example, the cladding 202 may comprise any stoichiometry of silicon, nitrogen and oxygen. For example, the layer 300 may comprise a stack of silicon oxide layers and silicon nitride layers. Preferably, the layer 300 consists only of silicon.
[0074] The insulating layer 300 is for example formed on and in contact with the face 102 of the substrate SUB2 and on and in contact with the part of the via 200 projecting from the face 102.
[0075] The insulating layer 300 is for example formed by one or more conformal deposition steps. The insulating layer is formed as a full plate, so that it completely covers the face 102 of the substrate SUB2 and the part of the via 200 projecting from this face 102.
[0076] The deposited layer 300 has a thickness greater than the height of the part of the via 200 which projects from the face 102. Thus, the entire face of the layer 300 which is not turned towards the face 102, that is to say the upper face of the layer 300 in the orientation of [Fig. 3], is further from the face 102 than the end of the via 200 which projects from the face 102.
[0077] View C of [Fig.3] illustrates the IR chip at a stage following the stage described in relation to view B of [Fig.3].
[0078] In this next step, chemical mechanical polishing (CMP) of the layer 300 is performed. The CMP step is performed until the core 201 of the via is uncovered, but in such a way as to leave in place a portion of the thickness of the layer 300 on the rear face 102 of the substrate SUB2, i.e. in such a way that, all around the via 200, the face 102 of the substrate SUB2 is entirely covered by the portion of the layer 300 left in place. In other words, only a portion of the thickness of the layer 300 is removed during the CMP step and the thickness removed is large enough for the CMP step to expose the core 201 of the via 200.
[0079] The CMP step is not selective, unlike the etching step described in relation to view A of [Fig. 3]. Thus, during this CMP step, the portion of the cladding 202 which covered the top (in the orientation of [Fig. 3]) is also removed, which makes it possible to expose the core 201. Because the CMP step is not selective, a portion of the core 201 can also be removed during this step.
[0080] As illustrated by view C of [Fig.3], at the end of the CMP step, the end of the via 200 which is arranged on the side opposite to the face 100, that is to say the end of the via which is arranged on the side of the face 102, is flush with the face 102. In other words, after the CMP step, the face of the IR chip which is exposed on the side of the face 102 of the substrate SUB2 is flat.
[0081] By way of example, the part of the layer 300 which is left in place at the end of the CMP step has a thickness of between 100 and 300 nm.
[0082] View D of [Fig.3] illustrates the IR chip at a step following the step described in relation to view C of [Fig.3]. The step described in relation to this view D is optional and may be omitted.
[0083] The step in view D is a step of etching a part of the core 201 of the via 200. This etching is implemented on the rear face side and is selective with respect to the cladding 202 and the insulating layer 300. In other words, the selectivity of the etching of view D of the figure is similar or identical to that of view A of [Fig.3], so that only the silicon of the core 201 is etched, the material(s) of the cladding and the material(s) of the layer 300 being left in place.
[0084] As a result, an exposed surface of the core 201 is then set back relative to the exposed surface of the layer 300. Furthermore, the substrate SUB2 is not exposed by this etching because the layer 300 and the cladding 200 are left in place. For example, the advantage of having the exposed surface of the core 201 set back relative to the exposed surface of the layer 300 is to have a topology on which to align in order to then define the electrode 104. For example, the distance between the exposed surface of the layer 300 and the exposed surface of the core 201 can be between a few nanometers and several hundred nanometers. For example, this distance can reach up to approximately half the thickness that the substrate SUB2 has at the end of the step in view A of [Fig. 3].
[0085] View E of [Fig. 3] illustrates the IR chip at a stage following the stage described in relation to view D of [Fig. 3], although, in an alternative embodiment where the stage of view D of [Fig. 3] is omitted, the stages which will be described in relation to view E of [Fig. 3] are implemented from the IR chip obtained at the end of the stages of view C of [Fig. 3].
[0086] More particularly, view E of [Fig.3] illustrates a step of forming the electrode 104 on the side of the face 102 and in contact with the core 201.
[0087] According to one embodiment, the formation of the electrode 104 comprises the deposition of an electrically conductive layer on and in contact with the layer 300 and the core 201, the conductive layer also being formed on and in contact with the portions of the sheath 202 which are exposed at the end of the step of view C of [Fig. 3] or of the step of view D of [Fig. 3] when the latter is implemented. By way of example, the conductive layer is deposited on the side of the face 102 of the substrate SUB2, for example in a conformal manner, and preferably in a full wafer manner.
[0088] According to one embodiment, the formation of the electrode 104 further comprises a step of removing, up to the layer 300, a portion of the conductive layer resting on this layer 300 while leaving the electrode 104 in place. In other words, the electrode 104 is defined by etching in the conductive layer.
[0089] The electrode 104 completely covers the top of the core 201 on the side of the face 102, and is in contact with the entire top of the core 201 on the side of the face 102. The electrode 104 can overflow onto the layer 300, around the via 200.
[0090] At the end of the step of view E of [Fig.3], the core 201 of the via 200, that is to say the part of the core 201 of the via 200 which was not removed during the previous steps, forms, or constitutes an electrical connection 112 extending from the face 100 of the substrate SUB2 to the electrode 104. Although this is not illustrated in [Fig.3], on the side of the face 100, the core 201 of the via 200, that is to say the connection 112, is electrically connected to the structure BEOL2, for example to a conductive element, conductive via or portion of conductive layer, of this structure BEOL2.
[0091] More particularly, at the end of the step of view E of [Fig. 3], the IR chip comprises the substrate SUB2, the interconnection structure BEOL2 covering the front face 100 of the substrate SUB2, the insulating layer 300 resting on, and preferably in contact with, the rear face 102 of the substrate SUB2, the via 200 comprising the conductive core 201 laterally covered with the insulating sheath 202. The via 200 passes through the substrate SUB2 from its face 100, and at least the sheath 202 of the via 200 passes through the layer 300 and is flush with a first face of the layer 300 opposite a second face of the layer 300 which is in contact with the substrate SUB2. The IR chip further comprises the electrode 104 which rests on and in contact with the core 201 on the side of the face 102 of the substrate SUB2.
[0092] The method described in relation to [Fig.3] allows that, during the formation of the electrode 104, the contact between the electrode 104 and the connection 112 (or core 201) is made in a self-aligned manner.
[0093] Furthermore, the method described in relation to [Fig. 3] allows that, at the end of the formation of the electrode 104, the latter is electrically isolated from the substrate SUB2 by the sheath 202 and by the layer 300, the substrate SUB2 being further electrically isolated from the connection 112 by the sheath 112. For example, the sheath 202 extends in height from the face 100 of the substrate SUB2 to the face of the layer 300 which is opposite the face of the layer 300 in contact with the substrate SUB2.
[0094] An advantage of the method described in relation to [Fig. 3] is that the mask alignment constraints, for example to define the electrode 104 in the conductive layer, are relaxed compared to the etching mask alignment constraints described in relation to view B of [Fig. 2]. Indeed, in the method described in relation to [Fig. 3], the alignment constraints are relaxed due to the selectivity of the etching of view A of [Fig. 3], the deposition of the layer 300 of view B of [Fig. 3], the CMP step of view C of [Fig. 3], and the selectivity of the etching of view D of [Fig. 3] when the latter is implemented.
[0095] For example, in a plane parallel to the faces 100 and 102, the largest dimension of the core 201, for example its diameter when the via 200 has a disc-shaped cross-section, is between 0.5 pm and 2 pm.
[0096] By way of example, the thickness of the sheath 202, for example measured in a plane parallel to the faces 100 and 102, is between 50 nm and 300 nm.
[0097] As an example, at the end of the step in view E of [Fig.3], the thickness of the substrate SUB2, for example measured orthogonally to its 100 and 102 faces, is between 200 nm and a few micrometers.
[0098] The implementation of the method described in relation to [Fig.3] to form the connection 112 and the electrode 104 of the IR chip described in relation to [Fig.1], makes it possible to ensure electrical insulation between the electrode 104 and the substrate SUB2, which is not the case with the example method described in relation to [Fig.2].
[0099] [Fig. 4] represents, by a sectional view, a step of a method of manufacturing the device 1 of [Fig. 1] according to one embodiment. More particularly, [Fig. 4] illustrates a step of forming the quantum film QF on the layer 300 and the electrode 104 of the structure obtained at the end of the method described in relation to [Fig. 3]. The formation of the quantum film QF is within the capabilities of a person skilled in the art.
[0100] According to one embodiment, the QF film is formed by one or more deposition steps, preferably full plate, on the side of the face 102 of the substrate.
[0101] According to one embodiment, the QF film is formed on and in contact with the layer 300 and the electrode 104. In an alternative embodiment, one or more conductive layers may be formed on the layer 300 and the electrode 104, for example during one or more full-wafer deposition steps, and the QF film is then formed on and in contact with the last conductive layer formed.
[0102] For example, the thickness of the quantum film QF is between 400 nm and 800 nm.
[0103] According to one embodiment, the QF film is configured to convert infrared light into electron-hole pairs, for example when the IR chip is intended to be part of the device 1 of [Fig.l].
[0104] According to one embodiment, when the IR chip is intended to be part of the device 1 of [Fig.l], the electrode 104 is made of a material transparent to infrared, for example zinc oxide and / or indium-tin oxide.
[0105] In alternative embodiments not shown, the IR chip may not be assembled with the RGB chip.
[0106] In such variants, the IR chip may be intended to receive light from the side of the face 102 of the substrate SUB2, and the QF film may then be configured to convert light other than infrared light into electron-hole pairs. When the IR chip is intended to receive light from the side of the face 102 of the substrate SUB2, the electrode may not be transparent to the light received by the IR chip, or at least to the wavelengths of light that the QF film converts into electron-hole pairs.
[0107] [Fig.5] represents, by a sectional view, another step of a method of manufacturing the device 1 of [Fig.l] according to one embodiment. More particularly, [Fig.5] illustrates a step of assembling the IR chip obtained after the implementation of the step of [Fig.4], with the RGB chip.
[0108] Thus, at the step of [Fig.5], the RGB chip is provided comprising the substrate SUBI whose face 108 is coated with the structure BEOL1 and whose face 110 is intended to receive the light 106 ([Fig. 1]).
[0109] In the step of [Fig. 5], the RGB chip is mounted on, or assembled with, the IR chip. More particularly, in the step of [Fig. 5], the BEOL1 structure is mounted on, or assembled with, the BEOL2 structure. For example, the BEOL1 structure is assembled with the BEOL2 structure by molecular bonding. The implementation of this assembly step is within the ability of a person skilled in the art.
[0110] Although this is not illustrated in [Fig.5], additional steps may be provided, for example to form on the exposed face 110 of the substrate SUB1 one or more passivation layers and / or one or more anti-reflection coatings and / or one or more filters and / or one or more lenses.
[0111] According to one embodiment, the device 1 is a light sensor, for example configured to provide an image of a scene. For example, the SUB 1 substrate of the RGB chip comprises a plurality of photodetector elements making it possible to acquire a two-dimensional and color or black and white image of a scene, and the IR chip comprises a plurality of depth pixels each configured to provide depth information on the scene, the IR chip making it possible for example to acquire a depth map of the scene. For example, the device 1 is a light sensor configured to implement facial recognition.
[0112] Embodiments and variants of a method comprising the fabrication of the connection 112 and the electrode 104 of the IR chip, the formation of the QF film of the IR chip and the assembly of the IR chip to the RGB chip have been described previously. As already indicated previously, the IR chip may not be assembled to the RGB chip, i.e. not be part of the device 1 of [Fig. 1], and, in this case, the step of [Fig. 5] may be omitted. Furthermore, in the described embodiments and variants, the IR chip comprises the QF film. In alternative embodiments not shown, the IR chip is devoid of the QF film, for example when the IR chip is not an infrared sensor, and the step of [Fig. 4] is omitted. The electrode 104 and the connection 112 then make it possible, for example, to electrically connect the BEOL2 structure of the IR chip to an electrical conductor external to the IR chip.
[0113] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. In particular, the steps described for forming an electrode 104 in contact with the core 201 of a via 200 may be implemented simultaneously for several vias 200, such that the core 201 of each of these vias 200 is in contact with an electrode 104.
[0114] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.
Claims
Claims
1. A method of manufacturing an electrical connection of an electronic circuit, the method comprising the following steps: providing a silicon substrate (SUB2) having a front face (100) coated with an interconnection structure (BEOL2), a rear face (102) opposite the front face (100), at least one via (200) penetrating vertically into the substrate (SUB2) from the front face (100) over a portion of the thickness of the substrate (SUB2), said at least one via (200) comprising a conductive core (201) made of silicon and an insulating sheath (202) made of silicon oxide which may comprise silicon nitride, the sheath (202) covering the core (201) and electrically insulating it from the substrate (SUB2); etching, from the rear face (102), the substrate (SUB2) selectively with respect to the cladding (202) so that a portion of said at least one via (200) protrudes from the rear face (102); depositing an insulating layer (300) of silicon oxide which may comprise silicon nitride on the side of the rear face (102) over a thickness greater than a height of the part of said at least one protruding via (200); performing chemical-mechanical polishing of the insulating layer (300) until exposing the conductive core (201) of said at least one via, leaving in place a portion of the thickness of the insulating layer (300) on the rear face (102); forming a conductive electrode (104) on the side of the rear face (102) and in contact with the core (201) of said at least one via (200), the electrode (104) being made of a material transparent to infrared light, for example zinc oxide and / or indium-tin oxide; forming a quantum film (QF) resting on the insulating layer (300) and the electrode (104), the quantum film (QF) being configured to convert infrared light into electron-hole pairs; providing an additional silicon substrate (SUBI) having a front face (108) coated with an additional interconnection structure (BEOL1) and a rear face (110) opposite the front face (108) of the additional substrate (SUBI) and intended to receive light (106); and assembling the interconnection structure (BEOL2) on the additional interconnection structure (BEOL1).
2. The method of claim 1, wherein the step of forming the electrode (104) comprises depositing a conductive layer on the insulating layer (300) and in contact with the core (201) of said at least one via (200), and a step of removing a portion of the conductive layer while leaving said electrode (104) in place.
3. Method according to claim 1 or 2, wherein the insulating layer (300) is deposited on and in contact with the rear face (102) of the substrate (SUB2) and the portion of said at least one via (200) protruding.
4. Method according to any one of claims 1 to 3, in which the method further comprises, between the polishing step and the step of forming the electrode (104), a step of etching a part of the core (201) of said at least one via (200), the etching being carried out on the side of the rear face (102) and being selective with respect to the cladding (202) and the insulating layer (300).
5. Method according to any one of claims 1 to 4, wherein the cladding (202) of said at least one via is in contact with the core (201) of said at least one via.
6. Device (1) comprising: a semiconductor substrate (SUB2) made of silicon comprising a front face (100) and a rear face (102) opposite the front face (100); an interconnection structure (BEOL2) covering the front face (100); an insulating layer (300) made of silicon oxide which may comprise silicon nitride, the insulating layer (300) resting on the rear face (102); at least one via (200) comprising a conductive core (201) made of silicon laterally covered with an insulating sheath (202) made of silicon oxide which may comprise silicon nitride, said at least one via (200) passing through the substrate (SUB2) from its front face (100), at least the sheath (202) of said at least via (200) passing through the insulating layer (300) and being flush with a first face of the insulating layer (300) opposite a second face of the insulating layer (300) facing the substrate (SUB2);a conductive electrode (104) resting on and in contact with the conductive core (201) of said at least one via, on the side of the rear face (102) of the substrate (SUB2), the electrode (104) being made of a material transparent to infrared light, for example zinc oxide and / or indium-tin oxide; a quantum film (QF) resting on the insulating layer (300) and; the electrode (104), the quantum film (QF) being configured to convert infrared light into electron-hole pairs; and an additional silicon substrate (SUBI) and an additional interconnection structure (BEOL1) resting on a front face (108) of the additional substrate (SUBI), the interconnection structure (BEOL2) being assembled on the additional interconnection structure (BEOL1) and the additional substrate (SUBI) comprising a rear face (110) opposite its front face (108) and intended to receive light (106).