Memory cell, electronic circuit comprising such cells, programming method, and associated multiplication and accumulation method

Abstract

Memory cell, electronic circuit comprising such cells, programming method and associated multiplication and accumulation method. This memory cell (10) comprises first (12) and second (14) main terminals, an auxiliary terminal (16); M memristor(s) (20) between the main terminals, M≥1; M primary switch(s) (22), each in parallel with a memristor; and a secondary switch (24) between the second main terminal and the auxiliary terminal.It is configured to write to at least one memristor by opening each primary switch in parallel with said at least one memristor, closing each other primary switch, closing the secondary switch, and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and to read from at least one memristor by opening each primary switch in parallel with said at least one memristor, closing each other primary switch, opening the secondary switch, and measuring a corresponding electrical quantity between the main terminals. See Figure 1 for abbreviations.

Description

Title of the invention: Memory cell, electronic circuit comprising such cells, associated programming method and multiplication and accumulation method

[0001] The present invention relates to a memory cell for an electronic circuit.

[0002] The invention also relates to an electronic circuit comprising value lines, programming lines, source lines, and a set of such memory cells.

[0003] The invention also relates to a method for programming at least one memory cell of a respective row of memory cells of such an electronic circuit.

[0004] The invention also relates to a method for multiplying and accumulating a batch of memory cell(s) of a respective column of memory cells of such an electronic circuit.

[0005] The invention relates to multiple applications, including automatic data processing, diagnostic assistance, predictive analysis, autonomous vehicles, bioinformatics or surveillance. These applications typically involve the classification or identification of objects previously detected by a sensor, for example making it possible to recognize or classify the identities of people whose faces have been detected by a face detector, or to recognize or classify surrounding objects detected by a sensor on board an autonomous vehicle, the recognition or classification of such objects being important for the autonomous driving of such a vehicle.

[0006] For the multiple applications mentioned above, it is known to use machine learning algorithms that are part of programs that can be executed on processors, such as CPUs (Central Processing Units) or GPUs (Graphics Processing Units).

[0007] Among the techniques for implementing learning, the use of neural networks, i.e. artificial neural networks, or ANN (from the English Artificial Neural Network) known per se, is becoming increasingly widespread, these structures being considered very promising due to their performance for numerous tasks such as automatic data classification, pattern recognition, automatic translation and understanding of languages, robotic control, automatic navigation, recommendation systems, anomaly detection, fraud detection, the study of DNA or even the discovery of new molecules.

[0008] A neural network is generally composed of a succession of layers of neurons, each of which takes its inputs from the outputs of the previous layer. More precisely, each layer comprises neurons taking their inputs from the outputs of the neurons in the previous layer. Each layer is connected by a plurality of synapses. A synaptic weight is associated with each synapse. It is a real number, which takes both positive and negative values. For each layer, the input of a neuron is the weighted sum of the outputs of the neurons in the previous layer, the weighting being done by the synaptic weights.

[0009] For an implementation in a CPU or a GPU, a Von Neumann bottleneck problem arises because the implementation of a deep neural network (with more than three layers and up to several dozen) involves using both the memory(s) and the processor while these latter elements are spatially separated. This results in congestion of the communication bus between the memory(s) and the processor both while the neural network, once trained, is used to perform a task, and, even more so, while the neural network is being trained, i.e. while its synaptic weights are being adjusted to solve the task in question with maximum performance.

[0010] It is therefore desirable to develop dedicated hardware architectures, intermixing memory and calculation, to create fast, low-power neural networks capable of learning in real time.

[0011] To reduce the size, it is known to use architectures in which the synapses are memristive. Memristive synapses are synapses using memristors. In electronics, the memristor (or memristance) is a passive electronic component. The name is a portmanteau word formed from the two English words memory and resistor. A memristor is a non-volatile memory component, the value of its electrical resistance changing with the application of a voltage for a certain duration, and remaining at this value in the absence of voltage.

[0012] An example of such an implementation is proposed in an article by S. Jung et al. entitled “A crossbar array of magnetoresistive memory devices for in-memory computing” published on January 12, 2022 in the journal Nature. The neural network is implemented by a set of 2T2R type memory cells, in reference to the presence of two switches (designated 2T) and two memristors (designated 2R) for each memory cell.

[0013] However, this implementation relates to a particular neural network which is a binary neural network, or BNN (from the English Binary Neural Network), that is to say a network in which the neurons and the synapses can only take binary values.

[0014] The aim of the invention is then to propose a memory cell, and an associated electronic circuit, allowing the implementation of all types of neural networks, and in particular networks other than binary neural networks.

[0015] To this end, the invention relates to a memory cell comprising:

[0016] - a first main terminal, a second main terminal and a terminal auxiliary;

[0017] - M memristor(s) connected between the two main terminals, M being a number integer greater than or equal to 1;

[0018] - M primary switch(es), each connected in parallel with a memristor respective; and

[0019] - a secondary switch connected between the second main terminal and the terminal auxiliary;

[0020] the memory cell being configured for writing a respective value in at least one memristor via the opening of the or each primary switch in parallel with said at least one memristor, the closing of the or each possible other primary switch, the closing of the secondary switch and the application of a corresponding programming voltage between the first main terminal and the auxiliary terminal;

[0021] the memory cell being configured for reading a respective value in at least one memristor via the opening of the or each primary switch in parallel with said at least one memristor, the closing of the or each possible other primary switch, the opening of the secondary switch and the measurement of a corresponding electrical quantity between the two main terminals.

[0022] With the memory cell according to the invention, the memory cell allows the writing, then the reading, of any value, in the form of the value of the electrical resistance of a respective memristor included in the memory cell, and not only of a binary value unlike the memory cell of the state of the art.

[0023] Preferably, the memory cell further allows the multiplication of a value of a respective memristor by a multiple, via the alternation - during an inference cycle - of opening(s) and closing(s) of the primary switch in parallel with said memristor. This then typically allows the implementation of a multiplication and accumulation operation, also called MAC (from the English Multiplication and Accumulation).

[0024] During the inference of an artificial neural network, each artificial neuron is typically able to perform a weighted sum of value(s) received as input from element(s) connected to its input, such as the neurons of the previous layer, each input value then being multiplied by a respective synaptic weight value, then to apply an activation function, typically a function non-linear, to said weighted sum, and to deliver to the element(s) connected to its output the value resulting from the application of said activation function. The memory cell according to the invention, and in particular a set of such memory cells connected in series, are then particularly suitable for efficiently calculating the aforementioned weighted sum.

[0025] According to other advantageous aspects of the invention, the memory cell comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0026] - the memory cell is further configured for multiplication of a value of at least at least one respective memristor by a multiple, via an alternation of opening(s) and closing(s) of the or each primary switch in parallel with said at least one memristor during an inference cycle, the closing of the or each possible other primary switch, the opening of the secondary switch and the measurement of a corresponding electrical quantity between the two main terminals, a ratio between a cumulative duration of opening of the or each primary switch in parallel with said at least one memristor during the inference cycle and a duration of said cycle being representative of the multiple;

[0027] - the memory cell comprises exactly M memristor(s);

[0028] - the memory cell comprises exactly M+1 switches;

[0029] the memory cell preferably being made up of the first and second main terminals, the auxiliary terminal, the memristor, and the primary and secondary switches;

[0030] - the memory cell further comprises M tertiary switch(es), each being connected to a respective memristor, the tertiary switch and the memristor being connected in series, in parallel with the associated primary switch;

[0031] the memory cell preferably being made up of the first and second main terminals, the auxiliary terminal, the memristor, and the primary, secondary and tertiary switches (22, 24, 300);

[0032] - M is equal to 1, and the memory cell is then configured for writing a respective value via opening the primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; the memory cell being configured for reading a respective value via opening the primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the two main terminals;

[0033] - M is strictly greater than 1, the M memristors are connected in series between the two main terminals;

[0034] - the memory cell is configured for writing a respective value into a memristor via opening the primary switch in parallel with said memristor, closing the or each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; the memory cell being configured for reading a respective value in a memristor via opening the primary switch in parallel with said memristor, closing the or each other primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the two main terminals.

[0035] - the or each memristor is a resistive memory component chosen from the group consisting of: a PCRAM component, an OxRAM component, an MRAM component, and a CBRAM component.

[0036] - each switch is a transistor;

[0037] each transistor preferably being a field effect transistor, such as an insulated gate field effect transistor, or MOSFET.

[0038] The invention also relates to an electronic circuit, comprising:

[0039] - value lines;

[0040] - programming lines;

[0041] - source lines; and

[0042] - a set of memory cells, each memory cell being according to one of any of the preceding claims,

[0043] for each memory cell, a control electrode of a respective primary switch being connected to a respective value line, a control electrode of the secondary switch being connected to a respective programming line, and the auxiliary terminal being connected to a respective source line.

[0044] According to other advantageous aspects of the invention, the electronic circuit comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0045] - the electronic circuit further comprises additional programming lines mentary, and for each memory cell, a control electrode of a respective tertiary switch is connected to a respective complementary programming line;

[0046] - the electronic circuit further comprises multiplexers, each source line being connected to a respective multiplexer, each multiplexer being configured to select, based on a selection signal and from among several predefined values, an electrical potential value to be applied to the associated source line;

[0047] - the electronic circuit further comprises auxiliary switches, each source line being connected to a respective auxiliary switch, each auxiliary switch being configured to, upon receipt of a li- limitation, limiting an electric current flowing in the associated source line;

[0048] each auxiliary switch preferably being a transistor, and the limiting control being a predefined limiting potential applied to a control electrode of said auxiliary switch;

[0049] the electronic circuit preferably further comprising auxiliary multiplexers, the control electrode of each auxiliary switch being connected to a respective auxiliary multiplexer, each auxiliary multiplexer being configured to select, as a function of a limitation signal and from among several predefined values ​​(VCOMPL, VDD), an electrical potential value to be applied to the associated control electrode;

[0050] - the set of memory cells is arranged in the form of a matrix comprising rows and columns, the memory cells of the same row being connected to M same value row(s) and to the same source row, and the memory cells of the same column being connected to the same programming row;

[0051] - the memory cells of the same row are further connected to M same(s) complementary programming line(s);

[0052] - the electronic circuit further comprises measurement modules, and the cells memory cells of the same column are connected in series with each other, each column having a first end connected to a reference potential and a second end connected to a respective measurement module, each measurement module being configured to measure a cumulative voltage of the memory cells of the column to which it is connected;

[0053] the electronic circuit preferably further comprising a reference line to which the reference potential is applied, the first ends of the columns then being connected to the reference line;

[0054] each measurement module preferably further comprising a comparator configured to detect the reaching, by the cumulative voltage of the memory cells of the respective column, of a respective predefined threshold voltage.

[0055] The invention also relates to a method for programming at least one memory cell of a respective row of memory cells of an electronic circuit as defined above, the method comprising the following steps:

[0056] - opening of primary switches of the memory cells of said row, via applying an open command to a respective value line connected to said row;

[0057] - closing of any other primary switches of the memory cells of said row, via the application of a close command on the possible other value row(s) connected to said row;

[0058] - closing of the at least one secondary switch of said at least one cell memory, via the application of a closing command on the at least one programming line connected to said at least one memory cell of said row;

[0059] - assignment of a value to at least one memristor of said at least one cell memory, with a programming voltage corresponding to the value between the at least one first main terminal and the at least one auxiliary terminal of said at least one memory cell, via the application of a first electrical potential to the source line(s) arranged on the side of the at least one first main terminal and a second electrical potential to the other source line(s), arranged on the side of the at least one auxiliary terminal, the programming voltage corresponding to the assigned value being equal to the difference between the first and second potentials, the or each primary switch in parallel with said at least one memristor being open.

[0060] According to other advantageous aspects of the invention, the programming method comprises one or more of the following characteristics, taken in isolation or in all technically possible combinations:

[0061] - the method further comprises, before the assignment step, a closing step tertiary switches of the memory cells of said row, via the application of a closing command on the complementary programming line(s) connected to said row;

[0062] during the assignment step, the first electrical potential being preferably applied to the only source line connected to the at least one first main terminal and the second electrical potential being applied to the only source line connected to the at least one auxiliary terminal of said row;

[0063] the method preferably further comprising, before the assignment step, in addition a step of opening the other tertiary switches, via the application of an opening command on the other complementary programming line(s) of the electronic circuit;

[0064] - the assignment step further comprises closing the auxiliary switches connected to the source lines to which one of the first and second potentials is applied;

[0065] the auxiliary switch associated with said row preferably being further controlled with a predefined limiting potential applied to its control electrode.

[0066] The invention also relates to a method for multiplying and accumulating a batch of memory cell(s) of a respective column of memory cells of an electronic circuit as defined above, the method comprising the following steps:

[0067] - opening of the secondary switches of the memory cells of said column, via the application of an opening command on the programming line connected to said column;

[0068] - if said batch does not include all the memory cells of said column, closing of each primary switch of each distinct memory cell of said batch within said column, via the application of a closing command on each value line connected to each distinct memory cell of said batch;

[0069] - controlling each primary switch of said batch of memory cell(s) with a alternating opening(s) and closing(s) during an inference cycle, via the application of alternating opening(s) and closing(s) commands on each value line connected to each primary switch of said batch, to multiply the value of each memristor of said batch by a respective multiple; a ratio between a cumulative duration of opening of the respective primary switch during the inference cycle and a duration of said cycle being representative of the respective multiple;

[0070] - obtaining a weighted sum of value(s) of memristor(s) of said batch, each memristor value being multiplied by the respective multiple, via a measurement of the cumulative voltage of the memory cells of said column.

[0071] According to another advantageous aspect of the invention, the multiplication and accumulation method comprises the following characteristic:

[0072] - the method further comprises, before the piloting step, a step of closing each tertiary switch of said batch, via the application of a closing command on each complementary programming line connected to each tertiary switch of said batch.

[0073] The invention also relates to a method for reading at least one memory cell of a respective row of memory cells of an electronic circuit as defined above, the method comprising the following steps:

[0074] - opening of primary switches of the memory cells of said row, via applying an open command to a respective value line connected to said row;

[0075] - closing of any other primary switches of the memory cells of said row, via the application of a close command on the possible other value row(s) connected to said row;

[0076] - closing of the at least one secondary switch of said at least one cell memory, via the application of a closing command on the at least one programming line connected to said at least one memory cell of said row;

[0077] - reading a value of at least one memristor of said at least one cell memory, with a read voltage between the at least one first main terminal and the at least one auxiliary terminal of said at least one memory cell, via the application of a third electrical potential to the source line(s) arranged on the side of the at least one first main terminal and a fourth electrical potential to the other source line(s), arranged on the side of the at least one auxiliary terminal, the reading voltage being equal to the difference between the third and fourth potentials, the or each primary switch in parallel with said at least one memristor to be read being open.

[0078] The invention also relates to a method for reading a batch of memory cell(s) from a respective column of memory cells of an electronic circuit as defined above, the method comprising the following steps:

[0079] - opening of the secondary switches of the memory cells of said column, via the application of an opening command on the programming line connected to said column;

[0080] - opening of the primary switch in parallel with the or each memristor to be read of said batch of memory cell(s), via the application of an opening command on the value line connected to each primary switch in parallel with the or each memristor to be read from said batch;

[0081] - closing of each other possible primary switch of said batch of cell(s) memory, via the application of an opening command on the value line connected to each other possible primary switch of said batch;

[0082] - if said batch does not include all the memory cells of said column, closing of each primary switch of each distinct memory cell of said batch within said column, via the application of a closing command on each value line connected to each distinct memory cell of said batch;

[0083] - reading a sum of value(s) of memristor(s) to be read from said batch, via a measurement of the cumulative voltage of the memory cells of said column.

[0084] According to another advantageous aspect of the invention, the reading method further comprises, before the reading step, a step of closing each tertiary switch of said batch, via the application of a closing command on each complementary programming line connected to each tertiary switch of said batch.

[0085] These characteristics and advantages of the invention will appear more clearly on reading the description which follows, given solely by way of non-limiting example, and made with reference to the appended drawings, in which:

[0086] [Fig-1] [Fig.l] is a schematic representation of a memory cell comprising two main terminals and one auxiliary terminal, M memristors and M primary switches connected between the two main terminals, each primary switch being connected in parallel with a respective memristor, as well as a secondary switch connected between the auxiliary terminal and one of the main terminals, in the case where M is strictly greater than 1, according to a first embodiment of the invention;

[0087] [Fig.2] [Fig.2] is a schematic representation of an electronic circuit comprising value lines, programming lines, source lines and a set of memory cells, each being of the type of the memory cell of [Fig.l], according to a first exemplary embodiment;

[0088] [Fig.3] [Fig.3] is a view similar to that of [Fig.2], according to a second exemplary embodiment, where the electronic circuit further comprises auxiliary switches connected to the source lines;

[0089] [Fig.4] [Fig.4] is a view similar to that of [Fig.l], in the case where M is equal to 1 ;

[0090] [Fig.5] [Fig.5] is a view similar to that of [Fig.2], in the case where M is equal to 1 ;

[0091] [Fig.6] [Fig.6] is a view similar to that of [Fig.3], in the case where M is equal to 1 ;

[0092] [Fig.7] [Fig.7] is a schematic representation of examples of timing diagrams controlling the primary switch of the memory cell, during a multiplication operation associated with it;

[0093] [Fig.8] [Fig.8] is a flowchart of a programming method of at least a memory cell of a respective row of memory cells of the electronic circuit, according to the first embodiment of the invention;

[0094] [Fig.9] [Fig.9] is a flowchart of a multiplication and accumulation process emulation of a batch of memory cell(s) of a respective column of memory cells of the electronic circuit, according to the first embodiment of the invention;

[0095] [Fig.10] [Fig.10] is a view similar to that of [Fig.l], according to a second embodiment of the invention, wherein the memory cell further comprises M tertiary switch(es), each being connected to a respective memristor, the tertiary switch and the memristor being connected in series, in parallel with the associated primary switch, with M being an integer greater than or equal to 1;

[0096] [Fig. 11] [Fig. 11] is a view similar to that of [Fig.5], according to the second embodiment of the invention, each memory cell being of the type of the memory cell of [Fig. 10];

[0097] [Fig. 12] [Fig. 12] is a view similar to that of [Fig.8], according to the second embodiment of the invention; and

[0098] [Fig. 13] [Fig. 13] is a view similar to that of [Fig.9], according to the second embodiment of the invention.

[0099] In the present description, unless otherwise indicated, when reference is made to two elements connected to each other, this preferably means that they are connected directly to each other, without any intermediate element between them other than connecting conductors; and when reference is made to two elements coupled or connected to each other, this means that these two elements are either connected to each other, or coupled or connected to each other by means of one or more other elements.

[0100] In the present description, unless otherwise specified, the expressions “substantially”, “about”, “approximately” and “of the order of” define a relationship of equality to plus or minus 10%, preferably to plus or minus 5%.

[0101] In [Fig.l], a memory cell 10 comprises a first main terminal 12, a second main terminal 14 and an auxiliary terminal 16.

[0102] The memory cell 10 comprises M memristor(s) 20 connected between the two main terminals 12, 14, M being an integer greater than or equal to 1; M primary switch(es) 22, each being connected in parallel with a respective memristor 20; and a secondary switch 24 connected between the second main terminal 14 and the auxiliary terminal 16. Each primary switch 10 forms with the respective memristor 20, in parallel with which it is connected, a sub-cell 25. In other words, the memory cell 10 comprises M sub-cells 25 connected in series with each other between the two main terminals 12, 14; and further the secondary switch 24 connected between the second main terminal 14 and the auxiliary terminal 16.

[0103] The memory cell 10 is typically a resistive random access memory cell, also called an RRAM cell or ReRAM cell (from the English Resistive Random Access Memory).

[0104] The memory cell 10 is configured for writing a respective value into at least one memristor 20 via the opening of the or each primary switch 22 in parallel with said at least one memristor 20, the closing of the or each possible other primary switch 22, the closing of the secondary switch 24 and the application of a corresponding programming voltage between the first main terminal 12 and the auxiliary terminal 16, i.e. to the ends of the memristor 20.

[0105] Those skilled in the art will then understand that this writing of value in at least one memristor 20 of the memory cell 10 corresponds to the assignment of a resistance value to said at least one memristor 20 by applying the programming voltage corresponding to said value to the ends of said at least one memristor 20.

[0106] The memory cell 10 is also configured for reading a respective value in at least one memristor 20 via the opening of the or each primary switch 22 in parallel with said at least one memristor 20, the closing of the or each possible other primary switch 22, the opening of the secondary switch 24 and the measurement of a corresponding electrical quantity between the two main terminals 12, 14, i.e. at the ends of said at least one memristor 20.

[0107] Those skilled in the art will then understand that this reading of the value contained in at least one memristor 20 of the memory cell 10 corresponds to the reading of the resistance value of said at least one memristor 20, via the measurement of the electrical quantity cor corresponding to the ends of said at least one memristor 20, for example via the measurement of the voltage at the ends of said at least one memristor 20.

[0108] As an optional addition, the memory cell 10 is further configured for the multiplication of a value of at least one respective memristor 20 by a multiple, via an alternation of opening(s) and closing(s) of the or each primary switch 22 in parallel with said at least one memristor 20 during an inference cycle, the closing of the or each possible other primary switch 22, the opening of the secondary switch 24 and the measurement of a corresponding electrical quantity between the two main terminals 12, 14. A ratio p between a cumulative duration of opening of the or each primary switch 22 in parallel with said at least one memristor 20 during the inference cycle and a duration of said cycle is representative of the respective multiple. The ratio p is equal to said multiple.

[0109] In the example of [Fig. 1], the memory cell 10 comprises exactly M memristor(s) 20.

[0110] In the example of [Fig. 1], the memory cell 10 comprises exactly M+1 switches 22, 24.

[0111] In the example of [Fig. 1], the memory cell 10 is then made up of the first and second main terminals 12, 14, the auxiliary terminal 16, the memristor 20, and the primary and secondary switches 22, 24.

[0112] In the example of [Fig. 1], the memory cell 10 is therefore a memory cell of type (M+1)TMR, with reference to the presence of M+1 switches (designated (M+1)T) and M memristor(s) (designated MR), and each sub-cell 25 is of type 1T1R.

[0113] In the example of [Fig. 1], the integer M is strictly greater than 1.

[0114] When the number M is strictly greater than 1, a person skilled in the art will understand that the writing of a given value in a respective memristor 20 is obtained in particular via the opening of the primary switch 22 in parallel with said memristor 20, and the closing of the other primary switch(es) 22, which then corresponds to the case where any other primary switch(es) 22 are to be closed.

[0115] When the number M is alternatively equal to 1, as will be described in more detail below with reference to FIGS. 4 to 6, those skilled in the art will also understand that the writing of a given value in the memristor 20 of the memory cell 10 is obtained in particular via the opening of the primary switch 22 which is arranged in parallel with said memristor 20, and that there is then no other possible primary switch 22 to close in this case.

[0116] Those skilled in the art will then observe that the memory cell 10 according to the invention is a 2T1R type cell in the case where M is equal to 1, and then comprises a memristor less than the state-of-the-art 2T2R type memory cell.

[0117] Those skilled in the art will note more generally that in the example of [Fig. 1], for M greater than 1, the memory cell 10 of type (M+1)TMR according to the invention makes it possible to write M distinct values, then to read and / or infer these values, each of the M sub-cells 25 being associated with a respective value; and that the memory cell 10 is therefore comparable to M memory cells of type 2T2R of the prior art, each sub-cell 25 of type 1T1R according to the invention being comparable to the memory cell of type 2T2R of the prior art.The person skilled in the art will then understand that the memory cell 10 according to the first embodiment of the invention comprises M fewer memristors, as well as (M1) fewer switch(es) than the M corresponding 2T2R type memory cells of the prior art, or that each 1T1R type sub-cell 25 according to the first embodiment comprises one fewer memristor and one fewer switch than the 2T2R type memory cell of the prior art.

[0118] Each memristor 20 is a passive electronic component whose electrical resistance value changes, permanently, when a current is applied. In other words, each memristor 20 is a resistive component, and more precisely a resistive memory component. Thus, data can be recorded and rewritten by a control current. Such behavior is notably observed in phase change materials, ferroelectric tunnel junctions or redox memories based on oxides, such as HfOx or TiO2 x.

[0119] Each memristor 20 is a non-volatile memory component, the value of its electrical resistance changing with the application of a voltage for a certain duration and remaining at this value in the absence of voltage.

[0120] The change in conductance of the memristor 20 depends on the amplitude and duration of the voltage pulses applied across the memristor 20, as well as the maximum current value that can pass through the memristor 20, for example for a “SET” operation, i.e. the transition from a high resistance to a low resistance. An inverse “RESET” operation corresponds to the transition from a low resistance to a high resistance.

[0121] The memristor 20 is capable of exhibiting two states, namely a high state and a low state.

[0122] The high state corresponds to a high resistance and is generally designated by the abbreviation HRS (from the English High Resistive State) which literally means highly resistive state. The high state is, therefore, called the high HRS state thereafter.

[0123] The low state corresponds to a low resistance and is generally designated by the abbreviation LRS (from the English Low Resistive State) which literally means weakly resistive state. The low state is therefore called the low LRS state thereafter.

[0124] The memristor 20 is for example a resistive memory component chosen from the group consisting of: a PCRAM component (from the English Phase-Change Random Access Memory), an OxRAM component (from the English hafnium-oxide RR AM, i.e. hafnium-oxide Resistive Random Access Memory), an MRAM component (from the English Magnetic Random Access Memory), and a CBRAM component (from the English Conductive Bridging Random Access Memory).

[0125] Those skilled in the art will note that the PCRAM component is also known by the following equivalent names: PCM component (from the English Phase Change Memory), PRAM component (from the English Phase-change Random Access Memory), OUM component (from the English Ovonic Unified Memory), and C-RAM or CRAM component (from the English Chalcogenide Random Access Memory).

[0126] Each primary switch 22 is also called a primary switch. Each primary switch 22 is for example produced in the form of a transistor 26.

[0127] The secondary switch 24 is similarly also called a secondary switch. The secondary switch 24 is for example produced in the form of the transistor 26.

[0128] Each switch 22, 24 comprises, as known per se, two conduction electrodes 27 and a control electrode 28.

[0129] The transistor 26 is typically a field effect transistor, also called FET (Field Effect Transistor). The field effect transistor is, for example, an insulated gate field effect transistor, also called MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Alternatively, the field effect transistor is a junction field effect transistor, also called JFET (Junction Field Effect Transistor); a field effect transistor with a metal gate, also called MESFET (MEtal Semiconductor Field Effect Transistor); a high electron mobility field effect transistor, also called MODFET (MOdulated-Doping Field Effect Transistor) or HEMT (High Electron Mobility Transistor); an organic field effect transistor, also called OFET (Organic Field Effect Transistor);a CNFET transistor (from the English Carbon Nanotube Field Effect Transistor); an EOSFET transistor (from the English Electrolyte Oxide Semiconductor Field Effect Transistor); a CMOS transistor (from the English Complementary Metal Oxide Semiconductor); an FDSOI transistor (from the English Fully Depleted Silicon On Insulator); a FinFET transistor (from the English Fin Field-Effect Transistor); or an ISFET transistor (from the English Ion Sensitive Field Effect Transistor).

[0130] When the transistor 26 is a field effect transistor, the conduction electrodes 27 are, as known per se, source electrodes S and drain electrodes D, the control electrode 28 being a gate electrode G.

[0131] In the example of [Fig. 1], the transistor 26 forming the primary switch 22 of a first sub-cell 25 directly connected to the first main terminal 12 is connected by its source electrode S to said first main terminal 12 and by its drain electrode D to the following sub-cell 25, in particular to the source electrode S of the transistor 26 forming the primary switch 22 of said following sub-cell 25. The transistor 26 forming the primary switch 22 of a respective sub-cell 25 of the series is connected by its source electrode S to the preceding sub-cell 25, in particular to the drain electrode D of the transistor 26 forming the primary switch 22 of said preceding sub-cell 25; and respectively by its drain electrode D to the following sub-cell 25, in particular to the source electrode S of the transistor 26 forming the primary switch 22 of said following sub-cell 25.The transistor 26 forming the primary switch 22 of the last sub-cell 25 directly connected to the second main terminal 14 is connected by its source electrode S to the previous sub-cell 25, in particular to the drain electrode D of the transistor 26 forming the primary switch 22 of said previous sub-cell 25; and respectively by its drain electrode D to the second main terminal 14. The transistor 26 forming the secondary switch 24 is connected by its source electrode S to the second main terminal 14 and by its drain electrode D to the auxiliary terminal 16.

[0132] Alternatively, transistor 26 is a bipolar transistor; or an insulated gate bipolar transistor, also called IGBT (from the English Insulated Gate Bipolar Transistor).

[0133] In [Fig.2], an electronic circuit 30 comprises value lines 32, programming lines 34, source lines 36; and a set 40 of memory cells 10, each memory cell 10 being as defined above.

[0134] For each memory cell 10, the control electrode 28 of each primary switch 22 is connected to a respective value line 32, the control electrode 28 of the secondary switch 24 is connected to a respective programming line 34, and the auxiliary terminal 16 is connected to a respective source line 36.

[0135] In addition, the electronic circuit 30 comprises a reference line 38 to which a reference potential VR is applied.

[0136] In addition, the electronic circuit 30 comprises a first controller 42 configured to control, that is to say drive or command, each of the value lines 32; a second controller 44 configured to control each of the programming lines 34; and a third controller 46 configured to control each of the source lines 36, as well as in addition the reference line 38.

[0137] In addition, the electronic circuit 30 comprises a measuring device 50 configured to carry out measurements representative of the electrical quantities of the memory cells 10 of the assembly 40, such as the voltages at the ends of the memristors 20 of said memory cells 10.

[0138] The set 40 of memory cells 10 is arranged to comprise one or more subsets of memory cells 10, where the memory cells 10 are connected in series with each other within each respective subset.

[0139] The set 40 of memory cells 10 is typically arranged in the form of a matrix comprising rows 52 and columns 54. According to this arrangement, each row 52 is preferably arranged horizontally, and each column 54 is preferably arranged vertically. The memory cells 10 of the same row 52 are for example connected to the same value line 32 and to the same source line 36, and the memory cells 10 of the same column 54 are for example connected to the same programming line 34.

[0140] When the assembly 40 is arranged in matrix form, the number of rows 52 is preferably substantially equal to the number of columns 54.

[0141] According to this arrangement, the memory cells 10 of the same column 54 are connected in series with each other, each column 54 comprising a first end 56 connected to the reference potential VR and a second end 58 connected to a respective measurement module 60. Each measurement module 60 is configured to measure a cumulative voltage of the memory cells 10 of the column 54 to which it is connected.

[0142] According to this arrangement, each second main terminal 14 of a given memory cell 10 of a respective column 54 is then connected to the first main terminal 12 of a following memory cell 10 of said column 54, the second main terminal 14 of a last memory cell of said column 54 being connected to a respective measurement module 60, and the first main terminal 12 of a first memory cell 10 of said column 54 being then connected to the reference line 38.

[0143] According to this arrangement, the measuring device 50 comprises the measuring modules 60. The measuring device 50 typically comprises a respective measuring module 60 for each of the columns 54.

[0144] Each measurement module 60 comprises, for example, a comparator 62 configured to detect the reaching, by the cumulative voltage of the memory cells 10 of the respective column 54, of a respective predefined threshold voltage Uth.

[0145] In addition, each measurement module 60 comprises a reset switch 64 and a capacitor 66. The capacitor 66 is configured, on the one hand, to be charged by the cumulative voltage of the memory cells 10 of the respective column 54 during a measurement phase, the reset switch 64 then being open; and on the other hand, to be discharged by being connected to an electrical ground 68 via the closing of the reset switch 64 during a reset phase.

[0146] In addition, the measuring device 50 comprises a measuring line 70 connected to each of the reset switches 64, in particular to their control electrode, to allow simultaneous control of the reset switches 64, and then simultaneous control of the different measuring modules 60.

[0147] The rows of value 32 are also denoted VLi>k with i an integer index varying from 1 to M where M represents the number of memristors 20 in each memory cell 10, which is equal to the number of primary switches 22 in each memory cell 10, M then also representing the number of primary switches 22 within each memory cell 10; and k an integer index varying from 1 to N, where N represents the number of rows 52. More precisely, the rows of value 32 are then denoted VLki, VL2,i, ..., VLMji for the first row 52 of index k equal to 1; then VLk2, VL2>2, • • - , VLM>2 for the second row 52 of index k equal to 2; up to VLkN, VL2N, ..., VLMN for the last row 52 of index k equal to N.

[0148] The set 40 typically comprises between 32 and 2,000 sub-cells 25, and preferably from a few hundred to approximately 1,000 sub-cells 25.

[0149] The number M of sub-cells 25 per memory cell 10 is typically between a few units and a few tens.

[0150] The programming lines 34 are also denoted PLj, j being an integer index varying from 1 to P, where P represents the number of columns 54. The programming lines 34 are then denoted PLi, PL2, ..., PLP.

[0151] The source lines 36 are also denoted SLk, with k the integer index varying from 1 to N, where N represents the number of rows 52. The source lines 36 are then denoted SLb SL2, ..., SLN.

[0152] In addition, the electronic circuit 30 comprises an additional source line 36, denoted SL0, making it possible to apply a predefined potential to the first main terminals 12 of the memory cells 10 of the first row of the assembly 40 during their programming.

[0153] According to this addition, the electronic circuit 30 further comprises a head switch 71 for each column 54, each respective head switch 71 being connected between the first main terminal 12 of the respective memory cell 10 of the first row and the additional source line 36 SL0. According to this addition, the conduction electrodes 27 of the head switch 71 are then connected to the respective first main terminal 12 on the one hand and to the additional source line SLo on the other hand, and the control electrode 28 of the head switch 71 is connected to a respective programming line 34. In the example of [Fig. 2], each head switch 71 is implemented in the form of the transistor 26, the latter preferably being a field effect transistor, and is connected by its drain electrode D to the additional source line SL0, by its source electrode S to the respective first main terminal 12, and by its gate electrode G to the respective programming line 34.

[0154] The reference line 38 is configured to charge the capacitor 66 of each measurement module 60 during the measurement phase, by applying the reference potential VR through the measurement cells 10 of a respective column 54 to the capacitor 66.

[0155] The first controller 42 is configured to control each of the value lines 32 connected to the control electrodes 28 of the primary switches 22 of the set 40 of memory cells, as a function of the operation carried out on the memory cells 10, in particular among a programming operation, that is to say a writing operation, when the programming method according to the invention is implemented; and respectively an inference operation when the multiplication and accumulation method according to the invention is implemented; as will be described in more detail hereinafter with reference to [Fig.8], and respectively to [Fig.9]; as well as a reading operation when the reading method according to the invention is implemented.

[0156] The first controller 42 is for example configured to control the primary switches 22 of a respective row 52, ​​during the programming of memory cell(s) 10 of said row 52, ​​in particular the opening of the primary switches 22 connected to a respective value line 32 associated with said row and the closing of any other primary switches 22 of the memory cells 10 of said row 52, ​​these possible other primary switches 22 then being connected to other value lines 32 than that to which an opening signal is applied.

[0157] The first controller 42 is for example configured to control an alternation of opening(s) and closing(s) of primary switches 22 of a respective column 54, during the implementation of an inference operation with a batch of memory cell(s) 10 of said column 54.

[0158] When the multiplication and accumulation method according to the invention is implemented, the first controller 42 is typically configured to control each primary switch 22 of said batch of memory cell(s) with the alternation of opening(s) and closing(s) during an inference cycle, by applying the alternating opening(s) and closing(s) commands on each value line 32 connected to each primary switch 22 of said batch, to multiply the value of each memristor 20 of said batch by a respective multiple. The ratio p between the cumulative opening duration of the respective primary switch 22 during the inference cycle and the duration of said cycle represents the respective multiple.

[0159] The respective multiple for each row of value 32 is denoted Xi>k, with i the integer index varying from 1 to M and k the integer index varying from 1 to N, where M represents the number of primary switches 22 per memory cell 10 and N represents the number of rows 52. The respective multiple Xi>k is equal to said ratio p, as will be described in more detail later with reference to [Fig.9] and the associated flowchart of the multiplication and accumulation method according to the invention. In a manner analogous to what was described previously for the rows of value 32, the multiples are then denoted Xi,b X 2,1, ..., XM,i for the first row 52 of index k equal to 1; then X1>2, X2>2, • • - , XM>2 for the second row 52 of index k equal to 2; up to X1>N, X2>N, ..., XM>N for the last row 52 of index k equal to N.

[0160] The second controller 44 is configured to control each of the programming lines 34 connected to the control electrodes 28 of the secondary switches 24 of the set 40 of memory cells, and in addition to the head switches 71, as a function of the operation carried out on the memory cells 10, in particular among the aforementioned programming operation, the inference operation and the reading operation.

[0161] The second controller 44 is for example configured to control the closing of the secondary switch 24 of each memory cell 10 to be programmed, during the programming of memory cell(s) 10 of a respective row 52.

[0162] The second controller 44 is for example configured to control the opening of the secondary switches 24 of the memory cells 10 of a respective column 54, during the implementation of the inference operation with the batch of memory cell(s) 10 of said column 54. The second controller 44 is preferably configured to control the opening of all the secondary switches 24 of the set 40 of memory cells during said inference operation.

[0163] The third controller 46 is configured to control each of the source lines 36 connected to the respective conduction electrodes 27 of the secondary switches 24 of the set 40 of memory cells, depending on the operation performed on the memory cells 10, in particular among the aforementioned programming operation, the inference operation and the reading operation.

[0164] During the programming operation, to assign a respective value to each of the memristors 20 of each memory cell 10 to be programmed, the third controller 46 is for example configured to impose a programming voltage corresponding to said value between the first main terminal 12 and the auxiliary terminal 16 of each memory cell 10 to be programmed, by applying a first electrical potential V1 to the source line(s) 36 arranged on the side of said first main terminal 12 and a second electrical potential V2 to the other source line(s) 36, arranged on the side of said auxiliary terminal 16. The pro voltage programming corresponding to the assigned value is equal to the difference between the first VI and second V2 potentials. During this programming operation, the primary switch 22 connected in parallel of the memristor 20 - to which the respective value is assigned - is furthermore opened, while the other primary switch(es) 22 of the respective memory cell 10 are closed, this by the first controller 42.

[0165] The third controller 46 comprises for example multiplexers 72 and a selection bus 74 connected to the multiplexers 72, each source line 36 being connected to a respective multiplexer 72. According to this example, each multiplexer 72 is then configured to select, as a function of a respective selection signal applied to the selection bus 74 and from among several predefined values ​​VH, VL, an electrical potential value to be applied to the associated source line 36. The predefined values ​​VH, VL typically correspond to the possible values ​​of the aforementioned first VI and second V2 potentials, the difference of which is equal to the programming voltage to be imposed between the first main terminal 12 and the auxiliary terminal 16 of the memory cell 10 to assign the respective desired value to each of the memristors 20 of this memory cell 10 to be programmed.

[0166] During the inference operation, or during the reading operation, the third controller 46 is for example configured to apply a default potential to the different source lines 36, the secondary switches 24 being open during the inference operation, or during the reading operation, and these source lines 36 then not being used.

[0167] In addition, the third controller 46 is configured to apply the reference potential VR to the reference line 38.

[0168] In the example of [Fig. 2], the first controller 42, the second controller 44 and the third controller 46 are produced in the form of controllers distinct from each other. Alternatively, at least two of the three aforementioned controllers 42, 44, 46, or even the three controllers 42, 44, 46 are grouped into a single controller then configured to control several types of lines, or even all types of lines, among the value lines 32, the programming lines 34 and the source lines 36, as well as in addition the reference line 38.

[0169] [Fig.3] illustrates an alternative embodiment of the electronic circuit 30 of [Fig.2], for which the elements common to the electronic circuit 30 of [Fig.2] are identified by identical references, and are not described again.

[0170] According to this variant embodiment, the electronic circuit 30 further comprises auxiliary switches 80, each source line 36 being connected to a respective auxiliary switch 80.

[0171] Each auxiliary switch 80 is configured to, upon receipt of a limitation command, limiting an electric current flowing in the associated source line 36. This limitation of the electric current in the corresponding source line 36 is typically implemented during a programming operation, in order to limit the current in the at least one memory cell 10 to be programmed, and in particular in the associated memristor(s) 20.

[0172] Each auxiliary switch 80 is also called an auxiliary switch. Each auxiliary switch 80 is for example produced in the form of the transistor 26, the transistor 26 preferably then being a field effect transistor. The limitation command is then typically a predefined limitation potential VCOMPL applied to the control electrode 28 of said auxiliary switch 80.

[0173] As known per se, the current flowing through the field effect transistor between the conduction electrodes 27 is - in saturation mode of the field effect transistor, in particular of the MOSFET transistor - limited to a maximum value depending on a voltage VGS between the source electrode S and the gate electrode G, and the lower the voltage VGS, the lower said maximum current value is also.

[0174] According to this variant embodiment, the person skilled in the art will then understand that the limitation of the current flowing through the corresponding source line 36 is obtained by applying to the control electrode 28 of the auxiliary switch 80 the predefined limitation potential VCOMPL, of a value lower than that of a default potential VDD, the default potential VDD corresponding to an absence of current limitation.

[0175] Each auxiliary switch 80 is typically connected between one end of the respective source line 36 and a respective multiplexer 72. In other words, each auxiliary switch 80 is arranged between the set 40 of memory cells and a respective multiplexer 72. Each auxiliary switch 80 is preferably included in the third controller 46.

[0176] According to this variant embodiment, and as an optional addition, the electronic circuit 30 further comprises auxiliary multiplexers 82 and an auxiliary selection bus 84 connected to the auxiliary multiplexers 82. The control electrode 28 of each auxiliary switch 80 is then connected to a respective auxiliary multiplexer 82, each auxiliary multiplexer 82 being configured to select - as a function of a limitation signal and from among several predefined values, such as the value of the predefined limitation potential VCOMPL and that of the default potential VDD - an electrical potential value to be applied to the associated control electrode 28.

[0177] Figures 4 to 6 illustrate the particular case of the first embodiment where the number M of memristor(s) 20 per memory cell 10 is equal to 1, for which the elements similar to those of the general case described previously (where the number M is greater than or equal to 1, and in particular strictly greater than 1) are identified by re- identical references, and are not described again.

[0178] In the example of [Fig.4], the memory cell 10 comprises the memristor 20 connected between the two main terminals 12, 14; the primary switch 22 connected between the two main terminals 12, 14, in parallel with the memristor 20; and the secondary switch 24 connected between the second main terminal 14 and the auxiliary terminal 16.

[0179] In this example, the memory cell 10 then comprises a single memristor 20. The memory cell 10 comprises exactly two switches 22, 24. In other words, the memory cell 10 comprises a single sub-cell 25.

[0180] In the example of [Fig.4], the memory cell 10 is then made up of the first and second main terminals 12, 14, the auxiliary terminal 16, the memristor 20, and the primary and secondary switches 22, 24.

[0181] In this example, the memory cell 10 is therefore a 2T1R type memory cell, with reference to the presence of two switches (designated 2T) and a single memristor (designated IR).

[0182] Those skilled in the art will then observe that the memory cell 10 of the example in [Fig.4] has one less memristor than the 2T2R type memory cell of the prior art.

[0183] In the example of [Fig.4], the transistor 26 forming the primary switch 22 is then connected by its source electrode S to the first main terminal 12 and by its drain electrode D to the second main terminal 14. The transistor 26 forming the secondary switch 24 is connected by its source electrode S to the second main terminal 14 and by its drain electrode D to the auxiliary terminal 16.

[0184] In the example of [Fig.5], the electronic circuit 30 is analogous to that of [Fig.2] then having the number M equal to 1, and also includes the value lines 32, the programming lines 34, the source lines 36 and the set 40 of memory cells 10, each memory cell 10 being as shown in [Fig.4].

[0185] In this example of [Fig.5], the number M being equal to 1, the index i is not necessary. The rows of value 32 are also noted VLk with k the integer index varying from 1 to N, where N represents the number of rows 52. More precisely, the rows of value 32 are then noted VLi, VL2, ..., VLN.

[0186] In the example of [Fig.5], the set 40 typically comprises between 32 and 2,000 memory cells 10, and preferably from a few hundred to approximately 1,000 memory cells 10.

[0187] The programming lines 34 are also denoted PLj, with j the integer index varying from 1 to P, where P represents the number of columns 54. The programming lines 34 are then denoted PLb PL2, ..., PLP.

[0188] Source lines 36 are also denoted SLk, with k the integer index varying from 1 to N, where N represents the number of rows 52. The source lines 36 are then noted SLb SL2, SLN.

[0189] In addition, the electronic circuit 30 comprises the additional source line 36, denoted SL0, making it possible to apply the predefined potential to the first main terminals 12 of the memory cells 10 of the first row of the assembly 40 during their programming.

[0190] In the example of [Fig.5], in addition, the electronic circuit 30 comprises the reference line 38 to which the reference potential VR is applied.

[0191] In addition, the electronic circuit 30 comprises the first controller 42, the second controller 44 and the third controller 46. In addition, the electronic circuit 30 comprises the measuring device 50.

[0192] The respective multiple for each row of value 32 is also denoted Xk, with k the integer index varying from 1 to N. In a manner analogous to what was described above for the rows of value 32, the multiples are then denoted Xb X2, ..., XN.

[0193] [Fig.6] illustrates an alternative embodiment of the electronic circuit 30 of [Fig.5], for which the elements common to the electronic circuit 30 of [Fig.5] are identified by identical references, and are not described again.

[0194] This variant embodiment is similar to the variant of the electronic circuit 30 of [Fig.3] compared to that of [Fig.2]. According to this variant embodiment, the electronic circuit 30 then further comprises the auxiliary switches 80, each source line 36 being connected to a respective auxiliary switch 80.

[0195] According to this variant embodiment, and as an optional addition, the electronic circuit 30 further comprises the auxiliary multiplexers 82 and the auxiliary selection bus 84 connected to the auxiliary multiplexers 82.

[0196] The operation of the memory cell 10 according to the invention, as well as of the electronic circuit 30, will now be described with reference to [Fig. 8] representing a flowchart of the method, according to the invention, of programming at least one memory cell 10 of a respective row 52 of memory cells 10 of the electronic circuit 30; then with reference to [Fig. 9] representing a flowchart of the method, according to the invention, of multiplying and accumulating a batch of memory cell(s) 10 of a respective column 54 of memory cells 10 of the electronic circuit 30.

[0197] In [Fig.8], the programming method comprises, during an initial step 100, the opening of the primary switches 22 of the memory cells 10 of the row 52 which is the subject of this programming, via the application of an opening command on a respective value line 32 connected to said row 52.

[0198] During this opening step 100, the first controller 42 then commands the opening of the primary switches 22 connected by their control electrode 28 to this respective value line 32 of said row 52.

[0199] Those skilled in the art will then understand that the respective value line 32, on which the opening signal is applied, is that associated with the memristor 20 which is to be programmed among the memristor(s) 20 of each memory cell 10 of said row 52. Indeed, for the programming of a respective memristor 20, the primary switch 22 connected in parallel with it must be open, so that said memristor 20 is not short-circuited and so that it can have a potential difference at its ends.

[0200] The method then comprises, during a following step 105, the closing of any other primary switches 22 of the memory cells 10 of said row 52, ​​via the application of a closing command on the other possible value line(s) 32 connected to said row 52.

[0201] As explained previously, the case of these possible other primary switches 22 to be closed depends on the value of the number M.

[0202] When the number M is strictly greater than 1, the writing of a given value in a respective memristor 20 is obtained in particular via the opening 100 of the primary switch 22 in parallel with said memristor 20, and the closing 105 of the M-1 other primary switch(es) 22, which then corresponds to the case where any other primary switch(es) 22 are to be closed.

[0203] Alternatively, when the number M is equal to 1, the writing of a given value in the memristor 20 of the memory cell 10 is obtained in particular via the opening 100 of the primary switch 22 which is arranged in parallel with said memristor 20, and there is then no other possible primary switch 22 to close in this case. In other words, those skilled in the art will understand that when the number M is equal to 1, the closing step 105 is not carried out, no other possible primary switch 22 being to be closed.

[0204] The programming method then comprises, during step 110, the closing of the at least one secondary switch 24 of said at least one memory cell 10, via the application of a closing command on the at least one programming line 34 connected to said at least one memory cell 10 of said row 52.

[0205] During this closing step 110, the second controller 44 then commands the closing of the secondary switch 24 of each memory cell 10 to be programmed within said row 52.

[0206] At the end of the opening 100 of the primary switches 22, the closing 105 of the possible other primary switch(es) 22, and the closing 110 of the at least one secondary switch 24, the method comprises, during the following step 120, the assignment of a value to the at least one memristor 20 of said at least one memory cell 10, with a programming voltage corresponding to the value between the at least one first main terminal 12 and the at least one auxiliary terminal 16 of said at least one memory cell 10.

[0207] During this assignment step 120, the third controller 46 then applies the first electrical potential VI to the source line(s) 36 arranged on the side of the at least one first main terminal 12, and respectively the second electrical potential V2 to the other source line(s) 36, arranged on the side of the at least one auxiliary terminal 16, the programming voltage corresponding to the assigned value being equal to the difference between the first potential VI and second potential V2.

[0208] Those skilled in the art will then understand that to assign the low state LRS to the memristor(s) 20 which are programmed, this assignment of the low state LRS corresponding to the SET operation, the third controller 46 selects a higher value, such as the value VH, for the first potential than that selected for the second potential, such as the value VL, with VH greater than VL by convention, the voltage applied to the memristor(s) 20 then being equal to VH-VL.

[0209] Conversely, to assign the high state HRS to the memristor(s) 20 which are programmed, this assignment of the high state HRS corresponding to the RESET operation, the third controller 46 selects a lower value, such as the value VL, for the first potential than that selected for the second potential, such as the value VH, with VH > VL, the voltage applied to the memristor(s) 20 then being equal to VL-VH.

[0210] For the programming of each memristor 20, the programming voltage is typically equal to approximately 2 volts, and the value VH is for example equal to approximately 2 volts, while the value VL is substantially zero.

[0211] For reading each memristor 20, the reading voltage is lower and typically between approximately 0.1 and 0.4 volts, and the value VH is for example between approximately 0.1 and 0.4 volts, while the value VL is substantially zero.

[0212] By convention again, a lower resistance of the memristor 20 corresponding to its low state LRS is associated with a lower value than that associated with a higher resistance of the memristor 20 corresponding to its high state HRS. For example, the low state LRS of the memristor 20 corresponds to a low weight, i.e. a logic “0”; and the high state HRS of the memristor 20 corresponds to a high weight, i.e. a logic “1”.

[0213] In addition, several distinct levels of the low state LRS and / or the high state HRS are used, in order to have more than two possible programming values ​​for the memristor 20. The plurality of distinct levels is preferably associated with the low state LRS, the latter being more easily controllable than the high state HRS.

[0214] Those skilled in the art will then understand that to assign, via the SET operation, the low state LRS to one of the memristors 20 of the memory cell 10 framed in dotted lines of row 52 with index equal to 1 in the example of [Fig.2] or to memristor 20 of memory cell 10 framed in dotted line in the example of [Fig.5], the first potential with value equal to VH is applied to the additional source line SL0, while the second potential with value equal to VL is applied to the source lines SLi, SL2, SLN. Conversely, in this example of [Fig.2] or [Fig.5], to assign, via the RESET operation, the high state HRS to the aforementioned memristor 20, the value of the first potential applied to the additional source line SL0 is equal to VL, while the value of the second potential applied to the source lines SLi, SL2, ..., SLn is equal to VH.

[0215] As described above, this positioning of the potential of each of the source lines 36 to one or the other value is typically carried out by controlling the multiplexers 72 in a corresponding manner via the positioning of a respective message on the selection bus 74. As an example, assuming that a bit of value 1 controls the selection of the value VH by the multiplexer 72, and respectively that a bit of value 0 controls the selection of the value VL by said multiplexer 72, and furthermore that - for the message applied on the selection bus 74 - the first bit of the message is associated with the first multiplexer, by convention that associated with the additional source line SL0, and respectively the last bit of the message is associated with the last multiplexer, by convention that associated with the source line SLN, then the low state LRS is assigned, via the SET operation, to the aforementioned memristor 20 in [Fig.2] or 5 by positioning the message (1000) on the selection bus 74; and conversely the high state HRS is assigned, via the RESET operation, to this memristor 20 by positioning the message (0111) on said selection bus 74.

[0216] As an optional addition, when the electronic circuit 30 further comprises the auxiliary switches 80, the third controller 46 further controls, during this assignment step 120, the closing of the auxiliary switches 80 connected to the source lines 36 to which one of the first V1 and second V2 potentials is applied. The auxiliary switch 80 associated with the row 52 being programmed, i.e. the auxiliary switch 80 connected to the source line 36 which is itself connected to the at least one auxiliary terminal 16 of said row 52, ​​is preferably further controlled with the predefined limitation potential VCOMPL applied to its control electrode 28, in order to limit the current flowing through each memristor 20 during its programming.

[0217] Alternatively, when the electronic circuit 30 does not include the auxiliary switches 80, the secondary switch 24 of each memory cell 10 to be programmed is preferably further controlled with the predefined limitation potential VCOMPL applied to its control electrode 28, in order to limit the current flowing through each memristor 20 during its programming. According to this alternatively, the second controller 44 then commands, during the closing step 110, the closing of the secondary switch 24 of each memory cell 10 to be programmed, with the predefined limitation potential VCOMPL.

[0218] In [Fig.9], the multiplication and accumulation method comprises, during an initial step 200, the opening of the secondary switches 24 of the memory cells 10 of the column 54 which are the subject of this multiplication and accumulation, via the application of an opening command on the programming line 34 connected to said column 54.

[0219] During this opening step 200, the second controller 44 then commands the opening of the secondary switches 24 of the memory cells 10 of said column 54.

[0220] During this opening step 200, the second controller 44 preferably still controls the opening of all the secondary switches 24 of the electronic circuit 30. Those skilled in the art will understand that the source lines 36 are used for programming the memory cells 10, or for reading these memory cells 10 independently of each other, and are not used during the inference of the memory cells 10, and in particular during multiplication and accumulation. The opening of all the secondary switches 24 then makes it possible to isolate the set 40 of memory cells 10 with respect to these source lines 36 when reading the memory cells 10.

[0221] If the batch of memory cell(s) 10 which is the subject of this multiplication and accumulation does not include all the memory cells 10 of the corresponding column 54, the multiplication and accumulation method then further comprises, during a step 210, the closing of each primary switch 22 of each memory cell 10 distinct from said batch within the column 54, via the application of a closing command on each value line 32 connected to each memory cell 10 distinct from said batch. In other words, during this closing step 210, each primary switch 22 of each memory cell 10 which is not included in said batch, while being located within said column 54, is closed.

[0222] During this closing step 210, the first controller 42 then commands the closing of each primary switch 22 for each memory cell 10 of said column 54 and which is not included in the batch of memory cell(s) 10 which is the subject of the multiplication and accumulation.

[0223] At the end of the opening of the secondary switches 24 and the closing of each primary switch 22 of each memory cell 10 which is not included in said batch which is the subject of the multiplication and accumulation, the method comprises, during the following step 220, the control of each primary switch 22 of said batch of memory cell(s) 10 with an alternation of opening(s) and closing(s) at during an inference cycle, via the application of alternating opening and closing commands on each value line 32 connected to each primary switch 22 of said batch.

[0224] During this control step 220, the first controller 42 then controls each primary switch 22 of each memory cell 10 of said batch with a control signal 90, 92, 94 comprising an alternation between a lower potential Vinf corresponding to the opening of the primary switch 22 and a higher potential Vsup corresponding to the closing of the primary switch 22, as shown in the example of [Fig.7].

[0225] The duration of an opening stage at the lower potential Vinf is noted tl, and the duration of a closing stage at the higher potential Vsup is noted th. The duration of an alternation of opening and closing of the primary switch 22 is then equal to th+tl, as shown in [Fig.7].

[0226] During this control step 220, this alternation of opening(s) and closing(s) of the primary switch 22 then makes it possible to multiply the value of each memristor 20 of said batch by a respective multiple Xijk, where said respective multiple Xijk is a function of the ratio p (denoted p; for the row 52 of index i) between the cumulative duration of opening of the respective primary switch 22 during the inference cycle and the duration of said cycle. The respective ratio p; is associated with the multiple Xijk, both being for the row 52 of index i.

[0227] This multiplication by the respective multiple Xi>k is all the more precise since the transistor 26 forming the primary switch 22 can be likened to a perfect switch. The primary switch 22 is for example considered to be a perfect switch if its resistance in the closed state, denoted Rf, is much lower, typically at least five times lower, and preferably at least ten times lower, than the resistance of the memristor 20, denoted Rm; and if its resistance in the open state, denoted Ro, is much higher, typically at least five times higher, and preferably at least ten times higher, than said resistance Rm of the memristor 20.Furthermore, the transition time, noted Tr, between the open state and the closed state of said primary switch 22 is preferably much lower, typically at least five times lower, and preferably at least ten times lower, than the duration tl of the opening stage at the lower potential Vinf, and also than the duration th of the closing stage at the higher potential Vsup. The primary switch 22 is then typically perfect if it satisfies the following conditions: Rf « Rm, Ro » Rm, Tr « th and Tr « tl.

[0228] When the primary switch 22 is comparable to such a perfect switch, the equivalent resistance R(t) of the sub-cell 25 of the corresponding memory cell 10 typically verifies the following equation:

[0229] [Math.l] R(t) - (lx(t) )jRm

[0230] where R(t) represents the value of the equivalent resistance of the respective sub-cell 25, variable over time t;

[0231] x(t) represents a binary signal for controlling the primary switch 22 of the sub-cell 25, where the upper potential Vsup then corresponds to the value 1, and the lower potential Vinf corresponds to the value 0; and

[0232] Rm represents the value of the resistance of the memristor 20.

[0233] This multiplication by the respective multiple Xi>k is also all the more precise since the duration th+tl of an alternation of opening and closing of the primary switch 22 is much lower, typically at least five times lower, and preferably at least ten times lower, than a duration r of charging of the capacitor 66 of the measuring module 60 for said column 54.

[0234] The duration r of charging of the capacitor 66 then typically verifies the following equation:

[0235] [Math.2] r= (Rs + pJim\C

[0236] where r represents the charging time of the capacitor 66;

[0237] Rs represents the series resistance of the other sub-cells 25 of column 54 connected in series with the respective sub-cell 25 for which the control signal is applied to the primary switch 22;

[0238] p represents the ratio between the cumulative duration of opening of the respective primary switch 22 during the inference cycle and the duration of said cycle;

[0239] Rm represents the value of the resistance of the memristor 20 of the respective sub-cell 25; and

[0240] C represents the capacitance of capacitor 66.

[0241] This multiplication by the respective multiple Xi>k is also all the more precise since the equivalent resistance R(t) of the corresponding memory cell 10 is much lower, typically at least five times lower, and preferably at least ten times lower, than the series resistance Rs of the other sub-cells 25 of the column 54 connected in series with the respective sub-cell 25 which is the subject of the inference operation.

[0242] To increase the series resistance Rs of the other sub-cells 25 of the column 54 with respect to the equivalent resistance R(t) of a respective sub-cell 25, the first controller 42 typically controls the openings and closings of the primary switches 22 of the column 54 with opening and closing time instants, respectively, varying from one row of value 32 to the other. In other words, the time instant of the start of the opening step at the lower potential Vinf is preferably distinct from one line of value 32 to the other; and similarly the time instant of the start of the closing step at the higher potential Vsup is also distinct from one line of value 32 to the other.

[0243] As a variant, this shift between the opening and closing time instants, respectively, between the sub-cells 25 of the column 54 is carried out by sub-batches of sub-cell(s) 25 within said column 54. According to this variant, the sub-cells 25 of the column 54 are for example distributed into B distinct sub-batches, with B being an integer greater than or equal to 2. The opening time instants of the primary switch(es) 22 are then identical for the sub-cell(s) 25 of the same sub-batch, and distinct from one sub-batch to another. Similarly, the closing time instants of the primary switch(es) 22 are identical for the sub-cell(s) 25 of the same sub-batch, and distinct from one sub-batch to another.

[0244] The control signal 90, 92, 94 is preferably periodic, and when it comprises several alternations of opening and closing of the primary switch 22, then the duration of each opening and closing alternation remains equal to th+tl.

[0245] The ratio p between the cumulative opening time of the respective primary switch 22 during the inference cycle and the duration of said cycle then typically satisfies the following equation:

[0246] [Math.3] n- tl P~

[0247] where p represents said ratio;

[0248] tl represents the duration of the opening stage of the primary switch 22, th representing the duration of the closing stage of said primary switch 22;

[0249] th+tl then representing the duration of a respective alternation of opening and closing of the primary switch 22.

[0250] In [Fig.7], different examples of signals 90, 92, 94 for controlling the primary switch 22 with this alternation of opening(s) and closing(s) are then represented.

[0251] A first control signal 90 comprises several alternations of opening and closing of the primary switch 22 during the cycle, with in addition the lower potential Vinf of substantially zero value.

[0252] Alternatively, a second control signal 92 also comprises several alternations of opening and closing of the primary switch 22, with the lower potential Vinf of strictly positive value according to this alternative. The fact of having the lower potential Vinf of strictly positive value, and therefore non-zero, then allows a resulting resistance Rcom of the primary switch 22 which is not zero in open position of said primary switch 22.

[0253] According to this variant, the equivalent resistance R(t) of the corresponding sub-cell 25 typically verifies the following equation:

[0254] [Math.4] *« = (M)

[0255] where R(t) represents the value of the equivalent resistance of the respective sub-cell, variable over time t;

[0256] x(t) represents the binary signal for controlling the primary switch 22 of the sub-cell 25, where the closing of the primary switch 22 corresponds to the value 1 and its opening corresponds to the value 0;

[0257] Rm represents the value of the resistance of the memristor 20;

[0258] Rcom represents the resulting resistance of the primary switch 22 in position opening, by the opening command at a strictly positive potential.

[0259] The high state HRS is likely to vary significantly from one memristor 20 to another, with values ​​of this high state HRS varying for example between approximately 40 kΩ and 200 kΩ, which may prove troublesome, given that the equivalent resistance R(t) is representative of the respective multiple, such as a synaptic weight when the electronic circuit 30 is used for the inference of an artificial neural network.

[0260] This variant with the lower potential Vinf of strictly positive value then makes it possible to limit this dispersion of resistive values, the value of the equivalent resistance R(t) then being essentially a function of the resulting resistance Rcom when the value of the resistance Rm of the memristor 20 is significantly higher than that of the resulting resistance Rcom, according to equation (4). If the resulting resistance Rcom is for example chosen to be equal to approximately 50 kΩ, then the distribution of values ​​for the maximum of the equivalent resistance R(t) will be between approximately 25 kΩ and 50 kΩ.

[0261]

[0262]

[0263] This variant with the lower potential Vinf of strictly positive value also allows better calculation efficiency, and in particular to authorize a greater number of sub-cells 25 connected in series in each column 54, given that the equivalent resistance R(t) of the sub-cell 25 according to this variant, for example according to equation (4), is lower than the equivalent resistance R(t) of the sub-cell 25 obtained in the case of the lower potential Vinf of substantially zero value, for example according to equation (1). Indeed, the person skilled in the art will observe the following inequality relation: [Math.5] Rm.Rctm Rm+Rcom < Rm

[0264] by the following inequality:

[0265] [Math.6] Rcom < i Rm+Rcom

[0266] Rcom and Rm being strictly positive values.

[0267] As a further variant, a third control signal 94 comprises a single alternation of opening and closing of the primary switch 22, with the lower potential Vinf of strictly positive value. The duration tmax of the inference cycle according to this variant is then equal to the duration th+tl of said alternation of opening and closing, that is to say to the sum of the duration tl of the opening stage and the duration th of the closing stage of the primary switch 22.

[0268] This variant with a single alternation of opening and closing of the primary switch 22 then requires that the duration tmax be much less than the duration r of charging of the capacitor 66 of the measurement module 60 for said column 54, which implies that a voltage threshold Vth, to be reached by the cumulative voltage of the sub-cells 25 of the column 54 to obtain - during the following step 230 - a weighted sum of values ​​of memristors 20 of said batch, be much lower, typically at least five times lower, and preferably at least ten times lower, than the reference potential VR allowing the capacitor 66 to be charged.

[0269] This variant with a single alternation of opening and closing of the primary switch 22 then also allows better calculation efficiency, since the weighted sum is then calculated more quickly, in a single alternation of opening and closing of the primary switch 22.

[0270] Those skilled in the art will then understand that among the first 90, second 92 and third 94 control signals, the third control signal 94 allows for the greatest calculation efficiency, given that it offers the two aforementioned advantages.

[0271] The multiplication and accumulation method then comprises, during step 230, obtaining the weighted sum of values ​​of memristors 20 of said batch via a measurement of the cumulative voltage of the memory cells 10 of said column 54, each value of memristor 20 being multiplied by the respective multiple Xi>k.

[0272] During this obtaining step 230, the measuring device 50 then measures this cumulative voltage for said column 54 via the respective measuring module 60 associated with said column 54, and then typically obtains the weighted sum via the sum of the equivalent resistances of the memory cells 10 of said column 54 during the inference cycle.

[0273] The measurement module 60 calculates for example this weighted sum from the previous equation (2), and after having determined the duration r of charging of the capacitor 66 associated with said column 54. To determine this duration r of charging of the capacitor 66, the measurement module 60 carries out for example a reset of the charge of the capacitor 66 by controlling the closing of the reset switch 64 at the start of the control step 220, then detects the reaching of the voltage threshold Vth corresponding to the charge of the capacitor 66 via the comparator 62, the comparator 62 receiving on the one hand the voltage gradually accumulated in the column 54 by having an input connected to the second end 58 of said column 54, and receiving on the other hand said voltage threshold Vth by having its other input connected to a potential equal to this voltage threshold Vth. When the voltage threshold Vth is reached, the measurement module 60 then determines this duration r of charge of the capacitor 66, by counting the number of cycles of an internal clock of the comparator 62 which have elapsed between the instant of resetting of the capacitor 66 at the start of the control step 220 and the detection of the reaching of said voltage threshold Vth.

[0274] As an optional addition, those skilled in the art will further observe that the measuring device 50 is further configured to obtain the weighted sums for several columns 54 at a time, and preferably for all the columns 54 at a time of the electronic circuit 30.

[0275] According to this supplement, the simultaneous obtaining of the weighted sums for several columns 54 is carried out using the following equation:

[0276] [Math.7]

[0277] where 1 is an integer index associated with the rows of value 32, i.e. the sub-cells 25 of each respective column 54, and varying from 1 to MxN, where M represents the number of sub-cells 25 per memory cell 10 and N represents the number of rows 52 of the set 40 of memory cells 10,

[0278] j is the integer index associated with columns 54 and varying from 1 to P, where P represents the number of columns 54 of said set 40,

[0279] Tj represents the charging time of the capacitor 66 associated with the column of index j,

[0280] C represents the capacitance of capacitor 66, this being identical from one column 54 to the other in the example of equation (7),

[0281] Rj i represents the resistance value of the memristor 20 of the sub-cell 25 belonging to the column of index j and associated with the row of index value 1, and

[0282] Xi represents the multiplicative value applied to the line of value 32 of index 1;

[0283] with in addition by convention:

[0284] [Math. 8]

[0285] where Xi represents the multiplicative value applied to the line of value 32 of index 1,

[0286] tl represents the duration of the opening stage of the primary switch 22 associated with the line of index value 1, and

[0287] th+tl represents the duration of a respective alternation of opening and closing of the primary switch 22 associated with the line of index value 1;

[0288] pi alternatively representing the respective ratio for the index value line 1.

[0289] Those skilled in the art will observe that the index 1 representative of a respective line of value 32 corresponds to the pair (i,k) of indices i and k, defined previously, and that the index 1 is used preferentially to the pair (i,k) in the preceding equations (7) and (8), in order to avoid having notations with too many indices, in particular for the value of the resistance of the memristor 20.

[0290] Those skilled in the art will then understand that the memory cell 10 according to the invention allows the writing, then the reading and / or the inference, of any value, in the form of the value of the electrical resistance of the memristor 20 included in each sub-cell 25 of the memory cell 10, and not only of a binary value unlike the memory cell of the state of the art.

[0291] Furthermore, each sub-cell 25 allows the multiplication of a value of the memristor 20 by a respective multiple Xi>k, via the alternation of opening(s) and closing(s) of the primary switch 22 during an inference cycle, as explained above.

[0292] Those skilled in the art will further observe that the respective multiple Xi>k is capable of taking any value, and is also not limited to a binary value. In the example of equation (8) above, the respective multiple Xijk is a real number between 0 and 1.

[0293] Those skilled in the art will also note that the electronic circuit 30 according to the invention further allows the implementation of the MAC multiplication and accumulation operation in a particularly efficient manner, in particular with the various gains in calculation efficiency described previously.

[0294] The electronic circuit 30 according to the invention further offers a possible implementation of the MAC operation for several columns 54 at a time, for example via the implementation implementation of the previous equation (7). When inferring an artificial neural network, this then makes it possible to chain together the calculations of weighted sums for several successive layers of the neural network, without waiting, for example, for the end of the MAC operation for a previous layer of the network.

[0295] Each sub-cell 25 also has a reduced size compared to the memory cell of the prior art, each sub-cell 25 comprising one memristor and one switch less than the 2T2R type memory cell of the prior art, the sub-cell 25 according to the first embodiment of the invention being of the 1T1R type.

[0296] Figures 10 to 13 illustrate a second embodiment for which the elements similar to those of the first embodiment described previously are identified by identical references and are not described again.

[0297] According to the second embodiment, the memory cell 10 further comprises M tertiary switch(es) 300, each being connected to a respective memristor 20, the tertiary switch 300 and the memristor 20 being connected in series, in parallel with the associated primary switch 22.

[0298] In the example of [Fig. 10], the memory cell 10 comprises exactly M memristor(s) 20.

[0299] In the example of [Fig. 10], the memory cell 10 comprises exactly 2M+1 switches 22, 24, 300.

[0300] In the example of [Fig. 10], the memory cell 10 is then made up of the first and second main terminals 12, 14, the auxiliary terminal 16, the memristor 20, and the primary, secondary and tertiary switches 22, 24, 300.

[0301] In the example of [Fig. 10], the memory cell 10 is therefore a memory cell of type (2M+1)TMR, with reference to the presence of 2M+1 switches (designated (2M+1)T) and M memristor(s) (designated MR), and each sub-cell 25 is of type 2T1R.

[0302] In the example of [Fig. 10], the integer M is strictly greater than 1.

[0303] When the number M is strictly greater than 1, a person skilled in the art will understand that the writing of a given value in a respective memristor 20 is obtained in particular via the opening of the primary switch 22 in parallel with said memristor 20, and the closing of the other M1 primary switch(es) 22, which then corresponds to the case where any other primary switch(es) 22 are to be closed. According to this second embodiment, the writing of the given value in the respective memristor 20 is further obtained via the closing of the tertiary switch 300 in series with said memristor 20.

[0304] When the number M is alternatively equal to 1, a person skilled in the art will also understand that writing a given value in the memristor 20 of the cell memory 10 is obtained in particular via the opening of the primary switch 22 which is arranged in parallel with said memristor 20, the closing of the tertiary switch 300 in series with said memristor 20, and that there is then no other possible primary switch 22 to close in this case.

[0305] Those skilled in the art will then observe that the memory cell 10 according to the invention is a 3T1R type cell in the case where M is equal to 1, and then comprises one less memristor than the 2T2R type memory cell of the prior art.

[0306] Those skilled in the art will note more generally that in the example of [Fig. 10], for M greater than 1, the memory cell 10 of type (2M+1)TMR according to the invention makes it possible to write M distinct values, then to read and / or infer these values, each of the M sub-cells 25 being associated with a respective value; and that the memory cell 10 is therefore comparable to M memory cells of type 2T2R of the prior art, each sub-cell 25 of type 2T1R according to the invention being comparable to the memory cell of type 2T2R of the prior art. Those skilled in the art will then understand that the memory cell 10 according to the invention comprises M fewer memristors than the M corresponding 2T2R type memory cells of the prior art, or that each 2T1R type sub-cell 25 according to the invention comprises one fewer memristor than the 2T2R type memory cell of the prior art.

[0307] The tertiary switch 300 is also called a tertiary switch. The tertiary switch 300 is for example produced in the form of the transistor 26. It comprises, as known per se, the two conduction electrodes 27 and the control electrode 28.

[0308] In the example of [Fig. 10], the transistor 26 forming the tertiary switch 300 of a first sub-cell 25 directly connected to the first main terminal 12 is connected by its source electrode S to said first main terminal 12, and by its drain electrode D to the memristor 20 of said first sub-cell 25. The transistor 26 forming the tertiary switch 300 of a respective sub-cell 25 of the series is connected by its source electrode S to the preceding sub-cell 25, in particular to the drain electrode D of the transistor 26 forming the primary switch 22 of said preceding sub-cell 25; and respectively by its drain electrode D to the memristor 20 of the respective sub-cell 25.The transistor 26 forming the tertiary switch 300 of the last sub-cell 25 connected directly to the second main terminal 14 is connected by its source electrode S to the previous sub-cell 25, and by its drain electrode D to the memristor 20 of said last sub-cell 25.

[0309] According to the second embodiment, the electronic circuit 30 further comprises complementary programming lines 310, as shown in [Fig.11]. For each memory cell 10, the control electrode 28 of each tertiary switch 300 is connected to a respective complementary programming line 310.

[0310] According to this second embodiment, the set 40 of memory cells 10 is similarly typically arranged in the form of a matrix comprising the rows 52 and the columns 54.

[0311] The complementary programming lines 310 are also denoted WLik with i the integer index varying from 1 to M where M represents the number of memristors 20 in each memory cell 10, which is equal to the number of tertiary switches 300 in each memory cell 10, M then also representing the number of tertiary switches 300 within each memory cell 10; and k the integer index varying from 1 to N, where N represents the number of rows 52. More precisely, the complementary programming lines 310 are then denoted WLi b WL2B ..., WLm,i for the first row 52 of index k equal to 1; then WLk2, WL22, ..., WLM2 for the second row 52 of index k equal to 2; up to WLijN, WL2N, ..., WLMN for the last row 52 of index k equal to N.

[0312] In the example of [Fig. 11], the number M is equal to 1, and the index i is not necessary. The complementary programming lines 310 are also denoted WLk with k the integer index varying from 1 to N, where N represents the number of rows 52. More precisely, the complementary programming lines 310 are then denoted WLb WL2, ..., WLn.

[0313] In a manner similar to what was described previously for the first embodiment, those skilled in the art will also understand that in practice the assembly 40 comprises a much larger number of memory cells 10 than that in the example of [Fig. 1 1] where the number of memory cells 10 shown is limited for the sake of simplifying the drawing.

[0314] According to the second embodiment, the first controller 42 is configured to further control each of the complementary programming lines 310 connected to the control electrodes 28 of the tertiary switches 300 of the set 40 of memory cells, as a function of the operation carried out on the memory cells 10, in particular among the programming operation when the programming method is implemented, and respectively the inference operation when the multiplication and accumulation method is implemented, as will be described in more detail hereinafter with reference to [Fig. 12], and respectively to [Fig. 13]; as well as the reading operation when the reading method according to the invention is implemented.

[0315] The first controller 42 is for example further configured to control the closing of the tertiary switches 300 of a respective row 52, ​​during the pro- programming of memory cell(s) 10 of said row 52.

[0316] Alternatively, the first controller 42 is configured to control the closing of the tertiary switches 300 connected to a respective complementary programming line 310 associated with said row and the opening of any other tertiary switches 300 of the memory cells 10 of said row 52, ​​these possible other tertiary switches 300 then being connected to other complementary programming lines 310 than the one to which a closing signal is applied.

[0317] Those skilled in the art will then observe that this variant makes it possible to close only the tertiary switch 300 of the sub-cell 25 being programmed and to open any other tertiary switches 300 of the memory cell 10. Those skilled in the art will then of course understand that the complementary programming line 310 to which the closing signal is applied is that associated with the sub-cell 25 which is itself associated with the value line 32 to which the opening signal is applied, given that the programming of a respective sub-cell 25 requires both the opening of the primary switch 22 and the closing of the tertiary switch 300 of said sub-cell 25.

[0318] As an optional addition, the first controller 42 is further configured to control the opening of the tertiary switches 300 of the row(s) other than the respective row 52 which is the subject of the programming of memory cell(s) 10.

[0319] The first controller 42 is for example configured, during the implementation of an inference operation with a batch of memory cell(s) 10 of a respective column 54, to control the closing of the tertiary switch(es) 300 of said batch of memory cell(s) 10 of the column 54.

[0320] Those skilled in the art will then understand that opening the tertiary switches 300 of the row(s) other than the respective row 52 which is the subject of the programming of memory cell(s) 10 then allows greater flexibility in controlling the source lines 36, since it is then necessary to control only the potential of the two source lines 36 located on either side of the row 52 which is the subject of the programming, i.e. to apply the first electrical potential V1 only to the source line 36 on the side of the first main terminal 12 of each memory cell 10 of said row 52, ​​and respectively to apply the second electrical potential V2 only to the source line 36 connected to the auxiliary terminal 16 of each memory cell 10 of said row 52, ​​the potentials applied to the other source lines 36 being indifferent.

[0321] Those skilled in the art will also understand that closing the tertiary switches 300 of a respective row 52, ​​during the programming of cell(s) memory 10 of said row 52, ​​further offers the possibility of limiting the current flowing through each memristor 20 of each memory cell 10 which is the subject of said programming, by then applying for example the predefined limitation potential VCOMPL to the control electrode 28 of each corresponding tertiary switch 300 via the associated complementary programming line 310.

[0322] Also, although it is possible according to the second embodiment, that the electronic circuit 30 comprises, as an optional addition, in addition the auxiliary switches 80 connected to the source lines 36, by analogy with the variant embodiment of [Fig. 3] in the case of the first embodiment, the person skilled in the art will understand that this optional addition is of lesser interest according to the second embodiment, since it is then already possible to limit the current flowing through each memristor 20 of each memory cell 10 by each respective tertiary switch 300.

[0323] The other advantages of this second embodiment are similar to those of the first embodiment described previously, and are not described again.

[0324] The operation of this second embodiment is similar to that of the first embodiment described previously, and will now be described with reference to [Fig. 12] representing a flowchart of the method of programming at least one memory cell 10 of a respective row 52 of memory cells 10 according to the second embodiment; then with reference to [Fig. 13] representing a flowchart of the method of multiplying and accumulating a batch of memory cell(s) 10 of a respective column 54 of memory cells 10 according to the second embodiment.

[0325] In [Fig. 12], the programming method comprises the step 100 of opening the primary switches 22 of the memory cells 10 of a respective row 52, ​​this step being identical to the opening step 100 described previously for the first embodiment with regard to [Fig. 8], and then not described again.

[0326] The programming method also comprises the step 105 of closing any other primary switches 22 of the memory cells 10 of said row 52, ​​this step being identical to the closing step 105 described previously for the first embodiment in [Fig.8], and therefore not being described again.

[0327] The programming method also comprises the step 110 of closing at least one secondary switch 24 of at least one memory cell 10 of said row 52, ​​this step being identical to the closing step 110 described previously for the first embodiment in [Fig.8], and therefore not being described again.

[0328] The programming method further comprises a step 115 of closing the tertiary switches 300 of the memory cells 10 of said row 52, ​​via the application of a closing command on the complementary programming line. 310 connected to said row 52.

[0329] During this closing step 115, the first controller 42 then commands the closing of the tertiary switches 300 of said row 52.

[0330] During this closing step 115, as a variant, the first controller 42 commands the closing of the tertiary switches 300 connected to a respective complementary programming line 310 associated with said row and the opening of any other tertiary switches 300 of the memory cells 10 of said row 52, ​​these other tertiary switches 300 then being connected to other complementary programming lines 310 than the one to which a closing signal is applied. The complementary programming line 310 to which the closing signal is applied is the one associated with the sub-cell 25 which is itself associated with the value line 32 to which the opening signal is applied, the programming of a respective sub-cell 25 requiring both the opening of the primary switch 22 and the closing of the tertiary switch 300 of said sub-cell 25.

[0331] As an optional addition, the programming method further comprises a step 117 of opening the other tertiary switches 300, i.e. the tertiary switches 300 for the row(s) 52 other than that which is the subject of the programming, via the application of an opening command on the other complementary programming line(s) 310 of the electronic circuit 30.

[0332] During this optional opening step 117, the first controller 42 then commands the opening of the tertiary switches 300 of said other row(s) 52.

[0333] At the end of these steps 100, 105, 110, 115, and optionally 117, the programming method comprises the assignment step 120 which is similar to that described previously for the first embodiment.

[0334] According to the second embodiment, during the assignment step 120, the first electrical potential V1 is preferably applied to the single source line 36 connected to the at least one first main terminal 12 and the second electrical potential V2 being applied to the single source line 36 connected to the at least one auxiliary terminal 16 of said row 52. According to this second embodiment, the electrical potential applied to the possible other source lines 36 is then indifferent, as explained above.

[0335] In [Fig. 13], the multiplication and accumulation method comprises the step 200 of opening the secondary switches 24 of the memory cells 10 of the column 54 which are the subject of this multiplication and accumulation, this step being identical to the opening step 200 described previously for the first embodiment with regard to [Fig. 9], and then not described again.

[0336] If the batch of memory cell(s) 10 which is the subject of this multiplication and accumulation does not include all the memory cells 10 of the corresponding column 54, the multiplication and accumulation method according to the second embodiment also comprises the step 210 of closing each primary switch 22 of each memory cell 10 distinct from said batch within said column 54, which is identical to that described previously for the first embodiment in [Fig.9], and is therefore not described again.

[0337] The multiplication and accumulation method according to the second embodiment further comprises, before the control step 220, a step 215 of closing each tertiary switch 300 of said batch, via the application of a closing command on each complementary programming line 310 connected to each tertiary switch 300 of said batch.

[0338] During this closing step 215, the first controller 42 then commands the closing of each tertiary switch 300 of said batch.

[0339] At the end of these steps 200, 210 and 215, the multiplication and accumulation method comprises the control step 220, then the obtaining step 230, which are each identical to those described previously for the first embodiment in [Fig.9], and are then not described again.

[0340] In addition, and whatever the embodiment, those skilled in the art will further understand that the memory cell 10 according to the invention, and the associated electronic circuit 30, also allow a simple reading method of a batch of memory cell(s) 10 of a respective column 54, this simple reading method being a simplified version of the multiplication and accumulation method described previously by having a multiple equal to 1 for each memory cell 10 which is the subject of this simple reading.

[0341] This simple reading is then carried out via the opening of each primary switch 22 of said batch which is the subject of this reading; and if said batch does not include all the memory cells 10 of said column 54, via further closing of each primary switch 22 of each separate memory cell 10 of said batch.

[0342] Those skilled in the art will then observe that the fact of having only the opening of each primary switch 22 of said batch during the inference cycle corresponds to a multiple equal to 1, the cumulative duration of opening of said primary switch 22 then being equal to the duration of said inference cycle, so that the aforementioned ratio p is equal to 1.

[0343] Those skilled in the art will nevertheless understand that the reading of at least one memory cell 10 of a respective row 52 is preferably carried out with a reading method comprising the following steps:

[0344] - opening of primary switches 22 of the memory cells 10 of said row 52, via the application of an opening command on a respective value line 32 connected to said row 52;

[0345] - closing of any other primary switches 22 of the memory cells 10 of said row 52, ​​via the application of a closing command on the possible other value line(s) 32 connected to said row 52;

[0346] - closing of the at least one secondary switch 24 of said at least one memory cell 10, via the application of a closing command on the at least one programming line 34 connected to said at least one memory cell 10 of said row 52;

[0347] - reading a value of at least one memristor 20 of said at least one cell memory 10, with a respective read voltage between the at least one first main terminal 12 and the at least one auxiliary terminal 16 of said at least one memory cell 10, via the application of a third electrical potential V3 to the source lines 36 arranged on the side of the at least one first main terminal 12 and of a fourth electrical potential V4 to the other source lines 36, arranged on the side of the at least one auxiliary terminal 16, the read voltage being equal to the difference between the third and fourth potentials V3, V4, the or each primary switch 22 in parallel with said at least one memristor 20 to be read being open.

[0348] The reading voltage is then typically approximately 0.1 to 0.4 volts, and it is for example obtained by positioning the value VH at this value of approximately 0.1 to 0.4 volts, the value VL at a substantially zero value, and where appropriate the value VCOMPL at VDD.

[0349] It is then understood that the memory cell 10 according to the invention, and the associated electronic circuit 30, allow the implementation of all types of neural networks, and in particular neural networks other than just binary neural networks, also called BNNs.

Claims

Claims

1. Memory cell (10), comprising: - a first main terminal (12), a second main terminal (14) and an auxiliary terminal (16); - M memristor(s) (20) connected between the two main terminals (12, 14), M being an integer greater than or equal to 1; - M primary switch(es) (22), each being connected in parallel with a respective memristor (20); and - a secondary switch (24) connected between the second main terminal (14) and the auxiliary terminal (16); the memory cell (10) being configured for writing a respective value into at least one memristor (20) via opening the or each primary switch (22) in parallel with said at least one memristor (20), closing the or each possible other primary switch (22), closing the secondary switch (24) and applying a corresponding programming voltage between the first main terminal (12) and the auxiliary terminal (16); the memory cell (10) being configured for reading a respective value in at least one memristor (20) via the opening of the or each primary switch (22) in parallel with said at least one memristor (20), the closing of the or each possible other primary switch (22), the opening of the secondary switch (24) and the measurement of a corresponding electrical quantity between the two main terminals (12, 14); the memory cell (10) being further configured for the multiplication of a value of at least one respective memristor (20) by a multiple (X ijk), via an alternation of opening(s) and closing(s) of the or each primary switch (22) in parallel with said at least one memristor (20) during an inference cycle, the closing of the or each possible other primary switch (22), the opening of the secondary switch (24) and the measurement of a corresponding electrical quantity between the two main terminals (12, 14), a ratio (p) between a cumulative duration of opening of the or each primary switch (22) in parallel with said at least one memristor (20) during the inference cycle and a duration of said cycle being representative of the multiple (Xi>k).

2. The memory cell (10) of claim 1, wherein the memory cell (10) comprises exactly M memristor(s) (20).

3. The memory cell (10) of claim 1 or 2, wherein the memory cell (10) comprises exactly M+1 switches (22, 24); the memory cell (10) preferably consisting of the first and second main terminals (12, 14), the auxiliary terminal (16), the memristor (20), and the primary and secondary switches (22, 24).

4. The memory cell (10) of claim 1 or 2, wherein the memory cell (10) further comprises M tertiary switch(es) (300), each connected to a respective memristor (20), the tertiary switch (300) and the memristor (20) being connected in series, in parallel with the associated primary switch (22); the memory cell (10) preferably consisting of the first and second main terminals (12, 14), the auxiliary terminal (16), the memristor (20), and the primary, secondary and tertiary switches (22, 24, 300).

5. Memory cell (10) according to any one of the preceding claims, wherein M is equal to 1, and the memory cell (10) is then configured for writing a respective value via opening the primary switch (22), closing the secondary switch (24) and applying a corresponding programming voltage between the first main terminal (12) and the auxiliary terminal (16); the memory cell (10) being configured for reading a respective value via opening the primary switch (22), opening the secondary switch (24) and measuring a corresponding electrical quantity between the two main terminals (12, 14).

6. Memory cell (10) according to any one of claims 1 to 4, in which M is strictly greater than 1, the M memristors (20) are connected in series between the two main terminals (12, 14).

7. The memory cell (10) of claim 6, wherein the memory cell (10) is configured for writing a respective value into a memristor (20) via opening the primary switch (22) in parallel with said memristor (20), closing the or each other primary switch (22), closing the secondary switch (24) and applying a corresponding programming voltage between the first main terminal (12) and the auxiliary terminal (16); the memory cell (10) being configured for reading a respective value into a memristor (20) via opening the primary switch (22) in parallel with said memristor (20), closing the or each other com- primary switch (22), opening of the secondary switch (24) and measuring a corresponding electrical quantity between the two main terminals (12, 14).

8. Electronic circuit (30), comprising: - value lines (32); - programming lines (34); - source lines (36); and - a set (40) of memory cells (10), each memory cell (10) being according to any one of the preceding claims, for each memory cell (10), a control electrode (28) of a respective primary switch (22) being connected to a respective value line (32), a control electrode (28) of the secondary switch (24) being connected to a respective programming line (34), and the auxiliary terminal (16) being connected to a respective source line (36).

9. An electronic circuit (30) according to claim 8, wherein each memory cell (10) is according to claim 4, the electronic circuit (30) further comprises complementary programming lines (310), and for each memory cell (10), a control electrode (28) of a respective tertiary switch (300) is connected to a respective complementary programming line (310).

10. Electronic circuit (30) according to claim 8 or 9, wherein the electronic circuit (30) further comprises multiplexers (72), each source line (36) being connected to a respective multiplexer (72), each multiplexer (72) being configured to select, as a function of a selection signal and from among several predefined values ​​(VH, VL), an electrical potential value to be applied to the associated source line (36).

11. An electronic circuit (30) according to any one of claims 8 to 10, wherein the electronic circuit (30) further comprises auxiliary switches (80), each source line (36) being connected to a respective auxiliary switch (80), each auxiliary switch (80) being configured to, upon receipt of a limiting command, limit an electric current flowing in the associated source line (36); each auxiliary switch (80) preferably being a transistor (26), and the limiting command being a predefined limiting potential applied to a control electrode (28) of said switch auxiliary (80); the electronic circuit (30) preferably further comprising auxiliary multiplexers (82), the control electrode (28) of each auxiliary switch (80) being connected to a respective auxiliary multiplexer (82), each auxiliary multiplexer (82) being configured to select, as a function of a limitation signal and from among several predefined values ​​(VCOMPL, VDD), an electrical potential value to be applied to the associated control electrode (28).

12. Electronic circuit (30) according to any one of claims 8 to 11, in which the set (40) of memory cells (10) is arranged in the form of a matrix comprising rows (52) and columns (54), the memory cells (10) of the same row (52) being connected to M same value line(s) (32) and to the same source line (36), and the memory cells (10) of the same column (54) being connected to the same programming line (34).

13. Electronic circuit (30) according to claims 9 and 12, in which the memory cells (10) of the same row (52) are further connected to M same complementary programming line(s) (310).

14. Electronic circuit (30) according to claim 12 or 13, wherein the electronic circuit (30) further comprises measurement modules (60), and the memory cells (10) of the same column (54) are connected in series with each other, each column (54) having a first end (56) connected to a reference potential (VR) and a second end (58) connected to a respective measurement module (60), each measurement module (60) being configured to measure a cumulative voltage of the memory cells (10) of the column (54) to which it is connected; the electronic circuit (30) preferably further comprising a reference line (38) to which the reference potential (VR) is applied, the first ends (56) of the columns (54) then being connected to the reference line (38);each measurement module (60) preferably further comprising a comparator (62) configured to detect the reaching, by the cumulative voltage of the memory cells (10) of the respective column (54), of a respective predefined threshold voltage.;

15. Method for multiplying and accumulating a batch of memory cell(s) (10) of a respective column (54) of memory cells (10) of an electronic circuit (30) according to claim 14, the method comprising the following steps: - opening (200) of the secondary switches (24) of the memory cells (10) of said column (54), via the application of an opening command on the programming line (34) connected to said column (54); - if said batch does not include all the memory cells (10) of said column (54), closing (210) each primary switch (22) of each memory cell (10) distinct from said batch within said column (54), via the application of a closing command on each value line (32) connected to each memory cell (10) distinct from said batch; - driving (220) each primary switch (22) of said batch of memory cell(s) with alternating opening(s) and closing(s) during an inference cycle, via the application of alternating opening(s) and closing(s) commands on each value line (32) connected to each primary switch (22) of said batch, to multiply the value of each memristor (20) of said batch by a respective multiple (Xijk); a ratio (p) between a cumulative duration of opening of the respective primary switch (22) during the inference cycle and a duration of said cycle being representative of the respective multiple (Xijk); - obtaining (230) a weighted sum of memristor value(s) (20) of said batch, each memristor value (20) being multiplied by the respective multiple (Xi>k), via a measurement of the cumulative voltage of the memory cells (10) of said column (54).

16. A multiplication and accumulation method according to claim 15, the electronic circuit (30) being according to claims 13 and 14, wherein the method further comprises, before the control step (220), a closing step (215) of each tertiary switch (300) of said batch, via the application of a closing command on each complementary programming line (310) connected to each tertiary switch (300) of said batch.

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