Optoelectronic device

Abstract

Optoelectronic Device This description relates to a pixel (14) comprising: a light-emitting element; a memory (28) comprising at least one phase-change memory cell (54); a first switch (34) comprising a first output terminal (42) connected to the light-emitting element, a second output terminal (46) connected to the phase-change memory (28), and an input terminal (44) connected to a power supply node (52) via a transistor (36); and a control circuit configured to generate a control voltage (VGS) on a control terminal of the transistor (36), the control voltage being equal to: a first voltage during a reset step of at least one memory cell; a second voltage during a programming step of at least one memory cell; a third voltage during a control step of the element. Figure for the abstract: Fig. 3

Description

Title of the invention: Optoelectronic device technical field

[0001] This description relates generally to optoelectronic devices and, more particularly, to devices comprising pixels and their drivers. Prior art

[0002] A pixel of an image corresponds to the unit element of the image displayed by a display screen. For displaying color images, the display screen generally comprises, for the display of each pixel of the image, at least three components, also called display sub-pixels, each of which emits light, called the image pixel color component, essentially in the form of a single color (for example, red, green, and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with the sensation of color corresponding to the pixel of the displayed image. In this case, the set of three display sub-pixels used for displaying a pixel of an image is called the display pixel of the display screen. Each display sub-pixel may include a light source, in particular a light-emitting diode.

[0003] Display pixels can be distributed in a matrix, each display pixel being located at the intersection of a row and a column of the matrix. Each display pixel includes, for example, a light-emitting element and associated electronic circuits, such as a driver. Electrodes are provided along the rows and columns to connect each display pixel to control circuits. Generally, each row of display pixels is selected successively by a ROW signal transmitted along the row electrodes, and the display pixels of the selected row are programmed to display the desired image pixels by COL signals transmitted along the column electrodes.

[0004] Pixels are generally manufactured to be identical. Therefore, pixels intended to generate the same brightness receive the same control signal. However, the components of a display pixel exhibit variations due to manufacturing. The brightness generated by a pixel may not correspond to the desired brightness. Summary of the invention

[0005] An embodiment overcomes all or part of the drawbacks of known optoelectronic devices.

[0006] One embodiment provides for a pixel comprising:

[0007] a light-emitting element;

[0008] a memory comprising at least one phase-change memory cell;

[0009] a first switch comprising a first output terminal connected to the light-emitting element, a second output terminal connected to the phase-change memory, and an input terminal connected to a power supply node via a transistor; and

[0010] a control circuit configured to generate a control voltage on a control terminal of the transistor, the control voltage being equal to:

[0011] a first voltage during a reset step of at least one memory cell;

[0012] a second voltage during a programming step of at least one memory cell;

[0013] a third voltage during a control step of the element. Such an embodiment allows each pixel to be calibrated independently.

[0014] Such a pixel generates a low static current. This allows data to be stored at a lower voltage than previously known circuits, such as volatile memory cells. The pixel does not require a dedicated analog circuit to generate the high voltage used to program the volatile cells, thus reducing the pixel size.

[0015] According to one embodiment, the first voltage is greater than the second voltage and the second voltage is greater than the third voltage.

[0016] According to one embodiment, the first switch is configured to connect the second output and the input of the first switch during the programming and memory cell reset steps and to connect the first output and the input of the first switch during the element control step.

[0017] According to one embodiment, during a read step of at least one memory cell of the memory, the control voltage is equal to the third voltage and the first switch is configured to connect the second output and the input of the first switch.

[0018] According to one embodiment, the transistor is connected to the power supply node by a second switch.

[0019] According to one embodiment, the second switch is configured to be closed for a first duration during the programming step, for a second duration during the reset step, and for a third duration during the element control step.

[0020] According to one embodiment, the first duration is longer than the second duration and the second duration is longer than the third duration.

[0021] According to one embodiment, the memory comprises between 20 and 50 cells.

[0022] According to one embodiment, the memory includes a third switch comprising an input connected to the second output terminal and an output connected to each memory cell.

[0023] According to one embodiment, the light-emitting element is a light-emitting diode.

[0024] Another embodiment provides for a display screen comprising a plurality of pixels as described above.

[0025] A pixel calibration method according to any one of claims 1 to 10, comprising:

[0026] reading data from memory;

[0027] the control of the element according to the data read from memory;

[0028] measuring the brightness of the element;

[0029] the comparison of brightness to a defined value;

[0030] if the brightness differs from the defined value, the modification of the value of said data by programming and reset steps.

[0031] This calibration process, applied to the pixel, ensures that all pixels of a display system generate the same brightness regardless of their individual deviations due to manufacturing. Brief description of the drawings

[0032] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0033] Fig. 1 represents an example of an optoelectronic device;

[0034] [Fig.2] schematically represents an example of a pixel;

[0035] [Fig.3] represents in more detail a part of the pixel of [Fig.2] according to one embodiment;

[0036] [Fig.4] represents in more detail part of the embodiment of [Fig.3];

[0037] [Fig.5] represents several functions of the embodiment of [Fig.3];

[0038] [Fig.6] represents in more detail the different functions of the embodiment of [Fig.3];

[0039] [Fig.7] represents an example of a VGS voltage generation circuit;

[0040] Fig. 8 represents another example of a VGS voltage generation circuit 73; and

[0041] [Fig.9] represents the calibration method of the embodiment of [Fig.3]. Description of the implementation methods

[0042] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the Different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0043] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been represented and are detailed.

[0044] Unless otherwise specified, when referring to two elements connected between them, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or linked via one or more other elements.

[0045] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0046] Unless otherwise specified, the expressions "approximately", "about", "meaning" "Suitably" and "of the order of" mean to within 10%, preferably to within 5%.

[0047] Fig. 1 represents an example of an optoelectronic device 10.

[0048] The device 10 includes a screen 12. The screen 12 is configured, for example, to project light, images, or videos. The screen includes a pixel matrix 14. The screen 12 includes, for example, at least one million pixels, at least two million pixels, or at least eight million pixels. The screen includes rows 16 of pixels 14 and columns 18 of pixels 14.

[0049] The device 10 further includes a row control circuit, or driver, 20 and a column control circuit, or driver, 22. The circuit 20 is configured to provide row voltages ROW, in other words, to provide control voltages common to all pixels in the same row. Similarly, the circuit 22 is configured to provide column voltages COL, in other words, to provide control voltages common to all pixels in the same column. For example, the ROW signal corresponds to row selection and the clock signal in lighting mode, for example, in pulse-width modulation (PWM) mode. For example, the COL signal corresponds to lighting data, for example, video data.

[0050] The device 10 includes, for example, a controller 24 configured to provide circuits 20 and 22 with the data to generate the ROW and COL voltages. The controller 24 can also provide the clock signal to circuits 20 and 22 and optionally to pixels 14. The controller 24 is, for example, a synchronization controller.

[0051] Figure 2 schematically represents an embodiment of a pixel 14. The pixel 14 comprises a first region 26, a second region 28, and a third region 30.

[0052] The first region 26 comprises at least one light-emitting element. For example, the light-emitting element is, in the remainder of the description, a light-emitting diode, for example, an inorganic light-emitting diode. However, the light-emitting element may be any type of light-emitting component. The first region comprises, for example, three light-emitting diodes: one diode configured to provide blue light, one diode configured to provide green light, and one diode configured to provide red light.

[0053] The second region 28, or non-volatile memory region, comprises at least one non-volatile memory cell. The memory region 28 is configured to store data for the pixel 14, for example, calibration data. The size of the memory 28 depends on the application. The memory 28 comprises, for example, between 2 and 2000 memory cells. The pixel 14 may also include at least one other memory, for example, volatile memory, configured for storing lighting data.

[0054] The third region 30 is, for example, the pixel driver. The third region includes analog and digital circuits. The third region includes peripheral circuits. The third region 30 includes, for example, a power supply circuit configured to provide the pixel supply voltages. The third region 30 includes, for example, control logic. The third region 30 includes, for example, a circuit configured to read from and / or write to the memory region.

[0055] For example, each pixel comprises only four pads, not shown. In other words, each pixel receives only four external voltages: a supply voltage, a reference voltage, for example ground GND, a ROW signal transmitted along the row electrodes and a COL signal transmitted along the column electrodes.

[0056] [Fig.3] represents in more detail a part of pixel 14 of [Fig.2] according to one embodiment.

[0057] Pixel 14 includes a light-emitting diode 32. The diode 32 is connected in series to a switch 34, a transistor 36, and a switch 38. The transistor 36 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), for example, a P-channel transistor. The transistor 36 includes a control terminal, for example, a gate, and two conduction terminals, for example, a drain and a source. The switch 34 includes an input terminal 44 and two output terminals 42 and 46. The switch 34 is configured to connect terminal 44 to either terminal 42 or terminal 46, depending on a PATH control voltage. The switch 38 comprises two terminals 48 and 50. The switch 38 is configured to connect or disconnect terminals 48, 50 according to a CTRLS control voltage.

[0058] The diode 32 is connected in series between a node 40 for applying a reference voltage, for example ground GND, and the switch 34. In other words, one terminal of the diode 32, for example the cathode, is connected, preferably connected, to the node 40 and another terminal of the diode, for example the anode, is connected, preferably connected, to the terminal 42 of the switch 34.

[0059] Transistor 36 is connected between switch 34 and switch 38. In other words, the conduction terminal 44 of transistor 36, for example the drain, is connected, preferably connected, to terminal 44 of switch 34, and the other conduction terminal 48 of transistor 36, for example the source, is connected, preferably connected, to terminal 48 of switch 38. The control terminal of transistor 36 is connected, preferably connected, to a node for applying a control voltage VGS. Terminal 50 of switch 38 is connected, preferably connected, to a supply node 52 for applying a supply voltage VCC. Several examples of circuits configured to generate the voltage VGS, at least in some operating mode, for example, the voltage VGS supplied while the diode is illuminated.

[0060] Terminal 46 of switch 34 is connected, preferably connected, to memory region 28 and, more specifically, to memory cells of memory 28.

[0061] The switch 38 and the transistor 36 are configured to generate a current I and to supply the current I to the switch 34.

[0062] Figure 4 shows in more detail a part of the embodiment of Figure 3. More specifically, Figure 4 schematically represents the memory circuit 28.

[0063] The circuit 28 comprises at least one memory cell 54, for example between 2 and 2000 memory cells 54. The memory cells are non-volatile memory cells. The memory cells 54 are resistive memory cells, preferably phase-change memory cells.

[0064] Each memory cell 54 comprises a memory element 56 and a selection element 58. The selection element is, for example, a transistor, for example, a MOSFET. Elements 56 and 58 are, for example, connected in series, for example, between an input 60 of the pixel and the reference voltage application node 40 (GND). More specifically, one terminal of element 56 is connected, preferably connected, to the input 60, and the other terminal of element 56 is connected, preferably connected, to a conduction terminal of element 58. The other conduction terminal of transistor 58 is connected, preferably connected, to node 40. The control terminal, or gate, of element 58 is connected, preferably connected, to a word line signal (WL) application node. The WL signal corresponds, for example, to a binary signal. The first value of the WL signal is, for example, such that the receiving cell 54 can be read and / or written to it, and the second value of the WL signal is, for example, such that the receiving cell 54 cannot be read or written to it. The WL signal is, for example, generated by the control logic present in region 30 ([Fig.2]).

[0065] The resistance of element 56 can be modified. If a current with a first value flows through element 56, the resistance of element 56 takes on a first value, corresponding to a first binary value. If the current flowing through element 56 has a second value, the resistance of element 56 takes on a second value, corresponding to a second binary value. Each element 56 is, for example, made of a phase-change material.

[0066] The circuit 28 further includes a switch matrix 62. The switch matrix 62 includes an input connected, preferably connected, to terminal 46. The switch matrix includes at least as many outputs as there are memory cells 54. Each input 60 of the memory cells 54 is connected, preferably connected, to an output of the switch matrix 62. The current I can therefore be distributed to the memory cell 54 being read or written.

[0067] Figure 5 represents several stages of the embodiment of Figure 3. More specifically, Figure 5 represents the current I during different operating stages of the embodiment of Figure 3 as a function of time (t).

[0068] A curve 64 represents the current I generated to reset a memory cell 54, in other words to write a first binary value into said memory cell 54. A curve 66 represents the current I generated to program a memory cell 54, in other words to write a second binary value into said memory cell 54. A curve 68 represents the current I generated to read the contents of a memory cell 54. A curve 70 represents the current I generated to illuminate the light-emitting diode.

[0069] Each curve 64, 66, 68, 70 comprises a first period of increase from a low value, for example substantially equal to zero amperes, to a high value, a second period during which the value of the current I is maintained at the high value II, 12, 13, a third period of decrease from the high value to the low value, and a fourth period during which the value of the current I is substantially equal to the low value. The second period corresponds to a pulse.

[0070] The lower values ​​of curves 64, 66, 68, and 70 are, for example, identical. The upper value II of curve 64 and the duration of the second period of curve 64 correspond to the current used to reset the memory cells 54. The upper value 12 of curve 66 and the duration of the second period of curve 66 correspond to the current used to program the memory cells 54. The upper value 13 of the Curve 68 and the duration of the second period of curve 68 correspond to the current used to read the memory cells 54. The high value 14 of curve 70 and the duration of the second period of curve 70 correspond to the current used to control the LED. In other words, the memory cells are programmed, reset, or read, and the LED is illuminated, when the current reaches the value of the second period of the corresponding curve.

[0071] The high value II of curve 64 is greater than the high value 12 of curve 66. The high value 12 of curve 66 is greater than the high value 13 of curve 68. The high value 13 of curve 68 is substantially equal to the high value 14 of curve 70. Furthermore, the duration of the second period of curve 64 is shorter than the duration of the second period of curve 66. Although the duration of the second period of curve 66 is shorter than the duration of the second period of curve 70 in the example of [Fig. 5], the duration of the second period of curve 70 depends on the lighting data and, therefore, may have a different duration. The duration of the second period of curve 68 is shorter than the duration of the second period of curve 64.

[0072] The current intensity I during the second period of each curve, corresponding to the high value, is, for example, determined by the voltage VGS applied to the control terminal of transistor 36. The duration of the second period is determined by the voltage CTRLS, which controls the switch 38. In other words, the voltage VGS is configured to have first V1, second V2, and third V3 values, the first value being configured to ensure that the current through transistor 36 has intensity II, the second value being configured to ensure that the current through transistor 36 has intensity I2, and the third value being configured to ensure that the current through transistor 36 has intensity I3. The first, second, and third values ​​are distinct. The first value of the voltage VGS is, for example, greater than the second value of the voltage VGS.The second value of the VGS voltage is, for example, greater than the third value of the VGS voltage.

[0073] Figure 6 shows in more detail the different functions of the embodiment of Figure 3. More specifically, Figure 6 includes four views 6A, 6B, 6C and 6D representing respectively the resetting of memory cells, the programming of memory cells, the reading of memory cells and the control of light-emitting diodes.

[0074] In view 6A, corresponding to the reset of the memory cells, the voltage VGS, which has the first value VI, is applied to the control terminal, for example the gate, of transistor 36. In addition, the control terminal of switch 38 receives a CTRLS pulse 1 ensuring that switch 38 is closed for a duration corresponding to the duration of the second period of curve 64. The com- switch 34 is configured to connect terminals 44 and 46.

[0075] Memory 28 receives the current I corresponding to a reset. The transistor 58 of the cell or cells to be reset receives, at its control terminal, a WL signal having a value configured to allow current to flow through element 56 and transistor 58. The current through element 56 is configured to modify the phase of element 56. The transistor 58 of the cell or cells that are not to be reset receives, at its control terminal, a WL signal having a value configured to stop current flow through element 56 and transistor 58. The phase of elements 58 is therefore not modified.

[0076] If the memory 28 includes the switch matrix 62, the matrix is ​​configured to supply the current I to the cells to be reset.

[0077] In view 6B, corresponding to the programming of the memory cells, the voltage VGS, which has the second value V2, is applied to the control terminal, for example the gate, of transistor 36. In addition, the control terminal of switch 38 receives a CTRLS2 pulse ensuring that switch 38 is closed for a duration corresponding to the duration of the second period of curve 66. Switch 34 is configured to connect terminals 44 and 46.

[0078] Memory 28 receives the current I corresponding to a memory program. The transistor 58 of the cell or cells to be programmed receives, at its control terminal, a WL signal having a value configured to allow current to flow through element 56 and transistor 58. The current through element 56 is configured to modify the phase of element 56. The transistor 58 of the cell or cells that are not to be programmed receives, at its control terminal, a WL signal having a value configured to stop current flow through element 56 and transistor 58. The phase of elements 58 is therefore not changed.

[0079] If the memory 28 includes the switch matrix 62, the matrix is ​​configured to supply the current I to the cells to be programmed.

[0080] In view 6C, corresponding to the reading of the memory cells, the voltage VGS, which has the third value V3, is applied to the control terminal, for example the gate, of transistor 36. In addition, the control terminal of switch 38 receives a pulse CTRLS3 ensuring that switch 38 is closed for a duration corresponding to the duration of the second period of curve 68. Switch 34 is configured to connect terminals 44 and 46.

[0081] Memory 28 receives the current I corresponding to a memory program. Transistor 58 of the cell or cells to be read receives, on its control terminal, a signal WL having a value configured to allow current to flow through element 56 and transistor 58. The current flowing through element 56 is not not sufficient to change the phase of element 56, but allows the cell to be read. Transistor 58 of the cell or cells that are not to be read receives, at its control terminal, a WL signal having a value configured to stop the flow of current in element 56 and transistor 58.

[0082] If the memory 28 includes the switch matrix 62, the matrix is ​​configured to supply the current I to the cells to be programmed.

[0083] In view 6D, corresponding to the control of the light-emitting diode 32, the voltage VGS, which preferably has the fourth value V4 equal to the value V3, is applied to the control terminal, for example the gate, of the transistor 36. In addition, the control terminal of the switch 38 receives a pulse CTRLS4 ensuring that the switch 38 is closed for a duration corresponding to the duration of the second period of the curve 70. The switch 34 is configured to connect terminals 44 and 42.

[0084] Consequently, the memory 28 does not receive the current I. The diode 32 receives the current I and is illuminated.

[0085] If the memory 28 includes the switch matrix 62, the matrix is ​​configured to supply the current I to the cells to be programmed.

[0086] Terminal 46 is, for example, connected to node 40 by a switch 72. In other words, one terminal of switch 72 is connected, preferably connected, to node 40 and another terminal is connected, preferably connected, to terminal 46. In views 6A, 6B, and 6C, switch 72 is configured to be open. In view 6D, switch 72 is configured to be closed, which minimizes the static current during the lighting period.

[0087] Fig. 7 represents an example of a VGS voltage generation circuit 73.

[0088] The circuit 73 comprises a transistor 75, a transistor 77 and a resistor 79 connected in series between node 40 and node 52. Transistors 75 and 77 are, for example, MOSFETs. Transistors 75 and 77 are, for example, respectively an N-channel transistor and a P-channel transistor.

[0089] One conduction terminal of transistor 75, for example the source, is connected, preferably connected, to node 40. Another conduction terminal of transistor 75, for example the drain, is connected, preferably connected, to a node 81. One conduction terminal of transistor 77, for example the drain, is connected, preferably connected, to node 81. Another conduction terminal of transistor 77, for example the source, is connected, preferably connected, to a node 83. One terminal of resistor 79 is connected, preferably connected, to node 83 and another terminal of resistor 79 is connected, preferably connected, to node 52.

[0090] The circuit 73 also includes a transistor 85 and a transistor 87 connected in series between node 40 and node 52. Transistors 85 and 87 are, for example, MOSFET. Transistors 85 and 87 are, for example, respectively an N-channel transistor and a P-channel transistor.

[0091] One conduction terminal of transistor 85, for example the source, is connected, preferably connected, to node 40. Another conduction terminal of transistor 85, for example the drain, is connected, preferably connected, to a node 89. One conduction terminal of transistor 87, for example the drain, is connected, preferably connected, to node 89. Another conduction terminal of transistor 87, for example the source, is connected, preferably connected, to node 52.

[0092] The control terminal, or gate, of transistor 75 is connected, preferably connected, to a node 91. The control terminal, or gate, of transistor 85 is connected, preferably connected, to node 91 and, consequently, to the control terminal of transistor 75. In addition, node 91 is connected, preferably connected, to node 81.

[0093] The control terminal of transistor 77 is connected, preferably connected, to node 89. The control terminal of transistor 87 is connected, preferably connected, to node 83.

[0094] The circuit 73 also includes a transistor 93 and a transistor 95 connected in series between node 40 and node 52. Transistors 93 and 95 are, for example, MOSFETs. Transistors 93 and 95 are, for example, respectively an N-channel transistor and a P-channel transistor.

[0095] One conduction terminal of transistor 93, for example the source, is connected, preferably connected, to node 40. Another conduction terminal of transistor 93, for example the drain, is connected, preferably connected, to a node 97. One conduction terminal of transistor 95, for example the drain, is connected, preferably connected, to node 97. Another conduction terminal of transistor 95, for example the source, is connected, preferably connected, to node 52.

[0096] The control terminal of transistor 93 is connected, preferably connected, to node 91. The control terminal of transistor 95 is connected, preferably connected, to a node 99. Node 99 is connected, preferably connected, to node 97. Node 99 corresponds to the output node of circuit 73. The voltage VGS is generated at node 99.

[0097] Fig. 8 represents circuit 14 comprising another example of a VGS voltage generation circuit 73.

[0098] The circuit 14 comprises, as an embodiment of [Fig. 3], diode 32, switch 34, transistor 36, and switch 38. Diode 32, switch 34, transistor 36, and switch 38 are connected in series between node 40 and node 52. Diode 32 is connected between node 40 and switch 34. In other words, the cathode of diode 32 is connected, preferably connected, to node 40, and the anode of diode 32 is connected, preferably connected, to the first terminal 42 of the switch 34. The second terminal 44 of switch 34 is connected to node 52 via transistor 36 and switch 38. In other words, the second terminal of switch 34 is connected, preferably connected, to a node 105, node 105 being connected, preferably connected, to one conduction terminal, for example the drain, of transistor 36, and the other conduction terminal, for example the source, of transistor 36 is connected to node 52 via switch 38. In other words, the other conduction terminal of transistor 36 is connected, preferably connected, to a terminal of switch 38, the other terminal of switch 38 being connected, preferably connected, to node 52. Switch 34 includes the other terminal 46, connected, preferably connected, as in [Fig. 3], to memory 28.

[0099] The control terminal of transistor 36 is connected, preferably connected, to the circuit 73 configured to generate the voltage VGS.

[0100] Circuit 73 includes a variable voltage divider. In other words, circuit 73 includes a voltage divider in which the ratio between the two capacitive branches is variable.

[0101] The voltage divider, and consequently the circuit 73, includes a capacitor 108. The capacitance of the capacitor 108 is preferably fixed. The capacitor 108 is connected between the control terminal of the transistor 36 and the node 52. A first terminal of the capacitor 108 is connected, preferably connected, to a node 109, the node 109 being connected, preferably connected, to the control terminal of the transistor 36. A second terminal of the capacitor 108 is connected, preferably connected, to the node 52.

[0102] The control terminal of transistor 36 is further connected to a node 118 for applying a reference voltage. The control terminal of transistor 36 is connected to node 118 via a capacitor 120. The capacitance of capacitor 120 is preferably fixed. More precisely, the control terminal of transistor 36 is connected, preferably connected, to one terminal of capacitor 120. In other words, said terminal of capacitor 120 is connected, preferably connected, to node 109. Another terminal of capacitor 120 is connected, preferably connected, to node 118.

[0103] The voltage divider also includes at least one capacitor 110 connected in parallel either to capacitor 108 or to capacitor 120, depending on a control signal. The capacitances of the capacitors 110 are, for example, fixed. The capacitances of the capacitors 110 are, for example, substantially equal.

[0104] In the example of [Fig.8], the divider comprises three capacitors 110, referenced 110a, 110b and 110c. In general, the number of capacitors 110 depends on the application.

[0105] Each capacitor 110 is connected in series to a switch 112. In other words, capacitor 110a is connected in series to a switch 112a, capacitor 110b is connected in series to a switch 112b, and capacitor 110c is connected in series to a 112c switch.

[0106] One terminal of each capacitor 110 is connected, preferably connected, to node 109. Another terminal of each capacitor 110 is connected, preferably connected, to an input terminal of the corresponding switch 112. Each switch 112 has a first output terminal connected, preferably connected, to node 52 and a second output terminal connected, preferably connected, to node 118. Each switch 112 is configured to connect the corresponding capacitor 110 to either node 52 or node 118 depending on the control voltage. Each switch 112 is preferably controlled by its own control voltage, for example, independently of the control voltages of the other switches 112.

[0107] The value of the voltage VGS is therefore determined by the control voltages of the switches 112, which determines the ratio of the capacitances of the two branches of the voltage divider.

[0108] The circuit 73 further includes a switch 114 connected between node 109 and node 52. The switch 114 includes a control terminal, for example connected, preferably connected, to a node for applying a reset voltage.

[0109] The memory 28 can include several configurations for the voltage divider, in other words several of the control voltages of the switches 112, for example a value corresponding to voltage VI, a value corresponding to voltage V2 and a value corresponding to voltage V3.

[0110] Fig. 9 represents steps, preferably successive steps, of a calibration process for the embodiment of Fig. 3, more specifically the calibration of a pixel.

[0111] The method includes a first step of illuminating the light-emitting diode (block 74). Illuminating the diode includes configuring the circuit to enter read mode (block 76). For example, entering read mode includes applying voltage V3 to transistor 36, applying the WL signal to transistors 58, and connecting terminals 44 and 46. Illuminating the diode further includes reading data from the memory cells (block 78). This corresponds to view 6C of [Fig. 6]. This step includes, for example, applying the CTRLS3 pulse to switch 38. The method includes a step of writing video data (block 80) and controlling the light emission mode (block 82), in other words, illuminating the diode, for example, by pulse-width modulation (PWM). Illuminating the diode corresponds to view 6D of [Fig. 6]. The diode is therefore illuminated.

[0112] The illumination step is followed by a step measuring the brightness and wavelength generated by the diode (block 84). The measured brightness is then compared to the desired brightness, for example by a device or circuit external to the pixel. Said device or circuit determines the modification to be made, for example in the value of the VGS voltage and in the duration of the second period of lighting to obtain the desired brightness.

[0113] For example, the process then includes a pixel reset step (block 86).

[0114] The pixel then enters a programming mode (block 88). Entering programming mode includes, for example, connecting terminals 44 and 46 of switch 34. The process then includes programming the memory (block 90). The data obtained by comparing the actual brightness with the desired brightness is programmed into the memory. For example, this data corresponds to a value representing the VGS voltage and the duration of the second period. The programming includes, for example, one or more programming steps, corresponding to view 6B of [Fig. 6], and reset steps corresponding to view 6A of [Fig. 6].

[0115] For example, the process then includes a pixel reset step (block 92).

[0116] The method includes a second illumination of the light-emitting diode (block 94). The diode illumination includes, as with the first illumination, configuring the circuit to enter read mode (block 96). For example, entering read mode includes applying voltage V3 to transistor 36, applying the WL signal to transistors 58, and connecting terminals 44 and 46. The diode illumination further includes reading data from the memory cells (block 98). This corresponds to view 6C of [Fig. 6]. This step includes, for example, applying the CTRLS3 pulse to switch 38. The method includes a data writing step (block 100) and controlling the light emission mode (block 102), in other words, illuminating the diode, for example, by pulse-width modulation (PWM). The illumination of the diode corresponds to the 6D view of [Fig.6]. The diode is therefore illuminated.

[0117] The second illumination step is followed by another step measuring the brightness generated by the diode (block 104). The measured brightness is then compared to the desired brightness, for example, by a device or circuit external to the pixel. If the brightness is at the desired level, the calibration is complete. If the brightness is not at the desired level, said device or circuit determines the modification to be made, for example, in the value of the VGS voltage and in the duration of the second illumination period to obtain the desired brightness. The process continues with the steps of block 88.

[0118] One advantage of the embodiments is that the use of phase-change memory allows data to be stored with a lower voltage than previously known circuits, including, for example, memory cells volatiles. The pixel does not need a dedicated analog circuit to generate the high voltage used to program volatile cells, which allows for a reduction in pixel size.

[0119] Another advantage of the embodiments is that each pixel does not generate any static current during pixel operation, thereby reducing the energy consumption of the display system.

[0120] Various embodiments and variations have been described. A person skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will become apparent to a person skilled in the art.

[0121] Finally, the practical implementation of the embodiments and variants described is within the reach of a person skilled in the art, based on the functional indications given above.

Claims

Demands

1. Pixel (14) comprising: - a transistor (36); - a light-emitting element (32); - a memory (28) comprising at least one phase-change memory cell (54); - a first switch (34) comprising a first output terminal (42) connected to the light-emitting element (32), a second output terminal (46) connected to the phase-change memory (28), and an input terminal (44) connected to a power supply node (52) via the transistor (36), the first switch being configured to connect the input terminal to either the first output terminal or the second output terminal; and - a control circuit configured to generate a control voltage (VGS) on a control terminal of the transistor (36), the control voltage being equal to: - a first voltage during a reset step of at least one memory cell; - a second voltage during a programming step of at least one memory cell;- a third voltage during a control step of element (32).;

2. Pixel according to claim 1, wherein the first voltage is greater than the second voltage and the second voltage is greater than the third voltage.

3. Pixel according to claim 1 or 2, wherein the first switch (34) is configured to connect the second output (46) and the input (44) of the first switch (34) during the memory cell programming and reset steps, and to connect the first output (42) and the input (44) of the first switch (34) during the element (32) control step.

4. Pixel according to any one of claims 1 to 3, wherein, during a read step of at least one memory cell of the memory (28), the control voltage is equal to the third voltage and the first switch (34) is configured to connect the second output (46) and the input (44) of the first switch (34).

5. Pixel according to any one of claims 1 to 4, wherein the transistor (36) is connected to the power node (52) by a second switch (38).

6. Pixel according to claim 5, wherein the second switch (38) is configured to be closed for a first duration during the programming step, for a second duration during the reset step, and for a third duration during the element control step.

7. Pixel according to claim 6, wherein the first duration is longer than the second duration and the second duration is longer than the third duration.

8. Pixel according to any one of claims 1 to 7, wherein the memory (28) comprises between 20 and 50 cells.

9. Pixel according to any one of claims 1 to 8, wherein the memory comprises a third switch (62) comprising an input connected to the second output terminal (46) and an output connected to each memory cell.

10. Pixel according to any one of claims 1 to 9, wherein the light-emitting element (32) is a light-emitting diode.

11. Display screen comprising a plurality of pixels according to any one of claims 1 to 10.

12. A method for calibrating the pixel according to any one of claims 1 to 10, comprising: - reading data from memory (28); - controlling the element (32) according to the data read from memory (28); - measuring the brightness of the element; - comparing the brightness to a defined value; - if the brightness differs from the defined value, modifying the value of said data by programming and resetting steps.

Images