Substrate containing nanowires

Abstract

A microstructured substrate comprising a main body and a plurality of elongated elementary microstructures extending from the main body; the microstructured substrate comprises a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the elementary microstructures extending from the main body over said area. Figure 7.

Description

Title of the invention: Substrate comprising nanowires

[0001] The present invention relates to the field of micro-energy storage devices, and more particularly, but not exclusively, to planar and / or microstructured substrates incorporating on their surface substructures with dimensions measurable at the nanometer scale. The manufacturing process for said substructures is also an object of the present invention.

[0002] Bibliographical references in the following text are noted in this way in the description text: [] ; and listed in the reference table. State of the art

[0003] The substrates used in the manufacture of energy storage devices are, for example, made from supports produced in semiconductor or dielectric materials and can be in the form of a thin disk, also known as a "wafer". Initially, such a support has a flat surface corresponding to a two-dimensional, 2D topology. However, depending on the substrate's intended use, it is advantageous to etch the substrate surface at the microscale or nanoscale so that it has a three-dimensional, 3D topology, thus defining a microstructured or nanostructured substrate.

[0004] Such a microstructured substrate has a useful surface, i.e. the developed surface, greater than a flat (or smooth) substrate, a microstructured substrate allows for example the deposition of a greater quantity of materials on its surface and more particularly on the lateral surfaces of the microstructures, which can for example improve the performance of an electrical energy storage device, increase the number of components that can be integrated on a substrate, etc.

[0005] Microstructured silicon substrates exhibiting a surface area gain due to their rough structure are described, as for example in patent application [1]. Such a microstructured structure is generally achieved by a surface treatment such as chemical or physical etching, microstructure growth, or electrolytic deposition of materials inside micrometric or even nanometric molds, followed by mold dissolution.

[0006] Energy storage devices are not exempt from the constant need to miniaturize electronic components and there is a permanent need to develop solutions that make it possible to increase the visible usable surface outside the substrates while maintaining the dimensions of the original support from which the substrate is made; and this is all the more important as it is proven that increasing the usable surface improves the performance of all-solid-state micro-batteries, microcapacitors or micro-supercapacitors.

[0007] To meet this demand, a first objective of the present invention is to modify the surface of a micro-structured or nanostructured substrate to increase its useful surface area.

[0008] Furthermore, it is known to use processes for forming thin films of materials on substrates, for example, processes for producing layers of lithia-based materials. These layered substrates are notably used in batteries, for example for the formation of electrodes or electrolytic barriers, or any other electrical storage device. These layers can be deposited by an atomic layer deposition technique (known as ALD in English and commonly referred to by the acronym ALD) from precursors, by a chemical vapor deposition technique (known as ALCVD in English and commonly referred to by the acronym ALCVD), or by an atomic layer epitaxy deposition technique (known as ALE in English and commonly referred to by the acronym ALCVD).In particular, the ALD technique is a thin film deposition technique that relies on gas-surface reactions to expose the surface on which a layer of material is to be deposited to different successive chemical precursors.

[0009] Patent application [2] describes a process involving the atomic layer deposition of a precursor of a first metal, such precursor being an organometallic complex comprising, for example, a transition metal (nickel, etc.) or another type of metal such as aluminum; said process making it possible to manufacture a compound containing thin layers of lithiated material. Such layers have thicknesses of 1 nm to 1 pm, are made of complex, electrochemically active materials, and are, among other things, homogeneous and adapted to conform to the more or less complex surface features of a microstructured substrate.

[0010] A second objective of the present invention is to modify the surface of a substrate to increase its useful surface area by implementing such layer deposition processes compatible with microstructured substrates whose surface is complex and difficult to access by all surface treatment processes of the prior art. Description of the invention

[0011] The present invention relates to a microstructured substrate comprising a main body and a plurality of elongated elementary microstructures extending from the main body, characterized in that the microstructured substrate comprises a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the elementary microstructures extending from the main body on said area. Such a configuration of the substrate incorporating the nanowires makes it possible to increase the developed surface area by at least a factor of 10, and thus to improve the storage capacity of a storage device incorporating the aforementioned substrate.

[0012] In the context of the present invention, the term "microstructured" or "microstructure" applies indifferently to surfaces having reliefs whose shapes have dimensions that are measurable at both the microscale and the nanoscale.

[0013] Preferably, the elementary microstructures of elongated shape are micropillars or microtubes (which are micropillars hollowed out in their centers).

[0014] The main body and the elementary microstructures which extend over said main body of the microstructured substrate according to the invention are advantageously made of the same material, preferably a material selected from materials comprising, or even composed exclusively of, silicon Si, silicon dioxide SiO2, gallium arsenide GaAs, silicon nitride Si3N4 and indium phosphide InP.

[0015] Preferably, the elementary microstructures comprise a section chosen from a circular, elliptical, rectangular, square and triangular section.

[0016] Preferably, the nanowires comprise a material selected from oxides, preferably selected from SiO2, ZnO and TiO2, and preferably the nanowires are exclusively composed of SiO2.

[0017] Preferably, the nanowires have a cross-sectional diameter of 20 to 250 nm and a length of 100 nm to 10 pm. Advantageously, the nanowires have a cross-sectional diameter of 50 to 200 nm and a length of 0.5 to 2 pm. The structure of these nanowires is characterized by an electron microscopy technique, and more particularly by scanning electron microscopy (SEM), and the evaluation of the dimensions and structures of the nanowires is carried out from the images collected by this technique.

[0018] Preferably, the area containing nanowires has a surface area 2 to 50 times the surface area of ​​the area without nanowires, and advantageously 10 to 40 times, or even 15 to 35 times. The surface area gain due to the presence of the nanowires is measured indirectly by electrochemical method using a capacitive, faradaic, or pseudo-capacitive material whose electrochemical properties are intrinsic to the surface area. The surface area represents the total surface area introduced through the creation of porosities and crevices by adding micro- and nano-objects compared to the initial object; this is generally represented by a surface area gain that is a numerical value greater than 1 (1 being the surface area gain of the initial object).

[0019] The present invention also relates to a method for manufacturing a flat substrate or a microstructured substrate previously described in the context of the invention, comprising the following steps: a- to cover a flat or microstructured support with a thin layer of SiO2; b- to deposit a layer of an unoxidized metal by an atomic layer deposition technique; c- carry out an optical lithography step on at least one area of ​​the surface of the flat or microstructured support having undergone steps a- and b-; d- to perform an etching treatment; and e- carry out thermal annealing, preferably by implementing at least one temperature plateau.

[0020] Step a- advantageously comprises a deposition of a nanometric thin film of SiO2 by low pressure chemical vapor deposition, also known by the Anglo-Saxon term "low pressure Chemical vapor deposition", also designated by the acronym "LP CVD".

[0021] Step b- comprises atomic layer deposition, also known by the acronym ALD. Layers deposited by such an atomic layer deposition technique are deposited from precursors, as described in reference [2], by a chemical vapor deposition technique (also known as ALCVD), or by an atomic layer epitaxy deposition technique (also known as ALE). In particular, the ALD technique is a thin-film deposition technique that relies on gas-surface reactions to expose the surface on which a layer of a material is to be deposited to different successive chemical precursors.

[0022] Step c- of optical lithography to limit the growth of SiO2 nanowires only on the areas of the substrate where the presence of the nanowires is desired. This step allows the formation of a resin mask that protects these areas of interest on the substrate, where the presence of the nanowires is desired, and which are areas of interest of a few mm2, and leaves the precursor material (the catalyst) exposed on the rest of the substrate surface.

[0023] The step d- of dry etching the catalyst in order to retain it only on the areas of interest is advantageously carried out by reactive thermal etching, also designated by the acronym "RIE", preferably the RIE etching is an etching using an RIE-ICP apparatus marketed as a reactor by the company Sentech®, for example, a device known under the reference Sentech SÎ500 (ICP-RIE). Such dry etching is based on the generation of a reactive plasma based on a Cl2 / Ar gas mixture (10 cm³, 30 cm³) in a reactor at a pressure of 5 mTorr, preferably at 10°C.

[0024] Step e- is advantageously an annealing process employing a vapor-liquid-solid synthesis technique, also known by the acronym "VLS"; such a technique has the advantage of not requiring the use of a gas-phase silane precursor as classically described in the literature. Growth is directly correlated, on the one hand, to the transition to the gas phase of the SiO2 thin film generated in step a- and, on the other hand, to the presence of the catalyst generated in step b-. Advantageously, step e- comprises at least two stages: the first stage enabling the formation of metallic clusters in order to control the diameter of the future nanowires; the second stage enabling the growth of the nanowires.

[0025] Preferably, the unoxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh, and Pd, preferably Pt. It should be noted that the precursor of the first metal can be in liquid or powder form. For example, the precursor of the first metal can be chosen from the following precursors: MeCpPtMe3, FeCl2, FeCp2, Fe(thd)3, La(thd)3, CoCp2, MnCp2, Mn(thd)3, NiCp2, TiCl4, NbOEt5, Cr(OCl)2, preferably MeCpPtMe3.

[0026] Preferably, step e- comprises two temperature steps: a first step from 200 to 1200°C applied for less than 5 min; and a second step from 300 to 1400°C applied for less than 15 min.

[0027] The present invention also relates to the use of a micro-structured substrate as previously presented in the context of the invention for the manufacture of a micro-energy storage device, preferably selected from micrometer-sized or even nanometer-sized batteries, supercapacitors and dielectric and electrolytic capacitors, energy harvesting components or a sensor-type device requiring the use of a large specific surface area.

[0028] The present invention is also described in the detailed description that follows, with reference to the experimental part which details certain embodiments by means of examples, given only by way of illustration and which should not be considered limiting, and the figures briefly described in the part that follows. Brief description of the figures

[0029] [Fig.1] - [Fig.1] represents an XRR (X-Ray Reflectometry) measurement on a thin layer of NiO deposited by ALD on a silicon substrate;

[0030] [Fig.2] - [Fig.2] represents a SEM (Scanning Electron Microscopy) view following the synthesis of nanowires by the VLS (Vapor-Liquid-Solid mechanism);

[0031] [Fig.3] - the [Fig.3] represents the rapid thermal annealing (RTA) profile used for the growth of SiO2 nanowires;

[0032] [Fig.4] - [Fig.4] represents XRR measurements of Pt thin films of 5, 10, 15, 20 nm thickness;

[0033] [Fig. 5] - [Fig. 5] represents images obtained by SEM for a SiO2 layer thickness of 15 nm and a Pt layer thickness of 10 nm

[0034] [Fig.6] - [Fig.6] represents a magnification by SEM on the surface of a substrate which has undergone annealing at 900°C for 1 min;

[0035] [Fig.7] - [Fig.7] represents a magnification by SEM on the surface of a substrate which has undergone annealing at 950°C for 1 min;

[0036] [Fig.8] - [Fig.8] represents a magnification by SEM on the surface of a substrate which has undergone annealing at 900°C for 1 min, followed by annealing at 1050°C for 3 min;

[0037] [Fig.9] - [Fig.9] represents a magnification by SEM at the surface of a substrate that has undergone annealing at 950°C for 1 min, followed by annealing at 1100°C for 3 min; and

[0038] [Fig. 10] - the [Fig. 10] represents the normalized surface capacitance as a function of the scanning speed of thin films of RuO2 deposited on different types of substrates allowing the estimation of the effective electrochemical gains. Experimental Section

[0039] Materials and methods The reagents used are marketed by STREM® Chemical and used without further purification.

[0040] Measurement of surfaces Area Enhancement Factor (AEF) is measured indirectly by cyclic voltammetry in a three-electrode cell. The electrolyte used is 0.5 M diluted sulfuric acid (H₂SO₄). The reference electrode is an Ag / AgCl electrode, the counter electrode is platinum, and the working electrode is the fabricated sample coated with a thin layer of platinum (30 nm) deposited by ALD (the substrate microstructure, the hierarchical backbone). The scan rate is 50 mV / s.

[0041] Measurement of the thicknesses of the deposited thin films The thickness of the layers is measured by X-ray reflectivity (XRR), an interferometric technique that provides quantitative information on interface roughness, density, and the thickness of thin, amorphous layers. or not. After a phase of aligning the height and surface of the sample, the measurement is performed. Such a measurement consists of directing an X-ray beam onto the surface of a sample at a small angle of incidence theta and collecting the reflected intensity. A measurement allowing the reflected intensity to be plotted as a function of the angle of incidence (20) is obtained, as shown in [Fig. 1]. The curve generally describes a plateau for 20 < 0C, where 0C corresponds to the critical angle, followed by a decay with one or more oscillations whose period is related to the layer thickness via the following relationship: 0m2 = j 2 + 0C2 equation 1 With m, the order of oscillations and 0m the corresponding angle in radians as illustrated in [Fig.1] and d, the thickness of the layer.

[0042] The slope of the oscillations allows us to determine the surface roughness. And the change in slope after the oscillations allows us to determine the layer density. X-ray reflectivity is a technique that allows us to accurately measure the thickness of a thin film (from approximately 5 to 100 nm) using Equation 1, provided that the layers are not very rough, making it a preferred technique for the ALD coatings performed in this work. The X-ray reflectivity measurements were carried out on a SMARTLAB® rotating copper anode system from Rigaku®.

[0043] The observation of the surface topography of the samples was carried out by scanning electron microscopy (SEM) in top view, cross-section and grazing incidence using a FEI Magellan 400™.

[0044] The size distribution of the nanowires is carried out by SEM and the size measurements of the nanowires are performed with the ImageJ™ software.

[0045] Within the framework of the invention, a mass percentage expressed in % w / w defines the percentage by mass of an ingredient used in the preparation and taken in relation to the total mass of the object considered: a mixture, a material (composite, etc.), a membrane, etc. Examples

[0046] Part 1: Synthesis of a Silicon oxide SiO2 by dry oxidation (LP CVD, Low Pressure Chemical Vapor Deposition) -Wafer cleaning: piranha (mixture of sulfuric acid H2SO4 and hydrogen peroxide H2O2) 1:1 (20 min), rinse with deionized water, dry with N2, HF 1% (2 min), rinse with edi, dry with N2; -Introduction of the silicon wafer into the oven at 500°C, under 2 sim (standard litre per minute, at T=0°C and P=lbar) of N2; -Temperature rise up to 675°C for 30 min (10°C / min); -Temperature rise to 900°C for 1 h (10°C / min); -Pre-oxidation at 900°C for 30 min, with 2 sim of N2 and 0.2slm of O2; -Oxidation at 900°C for 42 min (15 nm of SiO2 - deposition rate 0.357 nm / min), with 2slm of O2; -Temperature descent to 500°C for 1 hour, with 2slm of N2.

[0047] Part 2: Deposition of a Pt catalyst by atomic layer (ALD, Atomic Layer) Deposition)

[0048] A layer of platinum is deposited by ALD, the reactants are "Pt" and dioxygen.

[0049] The sample obtained in Part 1 is placed in the ALD chamber (Beneq model TFS200), the pressure is lowered to 2 mBar and the temperature is adjusted to 300°C.

[0050] To form an atomic monolayer, several steps (corresponding to a cycle) are necessary: ​​nitrogen is injected for 500 ms into the source containing a first reactant (1), which is MeCpPtMe3, i.e., (trimethyl)methylcyclopentadienylplatinum(IV), declared 99% pure from STREM® Chemical, the temperature of which is maintained at 54°C. A waiting time of 100 ms is observed to pressurize the precursor chamber, then the source is opened for a duration of 500 ms (pump time). A 2-second purge is then performed to remove excess species and reaction products. A second reactant (2) in the form of gaseous O2 is then injected for a duration of 500 ms, followed by a 1-second purge. The deposition rate is 0.83 Â / cy (Angstroms per cycle) and allows precise control of the deposited thickness from 5 to 60 nm.

[0051] Part 3: Optical lithography to select areas of interest

[0052] 1-Cleaning and deoxidation of the wafer:

[0053] The plate obtained in part 2 is placed in a beaker of acetone for 5 min and then in isopropanol for 5 min, allowing the plate to be degreased. The plate is then dehydrated at 110°C for 10 minutes.

[0054] 2-Resin coating and sun exposure:

[0055] Coating of an adhesion promoter HMDS (speed = 2000 revolutions per minute (rpm); acceleration = 1000 revolutions per minute per second (rpm / s); time = 20s).

[0056] Coating with AZ1505 resin (speed = 3000 revolutions per minute; acceleration = 1000 revolutions per minute per second; time = 20s).

[0057] Annealed for 1 minute at 110°C, no relaxation time.

[0058] 3s exposure in Hardcontact, no relaxation time.

[0059] Development 50s in MIF 726 then 30s in deionized water.

[0060] This optical lithography allows the formation of a resin mask which protects the areas of interest of a few mm2 and leaves the platinum "exposed" over the entire substrate.

[0061] Part 4: Dry etching of the catalyst to preserve it only on the areas of interest

[0062] Platinum etching is performed by RIE-ICP (Sentech®). This dry physicochemical etching process is achieved through the physical attack of a Cl2 / Ar plasma (10 cm⁻¹, 30 cm⁻¹) in a reactor at a pressure of 5 mTorr and a temperature of 10°C. The ICP source generates a high-density plasma through inductive coupling between the RF antenna and the plasma. The RF antenna creates an alternating RF magnetic field and induces RF electric fields that accelerate the electrons involved in the ionization of the gas molecules. For platinum etching, the power of the source is set at 600 W, while that of the RF generator is set at 200 W. The etching speed is 2.8 Å / s (Angstroms per second, or 10⁻¹⁰ meters per second: this is the speed at which the platinum is etched to be structured).

[0063] Part 5: Rapid Thermal Annealing (RTA)

[0064] Annealing is carried out by respecting two stages under a nitrogen atmosphere in a Flash annealing furnace marketed by the company Jipelec®.

[0065] The synthesis technique employed is described as vapor-liquid-solid (VLS). A first step at 1000°C (10°C / sec) is maintained for 1 min to dewet the Pt catalyst. During this step, small Pt clusters, which are droplets a few tens of nanometers in diameter, form on the surface of the SiO2 and SiO in the vapor phase. The SiO diffuses into the droplets and precipitates at the metal / substrate interface during a second supersaturation / precipitation phase. This results in the growth of the SiO2 nanowires. The growth is directly correlated to the transition to the gaseous phase of the SiO2 layer previously synthesized on the substrate in Part 1 and to the presence of the catalyst (here, platinum).

[0066] A second step at 1100°C is maintained for 5 min to promote the growth of the SiO2 nanowires. The diameter, length, and density (number of nanowires per mm2) of the SiO2 nanowires are controlled by the properties of the initial SiO2 and Pt thin films, as well as by the annealing parameters (temperature and holding time of the high-temperature steps). The first step allows the formation of Pt clusters to control the diameter of the future nanowires, and the second step induces the growth phenomenon by controlling the length of the nanowires. A SEM image is shown in [Fig. 2], with a scale bar to observe the dimensions of the nanowires. [Fig. 3] shows the temperature profile of the steps as a function of time. Analyses and results

[0067] Different silicon samples were treated after thermal annealing by controlling different thickness parameters of the SiO2 thin film and the Pt layer (5, 10, 15, 20 nm). The Pt thin films were measured by XRR; the diagrams are shown in [Fig. 4].

[0068] The samples are observed by SEM microscopy.

[0069] By varying the thickness of SiO2 from 10 to 15 nm, the inventors observed the presence of very strong nanowires in the form of matchsticks which are strictly perpendicular to the surface with an average length greater than 1 pm and a diameter that can be greater than 80 nm.

[0070] A statistical study of SEM images makes it possible to determine the average diameter and length parameters of the nanowires. The general method consists of analyzing the images by means of a processing that delimits the boundaries of the objects that compose them. An image analysis then makes it possible to count, pixel by pixel, the space occupied by each object (length, diameter, intersections with other objects, surfaces, etc.).

[0071] The results are shown in Table 2 for a Pt layer thickness of 15 nm: [Tables 2] SiO2 layer thickness (nm) Average diameter (nm) Average length (pm) 5 30-47 12-20 10 33-53 15-20 15 32-70 2-3 20 47-75 1-3

[0072] Other results are shown in Table 3 for a SiO2 layer thickness of 15 nm and a Pt layer thickness of 10 nm, and the resulting images are shown in [Fig. 5]: [Tables 3] Sample Number Average Diameter (nm) Average Length (pm) 1 70-100 0.9-1 2 79-90 1.4-1.6 3 104-120 1.2-1.4 4 114-145 1.09

[0073] Study of phenomena related to temperature plateaus:

[0074] The role of the two annealing stages was determined using SEM images. The first stage allows the dewetting of the platinum via the formation of Pt droplets on the surface, beneath which the evaporated SiO2 condenses during the second temperature stage: -the [Fig.6] corresponds to a substrate that has undergone annealing at 900°C for 1 min; -the [Fig.7] corresponds to a substrate that has undergone annealing at 950°C for 1 min; -the [Fig.8] corresponds to a substrate that has undergone annealing at 900°C for 1 min, then to 1050°C for 3 min; -the [Fig.9] corresponds to a substrate that has undergone annealing at 950°C for 1 min, then at 1100°C for 3 min.

[0075] Figures 6 to 8 show the importance of the first step in promoting the dewetting of the catalyst (Pt) for nanowire growth. Figure 8 shows in particular that the first step at 900°C is insufficient to promote growth during the second step. Figure 9 shows that a first step at 950°C followed by a second at 1100°C allows for the initiation of growth. Figure 9 also shows the importance of the duration of the second step on the length of the nanowires, which is applied here for a duration of 3 min (whereas for the other results described in this experimental section, the second step is applied for 5 min).

[0076] Measurement of the surface area gain provided by the nanowires:

[0077] The inventors have demonstrated that the high surface area capacity of the components incorporating the substrates according to the invention is intimately linked to their structure, even when said structure comprises an infinite number of complex structural elements from a material architecture point of view, or even highly intertwined with one another. The high surface area capacity consists of a large surface area relative to the projected surface area, this being provided by the presence of micropillars (microstructured substrate) covered by nanowires. The methodology adopted to determine the surface area gain consists of using a parameter designated by the English term "Area Enlargement Factor," also known by the acronym "AEF," and comparing the AEF of the different structures and the contribution of each of them, the AEFs being measured independently, first on a 2D flat surface, then on a 3D and 2D surface with nanowires and 3D with nanowires.

[0078] The various measurements were carried out under the same conditions to calculate the surface gain (AEF) measured by cyclic voltammetry in a 3-electrode cell. The electrolyte used was 0.5M diluted sulfuric acid (H2SO4), the reference electrode was an Ag / AgCl electrode, the counter electrode was platinum, and the working electrode was platinum (30 nm) deposited by ALD on the sample to be measured (the microstructured "skeleton"). The scan rate was 50 mV / s. The projected surface seen The measurement area is 0.407 cm². The results are presented in Table 4 below: [Tables 4] Samples Area Surface (cm2) AEFMe sure 2D Structure (reference plane surface) 0.00473 0.45 1.1 3D Structure - Expected Gain 18 0.03347 3.22 18.6 3D Structure - Expected Gain 55 0.0972 8.83 57 Nanowires 10 nm SiO2 -5 nm Pt 0.08085 7.77 19.1 Nanowires 10 nm SiO2 -10 nm Pt 0.07281 7.00 17.2 Nanowires 15 nm SiO2 -10 nm Pt 0.01693 1.63 4.00 Nanowires 15 nm SiO2 - 20 nm Pt 0.00721 ​​0.63 1.7

[0079] Thus, Table 4 shows that the measurement method makes it possible to derive the calculated 3D gains (table entries in rows 3 and 4) from the models of 3D microtube-type structures. This method demonstrates that nanowires provide a surface area gain of 2 to 19 in the examples cited in the remainder of Table 2, corresponding to entries in rows 5 to 8, respectively.

[0080] An identical measurement was carried out using a supercapacitor electrode material (RuO2) which shows a gain of 10 on microstructures exhibiting a gain of 50 (i.e., a total surface area gain of 50 x 10 = 500). It was thus shown that the surface area gain of the microstructures is between 50 and 70, that of the nanowires between 4 and 10. Figure 10 shows the capacitance as a function of the scanning speed of RuO2 thin films on different types of substrates. The inventors were thus able to demonstrate, quite unexpectedly, that the cumulative gains do not add up but multiply, allowing gains to be reached between 200 and 700. Figure 10 also shows the capacitance of RuO2 thin films, enabling a surface area gain of 50 (squares) for a typical structure. microtube and 500 (circles) on hierarchical substrate relative to a flat surface (triangles). References

[0081] The following table lists the references cited earlier in the text: [Tables 1] 1 WO2015 / 052412 2 WO2022 / 069842

Claims

Demands

1. Microstructured substrate comprising a main body and a plurality of elongated elementary microstructures extending from the main body, characterized in that the microstructured substrate comprises a plurality of nanowires positioned on at least one area of ​​the surface of the main body and on the surface of the elementary microstructures extending from the main body over said area.

2. Microstructured substrate according to claim 1, wherein the main body and the elementary microstructures extending over said main body are made of the same material, preferably a material selected from materials comprising, or even composed exclusively of, Silicon, Silicon dioxide SiO2, gallium arsenide GaAs, silicon nitride Si3N4 and indium phosphide InP.

3. Microstructured substrate according to any one of claims 1 or 2, wherein the elementary microstructures comprise a section selected from a circular, elliptical, rectangular, square and triangular section.

4. Microstructured substrate according to any one of claims 1 to 3, wherein the nanowires comprise a material selected from oxides, preferably selected from SiO2, ZnO and TiO2, and preferably the nanowires are exclusively composed of SiO2.

5. Microstructured substrate according to any one of claims 1 to 4, wherein the nanowires have a diameter cross-section of 20 to 250 nm, and a length of 100 nm to 10 pm.

6. Microstructured substrate according to any one of claims 1 to 5, wherein the areas containing nanowires have a developed surface area of ​​2 to 50 times the developed surface area of ​​said area devoid of nanowires.

7. A method for manufacturing a microstructured substrate according to any one of claims 1 to 6, comprising the following steps: a- coating a microstructured support with a thin layer of SiO2; b- depositing a layer of an unoxidized metal by an atomic layer deposition technique; c- performing optical lithography on at least one area of ​​the surface of the microstructured support having undergone steps a- and b-; d- carry out an etching treatment; and e- carry out a thermal annealing, preferably by implementing at least one temperature plateau.

8. A method for manufacturing a micro-structured substrate according to claim 7, wherein the unoxidized metal deposited in step b- is selected from Pt, Ag, Au, Ga, In, Ti, Sn, Zn, Sb, Cu, Ni, Be, Fe, Co, Cr, Al, Ru, Rh and Pd, preferably Pt.

9. A method for manufacturing a micro-structured substrate according to claim 8, wherein step e) comprises two temperature steps: a first step from 200 to 1200°C applied for less than 5 min; and a second step from 300 to 1400°C applied for less than 15 min.

10. Use of a microstructured substrate according to any one of claims 1 to 6, for the manufacture of a micro-energy storage device, preferably selected from micrometer-sized or even nanometer-sized batteries, supercapacitors and dielectric and electrolytic capacitors, energy harvesting components or a sensor-type device requiring the use of a large specific area.

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