Neuromorphic circuit

Abstract

Neuromorphic Circuit This description concerns a neural circuit (200) comprising: - a first plurality of synapses, each comprising a first resistive memory element having an associated parasitic capacitance, each of the first resistive memory elements being configured to supply a current to a first common conductive line (SL); and - an output device (206) configured to compare a first voltage on the first common conductive line to a threshold voltage (Δ) and to generate an output voltage (Δ) of the neural circuit based on the comparison. Figure for the abstract: Fig. 2

Description

Title of the invention: Neuromorphic circuit Technical field

[0001] The present description relates generally to a neuromorphic circuit and, more particularly, to a neuromorphic circuit implemented using resistive random access memory (RRAM). Prior art

[0002] Neuromorphic circuits have been proposed to reproduce the main characteristics of a biological neuron. Such circuits are configured to integrate signals, coming from other neuromorphic circuits, over time.

[0003] Conventional neuromorphic circuits are based on CMOS (Complementary Metal Oxide Semiconductor) technology. Static random access memory (SRAM) or resistive random access memory (RRAM) is used to store the equivalent of the synaptic coefficient. Large capacitors are used to implement dynamic neurons, equivalent to the membrane potential of a biological neuron. Alternatively, digital solutions can be used, by sampling signals and copying them to an external memory.

[0004] However, the use of large capacitors or digital solutions generally requires excessive power consumption and / or circuit area. Summary of the invention

[0005] There is a need in the state of the art to implement neuromorphic circuits which overcome all or part of the problems of the state of the art.

[0006] Embodiments of the present description overcome all or part of the disadvantages of known neural circuits.

[0007] According to one aspect, a neural circuit is provided comprising: - a first plurality of synapses, each comprising a first resistive memory element having an associated parasitic capacitance, each of the first resistive memory elements being configured to supply a current to a first common conductive line; and - an output device configured to compare a first voltage on the first common conductive line to a threshold voltage and to generate an output voltage of the neural circuit based on the comparison.

[0008] According to one embodiment, the output device is a voltage comparator configured to generate a transition of the output voltage of the neural circuit when the first voltage exceeds the threshold voltage.

[0009] According to one embodiment, the output device is a voltage amplifier configured to generate an analog output voltage.

[0010] According to one embodiment, the neural circuit further comprises a first delay circuit connected to an output of the voltage comparator and configured to reset the first voltage on the first common conductive line in response to the transition of the output voltage.

[0011] According to one embodiment, the first resistive element of each synapse is connected to an output of an additional corresponding neural circuit.

[0012] According to one embodiment, the first resistive element of each synapse is connected to a supply voltage via a corresponding first transistor, each of the first transistors having its gate connected to an output of an additional corresponding neural circuit.

[0013] According to one embodiment, each synapse further comprises a second resistive memory element having an associated parasitic capacitance, each of the second resistive memory elements being configured to supply a current to a second common conductive line, the second conductive line supplying the threshold voltage to the output device.

[0014] According to one embodiment, the second resistive element of each synapse is connected to the output of the additional corresponding neural circuit.

[0015] According to one embodiment, the second resistive element of each synapse is connected to the supply voltage via a corresponding second transistor, each of the second transistors having its gate connected to an output of the additional corresponding neural circuit.

[0016] According to one embodiment, the neural circuit further comprises a second delay circuit connected to the output of the voltage comparator and configured to reset the threshold voltage on the second common conductive line in response to the transition of the output voltage.

[0017] According to one embodiment, the first resistive memory elements are ferrotunnel junction elements.

[0018] According to one aspect, there is provided a neural network comprising a plurality of layers of neural circuits as described above. Brief description of the drawings

[0019] These characteristics and advantages, as well as others, will be explained in detail in the following description of particular embodiments given without limitation in relation to the attached figures among which:

[0020] [Fig.l] schematically represents a hardware implementation of a circuit CMOS-based pulsed neural array according to one embodiment that has been proposed;

[0021] [Fig.2] schematically represents a neural circuit based on RRAM according to an embodiment of the present description;

[0022] [Fig.3] schematically represents a RRAM-based neural circuit according to another embodiment of the present description;

[0023] [Fig.4] represents an example of a ferro-tunnel junction stack and its equivalent circuit;

[0024] [Fig.5] schematically represents a RRAM-based pulse neural circuit according to an embodiment of the present description;

[0025] [Fig.6] is a timing diagram representing voltages present in the RRAM-based pulsed neural circuit of [Fig.5] according to an exemplary embodiment;

[0026] [Fig.7] schematically represents an RRAM-based neural circuit having a differential structure according to an embodiment of the present description;

[0027] [Fig.8] schematically represents an RRAM-based pulse neural circuit having a differential structure according to an embodiment of the present description;

[0028] [Fig.9] is a timing diagram representing voltages present in the RRAM-based pulsed neural circuit of [Fig.8] according to an exemplary embodiment;

[0029] [Fig. 10] is a timing diagram representing voltages present in the RRAM-based pulsed neural circuit of [Fig. 8] according to another exemplary embodiment;

[0030] [Fig.l 1] schematically represents an analog neural circuit based on RRAM having a differential structure according to another embodiment of the present description;

[0031] [Fig. 12] is a timing diagram representing voltages present in the RRAM-based analog neural circuit of [Fig. 11] according to an exemplary embodiment of the present disclosure; and

[0032] [Fig. 13] schematically represents a neural network consisting of a plurality of neural circuits according to an exemplary embodiment of the present description. Description of the embodiments

[0033] The same elements have been designated by the same references in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same references and may have identical structural, dimensional and material properties.

[0034] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and are detailed. For example, circuits and methods for programming the resistance of a resistive memory element have not been described in detail, the selection of appropriate circuits and methods depending on the particular type of resistive memory element falling within the skills of the person skilled in the art.

[0035] Unless otherwise specified, when referring to two elements connected to each other, this means directly connected without intermediate elements other than conductors, and when referring to two elements connected (in English "coupled") to each other, this means that these two elements can be connected or be connected by means of one or more other elements.

[0036] In the various embodiments, transistors are described as having main conduction nodes and a gate node, without limitation to any particular transistor technology. The person skilled in the art will understand that, in the case where the transistors are implemented by MOS transistors, the main conduction nodes are the source and the drain. Unless otherwise specified, the MOS transistors are N-channel devices, although the person skilled in the art will know how to adapt the embodiments to the case of P-channel MOS transistors. It would also be possible to use other transistor technologies. For example, in the case of bipolar transistors, the main conduction nodes are the collector and emitter and the gate is implemented by the base.

[0037] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "upper", "lower", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made unless otherwise specified to the orientation of the figures.

[0038] Unless otherwise specified, the expressions "about", "approximately", "substantially", and "of the order of" mean to within 10%, preferably to within 5%.

[0039] [Fig.l] schematically represents a hardware implementation of a CMOS-based pulsed neural circuit 100 according to one embodiment that has been proposed. For example, the neural circuit 100 is part of a neural network (not shown in [Fig.l]) comprising a plurality of neural circuits similar to the circuit 100.

[0040] The neural circuit 100 comprises three stages.

[0041] A first stage 102 comprises for example a resistive random access memory (RRAM) matrix. For example, the RRAM matrix 102 comprises a number Af + 1 of programmable resistive elements Go to GN implementing the synapses of the neural circuit 100. Each resistive element Gb ie {O, ..., N} has for example a first electrode, for example its lower electrode, connected to a supply voltage rail at a voltage V hM via a corresponding transistor Tb Each transistor T15 ig {0, ..., N} has its gate connected to receive a corresponding voltage V^ i G {0, ..., TV} provided by another neural circuit of the neural network or by an input node of the neural network. Each resistive element Gh ie {0, ..., N} has for example a second electrode, for example its upper electrode, connected to a common conductive line SL. Thus, the RRAM matrix 102 consists of N + 1 branches connected between the conductive line SL and the supply voltage rail V^ each branch comprising the series connection of a resistive element Gb i G {0, ..., N} and a transistor T).

[0042] A second stage 104 of the neural circuit 100 is a current replication circuit having an analog CMOS implementation and configured to generate a current on its output line 105 which is equal to or proportional to the sum of the currents flowing through the A^ + 1 branches of the RRAM matrix 102. For example, the current replication circuit 104 comprises a transistor Mt connected by its main conduction nodes between a supply voltage rail at a voltage Vdd and the conductive line SL and a transistor M2 connected by its main conduction nodes between the supply voltage rail Vdd and the output line 105. The supply voltage Vdd is for example greater than the supply voltage Vbot.The current replication circuit 104 further comprises an operational amplifier 106 having a positive input connected to the conductive line SL, a negative input connected to a threshold voltage Vth and its output connected to the gates of the transistors Mj and M2. The threshold voltage Vth is an intermediate voltage between the voltages Vhot and Vdd and the operational amplifier 106 is for example configured to adjust the gate voltage of the transistors Mj and M2 so that the voltage on the conductive line SL is equal to the threshold voltage VJh. Thus, the transistor M2 conducts a current Iout equal to or proportional to the current in the transistor Mb. The current replication circuit 104 further comprises a transistor M3 connected in series with the transistor M2, having for example its main conduction nodes connected respectively to the output line 105 and to ground (GND).The gate of transistor M3 is for example connected to output line 105, which supplies a current to the third stage 108. For example, the current supplied by output line 105 charges a capacitor (not shown) of the third stage 108.

[0043] A third stage 108 comprises for example a differential pair integrator (DPI) synapse 110 (DPI SYNAPSE) and a leaky integrate-and-fire (LIF) neuron 112. The DPI synapse 110 receives for example the output signal from the current replication circuit 104 and performs an integration of this signal. The LIF neuron 112 receives for example the integrated signal from the DPI synapse 110 and generates a output voltage Vmit having a pulse when the integrated signal exceeds a threshold.

[0044] A problem with the neural circuit 100 of [Fig.l] is that relatively high capacitances are present in the DPI synapse 110 and the LIF neuron 112, leading to relatively large power consumption and area. This is a serious problem as the complexity of the neural network increases, involving a relatively large number of neurons.

[0045] [Fig.2] schematically represents a neural circuit based on RRAM 200 according to an exemplary embodiment of the present description.

[0046] The neural circuit 200 comprises an input stage 202 and an output stage 204.

[0047] The input stage 202 comprises, for example, a resistive RAM matrix (RRAM). For example, the RRAM array 202 comprises a number N + 1 of programmable resistive elements Go to GN implementing the synapses of the neural circuit 100. Similar to the neural circuit 100 of FIG. 1, each resistive element Gi5 i G {0, ..., N} has for example one of its electrodes, for example its upper electrode, connected to a common conductive line SL.

[0048] Each resistive element G,, ie {0, ..., N) of the memory matrix 202 has for example a first electrode, for example its lower electrode, connected to a supply voltage rail V hot via a corresponding transistor T,. Each transistor F, ie {0, ..., N) has for example its gate connected to receive a corresponding voltage i G {0, ..., TV} provided by another neural circuit of the neural network or by an input node of the neural network. Thus, the RRAM matrix 202 is made up of N + 1 branches connected between the conductive line SL and the supply voltage rail, each branch comprising the series connection of a resistive element Gb ie {0, ..., N}, with its associated capacitance and a corresponding transistor Tj.

[0049] Therefore, the voltage VSL on the conductive line SL at a given time t respects the equation:

[0050] [Math.l] VSL =

[0051] where £ _ y N ¢2 and Vi ( S") is the individual voltage which is applied between the electrodes of the resistive element Gj at an instant, and G, is the conductivity of the resistive element G^ The voltage V (i') depends on the voltages Vbot and

[0052] Each resistive element Gi; ie [O, ..., N} has a parasitic capacitance Ch i G {0, ..., TV}, corresponding to the low capacitance effect of each resistive element. The memory type of the resistive element Gj is for example chosen so that the parasitic capacitances C; are relatively high, which leads to a relatively high capacitance at the common conductive line SL. For example, as will be described in more detail below in connection with Figure 4, in some embodiments, each resistive element Gb ie {0, ..., N} is implemented by a ferrotunnel junction element. Ferrotunnel junction elements are well known to those skilled in the art and are for example described in more detail in the publication "Low-power linear computation using nonlinear ferroelectric tunnel junction memristors" published in "Nature Electronics 3.5 (2020)" by Berdan, Radu, et al. Alternatively, it would be possible to use other types of resistive memory elements, in particular, those with relatively high parasitic capacitances, such as, for example, ferroelectric field effect transistors (FeFETs) or high-resistance OxRAM devices.

[0053] The output stage 204 of the neural circuit 200 comprises for example a comparator 206 having a positive input connected to the common conductive line SL and a negative input connected to a threshold voltage Vth- The comparator 206 is for example configured to compare the voltage on the common conductive line SL with the threshold voltage VJh and to generate a transition of an output voltage Vout of the neural circuit 200 when the voltage on the common conductive line SL exceeds the threshold voltage Vth,

[0054] According to embodiments described herein, the capacitive effect of the resistive elements G, of the memory matrix 202 replaces capacitors to be integrated in the DPI synapse and / or the LIF neural circuits of the stage 108 of FIG. 1. In particular, in operation, the common conductive line SL is charged by the sum of the currents flowing through each of the N+1 branches of the input stage 202 and the comparator 206 is used to detect the moment at which the voltage on the common conductive line SL exceeds the threshold voltage Vth and to generate a corresponding output transition in the output voltage Vout.

[0055] [Fig. 3] schematically represents an RRAM-based neural circuit 300 according to another embodiment of the present disclosure. The neural circuit 300 is similar to the neural circuit 200 of [Fig. 2] and includes the same output stage 204, but includes an input stage 302 instead of the input stage 202.

[0056] The input stage 302 is similar to the input stage 202 in that it comprises N+1 branches each comprising a resistive element G,, i £ {0. ..., N} one of the electrodes of which, for example its upper electrode, is connected to the common conductive line SL. However, instead of being connected to a transistor Tb the other electrode of each resistive element G,, i.e. {0, ..., N], which is for example its lower electrode, is connected directly to the corresponding voltage Vinj, i G {O, ..., / V] supplied by another neural circuit of the neural network or by an input node of the neural network. In other words, the transistors T; described in relation to [Fig.2] are omitted in the embodiment of [Fig.3].

[0057] The operation of the neural circuit 300 of Figure 3 is similar to that of the neural circuit 200 of Figure 2, except that the voltage applied to each resistive element Gb ie {0, .... N} is no longer a function of the supply voltage bot, but only of the corresponding input voltage Vuû, ie {0, ..., / V}.

[0058] Figure 4 shows an example of a ferro-tunnel junction (FTJ) element 400 and its equivalent circuit 400'. The FTJ element 400 is for example used to implement the resistive elements Gj in the neural circuits 200 and 300 of Figures 2 and 3.

[0059] The FTJ element 400 is for example made up of a stack of layers comprising a lower electrode 402 (BE), a layer of silicon dioxide 404 (SiO2) formed in the lower electrode 402, a layer of silicon and hafnium oxide 406 (HfSiO) formed on the layer of silicon dioxide 404 and an upper electrode 408 (TE) formed on the layer of silicon and hafnium oxide 406.

[0060] As represented by the equivalent circuit 400', the FTJ element 400 can be considered as having a leakage resistance 410 of a resistance R, in parallel with a ferro-capacitor 412 of a capacitance Cfe, the resistance 410 and ferro-capacitor 412 being in parallel with a linear capacitor 413 of capacitance The capacitance Cfe of the ferro-capacitor 412 is for example non-linear.

[0061] The 7D current flowing in an FTJ element is a tunnel current, which is not linear as a function of the applied voltage. This current is also relatively small compared to that flowing in most other types of resistive memory devices. In such a ferroelectric element, by adjusting the ferroelectric bias, a continuous tunnel current, or a Fowler Nordheim-assisted tunnel effect, can appear. This physical property allows the creation of several resistive states in FTJ elements.

[0062] The current / f» which flows in an FTJ element is described by the equation:

[0063] [Math.2] ^R + h •>

[0064] where

[0065] [Math.3] = (Vpo- A VPPlPsat) ) - 1)

[0066] and

[0067] [Math.4] Zc=^

[0068] where Ko is a trimming constant, 5 is the total area of ​​the device, V is the voltage applied between the lower and upper electrodes, and Vpo and AVP are trimming constants. Since the value P is the polarization which can essentially switch between + Pr and - Pr polarizations, depending on the actual polarization, the voltage V will switch between voltage values ​​VPO+ A VP and VPO- AVP

[0069] [Fig.5] schematically represents an RRAM-based pulse neural circuit 500. The neural circuit 500 is similar to the neural circuit 200 of [Fig.2] and includes the same input stage 202, but includes an output stage 504 replacing the output stage 204.

[0070] The output stage 504 comprises, for example, the comparator 206 having its positive input connected to the conductive line SL and its negative input connected to the threshold voltage Vth. The output of the comparator 206 is further connected to a delay circuit 508 (DELAY). The delay circuit 508 has an output connected to the gate of a transistor 510. For example, the delay circuit 508 is configured to provide the voltage transition present at the output of the comparator 506 to the transistor 510 after a delay. The delay circuit 508 is, for example, implemented by the series connection of an even number of inverters, although those skilled in the art will understand that other embodiments are possible.

[0071] Transistor 510 has its main conduction nodes connected respectively to the conductive line SL and to the ground voltage rail (GND).

[0072] In operation, when the voltage on the common conductive line SL exceeds the threshold voltage Vth, the comparator 206 generates a voltage transition of the output voltage and the delay circuit 508 and transistor 510 cause for example the voltage on the common conductive line SL to be reset to a voltage close to the ground voltage after a delay which follows the voltage transition of the output voltage VOut. Furthermore, the resetting of the voltage on the common conductive line SL in turn resets the output voltage Vout of the comparator 206. This means that, when the voltage on the common conductive line SL exceeds the threshold voltage Vth, the output stage 504 will generate a voltage pulse on the output voltage Vout, the duration of the voltage pulse being a function of the delay introduced by the delay circuit 508.

[0073] Figure 6 is a timing diagram showing voltages present in the RRAM-based pulsed neural circuit 500 described in relation to Figure 5 according to an exemplary embodiment. For the sake of clarity, a case is considered in which input pulses are present on only the input voltages Kxo and Vin,i of the transistors Tq and T\ of the neural circuit 500.

[0074] Figure 6 represents the time evolution of the output voltage Vout and the voltage Vsl on the conductive line SL as a function of the contribution of the voltages Vinp and Vin^. The voltage value VSL is represented by a curve 600 and is initially close to the ground voltage. The synchronization of the voltage pulses of the voltage Vest represented by broken lines 602 and the synchronization of the voltage pulses of the voltage V jni is represented by dashed lines 604. The output voltage Voat of the comparator 206 is represented by a curve 606. In addition, the threshold voltage Vth is represented by a broken line 608.

[0075] In the example shown in Figure 6, the input voltage has a pulse that occurs at a time Îq. For example, the voltage pulse Vùm is generated by another neural circuit. This voltage pulse causes, for example, an increase in the voltage VSc on the common conductive line SL, so that it reaches a first voltage level V,. Similarly, the input voltage has another pulse that occurs at a time 1] causing the voltage VSL on the common conductive line SL to increase to a second voltage level V2, the input voltage has a pulse that appears at a time ^2 causing the voltage sl on the common conductive line SL to increase to a third voltage level V3 and the input voltage V has another pulse that occurs at a time £3 causing the voltage VSL on the common conductive line SL to increase to a fourth voltage level V4.Then, at time ^4, the input voltage Ein,o another pulse which causes the voltage VSL on the common conductor line SL to exceed the threshold voltage Vth. .

[0076] The output stage 504 therefore generates a voltage pulse of the output voltage Vout at time I4, which continues until time ^5. The duration of the pulse is for example between 1 microsecond and 10 milliseconds. In particular, when the voltage VSL exceeds the threshold voltage Vth at time ^4, the comparator 206 outputs the rising edge of the voltage pulse. The delay circuit 508 outputs a rising edge after its delay, which activates the transistor 510, causing the voltage VSL to be discharged to the ground voltage. As soon as the voltage VSL drops below the threshold voltage Vth, the comparator 206 generates a falling edge on the output voltage Vouh completing the voltage pulse. The delay circuit 508 generates a falling edge after its delay and, at the same time, the VSL voltage continues to drop to a level close to the ground voltage, which is represented by a decreasing phase of the curve 600.

[0077] The process is then repeated for other series of pulses of the input voltages Vén,o and Vin^ between times ^6 and ^7 and the pulse at time h causes for example the voltage V SL on the common conductive line to exceed the threshold voltage Par Therefore, the output stage 504 generates the pulse on the output voltage Vout from the instant ^7 until a The transistor 510, controlled by the delay circuit 508, resets for example the voltage VSL to a voltage close to ground.

[0078] [Fig.7] schematically represents an RRAM-based neural circuit 700 having a differential structure according to an embodiment of the present description. The neural circuit 700 comprises a differential input stage 702 and an output stage 703 comprising the comparator 206.

[0079] The differential input stage 702 is similar to the input stage 302 in that it comprises a set 704 of N+1 branches each comprising a corresponding resistive element Gf, J e {0, ..., A7} which has an associated parasitic capacitance / 'e [O, ..., A}. Each resistive element G?, i G {0, ..., furthermore has one of its electrodes, for example its upper electrode, connected to the common conductive line SL. The other electrode of each resistive element Gf,? e {U • • •, N}, which is for example its lower electrode, is connected directly to the corresponding voltage Virù, i G {0, ..., N] provided by another neural circuit of the neural network or by an input node of the neural network. The common conductive line SL is connected to the positive input of the comparator 206.

[0080] The differential input stage 702 further comprises a set 706 of N+1 additional branches, each comprising a corresponding resistive element G®, i G {0, .... A] which has an associated parasitic capacitance cf,1: e {U • • •, A}. Each resistive element G®,ze {0, ..., N} further has one of its electrodes, for example its upper electrode, connected to another common conductive line SL'. The other electrode of each resistive element G?,ze {Q • • •, A}, which is for example its lower electrode, is connected directly to the corresponding voltage i G {0, ..., A}. In other words, for each i G {0, ..., A'}, the resistive elements Gf and G? are connected, for example by their lower electrode, to the same voltage zg{0, ..., A}.

[0081] In addition, the common conductive line SL' is connected to the negative input of the comparator 206.

[0082] In operation, the common conductive line SL will be charged by the sum of the currents flowing in each of the N+1 branches of the assembly 704, while the common conductive line SL' will be charged by the sum of the currents flowing in each of the N+1 branches of the assembly 706. The comparator 206 is then used to detect the moment at which the voltage Vsl on the common conductive line SL exceeds the voltage Vsl on the common conductive line SL' and to generate a corresponding output transition of the output voltage Vout.

[0083] The embodiment described in relation to figure 7 makes it possible to model co positive and negative synaptic efficiencies. Indeed, each synaptic coefficient is represented by the conductivity value G? - G?, i.e. {0, ..., jV}, when the synaptic coefficient is negative if G^ > G^■

[0084] [Fig. 8] schematically represents an RRAM-based pulse neural circuit 800 having a differential structure according to an embodiment of the present disclosure. The neural circuit 800 comprises a differential input stage 802 and an output stage 804.

[0085] The input stage 802 comprises two sets 806 and 808 of N+1 branches, each comprising the resistive elements Gf and G?,ze {0, - - ■, N}. Each resistive element Gf and Gf has one of its electrodes, for example its lower electrode, connected to the supply voltage rail Vhot via a corresponding transistor T? and Tf ■ Each transistor T?, rf has for example its gate connected to receive the corresponding voltage Finj.

[0086] The output stage 804 comprises a transistor 810 and a transistor 812. The transistor 810 is for example connected by its main conduction nodes between the common conductive line SL and the ground voltage rail. The transistor 812 is for example connected by its main conduction nodes between the common conductive line SL' and the ground voltage rail. The gate of the transistor 810 is connected to the common conductive line SL', while the gate of the transistor 812 is connected to the common conductive line SL.

[0087] The output stage 804 further comprises the comparator 206, the positive input of which is connected to the common conductive line SL and the negative input of which is connected to the common conductive line SL'. The comparator 206 is used to generate a corresponding output transition of the output voltage V out based on the relative levels of the voltages VSL and VSL' on the common conductive lines SL and SL'.

[0088] Furthermore, the output of comparator 206 is connected to the gate of transistor 510 via delay circuit 508 and, similarly, to the gate of a transistor 510' via a delay circuit 508'. Like transistor 510 of [Fig. 5], transistor 510 of [Fig. 8] is connected between the common conductive line SL and the ground rail. Transistor 510 of [Fig. 5], transistor 510 of [Fig. 8] is connected between the common conductive line SL and the ground rail.

[0089] The implementation of the output stage 804 allows two different operating regimes.

[0090] In the first operating regime, rather than comprising voltage pulses, the input voltages Vmj, ie {0, ..., Af} are continuous analog voltage levels, which are for example fixed or substantially fixed in time. In operation, the voltage of one of the common conductive lines SL or SL' increases and exceeds the voltage on the other common conductive line. This will cause one or other of the transistors 810 and 812 to gradually discharge to ground the common conductive line having the lower voltage. When the voltage difference between the common conductive lines SL and SL' exceeds the threshold voltage V, the comparator 206 will generate a voltage pulse on the output voltage Vout, the duration of the voltage pulse being a function of the delay introduced by the delay circuits 508, 508'. The threshold comparison is for example a function of the structure of the comparator 206 and the current leakage which passes to ground through each of the transistors 510 and 510'.The two delay circuits 508, 508' and transistors 510, 510' further cause, for example, the voltage on the common conductor lines SL and SL' to be reset to a voltage close to the ground voltage a delay after a voltage transition of the output voltage Vout. Furthermore, the resetting of the voltage on the common conductor lines SL and SL' in turn resets the output voltage Vout of the comparator 206.

[0091] An example of the temporal evolution of the voltages of the common conductive lines and of the voltage Vout, in accordance with the first operating regime 800, is represented in [Fig.9].

[0092] [Fig.9] is a timing diagram representing voltages present in the RRAM-based pulsed neural circuit 800 according to an exemplary embodiment.

[0093] The time evolutions of the voltages Vsl and VSL^ respectively on the conductive line SL and on the conductive line SL', are represented by curves 900 and 902 and are initially close to ground. The output voltage Vout is represented by a curve 904.

[0094] In the example shown, the voltages on the common conductive lines SL and SL' begin to increase at an instant following the application of the analog input voltages V^ i G {0, ..., N}. At an instant 1], the voltage VSL exceeds the voltage VSL^ causing the transistor 812 to conduct more than the transistor 810. The voltage VSL' is thus discharged to the ground voltage, while the voltage VSL continues to increase. At an instant / 2, the difference between the voltages V SL and VSL' exceeds the value of the threshold voltage Vth. Consequently, the comparator 206 generates the voltage pulse on the output voltage Vmt, the duration of which depends on the delay circuits 508, 508', which for example apply substantially the same delay as each other. The voltages VSL and Vsl are thus reset to a value close to ground via the transistors 510, 510' activated by the delay circuits 508.

[0095] After the voltages Vsl and V SL\ have been reset, they remain low for example until a time ^3. For example, the voltages Vsl and Vsl are discharged after a fixed time delay of the delay circuit 508, 508'. Once this time delay has elapsed, the lines SL and SL' are for example left floating until a new neuronal operating cycle begins. A new neuronal operating cycle therefore begins and, this time, it is for example the voltage Vsl which exceeds the voltage VSL. The voltages Vsl and Vsl are then reset, leading to the generation of the voltage pulse Vout at an instant ^4.

[0096] Again in relation to Figure 8, in the second operating regime of the circuit 800, the charge of the conductive lines SL and SL' differs from the first operating regime, the input voltages zs {0, .zV} comprising voltage pulses for example in the form of voltage pulses. The rows of transistors rf and Tf, is {0, ..., A} receive the voltage pulses, coming for example from other neurons of the neural circuit. The voltage pulses cause an accumulation of charges on the common conductive lines SL and SL'.

[0097] Figure 10 is a timing diagram representing an example of the temporal evolution of the input voltages V^ i G {0, ..., TV} at the gates of the transistors T? and of the voltages VSL and VSL' on the common conductive lines SL and SL' and of the voltage V[mt, in accordance with the second operating regime of the circuit 800 is represented in Figure 10. Indeed, for the sake of clarity, we consider a case in which input pulses are present on only the input voltages o and of the transistors Tn, and T^, T? of the neural circuit 800.

[0098] In the example shown in Figure 10, at an instant ^o, the transistors Tq and receive a voltage pulse 1000, generating a first accumulation of charges on the common conductive lines SL and SL'. Consequently, the voltages VSL and VSL\ represented respectively by curves 1002 and 1004, increase suddenly and these voltages are applied to the gates of the transistors 810 and 812, leading to a progressive and relatively slow decrease of the two voltages VSL and Vsl- At an instant and again at an instant ?2, the transistors T? and T® receive a voltage pulse 1006. The voltages VSL and VSL' increase abruptly, then gradually decrease. Then, after receiving a voltage pulse in the voltage Vin$ at a time fy, again the two voltages VSL and sl increase abruptly again, then gradually decrease. In the example of Figure 10, each of the voltage pulses at times h and ^3 causes the voltage Vsl to be higher than the voltage Vsl, and therefore the transistor 810 conducts more than the transistor 812, causing the voltage VSL to decrease more quickly than the voltage VSL. Due to the difference in value between the voltages VSL and VSL' at a time the difference between the voltages on the lines conductive SL and SL' becomes greater than the threshold voltage V triggering the generation of the output pulse Vma and the reset to a voltage close to the mass voltage, VSL and VSL' voltages. A new neuronal cycle then begins for example and, at an instant %, the VSL voltage becomes higher than the Vsl voltage by a value greater than the threshold voltage V^,.

[0099] [Fig. 11] schematically represents an RRAM-based analog neural circuit 1100 having a differential structure according to another embodiment of the present disclosure. The neural circuit 1100 comprises the differential input stage 702 and an output stage 1104.

[0100] Output stage 1104 is similar to output stage 804 of Figure 8 in that it includes transistors 810 and 812 connecting common conductive lines SL and SL' to ground and having their gates connected to the opposite common conductive line. Output stage 1104 differs from output stage 804 in that comparator 206 is replaced by a voltage amplifier 1106, which is for example a differential amplifier, and has for example unity gain and delay circuits 508, 508' and transistors 510, 510' are omitted. Therefore, the output voltage Vout is generated as an analog DC voltage and no longer includes voltage pulses or pulses, unlike in the case of circuit 800. The output voltage Vm(t is for example the membrane potential of the neural circuit and is equal to the voltage difference VSL- Vsl>. This makes it possible to encode positive or negative values ​​of the output voltage

[0101] [Fig. 12] is a timing diagram representing voltages present in the RRAM-based analog neural circuit 1100 according to an exemplary embodiment of the present disclosure.

[0102] The values ​​of the voltages Vsl and V on the conductive lines are represented respectively by dotted curves 1200 and 1202, while the output voltage Vout is represented by a continuous curve 1204.

[0103] Initially, at a time ?o, the voltages VSL, VSL> and Vout are close to the ground voltage. Between time ?o and a time I], the voltage on the conductive line SL is higher than the voltage on the conductive line SL'. Therefore, the output voltage is positive between times and Ij. Between time li and a time C, the voltage on the conductive line SL' becomes higher than the voltage on the conductive line SL, therefore, the output voltage Volü becomes negative. For similar reasons, the output voltage Vout is positive between time and a time ^3, negative between time h and a time ^4, positive between time ^4 and a time ^5, negative between time % and a time %, and then positive after time

[0104] Although [Fig.l 1] represents an example of an analog operation applied to a differential structure of the neural circuit similar to that of [Fig.8], the person skilled in the art will understand that such an analog operation could be applied to the non-differential neural circuits 200, 300 of Figures 2 and 3 respectively. tively or to the differential neural circuit 700 of the figure, which does not include the transistors 810, 812. This involves, for example, replacing, in the different embodiments, the comparator 206 with the voltage amplifier 1106.

[0105] [Fig. 13] schematically represents a neural network 1300 consisting of a plurality of neural circuits 1302 according to an exemplary embodiment of the present description.

[0106] The neural network 1300 comprises a plurality of layers and each layer of the neural network 1300 is comprised of a plurality of neural circuits 1300. For example, the network comprises an input layer 1304 comprising a plurality of neural circuits 1302, one or more hidden layers 1306, each hidden layer comprising a plurality of neural circuits 1302, and an output layer 1308 comprising a plurality of neural circuits 1302.

[0107] The neural circuits 1302 of the input layer 1304 receive for example one or more voltages from an INPUT signal, for example via one or more input nodes of the circuit.

[0108] The output voltages Vout generated by the neural circuits of the output layer 1308 make it possible, for example, to generate an output signal OUTPUT.

[0109] The neural circuits 1302 of each layer of the network 1300 are for example produced by the same circuit among the different neural circuits described here, or by a plurality of different neural circuits among the different neural circuits described here, for example by one or more of the neural circuits 200, 300, 500, 700, 800 or 1100 of FIGS. 2, 3, 5, 7, 8 and 11 respectively.

[0110] In another example, in each layer, all the neural circuits 1302 are implemented in the same way among the embodiments described in relation to FIGS. 2, 3, 5, 7, 8 and 11. The modes of implementation of the neural circuit change for example from one layer to another.

[0111] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will occur to those skilled in the art. For example, although embodiments have been described in which the memory elements used to implement input synapses of the neural circuits are FTJ elements, those skilled in the art will understand that, in alternative implementations, other types of programmable resistive memory elements could be used.

[0112] Finally, the practical implementation of the embodiments and variants described is within the reach of those skilled in the art from the functional indications given above.

Claims

Claims

1. A neural circuit (200, 300, 500, 700, 800, 1100) comprising: - a first plurality of synapses, each comprising a first resistive memory element (Gb qP) having an associated parasitic capacitance (each of the first resistive memory elements being configured to supply a current to a first common conductive line (SL); and - an output device (206, 1106) configured to compare a first voltage (VSL) on the first common conductive line to a threshold voltage (Vth) and to generate an output voltage (Vout) of the neural circuit based on the comparison.

2. The neural circuit of claim 1, wherein the output device is a voltage comparator (206) configured to generate a transition of the output voltage (Vont) of the neural circuit when the first voltage exceeds the threshold voltage.

3. The neural circuit of claim 1, wherein the output device is a voltage amplifier (1106) configured to generate an analog output voltage (Vont)-

4. The neural circuit of claim 2, further comprising a first delay circuit (508) connected to an output of the voltage comparator (208) and configured to reset the first voltage (Vsl) on the first common conductive line (SL) in response to the transition of the output voltage (Vout).

5. A neural circuit according to any one of claims 1 to 4, wherein the first resistive element (Gb qP) of each synapse is connected to an output of a further corresponding neural circuit.

6. Neural circuit according to any one of claims 1 to 5, in which the first resistive element (Gb qP) of each synapse is connected to a supply voltage (Vbot) via a first corresponding transistor Tf), each of the first transistors having its gate connected to an output (Vinj) of an additional corresponding neural circuit.

7. A neural circuit according to any one of claims 1 to 6, wherein each synapse further comprises a second resistive memory element (Q?) having an associated parasitic capacitance (£p), each second resistive memory elements being configured to supply current to a second common conductive line (SL1), the second conductive line supplying the threshold voltage (Kst / ) to the output device (206, 1106).

8. A neural circuit according to claim 7 in its dependence on claim 5, wherein the second resistive element (Q?) of each synapse is connected to the output of the additional corresponding neural circuit.

9. A neural circuit according to claim 7 in its dependence on claim 6, wherein the second resistive element (Q?) of each synapse is connected to the supply voltage (Vbot) via a corresponding second transistor (T1?), each of the second transistors having its gate connected to an output (V^) of the additional corresponding neural circuit.

10. A neural circuit according to any one of claims 7 to 9 as dependent on claim 4, further comprising a second delay circuit (508) connected to the output of the voltage comparator (206) and configured to reset the threshold voltage (Kst') on the second common conductive line (SL1) in response to the transition of the output voltage (VOHf).

11. A neural circuit according to any one of claims 1 to 10, wherein the first resistive memory elements (qP, G,) are ferro-tunnel junction elements.

12. A neural network (1300) comprising a plurality of layers of neural circuits (200, 300, 500, 700, 800, 1100) according to any one of claims 1 to 11.

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