Detection of I and Q signals

Abstract

Signal Detection I and Q This description concerns a device comprising a circuit receiving two sinusoidal signals (sig1, sig3) in quadrature and providing: - a first square wave signal (sig11) corresponding to the first of the two signals, and - a second square wave signal (sig31) corresponding to the second of the two signals; and a logic gate receiving the two square waves signals (sig11, sig31) and providing, when the first and second square waves are simultaneously at a first level, third and fourth square waves (O1, O2) respectively at a first level and a second level if the first sinusoidal signal is phase-leading, and respectively at the second level and the first level if the second sinusoidal signal is phase-leading. Figure for the abbreviation: Fig. 3

Description

Title of the invention: Detection of I and Q signals technical field

[0001] This description relates generally to electronic circuits, and more particularly to electronic circuits comprising circuits for supplying two signals in quadrature. Previous technique

[0002] Electronic circuits are known for Ultra Wide Band (UWB) technologies or applications that allow precise measurements of the distance between a wireless transmitter and receiver. Such circuits are called Ultra Wide Band circuits.

[0003] In particular, a UWB receiver circuit includes a mixer configured to frequency-translate a received signal having a frequency between, for example, 6 and 10 GHz into two baseband signals. The first of the two baseband signals is phase-leading with respect to the second, the second baseband signal therefore being phase-lag with respect to the first. Obtaining the two baseband signals requires two signals, commonly called local oscillator signals, respectively in phase and in quadrature phase.To enable digital processing of baseband signals, for example to accurately determine a distance measurement between a UWB receiver and a UWB transmitter, there is a need to know which of the two local oscillator signals is the in-phase I signal and which is the in-phase quadrature Q signal, so as to know which of the two baseband signals is the phase-leading signal and which is the phase-lagging signal. Summary of the invention

[0004] There is a need to overcome all or part of the drawbacks of known Ultra Wideband circuits.

[0005] For example, there is a need for an Ultra Wide Band circuit to identify, among two local quadrature oscillator signals, which is the in-phase I signal and which is the quadrature Q signal.

[0006] One embodiment overcomes all or part of the drawbacks of known Ultra Wideband circuits.

[0007] For example, one embodiment provides an Ultra Wide Band circuit capable of identifying, among two local quadrature oscillator signals, which is the in-phase I signal and which is the quadrature Q signal.

[0008] More generally, an embodiment overcomes all or part of the drawbacks of known circuits in which two quadrature signals are generated.

[0009] For example, one embodiment provides a circuit capable of identifying which signal I is in phase and which signal Q is in quadrature among two quadrature signals generated in the circuit.

[0010] One embodiment provides a device comprising: a first circuit designed to receive a first sinusoidal signal and a second sinusoidal signal in quadrature with respect to each other, the first circuit being configured to provide: - a first square wave signal having a first level if the first sinusoidal signal is positive with respect to its DC component and a second level otherwise, and - a second square wave signal having a first level if the second sinusoidal signal is positive with respect to its DC component and a second level otherwise; and a current-switching logic gate configured to receive the first and second square waves, and to provide: - a third square wave at a first level and a fourth square wave at a second level when the first and second square waves are simultaneously at their first levels and the first square wave is in phase with the second square wave; and - the third square signal at a second level and the fourth square signal at a first level when the first and second square signals are simultaneously at their first levels and the second square signal is in phase lead over the first square signal.

[0011] According to one embodiment, the logic gate is configured so that: - the third square wave switches from its first level to its second level only when the second square wave switches from its second level to its first level during the first level of the first square wave, the third square wave then remaining at its second level only as long as the first and second square waves remain at their first levels; and - the fourth square signal switches from its first level to its second level only when the first square signal switches from its second level to its first level during the first level of the second square signal, the fourth square signal then remaining at its second level only as long as the first and second square signals remain at their first levels.

[0012] According to one embodiment: The first circuit comprises two identical conversion circuits, each conversion circuit comprising: - an input node and an output node, - an inverter having an output coupled to the output node, - a resistor coupling an input of the inverter to the output of the inverter, and - a capacitor coupling the input node and the input of the inverter; The input node and output node of one of the two conversion circuits are configured to respectively receive the first sinusoidal signal and provide the first square wave signal; and The input node and output node of the other of the two conversion circuits are configured to respectively receive the second sinusoidal signal and provide the second square wave signal.

[0013] According to one embodiment, each conversion circuit further comprises: a first switch in series with said resistor, between the input and output of the inverter; and a second switch coupling the inverter input to a voltage capable of forcing a given state of the inverter output when the second switch is closed.

[0014] According to one embodiment, said logic gate comprises: a reference node, a power node and the first, second, third, fourth, fifth and sixth nodes; a first transistor connected between the reference node and said first node and having a gate configured to receive a first control signal determined by the first square wave; a second transistor connected between said first and second nodes and having a gate connected to said third node; a first resistance coupling said second node to said power supply node; a third transistor connected between said first and third nodes and having a gate connected to said fourth node; a second resistance coupling said third node to said power supply node; a fourth transistor connected between said reference node and said fifth node and having a gate configured to receive a second control signal determined by the second square wave; a fifth transistor connected between said fifth and fourth nodes and having a gate connected to said sixth node; a third resistance coupling said sixth node to said power supply node; a sixth transistor connected between said fifth and sixth nodes and having a gate connected to said second node; and a fourth resistor coupling said fourth node to said power node, said second and fourth nodes being configured to provide respectively the third and fourth square signals.

[0015] According to one embodiment, said logic gate further comprises two identical control circuits, each comprising an input and an output, each circuit of control being configured to provide, on its output, a square signal having an alternating component determined by the alternating component of a square signal received on its input and to fix an alternating component of the signal provided on its output, a first of the two control circuits being configured to receive the first square signal on its input and to provide the first control signal on its output and a second of the two control circuits being configured to receive the second square signal on its input and to provide the second control signal on its output.

[0016] According to one embodiment, the first circuit is further intended to receive a third sinusoidal signal in opposite phase to the first sinusoidal signal and a third sinusoidal signal in opposite phase to the second sinusoidal signal, the first circuit being further configured to provide: - a fifth square wave signal having a first level if the third sinusoidal signal is positive with respect to its DC component and a second level otherwise, and - a sixth square wave signal having a first level if the fourth sinusoidal signal is positive with respect to its DC component and a second level otherwise.

[0017] According to one embodiment, each of the two control circuits comprises: - an additional entry, - of the first, second and third nodes, the third node being coupled to the output of said control circuit, - a first transistor connected between the reference node and the first node of said control circuit and having a gate configured to receive a first bias voltage, - a second transistor connected between the first and second nodes of said control circuit and having a gate coupled to the input of said control circuit, - a first resistor coupling the second node of said control circuit to the power supply node, - a third transistor connected between the first and third nodes of said control circuit and having a gate coupled to the additional input of said control circuit, and - a second resistor coupling the third node of said control circuit to the power supply node; the additional input of the first control circuit is configured to receive the fifth square wave signal; and The additional input of the second control circuit is configured to receive the sixth square wave signal.

[0018] According to one embodiment, each control circuit further comprises: a first capacitor coupling the input of said control circuit to the gate of the second transistor of said control circuit; a third resistor coupling the gate of the second transistor of said control circuit to a fourth node of said control circuit, said fourth node configured to receive a first DC voltage; a second capacitor coupling the additional input of said control circuit to the gate of the third transistor of said control circuit; a fourth resistor coupling the gate of the third transistor of said control circuit to said fourth node; a third capability coupling the third node of said control circuit to the output of said control circuit; and a fifth resistor coupling the output of said control circuit to a fifth node of said control circuit, said fifth node being configured to receive a second DC voltage.

[0019] According to one embodiment: The device further includes a current-switched writing and storage circuit comprising: - a first input configured to receive the third square wave signal, - a second input configured to receive the fourth square wave signal, - a first output configured to provide a first output signal, and - a second output configured to provide a second output signal; and the write and store circuit is configured so that a level of the first and second output signals is determined by the level respectively of the third and fourth square signals when the first and second square signals are simultaneously at their first levels, and to store the level of the first and second output signals otherwise.

[0020] According to one embodiment: the writing and storage circuit includes a first current-switching flip-flop and a second current-switching flip-flop; the first flip-flop is configured to receive the third square wave signal and provide the first output signal; and the second flip-flop is configured to receive the fourth square wave signal and provide the second output signal.

[0021] According to one embodiment: Each of the first and second rocker arms includes: - a reference node, a power node, and first, second, third, and fourth nodes, - a current-switching circuit configured to receive a signal and to provide a signal in phase with the received signal and a signal in opposite phase with the received signal, - a first transistor connected between said reference node and said first node, a gate of said first transistor being configured to receive a signal indicating when the first and second square waves are simultaneously at their first levels, - a second transistor connected between the aforementioned first and second nodes and having a gate configured to receive the signal in phase, - a first resistance coupling said second node to the power supply node, - a third transistor connected between the aforementioned first and third nodes and having a gate configured to receive the signal in opposite phase, - a second resistor coupling said third node to the power supply node, - fourth, fifth and sixth transistors each connected between the reference node and said fourth node, a gate of the fourth transistor being configured to receive a signal indicating when the first and second square waves are simultaneously at their second levels, a gate of the fifth transistor being configured to receive a signal indicating when the first and second square waves are simultaneously and respectively at their first level and second level, and a gate of the sixth transistor being configured to receive a signal indicating when the first and second square waves are simultaneously and respectively at their second level and first level, - a seventh transistor connected between said fourth and second nodes and having a gate connected to said third node, and - an eighth transistor connected between said fourth and third nodes and having a gate connected to said second node; the current-switching circuit of the first flip-flop is configured to receive the third square wave signal; the current-switching circuit of the second flip-flop is configured to receive the fourth square wave signal; One of the first and second nodes of the first flip-flop is configured to provide the first output signal; and One of the first and second nodes of the second flip-flop is configured to provide the second output signal.

[0022] According to one embodiment, each current-switching circuit comprises: - a reference node, a power node and the first, second and third nodes; - a first MOS transistor connected between said reference node and said first node and having a gate configured to receive a bias voltage; - a second MOS transistor connected between the aforementioned first and second nodes and having a grid configured to receive the signal received by said current-switching circuit; - a third MOS transistor connected between said first and third nodes and having a gate connected to said second node; - a resistor coupling said second node to said power supply node; and - another resistor coupling said third node to said power supply node, said second and third nodes being configured to provide respectively the signals in opposite phase and in phase supplied by said current-switching circuit.

[0023] According to one embodiment, the writing and storing circuit further includes a current-switching logic gate configured to provide the signal indicating when the first and second square signals are at their first levels, the signal indicating when the first and second square signals are at their second levels, the signal indicating when the first and second square signals are respectively at their first and second levels, and the signal indicating when the first and second square signals are respectively at their second and first levels.

[0024] According to one embodiment, the writing and storing circuit further comprises a current-switching logic gate configured to receive the first, second, fifth and sixth square signals and to provide, from said received signals, the signal indicating when the first and second square signals are at their first levels, the signal indicating when the first and second square signals are at their second levels, the signal indicating when the first and second square signals are respectively at their first and second levels, and the signal indicating when the first and second square signals are respectively at their second and first levels.

[0025] According to one embodiment, the logic gate of the write and store circuit comprises: a current-switched NAND gate configured to review four signals determined respectively by the first, second, fourth, and fifth square waves and to provide first, second, third, and fourth output signals; and four inverters configured to receive the four output signals of the NAND logic gate and to provide, respectively, the signal indicating when the first and second square waves are at their first levels, the signal indicating when the first and second square waves are at their second levels, the signal indicating when the first and second square waves are at their first and second levels, and the signal indicating when the first and second square signals are respectively at their second and first levels. Brief description of the drawings

[0026] These features and advantages, as well as others, will be described in detail in the following description of particular embodiments, given by way of non-limiting example, in relation to the accompanying figures, among which:

[0027] [Fig.1] represents, in block form, an example of a circuit using I and Q signals;

[0028] [Fig.2] represents, in block form, an embodiment of a signal detection circuit I and Q;

[0029] [Fig.3] illustrates by means of timing diagrams an example of a mode of operation of the circuit of [Fig.2];

[0030] [Fig.4] represents an example of an embodiment of a detector circuit of [Fig.2];

[0031] [Fig.5] represents an example of an embodiment of a detector circuit of [Fig.2];

[0032] [Fig.6] represents an example of an embodiment of part of the circuit of [Fig.5];

[0033] [Fig.7] represents another example of an embodiment of part of the circuit of [Fig.5];

[0034] [Fig.8] represents, in block form, a variant embodiment of the signal detection circuit of [Fig.2];

[0035] [Fig. 9] represents an example of an embodiment of part of the circuit of the [Fig. 8]; and

[0036] [Fig. 10] represents an example of an embodiment of part of the circuit of [Fig. 8], Description of the implementation methods

[0037] The same elements have been designated by the same reference numerals in the different figures. In particular, the structural and / or functional elements common to the different embodiments may have the same reference numerals and may have identical structural, dimensional and material properties.

[0038] For the sake of clarity, only the steps and elements useful for understanding the described embodiments have been shown and detailed. In particular, the usual functionalities associated with I and Q signals have not been detailed, as the described embodiments are compatible with these usual functionalities.

[0039] Unless otherwise specified, when referring to two interconnected elements, this means directly connected without intermediate elements other than conductors, and when referring to two connected (in English "coupled") elements between them, this means that these two elements can be connected or linked via one or more other elements.

[0040] In the following description, when reference is made to absolute position qualifiers, such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position qualifiers, such as the terms "above", "below", "superior", "inferior", etc., or to orientation qualifiers, such as the terms "horizontal", "vertical", etc., reference is made, unless otherwise specified, to the orientation of the figures.

[0041] Unless otherwise specified, the expressions "approximately", "roughly", and "in the order of" mean within 10%, preferably within 5%.

[0042] In the following description, when it is stated that a signal has a first level and a second level, for example a high level and a low level, this means that the signal alternates between the first level and the second level, it being understood that, in practice, each level may correspond to a voltage or a current that may not be perfectly constant. Such a signal is, for example, called a square wave signal.

[0043] In an Ultra Wideband receiver circuit, due to the frequency of the received signal, it is complex, if not impossible, to generate, with a single oscillator, for example with a single voltage-controlled oscillator (VCO), the two local oscillator signals I and Q used to generate the two baseband signals. This is even more true when it is desired that the receiver circuit operate on several, or even all, of the channels of the UWB standard.

[0044] One solution for generating the local oscillator signals I and Q is then to use two interconnected oscillators, i.e. coupled to each other, configured so that one of the two oscillators provides the signal I and the other provides the signal Q. An example of two voltage-controlled oscillators allowing the generation of two sinusoidal signals in quadrature with respect to each other is described in the article "900 MHz CMOS LC-Oscillator with Quadrature Outputs" by Rofougaran et al published in 1996, in IEEE International Solid-State Circuits Conference (ISSCC).

[0045] Fig. 1 represents, in block form, an example of a circuit or device 1 providing and using signals I and Q, in which the signals I and Q are two local oscillator signals generated by two quadrature oscillators.

[0046] In this example, device 1 is a receiver for an ultra-wideband wireless signal signal. The signal signal is received by an antenna 100, which transmits it to a processing circuit 102. By way of example, circuit 102 includes a frequency translator circuit (not shown) configured to generate two baseband signals by mixing the received signal signal with the two local oscillator signals I and Q.

[0047] To generate the two signals I and Q, device 1 comprises two oscillators VCO1 and VCO2 are voltage-controlled. Oscillators VCO1 and VCO2 are coupled to each other and controlled to provide sinusoidal signals at a frequency determined by the carrier frequency of the signal signal. The frequency of the local oscillator signals is, for example, close to, or even equal to, the carrier frequency of the signal signal. For example, oscillators VCO1 and VCO2 are part of a phase-locked loop (not shown) configured so that the frequency of the signals generated by oscillators VCO1 and VCO2 is determined by the carrier frequency of the signal signal.

[0048] The oscillator VCO1, respectively VCO2, is configured to provide a sinusoidal signal sig1, respectively sig3, the local oscillator signals sig1 and sig3 being in quadrature with each other. In practice, the oscillator VCO1, respectively VCO2, also provides a sinusoidal signal sig2, respectively sig4, in opposite phase to the signal sig1, respectively sig3.

[0049] The sigl and sig3 signals are supplied to circuit 102, the sig2 and sig3 signals can also be supplied to circuit 102.

[0050] A problem which arises in device 1 is that the one of the signals sigl and sig3 which is the signal I is not determined and depends on the start of the oscillators VCO1 and VCO2.

[0051] It is known to have different start-up sequences between the VCO1 and VCO2 oscillators, so as to force one of the two signals sigl and sig3 to be the I signal. However, this increases the time required for the stabilization of both VCO1 and VCO2 oscillators at each start-up or carrier frequency change.

[0052] It is also known to add a phase error in one of the two oscillators VCO1 and VCO2 so as to force one of the two signals sigl and sig3 to be the signal I. However, the introduction of a phase error is not desirable, for example because it leads to an error in the distance determined by device 1 from the signal sig and the signals I and Q.

[0053] It is also known to introduce a difference between the bias currents of the two oscillators VCO1 and VCO2 so as to force one of the two signals sigl and sig3 to be the signal I. However, this results in a difference in amplitude between the signals sigl and sig3, which is not desirable.

[0054] A signal detection circuit for I and Q is proposed here, allowing the determination among the signals sigl and sig3 of which is the I signal and which is the Q signal, without introducing an imbalance between the two oscillators VCO1 and VCO2, unlike what is done in the known solutions described above.

[0055] The proposed circuit is intended to receive the sig1 and sig3 signals, can also be intended to receive the sig2 and sig4 signals, and is configured to provide two signals 01 and 02 from which it is possible to identify, after the startup of the operating systems VC01 and VCO2 converters, if the sigl and sig3 signals correspond respectively to the I and Q signals or respectively to the Q and I signals. Thus, from the two signals 01 and 02, the processing circuit 102 can switch between a configuration where it uses the sigl and sig3 signals as I and Q signals respectively, and a configuration where it uses the sigl and sig3 signals as Q and I signals respectively.

[0056] Fig. 2 represents, in block form, an embodiment of a circuit or device 2 for detecting I and Q signals.

[0057] Device 2 includes a circuit 200 configured to convert sinusoidal signals sigl and sig3 into two corresponding square signals sigll and sig31.

[0058] Circuit 200 is configured to receive the sigl and sig3 signals in quadrature with each other. Circuit 200 is configured to provide the sigl1 signal at a first level, for example high, when the sigl signal is positive with respect to its DC component (Direct Current), that is, when the value of the sigl signal is greater than the value of its DC component, and at a second level, for example low, when the sigl signal is negative with respect to its DC component, that is, when the value of the sigl signal is less than the value of its DC component. Circuit 200 is further configured to provide the sig31 signal at a first level, for example high, when the sig3 signal is positive with respect to its DC component, and at a second level, for example low, when the sig3 signal is negative with respect to its DC component.Preferably, the first levels of the square signals sigl 1 and sig31 correspond to the same first voltage value, and the second levels of the square signals sigll and sig31 correspond to the same second voltage value.

[0059] According to one embodiment, the circuit 200 comprises two identical circuits 202, each configured to convert a sinusoidal signal into a corresponding square wave signal. Thus, each circuit 202 comprises an input 204 configured to receive a sinusoidal signal and an output 206 configured to provide the corresponding square wave signal.

[0060] More specifically, one of the two circuits 202 is configured to receive the sigl signal on its input 204 and to provide the sigl 1 signal on its output 206, the other of the two circuits 202 being configured to receive the sig3 signal on its input 204 and to provide the sig31 signal on its output 206.

[0061] Device 2 further includes a logic gate 208. Logic gate 208 is implemented using CML (Current Mode Logic) technology. In other words, gate 208 is a current-switching logic gate. Gate 208 is configured to receive signals sigl 1 and sig31, for example, at respective inputs S and R. Gate 208 is further configured to provide the two signals 01 and 02, for example, at respective outputs Q and Qn. Signals 01 and 02 are square waves. The switching of signals 01 and 02 between their two levels are determined by the order of arrival, i.e. the sequence, and the direction of switching of the signals sigl 1 and sig31 on the logic gate 208. The two signals 01 and 02 are two signals allowing to determine which of the signals sigl and sig3 is the signal I.

[0062] According to one embodiment, the gate 208 is configured so that signals 01 and 02 are respectively at a first level, for example high, and at a second level, for example low, when the two signals sigl 1 and sig31 are at their first levels, for example high, and that signals sigll and sig31 (therefore signals sigl and sig3) are signals I and Q respectively. Complementarily, the gate 208 is further configured so that signals 01 and 02 are respectively at a second level, for example low, and at a first level, for example high, when the two signals sigl 1 and sig31 are at their first levels (for example high) and that signals sigll and sig31 (therefore signals sigl and sig3) are signals Q and I respectively.Preferably, gate 208 is further configured so that signals 01 and 02 are at their first levels, e.g. high, when signals sigll and sig31 are simultaneously at their second levels, e.g. low.

[0063] According to one embodiment, the gate 208 is more particularly configured so that the signal 01 (output Q) switches from a first level, for example high, to a second level, for example low, only when the signal sigl 1 (input S) switches from its second level to its first level while the signal sig31 (input R) is at its first level. Furthermore, following such a switching of the signal 01, the gate 208 is configured to maintain the signal 01 at its second level only as long as both the signals sigl 1 and sig31 remain at their first levels. The gate 208 is, for example, configured so that the signal 01 is at its first level in all other cases.In a symmetrical or complementary manner, gate 208 is further configured so that signal 02 (output Qn) switches from a first level, for example high, to a second level, for example low, only when signal sig31 (input R) switches from its second level to its first level while signal sigl 1 (input S) is at its first level. Furthermore, following such a switching of signal 02, gate 208 is configured to maintain signal 02 at its second level only as long as both signals sigl 1 and sig31 remain at their first levels. Gate 208 is, for example, configured so that signal 02 is at its first level in all other cases.

[0064] Preferably, the first levels of the square signals 01 and 02 correspond to the same first voltage value, and the second levels of the square signals 01 and 02 correspond to the same second voltage value.

[0065] Figure 3 illustrates, by means of timing diagrams, an example of an operating mode of the circuit in [Fig.2]. In the example in [Fig.3], the first levels of the signals sigll, sig31, 01 and 02 are high levels, the second levels of the signals sigll, sig31, 01 and 02 are low levels. In particular, this [Fig.3] illustrates the operation of the circuit of [Fig.2] in the case where the circuit 208 is configured so that signal 01 switches to its second level only when signal sigl 1 switches to its first level while signal sig31 is at its first level, signal 02 switches to its second level only when signal sig31 switches to its first level while signal sigl 1 is at its first level, the levels of signals 01 and 02 are maintained when signals sigll and sigl3 are both at their first levels, signals 01 and 02 are at their first levels when signals sigll and sig31 are simultaneously at their second levels.

[0066] Figure 3 illustrates, for two cases, respectively on the left and right in Figure 3, the shape of the signals sigl, sig3, sigll, sig31, 01 and 02. The case on the left in Figure 3 corresponds to the case where the signals sigl and sig3 are the respective signals I and Q, the case on the right in Figure 3 corresponds to the case where the signals sigl and sig3 are the respective signals Q and I. In Figure 3, the DC component of the signals sigl and sig3 is referenced as DC1 and DC3 respectively.

[0067] On the left in [Fig. 3], at time t0, the signal sig1, respectively sig3, has a value lower than its DC component DC1, respectively DC3. The signals sig1 and sig31 are then at their second levels. Furthermore, the signals 01 and 02 are then at their first levels.

[0068] At a time t1 after time t0, the signal sigl becomes greater than its DC component DC1, while the signal sig3 is still less than its DC component DC3. As a result, the signal sigl1 switches to its first level, while the signal sig31 remains at its second level. Signals 01 and 02 then remain at their first levels.

[0069] At a time t2 after time t1, the signal sig3 becomes greater than its DC component DC3, while the signal sigl is still greater than its DC component DC1. As a result, the signal sig31 switches to its first level while the signal sigl1 is at its first level. This causes the signal 02 to switch from its first level to its second level, while the signal 01 remains at its first level.

[0070] At a time t3 after time t2, the signal sigl becomes lower than its DC component DC1, while the signal sig3 is still higher than its DC component DC3. As a result, the signal sigl 1 switches to its second level, while the signal sig3 1 remains at its first level. Thus, between times t2 and t3, the signal 02 is maintained at its second level and the signal 01 remains at its first level, and, moreover, at time t3 the signal 02 switches to its first level.

[0071] At a time t4 after time t3, the signal sig3 becomes less than its DC component DC3 while the signal sigl is still less than its DC component DC1. As a result, the signal sig31 switches to its second level while the signal sigl 1 remains at its second level.

[0072] After time t4, the signals sigl, sig3, sigl 1, sig31, 01 and 02 are in the same configuration as at time t0, and the switching described in relation to the successive times t1, t2, t3 and t4 are repeated for the following periods of the signals sigl and sig2.

[0073] On the right in [Fig.3], at a time t1O, the signals sigl, sig3, sigl 1, sig31, 01 and 02 are in the same configuration as that described in relation to the time tO.

[0074] At a time tl1 after time tl0, the signal sig3 becomes greater than its DC component DC3, while the signal sigl is still less than its DC component DC1. As a result, the signal sig31 switches to its first level, while the signal sigl1 remains at its second level. Signals 01 and 02 then remain at their first levels.

[0075] At a time tl2 subsequent to time tl1, the signal sigl becomes greater than its DC component DC1, while the signal sig3 is still greater than its DC component DC3. As a result, the signal sigl1 switches to its first level, while the signal sig31 is at its first level. This causes the signal 01 to switch from its first level to its second level, while the signal 02 remains at its first level.

[0076] At a time tl3 after time tl2, the signal sig3 becomes lower than its DC component DC3, while the signal sigl is still higher than its DC component DC1. As a result, the signal sig31 switches to its second level, while the signal sigl1 remains at its first level. Thus, between times 112 and 113, the signal 01 is maintained at its second level, the signal 02 remains at its first level, and, moreover, at time tl3 the signal 01 switches to its first level.

[0077] At a time tl4 after time tl3, the signal sigl becomes less than its DC component DC1 while the signal sig3 is still less than its DC component DC3. As a result, the signal sigl 1 switches to its second level while the signal sig31 remains at its second level.

[0078] After time tl4, the signals sigl, sig3, sigl 1, sig31, 01 and 02 are in the same configuration as at time tl0, and the switching described in relation to the successive times tl 1,112,113 and tl4 are repeated for the following periods of the signals sigl and sig3.

[0079] As shown in [Fig.3], when the signals sigl 1 and sig31 are both at their first levels: - signals 01 and 02 are respectively at their first and second levels if signals sigl and sig3 are signals I and Q respectively, and, conversely, - signals 01 and 02 are respectively at their second and first levels if signals sigl and sig3 are signals Q and I respectively.

[0080] The levels of signals 01 and 02 when signals sigl 1 and sig31 are at their first levels therefore allow us to determine which of the signals sigl and sig3 is signal I and signal Q.

[0081] Referring again to [Fig. 2], optionally, the circuit 200 is further configured to convert the signals sig2 and sig4 into two corresponding square waves sig21 and sig41. The circuit 200 is then configured to receive the signal sig2 in opposite phase to the signal sig1 and the signal sig4 in opposite phase to the signal sig3. The circuit 200 is then configured to provide the signal sig21 at a first level, for example high, when the signal sig2 is positive with respect to its DC component and at a second level, for example low, when the signal sig2 is negative with respect to its DC component, and to provide the signal sig41 at a first level, for example high, when the signal sig4 is positive with respect to its DC component and at a second level, for example low, when the signal sig4 is negative with respect to its DC component.Preferably, the first levels of the square signals sigl 1, sig21, sig31 and sig41 correspond to the same first voltage value, and the second levels of the square signals sigl 1, sig21, sig31 and sig41 correspond to the same second voltage value.

[0082] According to one embodiment, the circuit 200 includes two additional circuits 202 to provide the sig21 and sig41 signals from the respective sig2 and sig4 signals.

[0083] More specifically, one of the two additional circuits 202 is configured to receive the signal sig2 on its input 204 and to provide the signal sig21 on its output 206, the other of the two additional circuits 202 being configured to receive the signal sig4 on its input 204 and to provide the signal sig41 on its output 206.

[0084] According to one embodiment, the signals sig21 and sig41 are supplied to the gate 208, for example to two respective inputs Sn and Rn of the gate 208. Indeed, in some embodiments, the gate 208 uses, in addition to the signals sig1 and sig31, the signals sig21 and sig41 to generate the signals 01 and 02.

[0085] Figure 4 represents an example of an embodiment of a circuit 202 of Figure 2.

[0086] The circuit 202 includes the input, or input node, 204 and the output, or output node, 206.

[0087] The circuit 202 includes an inverter 2000. The inverter 2000 couples node 204 to node 206. The inverter 2000 has, for example, an input coupled to node 204 and a output coupled to node 206.

[0088] The circuit 202 further includes a resistive feedback loop coupling the output of the inverter 2000 to the input of the inverter 2000. The feedback loop is configured so that the inverter operates at its midpoint.

[0089] More specifically, in this example, the feedback loop includes a resistor 2002 coupling the input and output of the inverter 2000 together. For example, one terminal of the resistor 2002 is coupled, preferably connected, to the input of the inverter 2000, and another terminal of the resistor 2002 is coupled to the output of the inverter 2000.

[0090] The input of the inverter 2000 is coupled to the input node 204 of the circuit 202 by a capacitor 2004. The capacitor 2004 has, for example, one terminal coupled, preferably connected, to the input of the inverter 2000, and another terminal coupled, preferably connected, to the node 204.

[0091] In other examples not shown, the resistor 2002 is in series with other resistors between the input and output of the inverter 2000. For example, an additional resistor may be provided between the switch ITA and the output of the inverter 2000.

[0092] According to one embodiment, the output of the inverter 2000 is coupled to the node 206 by one or more inverters 2006 in series between the output of the inverter 2000 and the node 206. The inverter(s) 2006 are sized to adapt a value of the current that the circuit 202 is able to supply to, or draw from, its output node 206. In the example of [Fig. 4], the circuit 202 has an even number of inverters in series between its nodes 204 and 206, namely the inverter 2000 and one inverter 2006, from which it follows that the signal on the node 206 is at a high level when the signal on the node 204 is positive with respect to its DC component, and at a low level otherwise. In other unillustrated examples, this number of inverters may be odd, hence the signal on node 206 is at a low level, respectively high, when the signal on node 204 is positive, respectively negative, with respect to its DC component.

[0093] In an alternative embodiment, the output of inverter 2000 is directly connected to node 206, with inverters 2006 being omitted.

[0094] According to one embodiment, the circuit 202 further comprises a switch ITA connected in series with the resistor 2002, between the input and output of the inverter 2000. The switch 2002 is configured to selectively open or close the feedback loop. For example, the switch ITA couples the resistor 2002 to the output of the inverter 2000. For example, the switch ITA has one conduction terminal coupled, for example, connected, to the output of the inverter 2000, and another conduction terminal coupled, for example, connected, to the resistor 2002. In another example not shown, the switch ITA is connected between the resistor 2002 and the input of the inverter. 2000. In yet another example not shown, in addition to the resistor 2002 between the input of the inverter 2000 and the switch ITA, the feedback loop includes another resistor 2002 between the switch ITA and the output of the inverter 2000.

[0095] In an embodiment including the ITA switch, the circuit 202 further includes, preferably, an ITB switch coupling the input of the inverter 2000 to a node 2008. The node 2008 is configured to receive a voltage capable of forcing the output of the inverter 2000 into a given state when the ITB switch is conducting and, preferably, the ITA switch is blocked. For example, the ITB switch has a first conduction terminal coupled, preferably connected, to node 2008, and a second conduction terminal coupled to the input of inverter 2000. In this example, the second conduction terminal of inverter 2000 is coupled to the input of inverter 2000 via resistor 2002. In another example not shown, the ITB switch has one terminal connected to the input of inverter 2000. As an example, the voltage across node 2008 is a first supply voltage VDD for circuit 202, and, more generally, for device 2 ([Fig. 2]).The VDD voltage is, for example, referenced to a second supply voltage (or reference voltage), for example ground GND, and is positive with respect to the latter. In another example, the voltage on node 2008 is ground GND.

[0096] Once signals 01 and 02 of device 2 ([Fig. 2]) have identified which of the signals sig1 and sig3 is signal I, switches ITA and ITB allow device 2 to be placed in a constant (or stationary) state, for example, a state where signals sig1 and sig31 no longer switch. Switch ITA, and ITB respectively, are then blocked (open) and conducting (closed), respectively. This stable state of device 2 reduces power consumption, since there is no longer any dynamic consumption resulting from switching in device 2. The choice of the voltage VDD or GND on node 2008 depends on the number of inverters 2006 and the desired high or low level on node 206 when switches ITA and ITB are open and closed, respectively.

[0097] In one embodiment, one and / or both of the ITA and ITB switches may be omitted.

[0098] By way of example, each inverter 2000, 2006 of circuit 202 is implemented using CMOS (Complementary MOS - Metal Oxide Semiconductor Complementary) technology. For example, each inverter is powered by the voltages VDD and GND.

[0099] The circuits 202 of the circuit 200 ([Fig.2]) are preferably identical to each other.

[0100] Fig. 5 represents an example of an embodiment of circuit 208 of device 2 of Fig. 2.

[0101] Gate 208 includes inputs R and S and outputs Q and Qn. Input S is configured to receive signal sigl 1, input R is configured to receive signal sig31. Output Q is configured to provide signal 01, output Qn is configured to provide signal 02.

[0102] Gate 208 includes a MOS (Metal Oxide Semiconductor) transistor ML. The transistor ML is connected between nodes 500 and 502 of gate 208. Node 500 is configured to receive a supply voltage, the reference voltage GND in this example, with node 500 being referred to as the reference node. For example, the conduction terminals (source and drain) of transistor ML are coupled, preferably connected, to the respective nodes 500 and 502. In this example, transistor ML is an N-channel transistor with its source connected to node 500 and its drain connected to node 502.

[0103] The gate of transistor Ml is configured to receive a control signal cmdl, the cmdl signal being determined by the sigl 1 signal. For example, the cmdl signal is a square wave signal having a first level, for example high, when the sigl 1 signal is at its first level, and a second level, for example low, when the sigl 1 signal is at its second level.

[0104] Symmetrically, gate 208 further includes a MOS transistor M2. Transistor M2 is connected between node 500 and a node 504 of gate 208. For example, the conduction terminals of transistor M2 are coupled, preferably connected, to the respective nodes 500 and 504. In this example, transistor M2 is an N-channel transistor and has its source connected to node 500, and its drain connected to node 504.

[0105] The gate of transistor M2 is configured to receive a control signal cmd2, the signal cmd2 being determined by the signal sig31. For example, the signal cmd2 is a square wave having a first level, for example high, when the signal sig31 is at its first level, and a second level, for example low, when the signal sig31 is at its second level.

[0106] Thus, the AC (Alternating Current) component of each of the cmdl and cmd2 signals is determined by that of the sigll and sig31 signals respectively. As an example, the cmdl, and cmd2, signals have a DC component configured so that the Ml, and M2, respectively, transistors operate in saturation (transistor conducting) when the cmdl, and cmd2, signals are at their first level (high in this example) and are blocked when the cmdl, and cmd2, signals are at their second level (low in this example).

[0107] Preferably, transistors M1 and M2 have identical dimensions.

[0108] Gate 208 further comprises four MOS transistors M3, M4, M5 and M6 connected respectively between node 502 and a node 506 of gate 208, between node 502 and a node 508 of gate 208, between node 504 and a node 510 of the gate 208, and between node 504 and a node 512 of gate 208. In addition, the gate of transistor M3 is connected to node 508, the gate of transistor M4 is connected to node 512, the gate of transistor M5 is connected to node 506 and the gate of transistor M6 is connected to node 510.

[0109] In this example, transistors M3, M4, M5 and M6 are N-channel and have their sources connected respectively to node 502, node 502, node 504 and node 504.

[0110] Preferably, transistors M3, M4, M5 and M6 have identical dimensions.

[0111] Transistors M3 and M4 form a differential pair biased by the transistor M1, transistors M5 and M6 forming another differential pair biased by transistor M2.

[0112] Nodes 506, 508, 510, and 512 are each coupled to a node 514 of gate 208 by resistors R1, R2, R3, and R4, respectively. Preferably, resistors R1, R2, R3, and R4 are identical. Node 514 is configured to receive a supply voltage different from that received by node 500; node 514 is then referred to as the supply node. In this example, node 514 is configured to receive the voltage VDD reference to ground (GND) and positive with respect to ground (GND).

[0113] In this embodiment, which corresponds to the operation described in relation to [Fig.3], node 506 is connected to output Q, and is configured to provide signal 01, and node 512 is connected to output Qn and is configured to provide signal 02.

[0114] Thus, in circuit 208 of [Fig. 5], if signal cmdl, respectively cmd2, is at its second level, for example low, then signal 01, respectively 02, is at its first level, for example high. Furthermore, if signal cmdl, respectively cmd2, switches to its first level, for example high, while signal cmd2, respectively cmdl, is already at its first level, for example high, signal 01, respectively 02, switches to its second level, for example low, while signal 02, respectively 01, remains at its first level, for example high.

[0115] To provide the cmdl and cmd2 signals to the respective transistors M1 and M2 from the respective sig1ll and sig31 signals, gate 208 includes two identical 520 circuits. 520 circuits are, for example, circuits for shaping a received signal into a control signal or, in other words, close-range control circuits (or "driver" circuits). That is to say, each 520 circuit is configured to adapt the first and second levels of the control signal it provides, for example, to control the current flowing through the transistor that this signal drives. Each 520 circuit includes a 522 input and a 524 output. One of the 520 circuits has its 522 input connected to the S input and its 524 output connected to the gate of the transistor M1, the other of the 520 circuits has its input 522 connected to the input R and its output 524 connected to the gate of transistor M2. In other words, one of the 520 circuits is configured to receive the signal sigl 1 (on its input 522) and to provide the signal cmdl (on its output 524), the other of the circuits being configured to receive the signal sig31 (on its input 522) and to provide the signal cmd2 (on its output 524). Each 520 circuit is configured so that the square wave signal supplied at its 524 output has an AC component determined by the AC component of the signal it receives at its 522 input, and, furthermore, to fix or determine the DC component of the signal it supplies at its 524 output. Preferably, each 520 circuit is configured to supply a high-level signal at its 524 output when the signal at its 522 input is high, and a low-level signal at its 524 output when the signal at its 522 input is low.

[0116] According to one embodiment, for example an embodiment in which the circuit 200 ([Fig. 2]) is configured to also provide the signals sig21 and sig41, each circuit 520 is configured to receive, in addition to the square wave signal on its input 520, a square wave signal on an input 526, the signals on inputs 522 and 526 being out of phase with each other. This is, for example, the case in [Fig. 5] where one of the circuits 520 receives the signals sig11 (input S) and sig21 (input Sn) on its respective inputs 522 and 526, and the other of the circuits 520 receives the signals sig31 (input R) and sig41 (input Rn) on its respective inputs 522 and 526.

[0117] In one embodiment, each circuit 520 is devoid of the input 526.

[0118] In one embodiment, node 508 is connected to output Qn and is configured to provide signal 02, and node 510 is connected to output Q and is configured to provide signal 01. In this variant, gate 208 remains configured so that: signals 01 and 02 are respectively at a first level, for example high, and at a second level, for example low, when the two signals sigl 1 and sig31 are at their first levels, for example high, and that signals sigl 1 and sig31 (therefore signals sigl and sig3) are signals I and Q respectively; and signals 01 and 02 are respectively at a second level, for example low, and at a first level, for example high, when both signals sigl 1 and sig31 are at their first levels (for example high) and that signals sigl 1 and sig31 (therefore signals sigl and sig3) are signals Q and I respectively. Preferably, in this variant, gate 208 is further configured so that signals 01 and 02 are at their first levels, for example high, when signals sigl 1 and sig31 are simultaneously at their second levels, for example low.

[0119] More specifically, in this variant, gate 208 is configured so that: - signals 01 and 02 are at their first levels (e.g., high) when the sigll and sig31 signals are at their second levels (e.g. low); - only the signal 02 switches from its first level (e.g. high) to its second level (e.g. low) when the signal sigl 1 (input S) switches from its second level (e.g. low) to its first level (e.g. high) while the signal sig31 (input R) is at its second level (e.g. low), the signals 02 and 01 then remain respectively at their second level (e.g. low) and at their first level (e.g. high) until the signal sigl 1 switches from its first level (e.g. high) to its second level (e.g. low) while the signal sig31 is at its first level (e.g. high); - signal 02 switches to its first level (e.g., high) and, for example, signal 01 switches to its second level (e.g., low) when signal sigl 1 switches from its first level (e.g., high) to its second level (e.g., low) while signal sigl 31 is at its first level (e.g., high); - only signal 01 switches from its first level (e.g., high) to its second level (e.g., low) when signal sigl 31 (input R) switches from its second level (e.g., low) to its first level (e.g., high) while signal sigl 1 (input S) is at its second level (e.g., low), signals 02 and 01 then remaining respectively at their first level (e.g., high) and second level (e.g., low) until signal sigl 31 switches from its first level (e.g., high) to its second level (e.g., low) while signal sigl 1 is at its first level (e.g., high); and - the signal 01 switches to its first level (for example high) and that, for example, the signal 02 switches to its second level (for example low) when the signal sig31 switches from its first level (for example high) to its second level (for example low) while the signal sigl 1 is at its first level (for example high).

[0120] Figure 6 shows an example of an embodiment of a circuit 520 of the gate 208 of Figure 5. In this example, the circuit 520 is without an input 526.

[0121] The 520 circuit includes a capacitor 600 coupling the input 522 to the output 524 of the 520 circuit. For example, one electrode 602 of the capacitor 600 is connected to the input 522, and a second electrode 604 of the capacitor 600 is connected to a node 606, which is itself connected to the output 524 in this example. Furthermore, the 520 circuit includes a resistor RO coupling the output 524 to a node 608 configured to receive a DC voltage, namely a VDC1 voltage in this example. The DC voltage from node 608 sets, or determines, the DC component of the signal available at the output 524 of the 520 circuit. For example, the resistor RO has one terminal connected to node 606 and one terminal connected to node 608.

[0122] By way of example, the capacitor 600 and the resistance R0 form a circuit 610 (outlined by dashed lines in [Fig. 6]) having the electrode (or node) 602 as its input, the node 606 as output and node 608 configured to receive a DC voltage determining the DC component of the signal on output 606 of circuit 610. Circuit 610 is, for example, configured to transmit a signal from its input 602 to its output 606 by adapting the DC component of the transmitted signal, that is, by fixing the DC component of its output 606.

[0123] [Fig.7] represents another example of an embodiment of a circuit 520 of the gate 208 of [Fig.5]. In this example, the circuit 520 includes the input 526.

[0124] The 520 circuit includes a MOS transistor M7 connected between the reference node 500 and a first node 700 of the 520 circuit. The conduction terminals of transistor M7 are coupled, preferably connected, to the respective nodes 500 and 700. In this example, transistor M7 is an N-channel transistor with its source connected to node 500 and its drain connected to node 700. The gate of transistor M7 is configured to receive a first bias voltage Vpoll. The voltage Vpoll is configured for transistor M7 to be in saturation (conducting).

[0125] The 520 circuit further includes a MOS transistor M8 connected between node 700 and a node 702 of the 520 circuit. The conduction terminals of transistor M8 are coupled, preferably connected, to the respective nodes 700 and 702. In this example, the transistor M8 is an N-channel transistor with its source connected to node 700 and its drain connected to node 702. The gate of transistor M8 is coupled to the input 522 of the 520 circuit. In other words, the gate of transistor M8 is configured to receive a control signal cmd3 determined by the signal received at the input 522 of the 520 circuit. A resistor R5 of the 520 circuit couples node 702 to the supply node 514. For example, resistor R5 has one terminal coupled, preferably connected, to node 700 and another terminal coupled, preferably connected, to node 702.The cmd3 signal is configured so that a first level of the cmd3 signal, for example high, keeps the M8 transistor in saturation (conducting), and a second level of the cmd3 signal, for example low, keeps the M8 transistor blocked.

[0126] Symmetrically, the 520 circuit further includes a MOS transistor M9 connected between node 700 and a node 704 of the 520 circuit. The conduction terminals of transistor M9 are coupled, preferably connected, to the respective nodes 700 and 704. In this example, transistor M9 is an N-channel transistor with its source connected to node 700 and its drain connected to node 704. The gate of transistor M9 is coupled to the input 526 of the 520 circuit. In other words, the gate of transistor M9 is configured to receive a control signal cmd4 determined by the signal received at the input 526 of the 520 circuit. A resistor R6 of the 520 circuit couples node 704 to the supply node 514. The cmd4 signal is configured so that a first level of the cmd4 signal, for example high, keeps transistor M9 in saturation (conducting), and that a second level of the cmd4 signal, for example low, keeps the M9 transistor blocked.

[0127] Preferably, transistors M8 and M9 have the same dimensions.

[0128] Preferably, resistors R5 and R6 are identical, that is to say they have the same resistance values.

[0129] Node 704 of circuit 520 is coupled to output 524 of circuit 520. In other words, the signal supplied by output 524 of circuit 520 is determined by the signal on node 704.

[0130] Transistor M7 biases a differential pair formed by transistors M8 and M9. Thus, depending on the level of the out-of-phase signals present at inputs 522 and 526 of circuit 520, the current flowing through transistor M7 flows predominantly through transistor M8 or transistor M9. When the current flows predominantly through transistor M8, the signal at node 702, respectively 704, is at a low level, respectively high level, and, conversely, when the current flows predominantly through transistor M9, the signal at node 702, respectively 704, is at a high level, respectively low level.

[0131] According to one embodiment, the gate of transistor M8 is coupled to the input 522 by a circuit similar to the circuit 610 described in relation to [Fig.6], the gate of transistor M9 is coupled to the input 526 by a circuit similar to the circuit 610 described in relation to [Fig.6], and, preferably, the node 704 is coupled to the output 524 by yet another circuit similar to the circuit 610 described in relation to [Fig.6].

[0132] The 520 circuit includes, for example, a capacitor 706 coupling the input 522 to the gate of transistor M8. For example, one electrode of the capacitor 706 is coupled, preferably connected, to the input 522, the other electrode of the capacitor 706 being coupled, preferably connected, to the gate of transistor M8. In addition, the 520 circuit includes, for example, a resistor R7 coupling the gate of transistor M8 to a node 707 of the 520 circuit, the node 707 being configured to receive a DC voltage VDC2. For example, one terminal of resistor R7 is coupled, preferably connected, to the gate of transistor M8, the other terminal of resistor R7 being coupled, preferably connected, to node 707. Resistor R7 and capacitor 706 form a circuit similar to circuit 610 described in relation to [Fig.6], which couples input 522 to the gate of transistor M8.

[0133] The circuit 520 includes, for example, a capacitor 708 coupling the input 526 to the gate of transistor M9. For example, one electrode of the capacitor 708 is coupled, preferably connected, to the input 526, the other electrode of the capacitor 708 being coupled, preferably connected, to the gate of transistor M9. In addition, the circuit 520 includes, for example, a resistor R8 coupling the gate of transistor M9 to node 707 of the circuit 520. For example, one terminal of the resistor R8 is coupled, preferably connected, to the gate of transistor M9, the other terminal of the resistor R8 being coupled, preferably connected, to node 707. The resistor R8 and the capacitor 708 form a another circuit similar to circuit 610 described in relation to [Fig.6], which couples input 526 to the gate of transistor M9.

[0134] Thus, the voltage VDC2 sets the DC component on the gate of transistors M8 and M9. As an example, the voltage VDC2 is determined so that transistor M8, respectively M9, operates in saturation (conducting) when signal cmd3, respectively cmd4, is at its first level, for example high, and so that transistor M8, respectively M9, is blocked when signal cmd3, respectively cmd4, is at its second level, for example low.

[0135] Preferably, the resistors R7 and R8 are identical and the capacitors 704 and 708 are identical, that is to say that the resistors R7 and R8 have the same resistance value and that the capacitors 704 and 708 have the same capacitance value.

[0136] The circuit 520 includes, for example, a capacitor 710 coupling node 704 to the output 524 of the circuit 520. For example, one electrode of the capacitor 710 is coupled, preferably connected, to node 704, the other electrode of the capacitor 710 being coupled, preferably connected, to the output 524. In addition, the circuit 520 includes, for example, a resistor R9 coupling the output 524 of the circuit 520 to a node 711 of the circuit 520, the node 711 being configured to receive a DC voltage VDC3. For example, one terminal of resistor R9 is coupled, preferably connected, to output 524, the other terminal of resistor R9 being coupled, preferably connected, to node 704. Resistor R9 and capacitor 710 form yet another circuit similar to circuit 610 described in relation to [Fig.6], coupling node 704 to output 524.

[0137] Thus, the VDC3 voltage fixes the DC component on the output 524 of the circuit 520.

[0138] In the example of [Fig.7], when the signals on inputs 522 and 526 are res When inputs 522 and 526 are high and low respectively, the signal at output 524 is high, and conversely, when inputs 522 and 526 are low and high respectively, the signal at output 524 is low. In other examples, capacitor 710 is connected to node 702 rather than node 704, so that when inputs 522 and 526 are high and low respectively, the signal at output 524 is low, and conversely, when inputs 522 and 526 are low and high respectively, the signal at output 524 is high. Thus, according to the example of circuit 520 considered, the signal on output 524 is in phase or in opposite phase with the signal on input 522, which determines, for example, whether the first level of signal 01, respectively 02, is a high or low level.

[0139] Fig. 8 represents, in block form, a variant embodiment of device 2 of Fig. 2.

[0140] Devices 2 in Figures 2 and 8 share many common elements, and only the differences between these devices are highlighted here. More particularly In relation to device 2 of [Fig.2], device 2 of [Fig.8] further includes a writing and storage circuit 800.

[0141] The 800 circuit is implemented in CML, or, put another way, the 800 circuit is a current-switched write and store circuit.

[0142] The 800 circuit includes an input DI configured to receive signal 01, an input D2 configured to receive signal 02, an output Q1 configured to provide an output signal meml and an output Q2 configured to provide an output signal mem2.

[0143] The 800 circuit is configured such that the levels of signals meml and mem2, in this case square waves, are determined by the respective levels of signals 01 and 02 when signals sigl1 and sig31 are simultaneously at their first levels, and are maintained (stored) otherwise, that is, when one and / or the other of signals sigll and sig31 is at its second level. In other words, when both signals sigll and sig31 are simultaneously at their first levels, the level of signal meml is determined by the level of signal 01 and the level of signal mem2 is determined by the level of signal 02; otherwise, the levels of signals meml and mem2 are maintained at their current levels. Put another way, when the sigll and sig31 signals are simultaneously at their first levels, the 800 circuit is in a phase of writing the meml and mem2 signals from the 01 and 02 signals respectively, and in a memorization phase otherwise.

[0144] The duration during which the level of signals 01 and 02 indicates which of the signals sigl and sig3 is signal I is approximately equal to one quarter of the period of signals sigl and sig3. However, at frequencies above 1 GHz and up to 10 GHz, it may be difficult to observe the levels of signals 01 and 02 during this quarter of the period.

[0145] The prediction of the circuit 800 in the device 2 allows that the levels of the signals meml and mem2 are constant and are different depending on whether the signal sigl is the signal I or the signal sig3 is the signal I.

[0146] According to one embodiment, the memory circuit 800 comprises a first flip-flop 802 and a second flip-flop 804. Both flip-flops 802 and 804 are implemented in CML, or, in other words, each flip-flop 802, 804 is a current-switching flip-flop.

[0147] Flip-flop 802 is configured to receive signal 01 and provide signal mem1, while flip-flop 804 is configured to receive signal 02 and provide signal mem2. Preferably, flip-flops 802 and 804 are identical. For example, flip-flop 802, or 804 respectively, has an input i5 coupled, preferably connected, to input D1, or D2 respectively, of circuit 800 and an output o coupled, preferably connected, to output Q1, or Q2 respectively, of circuit 800.

[0148] Each 802, 804 flip-flop is further configured to receive at least one cmdl3 signal indicating when the sigll and sig31 signals are simultaneously at their first levels and when they are not.

[0149] According to one embodiment, each of the flip-flops 802 and 804 receives a cmdl3 control signal, a cmdln3 control signal, a cmdln3n control signal, and a cmdl3n control signal. The cmdl3 signal is configured to indicate when the sigl1 and sig31 signals are simultaneously at their first levels. The cmdln3 signal is configured to indicate when the sigl1 and sig31 signals are simultaneously at their second and first levels, respectively. The cmdl3n signal is configured to indicate when the sigl1 and sig31 signals are simultaneously at their first and second levels, respectively. The cmdln3n signal is configured to indicate when the sigl1 and sig31 signals are simultaneously at their second levels.As an example, each of the 802 and 804 flip-flops includes an i1 input configured to receive the cmdl3 signal, an i2 input configured to receive the cmdln3 signal, an i3 input configured to receive the cmdl3n signal, and an i4 input configured to receive the cmdln3n signal.

[0150] According to one embodiment, the circuit 800 includes a current-switching logic gate 806 configured to provide the signals cmdl3, cmdln3, cmdl3n and cmdln3, for example from at least the signals sigl 1 and sig31, preferably from the signals sigll, sig21, sig31 and sig41.

[0151] According to one embodiment, the logic gate 806 is configured to provide the signals cmdl3, cmdln3, cmdl3n and cmdln3n from the signals sigll, sig21, sig31 and sig41, and the circuit 200 is configured to receive the signals sigl, sig2, sig3 and sig4 and to provide the signals sigl 1, sig21, sig31 and sig41, the circuit 208 then being able to include the inputs Rn and Sn in addition to its inputs S and R.

[0152] According to one embodiment, the logic gate 806 is configured to receive the signals sigl 1, sig21, sig31 and sig41 and to generate the signals cmdl3, cmdln3, cmdl3n and cmdln3n from these signals sigl1, sig21, sig31 and sig41. According to an alternative embodiment in which the 520 circuits of the 800 circuit are implemented as described in relation to [Fig. 7], the logic gate 806 is configured to receive the signals from nodes 702 and 704 of each of the two 520 circuits, and to generate the signals cmdl3, cmdln3, cmdl3n and cmdln3n from these signals.

[0153] Fig. 9 represents an example of an embodiment of the flip-flop 802 of the circuit 800 of Fig. 8.

[0154] The flip-flop 802 includes a current-switching circuit 900 configured to receive a square wave signal and to output a square wave signal sigc in phase with the received signal and a square wave signal sigcn in opposite phase with the received signal. In the example in [Fig. 9], the circuit 900 is configured to receive the signal 01 received by an input i5 of the 802 switch, and is therefore connected to this i5 input.

[0155] The 802 flip-flop includes a MOS transistor M10 connected between the reference node 500 and a node 902 of the flip-flop. One gate of the transistor M10 is configured to receive the cdml3 signal. For example, the gate of the transistor M10 is coupled, preferably connected, to the input 11 of the 802 flip-flop. As an example, the transistor M10 is N-channel and has its source coupled, preferably connected, to the node 500 and its drain coupled, preferably connected, to the node 902. The cmdl3 signal is at a first level, preferably high, if the cmdl1 and cmd31 signals are simultaneously at their first levels, and at a second level, preferably low, otherwise.

[0156] The 802 flip-flop includes a MOS transistor Mil connected between node 902 and a node 904 of the 802 flip-flop. One gate of the Mil transistor is configured to receive the sigc signal provided by the 900 circuit. As an example, the Mil transistor is N-channel and has its source coupled, preferably connected, to node 902 and its drain coupled, preferably connected, to node 904. The 802 flip-flop includes an RIO resistor coupling node 904 to the supply node 514.

[0157] In a symmetrical or complementary manner, the 802 flip-flop includes a MOS transistor M12 connected between node 902 and a node 906 of the 802 flip-flop. One gate of the transistor M12 is configured to receive the signal sigcn provided by the circuit 900. By way of example, the transistor M12 is N-channel and has its source coupled, preferably connected, to node 902 and its drain coupled, preferably connected, to node 906. The 802 flip-flop includes a resistor RI1 coupling node 906 to the supply node 514.

[0158] Preferably, the RIO and RI 1 resistors are identical.

[0159] Preferably, transistors M11 and M12 have the same dimensions.

[0160] The transistor M10 allows, for example, to bias a differential pair comprising the transistors Mil and M12 from the cmdl 3 signal.

[0161] The flip-flop 802 further includes MOS transistors M13, M14 and M15, each connected between node 500 and a node 908 of the flip-flop 802. By way of example, the transistors M13, M14 and M15 are N-channel and all have their sources coupled, preferably connected, to node 500, and their drains coupled, preferably connected, to node 908. Preferably, the transistors M13, M14 and M15 have the same dimensions, these dimensions being for example the same as those of the transistor M10.

[0162] A gate of transistor M13 is configured to receive the cmdln3 signal. For example, the gate of transistor M13 is coupled, preferably connected, to the i2 input of the 802 flip-flop. The cmdln3 signal is at a first level, preferably high, if the cmdl1 and cmd31 signals are simultaneously and respectively at the second level and the first level, and at a second level, preferably low, otherwise.

[0163] A gate of transistor M14 is configured to receive the cmdl3n signal. By For example, the gate of transistor M14 is coupled, preferably connected, to the i3 input of the 802 flip-flop configured to receive the cmdl3n signal. The cmdl3n signal is at a first level, preferably high, if the cmdl1 and cmd31 signals are simultaneously and respectively at their first and second levels, and at a second level, preferably low, otherwise.

[0164] A gate of transistor M15 is configured to receive the cmdln3n signal. For example, the gate of transistor M15 is coupled, preferably connected, to input i4 of the 802 flip-flop configured to receive the cmdln3n signal. The cmdln3n signal is at a first level, preferably high, if the cmdl1 and cmd31 signals are simultaneously at their second levels, and at a second level, preferably low, otherwise.

[0165] The flip-flop 802 further includes two MOS transistors M16 and M17. Transistor M16 is connected between node 908 and node 906, and has its gate connected to node 904. Symmetrically, transistor M17 is connected between node 908 and node 904, and has its gate connected to node 906. Transistors M16 and M17 have, for example, the same dimensions.

[0166] In addition, one of the nodes 906 and 904, in this example node 906, is coupled, for example connected, to the output o of the flip-flop 802, configured to provide the output signal meml of the flip-flop 802.

[0167] According to one embodiment, the circuit 900 includes a MOS transistor M18 connected between the reference node 500 and a node 9002 of the circuit 900. The transistor M18 has a gate configured to receive a bias voltage Vpol2. As an example, the MOS transistor M18 is N-channel and its source is coupled, preferably connected, to node 500, and its drain is coupled, preferably connected, to node 9002. Circuit 900 further includes a MOS transistor M19 connected between node 9002 and a node 9004 of circuit 900. As an example, the MOS transistor M19 is N-channel and its source is coupled, preferably connected, to node 9002, and its drain is coupled, preferably connected, to node 9004. The gate of transistor M19 in flip-flop 802 is configured to receive signal 01, and is therefore coupled, preferably connected, to input i5 of flip-flop 802. A resistor R13 in circuit 900 couples node 9004 to the power supply node 514.In a complementary or symmetrical manner, the 900 circuit includes a transistor M20 connected between node 9002 and a node 9006 of the 900 circuit. As an example, the MOS transistor M20 is an N-channel transistor with its source coupled, preferably connected, to node 9002, and its drain coupled, preferably connected, to node 9006. The gate of the transistor M20 is coupled, preferably connected, to node 9004. A resistor R12 couples node 9006 to the power supply node 514. The signal sigc, respectively sigcn, is available at node 9006, respectively 9004, of the 900 circuit.

[0168] Although not illustrated, the 804 flip-flop is identical to the 802 flip-flop, except that the i5 input of the 804 flip-flop receives the 02 signal and the o output of the 804 flip-flop provides the mem2 signal.

[0169] In an alternative embodiment not shown, transistors M13, M14 and M15 of each flip-flop 802, 804 are replaced by a single MOS transistor whose gate receives a signal complementary to the cmdl3 signal. However, this may result in the introduction of a shift in the DC component on nodes 906 and 904 between the write and store phases.

[0170] Fig. 10 represents an example of an embodiment of gate 806 of circuit 800 of Fig. 8,

[0171] Logic gate 806 includes a current-switched NAND gate, referenced 1000 and delimited by dashed lines in [Fig. 10]. Gate 1000 is configured to review four signals sig11', sig21', sig31' and sig41' determined by the signals sig1, sig21, sig31 and sig41 respectively, and to provide output signals SI, S2, S3 and S4.

[0172] According to one embodiment, the gate 1000 comprises four inputs 1001, 1002, 1003, and 1004. Inputs 1001 and 1002 are configured to receive signals in opposite phase, for example, the signals sig11' and sig21' in [Fig. 10], while inputs 1003 and 1004 are configured to receive two other signals in opposite phase, for example, the signals sig31' and sig41' in [Fig. 10]. In addition, the gate 1000 comprises seven MOS transistors M21, M22, M23, M24, M25, M26, and M27. Transistor M21 is connected between node 500 and a node 1010, transistor M22 is connected between node 1010 and a node 1011, transistor M23 is connected between node 1010 and a node 1012, transistor M24 is connected between node 1011 and a node 1013, transistor M25 is connected between node 1011 and a node 1014, transistor M26 is connected between node 1012 and a node 1015 and transistor M26 is connected between node 1012 and a node 1016.The gates of transistors M22, M23, M24, M25, M26, and M27 are coupled, preferably connected, to the inputs 1003, 1004, 1002, 1001, 1002, and 1001 of gate 1000, respectively. In addition, resistors R15, R16, R17, and R18 couple nodes 1013, 1014, 1015, and 1016, respectively, to node 514. Signals S1, S2, S3, and S4 are available at nodes 1013, 1014, 1015, and 1016, respectively. The gate of transistor M21 receives a bias voltage Vpol4.

[0173] In the example illustrated by [Fig. 10], the gate 806 receives the signals sigl 1, sig21, sig31 and sig41.

[0174] According to one embodiment, the gate 806 then comprises two circuits 520' similar to the circuit 520 described in relation to [Fig. 7]. More particularly, each circuit 520' differs from the circuit 520 described in relation to [Fig. 7] in that: the 520' circuit also includes a 528 output; the 520' circuit further includes a 710' capacitor, for example identical to the 710 capacitor, coupling the 702 node to the 528 output; the 520' circuit further includes a resistor R9', for example identical to the resistor R9, coupling the output 528 to the node 711; the bias voltage received by the gate of transistor M7 is a voltage Vpol3 which may be different from the voltage Vpoll ([Fig.7]); the DC voltage received by node 707 is a VDC4 voltage which may be different from the VDC2 voltage ([Fig.7]); and the direct current voltage received by node 711 is a VDC5 voltage which may be different from the VDC3 voltage ([Fig.7]).

[0175] In such an embodiment, the inputs 522 and 526 and the outputs 524 and 528 of a first of the two circuits 520' are configured to receive the signals sigl 1 and sig21 and to provide the signals sigl 1' and sig21', and the inputs 522 and 526 and the outputs 524 and 528 of a second of the two circuits 520' are configured to receive the signals sig31 and sig41 and to provide the signals sig31' and sig41'.

[0176] In an alternative embodiment (not shown), the gate 806 comprises four circuits identical to the circuit 520 described in relation to [Fig. 6], except that the DC voltage received by the node 608 of each of these four circuits may be different from the voltage VDC1 ([Fig. 6]). In this embodiment, the first of these four circuits receives the signal sigl 1 and provides the signal sigl 1', the second of these four circuits receives the signal sig21 and provides the signal sig21', the third of these four circuits receives the signal sig31 and provides the signal sig31', and the fourth of these four circuits receives the signal sig41 and provides the signal sig41'.

[0177] In another example not shown, gate 806 does not receive the signals sigl 1, sig21, sig31, and sig41. According to one embodiment, gate 806 then receives the four signals available at nodes 704 and 702 of the two circuits 520 of circuit 208 implemented as described in relation to [Fig. 7]. By way of example, the four signals sigl 1', sig21', sig31', and sig41' then correspond to the four signals available at nodes 704 and 702 of the circuits 520 of circuit 208 when these circuits 520 are implemented as described in relation to [Fig. 7]. In another example, the signals sigl 1', sig21', sig31' and sig41' are obtained at the output of four 520 circuits which are implemented in the manner described in relation to [Fig.6] and which are connected respectively to nodes 704 and 702 of the two 520 circuits of circuit 208 when these two 520 circuits are implemented in the manner described in relation to [Fig.7].

[0178] The transistors of gate 1000 are, for example, N-channel, from which it follows that an output signal SI, S2, S3, S4 of gate 1000 is at a low level only when The two transistors that connect the supply node of this signal SI, S2, S3, S4 to node 500 both receive signals at high levels. Thus, in examples where: the first levels, respectively the second levels, of the signals sigl 1, sig21, sig31 and sig41 are high levels, respectively low levels; and the signals sigl 1', sig21', sig31' and sig41' are in phase with the signals sigl 1, sig21, sig31 and sig41, then when the signals sigl1 and sig31 are simultaneously at their first levels, the signal S2 in the example of [Fig. 10] is at its low level and the other signals SI, S3 and S4 are all at the high level. Referring again to [Fig.9], in the case where transistors M10 and M13 to M15 are N-channel, transistor M10 must be conducting when both signals sigl 1 and sig31 are at their high levels (first levels of signals sigll and sig31), and transistors M13 to M15 must then be blocked.It is therefore understood that the S2 signal must be inverted to obtain the cmdl3 signal. Similarly, the SI, S3 and S4 signals must be inverted to obtain the cmdln3, cmdl3n and cmdln3n signals.

[0179] In other examples where the high and low levels of at least some signals are reversed from what has been indicated above by way of example, the inversions of at least some signals SI, S2, S3 and S4 may be omitted.

[0180] In examples where the SI, S2, S3, and S4 signals are inverted to obtain the cmdl3, cmdln3, cmdl3n, and cmdln3n signals, the 806 gate includes four 1030 inverters. Each 1030 inverter is configured to provide an output signal that is the inverse of the inverter's input signal, while maintaining a gap (or dynamic range) between the high and low levels of the output signal that is the same as that between the high and low levels of the input signal. The 1030 inverters are configured to receive the SI, S2, S3, and S4 signals and to provide the cmdl3, cmdln3, cmdl3n, and cmdln3n signals.

[0181] For example, as shown in the example in [Fig.10], inverter 1030 connected to node 1013 provides the signal cmdln3, inverter 1030 connected to node 1014 provides the signal cmdl3, inverter 1030 connected to node 1015 provides the signal cmdln3n and inverter 1030 connected to node 10167 provides the signal cmdl3n.

[0182] By way of example, as illustrated for just one of the inverters 1030 (bottom right in [Fig. 10]), each inverter 1030 includes a capacitor 1031 configured to receive the input signal on a first electrode and having its second electrode coupled, preferably connected, to the gate of a MOS transistor M30. The transistor M30 is connected between node 500 and a node 1032 of the inverter. For example, the transistor M30 has one conduction terminal connected to node 500 and another conduction terminal coupled to node 1032 by a MOS transistor M31. The transistor M31 is cascoded with the transistor M30 and receives Therefore, a bias voltage Vcasc is applied to its gate. In another example, transistor M31 can be omitted. A capacitor 1033 in inverter 1030 couples node 1032 to the inverter's output. The inverter further includes a resistor 1036 coupling the gate of transistor M30 to a DC voltage VDC6, a resistor 1035 coupling node 1032 to node 514, and a resistor 1034 coupling the inverter's output to a DC voltage VDC7.

[0183] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations could be combined, and other variations will be apparent to those skilled in the art. In particular, the device 2 may include, following the circuit 800, a circuit configured to receive the meml and mem2 signals and to provide corresponding signals suitable for processing by a CMOS circuit, i.e., signals whose high and low levels are substantially equal to the respective voltages VDD and GND.

[0184] In the present application, where it is indicated by way of example that the first level of a square signal is a high level, respectively low level, the person skilled in the art is able to adapt the embodiments and variants described to other examples where the first level of this square signal is a low level, respectively high level.

[0185] Furthermore, although examples of embodiments have been described in which the transistors are N-channel and the voltage VDD is positive with respect to the reference voltage GND, a person skilled in the art can adapt the description made for the case where the voltage VDD is negative with respect to the voltage GND, for example by replacing all N-channel transistors with P-channel transistors.

[0186] Finally, the practical implementation of the described embodiments and variants is within the reach of a person skilled in the art, based on the functional indications given above. In particular, a person skilled in the art is able to determine the values ​​of the bias voltages Vpoll, Vpol2, Vpol3, Vpol4 and Vcasc and the DC voltages VDC1, VDC2, VDC3, VDC4, VDC5, VDC6 and VDC7 to obtain the operation described in relation to [Fig.2] or [Fig.8].

Claims

Claims

1. Device comprising: a first circuit (200) intended to receive a first sinusoidal signal (sigl) and a second sinusoidal signal (sig3) in quadrature with respect to each other, the first circuit (200) being configured to provide: - a first square signal (sigl 1) having a first level if the first sinusoidal signal (sigl) is positive with respect to its DC component (DC1) and a second level otherwise, and - a second square signal (sig31) having a first level if the second sinusoidal signal (sig3) is positive with respect to its direct component (DC3) and a second level otherwise; and a current-switching logic gate (208) configured to receive the first and second square signals (sigl 1, sig31), and to provide: - a third square signal (01) at a first level and a fourth square signal (02) at a second level when the first and second square signals (sigl 1, sig31) are simultaneously at their first levels and the first square signal is in phase advance of the second square signal; and - the third square signal (01) at a second level and the fourth square signal (02) at a first level when the first and second square signals (sigl 1, sig31) are simultaneously at their first levels and the second square signal is in phase advance of the first square signal, wherein the logic gate (208) comprises: a reference node (500), a feed node (514) and first (502), second (506), third (508), fourth (512), fifth (504) and sixth (510) nodes; a first transistor (Ml) connected between the reference node and said first node (502) and having a gate configured to receive a first control signal (cmdl) determined by the first square signal (sigl 1); a second transistor (M3) connected between said first and second nodes (502, 506) and having a gate connected to said third node (508); a first resistor (RI) coupling said second node (506) to said power node (514); a third transistor (M4) connected between said first and third nodes (502, 508) and having a gate connected to said fourth node (512); a second resistor (R2) coupling said third node (508) to said power node (514); a fourth transistor (M2) connected between said reference node (500) and said fifth node (504) and having a gate configured to receive a second control signal (cmd2) determined by the second square signal (sig31); a fifth transistor (M6) connected between said fifth and fourth nodes (504, 512) and having a gate connected to said sixth node (510); a third resistor (R3) coupling said sixth node (510) to said power node (514); a sixth transistor (M5) connected between said fifth and sixth nodes (504, 510) and having a gate connected to said second node (506);and a fourth resistor (R4) coupling said fourth node (512) to said power node (514), and wherein said second and fourth nodes (506, 512) are configured to provide the third and fourth square wave signals (01, 02) respectively or said third and sixth nodes (508, 510) are configured to provide the fourth and third square wave signals (02, 01) respectively.;

2. Device according to claim 1, wherein the logic gate is configured so that: - the third square signal (01) switches from its first level to its second level only when the second square signal (sig31) switches from its second level to its first level during the first level of the first square signal (sigl 1), the third square signal (01) then remaining at its second level only as long as the first and second square signals (sigl 1, sig31) remain at their first levels; and - the fourth square signal (02) switches from its first level to its second level only when the first square signal (sigl 1) switches from its second level to its first level during the first level of the second square signal (sig31), the fourth square signal (02) then remaining at its second level only as long as the first and second square signals (sigl 1, sig31) remain at their first levels.

3. A device according to claim 1 or 2, wherein: the first circuit (200) comprises two identical conversion circuits (202), each conversion circuit (202) comprising: - an input node (204) and an output node (206), - an inverter (2000) having an output coupled to the output node (206), - a resistor (2002) coupling an input of the inverter (2000) to the output of the inverter, and - a capacitor (2004) coupling the input node (204) and to the input of the inverter (2000); the input node (204) and the output node (206) of one of the two conversion circuits (202) are configured to respectively receive the first sinusoidal signal (sigl) and provide the first square signal (sigl 1); and the input node and the output node of the other of the two conversion circuits are configured to respectively receive the second sinusoidal signal (sig3) and provide the second square signal (sig31).

4. Device according to any one of claims 1 to 3, wherein each conversion circuit (202) further comprises: a first switch (ITA) in series with said resistor (2002), between the input and the output of the inverter (2000); and a second switch (ITB) coupling the input of the inverter (2000) to a voltage (VDD) capable of forcing a given state of the output of the inverter (2000) when the second switch (ITB) is closed.

5. Device according to any one of claims 1 to 4, wherein said logic gate (208) further comprises two identical control circuits (520) each comprising an input (522) and an output (524), each control circuit (520) being configured to provide, on its output (524), a square signal having an alternating component determined by the alternating component of a square signal received on its input (522) and to set an alternating component of the signal provided on its output (526), a first of the two control circuits (520) being configured to receive the first square signal (sigl 1) on its input (522) and to provide the first control signal (cmdl) on its output (524) and a second of the two control circuits (520) being configured to receive the second square signal (sig31) on its input (522) and to provide the second control signal (cmd2) on its exit (524).

6. Device according to any one of claims 1 to 5, wherein the first circuit (200) is further intended to receive a third sinusoidal signal (sig2) in phase opposition with the first sinusoidal signal (sigl) and a third sinusoidal signal (sig4) in phase opposition with the second sinusoidal signal (sig2), the first circuit being further configured to provide: - a fifth square signal (sig21) having a first level if the third sinusoidal signal (sig2) is positive with respect to its DC component and a second level otherwise, and - a sixth square signal (sig41) having a first level if the fourth sinusoidal signal (sig4) is positive with respect to its DC component and a second level otherwise.

7. A device according to claim 6 in its dependence on claim 5, wherein: each of the two control circuits (520) comprises: - an additional input (526), - first, second and third nodes (700, 702, 704), the third node (704) being coupled to the output (524) of said control circuit, - a first transistor (M7) connected between the reference node (500) and the first node (700) of said control circuit and having a gate configured to receive a first bias voltage (Vpoll), - a second transistor (M8) connected between the first (700) and second (702) nodes of said control circuit and having a gate coupled to the input (522) of said control circuit, - a first resistor (R5) coupling the second node (702) of said control circuit to the power supply node (514), - a third transistor (M9) connected between the first and third nodes (700,704) of said control circuit and having a gate coupled to the additional input (526) of said control circuit, and - a second resistor (R6) coupling the third node (704) of said control circuit to the power supply node (514); the additional input (526) of the first control circuit is configured to receive the fifth square signal (sig21); and the additional input (526) of the second control circuit is configured to receive the sixth square signal (sig41).,

8. Device according to claim 7, wherein: each control circuit (520) further comprises: a first capacitor (706) coupling the input (522) of said control circuit (520) to the gate of the second transistor (M8) of said control circuit (520); a third resistor (R7) coupling the gate of the second transistor of said control circuit (520) to a fourth node (707) of said control circuit (520), said fourth node configured to receive a first direct voltage (VDC2); a second capacitor (708) coupling the additional input (526) of said control circuit (520) to the gate of the third transistor (M9) of said control circuit (520); a fourth resistor (R8) coupling the gate of the third transistor (M9) of said control circuit (520) to said fourth node (707); a third capacitor (710) coupling the third node (704) of said control circuit (520) to the output (524) of said control circuit (520); and a fifth resistor (R9) coupling the output (524) of said control circuit to a fifth node (711) of said control circuit, said fifth node (711) being configured to receive a second direct voltage (VDC3).

9. A device according to any one of claims 1 to 8, wherein: the device further comprises a current-switching write and storage circuit (800) comprising: - a first input (Dl) configured to receive the third square signal (01), - a second input (D2) configured to receive the fourth square signal (02), - a first output (Ql) configured to provide a first output signal (meml), and - a second output (Q2) configured to provide a second output signal (mem2); and the write and store circuit (800) is configured such that a level of the first and second output signals (meml, mem2) is determined by the level of the third and fourth square signals (01, 02) respectively when the first and second square signals (sigl 1, sig31) are simultaneously at their first levels, and to store the level of the first and second output signals otherwise.

10. Device according to claim 9, wherein: the write and storage circuit (800) comprises a first current-switching flip-flop (802) and a second current-switching flip-flop (804); the first flip-flop (802) is configured to receive the third square signal (01) and provide the first output signal (meml); and the second flip-flop (804) is configured to receive the fourth square signal (02) and provide the second output signal (mem2).

11. Device according to claim 10, wherein: each of the first and second flip-flops (802, 804) comprises: - a reference node (500), a power supply node (514) and first (902), second (904), third (906) and fourth (908) nodes, - a current switching circuit (900) configured to receive a signal (01, 02) and to provide a signal in phase (sigc) with the received signal and a signal in phase opposition (sigcn) with the received signal, - a first transistor (M10) connected between said reference node (500) and said first node (902), a gate of said first transistor (M10) being configured to receive a signal (cmdl3) indicating when the first and second square signals (sigl 1, sig31) are simultaneously at their first levels, - a second transistor (Mil) connected between said first and second nodes (902, 904) and having a gate configured to receive the in-phase signal (sigc), - a first resistor (RIO) coupling said second node (904) to the power supply node (514), - a third transistor (Ml2) connected between said first and third nodes (902, 906) and having a gate configured to receive the phase-opposite signal (sigcn), - a second resistor (RI 1) coupling said third node (906) to the power supply node (514), - fourth, fifth and sixth transistors (M13, M14, M15) each connected between the reference node (500) and said fourth node (908), a gate of the fourth transistor (M15) being configured to receive a signal (cmdln3n) indicating when the first and second square signals are simultaneously at their second levels, a gate of the fifth transistor (M14) being configured to receive a signal (cmdl3n) indicating when the first and second square signals are simultaneously and respectively at their first level and at their second level, and a gate of the sixth transistor (Ml5) being configured to receive a signal (cmdln3) indicating when the first and second square signals are simultaneously and respectively at their second level and their first level, - a seventh transistor (M17) connected between said fourth and second nodes (908, 904) and having a gate connected to said third node (906), and - an eighth transistor (Ml6) connected between said fourth and third nodes (908, 906) and having a gate connected to said second node (904); the current switching circuit (900) of the first flip-flop (802) is configured to receive the third square signal (01); the current switching circuit (900) of the second flip-flop (804) is configured to receive the fourth square signal (02); one of the first and second nodes (904, 906) of the first flip-flop (802) is configured to provide the first output signal (meml); and one of the first and second nodes (904, 906) of the second flip-flop (804) is configured to provide the second output signal (mem2).

12. A device according to claim 11, wherein each current switching circuit comprises: - a reference node (500), a power node (514) and first (9002), second (9004) and third (9006) nodes; - a first MOS transistor (Ml8) connected between said reference node (500) and said first node (9002) and having a gate configured to receive a bias voltage (Vpol2); - a second MOS transistor (M19) connected between said first and second nodes (9002, 9004) and having a gate configured to receive the signal received (01, 02) by said current switching circuit (900); - a third MOS transistor (M20) connected between said first and third nodes (9002, 9006) and having a gate connected to said second node (9004); - a resistor (R13) coupling said second node (9004) to said power supply node (514); and - another resistor (R 14) coupling said third node (9006) to said power supply node (514), said second and third nodes (9004, 9006) being configured to provide the signals in phase opposition and in phase respectively provided by said current switching circuit (900).

13. The device of claim 11 or 12, wherein the write and store circuit further comprises a current-switching logic gate (806) configured to provide the signal (cmdl3) indicating when the first and second square signals (sigl 1, sig31 ) are at their first levels, the signal (cmdln3n) indicating when the first and second square signals (sigl 1, sig31 ) are at their second levels, the signal (cmdl3n) indicating when the first and second square signals (sigl 1, sig31 ) are respectively at their first and second levels, and the signal (cmdln3) indicating when the first and second square signals (sigl 1, sig31 ) are respectively at their second and first levels.

14. A device according to claim 11 or 12 taken in its dependence on claim 6, wherein the writing and storage circuit further comprises a current-switching logic gate (806) configured (800) to receive the first, second, fifth and sixth square signals (sigl 1, sig31, sig21, sig41) and to provide, from said received signals, the signal (cmdl3) indicating when the first and second square signals (sigl 1, sig31) are at their first levels, the signal (cmdln3n) indicating when the first and second square signals (sigl 1, sig31) are at their second levels, the signal (cmdl3n) indicating when the first and second square signals (sigl 1, sig31) are respectively at their first and second levels, and the signal (cmdln3) indicating when the first and second square signals (sigl 1, sig31) are respectively at their second and first levels.

15. The device of claim 13 taken in its dependence on claim 6, wherein the logic gate (806) of the write and storage circuit (900) comprises: a current-switching NAND gate configured to review four signals (sigl 1', sig21', sig31', sig41') determined by respectively the first, second, fourth and fifth square signals (sigl 1, sig21, sig31, sig41) and to provide first, second, third and fourth output signals (SI, S2, S3, S4); and four inverters (1030) configured to respectively receive the four output signals (SI, S2, S3, S4) of the NAND logic gate and to respectively provide the signal indicating when the first and second square signals are at their first levels, the signal indicating when the first and second square signals are at their second levels, the signal indicating when the first and second square signals are at their first and second levels respectively, and the signal indicating when the first and second square signals are at their second and first levels respectively.

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