Stacking of single-crystal layers for the fabrication of 3D-architecture microelectronic devices
The layer stacking of unintentionally doped silicon and P-type doped silicon or SiGe layers addresses mechanical stability and etching selectivity issues, enhancing memory density and transistor channel count in 3D microelectronic devices by minimizing dislocations and improving etching selectivity.
Patent Information
- Authority / Receiving Office
- FR · FR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-11-08
- Publication Date
- 2026-03-13
AI Technical Summary
Existing 3D microelectronic device technologies face limitations in mechanical stability and etching selectivity due to high Ge concentration in SiGe layers, leading to dislocation generation and restricted stack thickness, which affects memory capacity and current density.
A layer stacking comprising unintentionally doped silicon and P-type doped silicon or SiGe layers, replacing high-Ge SiGe layers to enhance mechanical stability and etching selectivity, allowing for thicker layers and improved memory density or transistor channels.
The proposed layer stacking minimizes dislocation generation and improves memory density or transistor channel count by ensuring mechanical stability and efficient etching selectivity, enabling thicker insulating structures and higher memory capacity per unit area.
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Abstract
Description
Title of the invention: Stacking of single-crystal layers for the fabrication of 3D architecture microelectronic devices technical field
[0001] The invention relates to the field of 3D architecture microelectronic devices comprising transistors, in particular made from multilayer stacks of single-crystal materials. The invention applies in particular to the realization of transistors in advanced GAA (Gate-Around) MOS technology of the NanoSheet (or nano-sheet), ForkSheet or CFET (Complementary Field-Effect Transistors) type, or to the realization of 3D architecture memory devices including access transistors in advanced GAA MOS technology and for example of type 1T1R (each memory point being formed by a resistive element coupled to an access transistor) or 1T1C (each memory point being formed by a capacitive element coupled to an access transistor). Prior art
[0002] The latest CMOS technologies use (and will use) an alternating arrangement of layers of two semiconductor materials that can be selectively removed relative to each other. This provides the conditions for obtaining so-called "suspended" layers and creating a GAA transistor. The layers used are generally made of Si, Ge, SiGe, or GeSn, although the most widespread technology is based on alternating layers of Si and SiGe.
[0003] GAA transistor technology based on alternating layers of Si and SiGe uses SiGe with a Ge concentration between 25 and 35%, and thicknesses typically less than 15 nm for each Si and SiGe layer. In terms of design, one aspect that limits the total number of achievable alternating layers is the mechanical stability of the structure. In the case of Si / SiGe growth on a Si substrate, the SiGe layers are under compressive stress. The layers can retain this stress up to a certain thickness, known as the critical thickness (see, for example, the document by JM Hartmann et al., "Critical thickness for plastic relaxation of SiG on Si(001) revisited," Journal of Applied Physics, vol. 110, 083529 (2011)). For a greater thickness, the SiGe layer will release some of this stress by emitting dislocations, which is detrimental to the performance / functionality of the device.The same applies to multi-layer stacking. As an indication, the average Ge concentration in the stack is taken. to define the critical stack thickness. It is then clear that using a higher Ge concentration for the stack layers limits the total SiGe thickness in the stack. A compromise must then be found between the number of layers, the etching selectivity, and mechanical stability.
[0004] For certain applications, a third layer with third etching selectivity can be added, for example, to isolate the transistor from the substrate or to isolate two channel levels or two stacked transistors, which may be, for example, complementary transistors (nMOS and pMOS). When this third layer is based on SiGe alloys, it must have a Ge concentration significantly higher than the Ge concentration in the other SiGe, i.e., at least 50%, to ensure sufficient etching selectivity. The article by JM Hartmann et al., "Critical thickness for plastic relaxation of SiG on Si(001) revisited," Journal of Applied Physics, vol. 110, 083529 (2011), shows that the critical thickness is not a linear characteristic with respect to the Ge concentration, but that it decreases sharply with increasing Ge concentration.This therefore raises a critical point in terms of design, concerning the mechanical stability of the structure, which could ultimately be a deal-breaker.
[0005] This limitation on the total stack thickness therefore translates into a limitation on the total number of stack layers. For example, a three-layer stack comprising alternating layers of silicon, SiO.75Geo.25, and SiO.5Ge0.5, with thicknesses between 12 nm and 13 nm, has a critical thickness between 100 nm and 150 nm. In this case, the number of superimposed layers used to form the transistor channels is at most 3. A high concentration of germanium within such a stack therefore limits the achievable memory capacity per unit area when this stack is used to implement a 3D memory architecture device, or limits the achievable current density when this stack is used to implement 3D transistor architectures.
[0006] Furthermore, the etching selectivity between the Sio,sGeo.2, or Sio.75Geo.25 layers, and the Si0,5Ge0.5 layers is not sufficient to avoid consuming one of these layers during an etching of the other of these layers. Description of the invention
[0007] An object of the present invention is to provide a layer stacking suitable for the fabrication of 3D microelectronic devices comprising transistors, resolving at least in part the etching selectivity problem explained above and capable of having a significant thickness (for example, greater than 100 nm or 150 nm) while minimizing or eliminating the generation of dislocations by re plastic laxation within the stack, in order to improve the memory density (per unit area) or the number of active layers (transistor channels) achievable by devices made from such a stack.
[0008] For this purpose, the invention proposes a layer stacking adapted to the realization of microelectronic devices with a 3D architecture comprising transistors, including several first layers of unintentionally doped silicon, several second layers of unintentionally doped SiGe, and at least one third layer of P-type doped silicon or P-type doped SiGe, and such that the first, second and third layers are stacked one on top of the other.
[0009] Compared to the three-layer stacks used in the prior art, it is proposed to replace the SiGe layer(s) with the highest Ge concentration by at least one layer of P-type doped silicon or SiGe with P-type doping and, for example, a low Ge concentration. Thus, this stack does not present the disadvantages associated with the presence of a SiGe layer with a high Ge concentration, which ultimately improves the memory density (per unit area) or the number of active layers (transistor channels) achievable by devices made from such a stack, while minimizing or eliminating the generation of dislocations by plastic relaxation due to exceeding the critical thickness within the stack.
[0010] Furthermore, the P-type doped silicon or P-type doped SiGe layer(s) may be thicker than the high-Ge SiGe layer(s) used in the prior art because their critical thickness before dislocations occur is greater. This allows, for example, when this or these P-type doped silicon or P-type doped SiGe layer(s) are intended to be etched and then replaced by one or more dielectric insulating materials, for better insulation to be formed between stacked structures within the stack, thanks to the creation of a thicker insulating structure and / or one comprising an insulating material with low permittivity.
[0011] Finally, the etching selectivity obtained between P-type doped silicon, or P-type doped SiGe, and unintentionally doped silicon and unintentionally doped SiGe is greater than that obtained in prior art three-layer stacks, which avoids excessive consumption of stack materials when implementing selective etching of these materials.
[0012] In the proposed stacking, the layers can be stacked such that each first layer is arranged between, and in contact with, two second layers or two third layers, and / or such that each second layer is arranged between, and in contact with, two first layers or two third layers. This feature may not apply to some of the first or second layers. layers, such as those at the top of the stack and / or those at the base of the stack.
[0013] Generally, the semiconductors of the first, second, and third layers can be single-crystal, which is particularly advantageous for the semiconductor intended to form transistor channels. Alternatively, the semiconductors of the first, second, and third layers may be polycrystalline.
[0014] P-type doping of silicon or SiGe can be obtained by Boron atoms for example.
[0015] The silicon or SiGe of the third layer may have a concentration of P-type dopants greater than or equal to 5.1019 at / cm3, and advantageously greater than or equal to 1.1020 at / cm3.
[0016] Unintentionally doped SiGe may have a germanium concentration greater than or equal to 10%, or greater than or equal to 20%, and less than 50%.
[0017] The number of first or second layers of the stack can be between 4 and 300.
[0018] In a first embodiment, each of the first and second layers can be arranged between two third layers and be in contact with these two third layers. A stacking according to this first embodiment can advantageously be used for the realization of 3D memory devices including access transistors in advanced MOS technology.
[0019] In a variant of this first embodiment, the stack may further comprise several other third layers of P-type doped silicon or P-type doped SiGe, and each of the first and third layers may be arranged between two of the second layers and be in contact with these two second layers.
[0020] In a second embodiment, the stacking may comprise at least:
[0021] - a first sub-stacking formed by an alternation of first and second layers and such that each first layer of the first substack is arranged between two second layers of the first substack or that each second layer of the first substack is arranged between two first layers of the first substack;
[0022] - a second sub-stacking formed by an alternation of first and second layers and such that each first layer of the second substack is arranged between two second layers of the second substack or that each second layer of the second substack is arranged between two first layers of the second substack;
[0023] and the third layer can be arranged between the first and second substacks. A stack according to this second embodiment can advantageously It can be used for the production of CFET transistors, i.e. n and p type transistors stacked one on top of the other and whose channels are formed by a superposition of nanowires or nanosheets.
[0024] In this second embodiment, the stack may further comprise several other third layers of P-type doped silicon or P-type doped SiGe between which the first and second sub-stacks are arranged.
[0025] In a third embodiment, the first and second layers can be arranged alternately one above the other, and the third layer can be arranged below the assembly formed by the first and second layers. A stacking according to this third embodiment can advantageously be used for the fabrication of GAA CMOS transistors.
[0026] The invention also relates to a first method for producing 3D architecture microelectronic devices comprising transistors, comprising the implementation of the following steps:
[0027] a) realization of a stack according to the first embodiment on a substrate and in which each of the first and second layers is arranged between two third layers and is in contact with these two third layers;
[0028] b) etching trenches and / or cavities through at least part of the thickness of the stack, such that remaining portions of the first, second and third layers form nanowires or nanosheets;
[0029] c) selective etching of a part of the remaining portions of the first layers such that the remaining parts of the first layers are configured to form channels of the transistors;
[0030] d) deposition of at least a first dielectric material in first spaces formed by the selective etching of a part of the remaining portions of the first layers, next to the channels of the transistors;
[0031] e) selective etching of at least a part of the remaining portions of the second layers;
[0032] f) deposition of at least a second dielectric material in second spaces formed by the selective etching of at least a part of the remaining portions of the second layers, between the remaining portions of the third layers;
[0033] g) selective etching of the remaining portions of the third layers;
[0034] h) deposition of at least one gate dielectric and at least one conductive material of grid in third spaces formed by the selective etching of the remaining portions of the third layers, forming a grid at least above and below each of the transistor channels.
[0035] Alternatively, the invention also proposes a method for manufacturing 3D architecture microelectronic devices comprising transistors, including the implementation implementing the following steps:
[0036] a) realization of a stack according to the first embodiment on a substrate and in which each of the first and second layers is arranged between two third layers and is in contact with these two third layers;
[0037] b) etching trenches and / or cavities through at least part of the thickness of the stack, such that remaining portions of the first, second and third layers form nanowires or nanosheets;
[0038] c) selective etching of a portion of the remaining portions of the second layers such that the remaining portions of the second layers are configured to form channels of the transistors;
[0039] d) deposition of at least a first dielectric material in first spaces formed by the selective etching of a part of the remaining portions of the second layers, next to the channels of the transistors;
[0040] e) selective etching of at least a part of the remaining portions of the first layers;
[0041] f) deposition of at least a second dielectric material in second spaces formed by the selective etching of at least a part of the remaining portions of the first layers, between the remaining portions of the third layers;
[0042] g) selective etching of the remaining portions of the third layers;
[0043] h) deposition of at least one gate dielectric and at least one conductive material of grid in third spaces formed by the selective etching of the remaining portions of the third layers, forming a grid at least above and below each of the transistor channels.
[0044] The two above processes can advantageously be implemented to produce 3D architecture memory devices including access transistors in advanced MOS technology.
[0045] According to another variant of this first embodiment, the invention proposes a method for manufacturing 3D architecture microelectronic devices comprising transistors, comprising the implementation of the following steps: a) realization of a stack according to the first embodiment on a substrate, the stack further comprising several other third layers of P-type doped silicon or P-type doped SiGe, and in which each of the first and third layers is arranged between two second layers and is in contact with these two second layers;
[0046] b) etching trenches and / or cavities through at least part of the thickness of the stack, such that remaining portions of the first, second and third layers form nanowires or nanosheets;
[0047] c) selective etching of a portion of the remaining parts of the first layers such that remaining parts of the first layers are configured to form transistor channels;
[0048] d) deposition of at least a first dielectric material in first spaces formed by the selective etching of a part of the remaining portions of the first layers, next to the channels of the transistors;
[0049] e) selective etching of at least a part of the remaining portions of the third layers;
[0050] f) deposition of at least a second dielectric material in second spaces formed by the selective etching of at least a part of the remaining portions of the third layers, between the remaining portions of the second layers;
[0051] g) selective etching of the remaining portions of the second layers;
[0052] h) deposition of at least one gate dielectric and at least one conductive material of grid in third spaces formed by the selective etching of the remaining portions of the second layers, forming a grid at least above and below each of the transistor channels.
[0053] Alternatively, steps e) and f) can be implemented between steps b) and c).
[0054] The invention also relates to a second method for producing 3D architecture microelectronic devices comprising transistors, comprising the implementation of the following steps:
[0055] a) realization of a stacking according to the second embodiment on a substrate;
[0056] b) etching trenches and / or cavities through at least part of the thickness of the stack, such that remaining portions of the first and second layers of the first and second sub-stacks and remaining portions of the third layer or third layers form nanowires or nano-sheets;
[0057] c) selective etching of at least a part of the remaining portions of the third layer or third layers;
[0058] d) deposition of at least a first dielectric material in first spaces formed by the selective etching of at least a part of the remaining portions of the third layer;
[0059] e) selective etching of at least a part of the remaining portions of the second layers of the first substack when, in the first substack, each first layer is arranged between two second layers, or selective etching of at least a part of the remaining portions of the first layers of the first substack when, in the first substack, each second layer is arranged between two first layers;
[0060] f) deposition of at least one gate dielectric and at least one gate conductive material in second spaces formed by the selective etching of step e), forming a grid at least above and below each of the remaining portions of the first or second layers of the first substack.
[0061] Such a process can advantageously be implemented to produce CFET transistors.
[0062] This second method can be such that:
[0063] - when each first layer is arranged between two second layers in the first and second substacks, step e) also includes a selective etching of at least a portion of the remaining portions of the second layers of the second substack, and step f) also includes a deposition of the gate dielectric and the gate conductive material in third spaces formed by the selective etching of at least a portion of the remaining portions of the second layers of the second substack, forming a grid at least above and below each of the remaining portions of the first layers of the second substack, or
[0064] - when each second layer is arranged between two first layers in the first and second substacks, step e) also includes a selective etching of at least a portion of the remaining portions of the first layers of the second substack, and step f) also includes a deposition of the gate dielectric and the gate conductive material in third spaces formed by the selective etching of at least a portion of the remaining portions of the first layers of the second substack, forming a grid at least above and below each of the remaining portions of the second layers of the second substack, or
[0065] - when each first layer is arranged between two second layers in the first substack and that each second layer is disposed between two first layers in the second substack, the process further comprises, after step f), a step g) of selectively etching at least a portion of the remaining portions of the first layers of the second substack, and then a step h) of depositing at least one gate dielectric and at least one gate conductive material in third spaces formed by etching at least a portion of the remaining portions of the first layers of the second substack, forming a grid at least above and below each of the remaining portions of the second layers of the first substack, or
[0066] - when each second layer is arranged between two first layers in the first substack and that each first layer is arranged between two second layers in the second substack, the process further comprises, after step f), a step g) of selectively etching at least a portion of the remaining portions of the second layers of the second substack, and then a step h) of deposition of at least one grid dielectric and at least one grid conductive material in third spaces formed by the selective etching of at least a portion of the remaining portions of the second layers of the second substack, forming a grid at least above and below each of the remaining portions of the first layers of the first substack.
[0067] The invention also relates to a method for manufacturing 3D architecture microelectronic devices comprising transistors, comprising the implementation of the following steps:
[0068] a) realization of a stacking according to the third embodiment on a substrate;
[0069] b) engraving of trenches and / or cavities through at least part of the thickness of the stacking, such as remaining portions of the first and second layers of the first and second sub-stacks and remaining portions of the third layer form nanowires or nano-sheets;
[0070] c) selective etching of at least a part of the remaining portions of the third layer;
[0071] d) deposition of at least a first dielectric material in first spaces formed under the remaining portions of the first and second layers, ensuring electrical insulation between the remaining portions of the first and second layers and the substrate;
[0072] e) selective etching of at least a part of the remaining portions of the first or second layers;
[0073] f) deposition of at least one grid dielectric and at least one grid conductive material in second spaces formed by etching at least a part of the remaining portions of the first or second layers, forming a grid at least above and below each of the remaining portions of the first or second layers.
[0074] Such a process can advantageously be implemented to produce GAA CMOS transistors.
[0075] Throughout this document, the term "on" is used without distinction as to the spatial orientation of the element to which it refers. For example, in the feature "on a face of the first substrate," this face of the first substrate is not necessarily oriented upwards but may correspond to a face oriented in any direction. Furthermore, the arrangement of a first element on a second element should be understood as either having the first element directly against the second element, without any intermediate elements between the first and second elements, or having the first element on the second element with one or more intermediate elements arranged between the first and second elements.
[0076] In the embodiment processes described above and in the particular embodiments described below, the steps described are not necessarily carried out directly one after the other, because intermediate steps may be carried out between two steps of these processes. Brief description of the drawings
[0077] The present invention will be better understood upon reading the description of exemplary embodiments given by way of illustration only and in no way limiting, with reference to the accompanying drawings in which:
[0078] [Fig.1] represents a stack of layers of single-crystal materials adapted to the realization of microelectronic devices with a 3D architecture comprising transistors, the subject of the present invention, according to a first embodiment;
[0079] [Fig.2] represents the steps of a process for manufacturing microelectronic devices tronics with 3D architecture comprising transistors, the subject of the present invention, implemented from a stack according to the first embodiment;
[0080] [Fig.3] represents the steps of a variant of the process described in connection with [Fig.2];
[0081] [Fig.4] represents a stacking of layers of single-crystal materials adapted to the realization of microelectronic devices with 3D architecture comprising CFET transistors, the subject of the present invention, according to a second embodiment;
[0082] [Fig.5] and
[0083] [Fig.6] represent the steps of a process for manufacturing microelectronic devices tronics with 3D architecture comprising CFET transistors, the subject of the present invention, implemented from a stack according to the second embodiment;
[0084] [Fig.7] represents a stacking of layers of single-crystal materials adapted to the realization of microelectronic devices with 3D architecture comprising CFET transistors, the subject of the present invention, according to a variant of the second embodiment;
[0085] [Fig.8] and
[0086] [Fig.9] represent the steps of a process for manufacturing microelectronic devices tronics with 3D architecture comprising CFET transistors, the subject of the present invention, implemented from a stack according to the variant of the second embodiment;
[0087] [Fig. 10] represents a stack of single-crystal material layers adapted to the realization of 3D architecture microelectronic devices comprising GAA transistors, the subject of the present invention, according to a third embodiment;
[0088] [Fig. 11] and
[0089] [Fig. 12] represent the steps of a process for making microelectronic devices with a 3D architecture comprising GAA transistors, the subject of the present invention, implemented from a stack according to the third embodiment.
[0090] Identical, similar or equivalent parts of the different figures described below bear the same numerical references so as to facilitate the transition from one figure to another.
[0091] The different parts represented in the figures are not necessarily shown on a uniform scale, in order to make the figures more legible.
[0092] The different possibilities (variants and embodiments) should be understood as not being mutually exclusive and can be combined with each other.
[0093] Detailed description of particular embodiments
[0094] A 100 stack of single-crystal material layers suitable for the realization of 3D architecture microelectronic devices comprising transistors, according to a first embodiment, is described below in relation to [Fig.1].
[0095] The stack 100 is arranged on a substrate 102 corresponding, for example, to a bulk semiconductor substrate, for example silicon. Advantageously, the substrate 102 may correspond to a semiconductor-on-insulator type substrate, for example SOI (Silicon On Insulator).
[0096] The stack 100 comprises several first layers 104 of unintentionally doped silicon, several second layers 106 of unintentionally doped SiGe, and at least one third layer 108 (several third layers 108 in the example of [Fig.1]) of P-type doped silicon or P-type doped SiGe.
[0097] In the first embodiment, each of the first and second layers 104, 106 is arranged between two third layers 108 and is in contact with these two third layers 108. In the example of [Fig.1], the stack 100 comprises four first layers 104, four second layers 106 and nine third layers 108.
[0098] The stack 100 shown in [Fig. 1] also includes a layer 110 similar to one of the first layers 104 and disposed between the substrate 102 and the stack 100. In the described embodiment, unlike the first layers 104, the layer 110 is not disposed between two third layers 108. Alternatively, it is possible to have the layer 110 disposed between two third layers 108. In the case of a SOI-type substrate 102, the layer 110 may correspond to the surface silicon layer of this substrate 102, a buried dielectric layer, or BOX (Buried-Oxide), being present in this case beneath the layer 110. (such a BOX is not visible on [Fig.1]).
[0099] In one variant, it is possible that the stack 100 has, at its top, a layer of SiGe not intentionally doped thicker than the layers 106.
[0100] Advantageously, the total number of first layers 104 of the stacking 100 is between 4 and 300.
[0101] In the embodiment shown in [Fig. 1], the third layers 108 comprise P-type doped silicon. Furthermore, the silicon in the third layers has a concentration of p-type dopants, advantageously corresponding to boron atoms, greater than or equal to 5 x 10¹⁹ at / cm³, or even greater than or equal to 10²⁰ at / cm³. Moreover, in the embodiment described here, the unintentionally doped SiGe has a germanium concentration greater than or equal to 10%, or greater than or equal to 20%, and for example, equal to 30%. Furthermore, in this embodiment, the unintentionally doped SiGe also has a germanium concentration of less than 50%.
[0102] The thickness of each of the layers 104, 106, 108 and 110 is for example between 5 nm and 30 nm.
[0103] A method for manufacturing 3D microelectronic devices 200 comprising transistors, implemented from the stack 100 according to the first embodiment, is described below with reference to [Fig. 2]. To simplify the description of this method, only a portion of the layers of the stack 100 are shown in [Fig. 2]. Furthermore, various elements of the manufactured transistors, such as the dummy gate, side spacers, source and drain regions, etc., as well as other elements of the device 200, are not shown in [Fig. 2] to facilitate understanding of the invention.
[0104] A first step of the process consists of carrying out the stack 100 on the substrate 102. The different layers 104, 106, 108, 110 of the stack 100 can be produced by epitaxy on the upper face of the substrate 102. The stack 100 obtained at the end of these epitaxy steps corresponds to that shown in [Fig.1].
[0105] Trenches and / or cavities (contact holes, for example) are then created through at least part of the thickness of the stack 100 (the entire thickness of the stack 100 in the example of [Fig. 2]), so that remaining portions of the various layers 104, 106, and 108 of the stack 100 form nanowires or nanosheets. In the embodiment described here, this etching step is also carried out through the layer 110. This etching step is performed by creating an etching mask (not shown) at the top of the stack 100, defining the pattern to be etched through the stack 100. This etching is, for example, a dry plasma etching based on C4F6 / O2 and / or HBr / O2. In the case of a 102-type SOI substrate, this etching can be stopped on the layer buried dielectric of substrate 102. On [Fig.2], view a, only one of the remaining portions of each of the layers 104, 106, 108, 110 of stack 100 is shown.
[0106] Although not visible in [Fig.2], the realization of the 3D architecture microelectronic devices 200 can be continued by forming, for example, a dummy grid on and against the lateral walls of the remaining portions of the stack 100. Lateral spacers, which are also not visible in [Fig.2], can then be made next to the dummy grid, also on and against the lateral walls of the remaining portions of the stack 100.
[0107] A selective etching of a portion of the remaining parts of the first layers 104, and also of layer 110 in the embodiment described here, is then carried out so as to form channels for the transistors that will be made from the stack 100. This etching of the material of the first layers 104 and of layer 110, i.e., unintentionally doped silicon, is selective with respect to the materials of the other layers 106 and 108 of the stack 100, i.e., selective with respect to the unintentionally doped SiGe of the second layers 106 and the P-type doped silicon of the third layers 108. In the embodiment described here, this etching corresponds to an isotropic etching, for example, a wet etching that can be carried out with a solution based on EDP (ethylenediamine pyrocatechol), KOH, NaOH, and LiOH.
[0108] As can be seen in [Fig. 2], view b, this etching forms the future channels 112 of the transistors corresponding to the remaining material portions of the first layers 104, and also of layer 110 in this example. With the implementation of this etching, the first spaces 114 are also formed next to the channels 112, exposing the lateral flanks of the channels 112.
[0109] A deposit of at least one first dielectric material 116 in the first spaces 114 is then carried out (see [Fig. 2], view c). Advantageously, this first dielectric material 116 corresponds to an oxide, for example SiO2. The deposit carried out is, for example, of the CVD or ALD type.
[0110] A selective etching of at least a portion of the remaining portions of the second layers 106, and preferably of all the remaining portions of the second layers 106, is then carried out. This etching of the material of the second layers 106, i.e., the unintentionally doped SiGe, is selective with respect to the materials of the other layers 102, 108, 116, and 110 of the stack 100, i.e., selective with respect to the unintentionally doped silicon of the first layers 104 and layer 110, the P-type doped silicon of the third layers 108, and also with respect to the first dielectric material of the portions 116. In the embodiment described here, this etching corresponds, for example, to an etching wet etching can be carried out with a solution based on acetic acid HF H2O2 or HNO3 combined with oxide etching agents (details of implementation given for example in the document "The Effect of Doping on the Digital Etching of Silicon-Selective Silicon-Germanium Using Nitric Acids" by Li et al., Na-nomaterials, 2021, 11(5), 1209). With the implementation of this etching, second spaces are formed between the third layers 108.
[0111] Although this is not visible in [Fig.2], the mechanical stability of the stack is ensured by the presence of materials located outside the planes shown in [Fig.2],
[0112] A deposit of at least one second dielectric material 118 is then carried out in the second spaces (see [Fig. 2], view d). By way of example, this second dielectric material 118 corresponds to a nitride, for example SiN. The deposit carried out is, for example, of the CVD or ALD type. The portions of this second dielectric material 118 are intended here to form dielectric insulating portions between the gates of the different levels of the GAA transistors that will be fabricated.
[0113] A selective etching of at least a portion of the remaining portions of the third layers 108, and preferably of all the remaining portions of the third layers 108, is then carried out. This etching of the material of the third layers 108, i.e., the doped silicon in the example described here, is selective with respect to the materials present, i.e., selective with respect to the unintentionally doped silicon of the first layers 104 and layer 110, the unintentionally doped SiGe of the second layers 106, and the first and second dielectric materials of the portions 116 and 118. In the embodiment described here, this etching corresponds, for example, to a wet etching that can be carried out with a solution based on HNA, i.e., HF, HNO3, and propionic acid.
[0114] A deposition of at least one gate dielectric and at least one gate conductive material in third spaces formed by the selective etching of one of the remaining portions of the third layers 108, forming a gate 120 above and below each of the channels 112 of the transistors. The gate dielectric and the gate conductive material correspond, for example, to a superposition of HfO2, TiN, and W. The resulting structure is shown in [Fig. 2], view e.
[0115] Alternatively, it is possible that the portions 116 are etched before the grid dielectric and the grid conductive material are deposited, and that one or more materials different from that of the portions 116 are deposited in the cavities obtained by this etching.
[0116] Other steps such as the realization of spacers, source and drain regions, electrical contacts, memory elements when the 100 stack is used to realize 3D memory devices, etc., are also implemented for complete the realization of the 3D architecture microelectronic devices 200.
[0117] Alternatively, the 100 stacking can be advantageously used to make a 3D memory device such as that described in patent application FR 21 05264, which makes it possible, compared to the materials described in application FR 21 05264, to make a 3D memory device comprising a greater number of superimposed memory levels, and therefore a greater memory density / unit area.
[0118] Another method for realizing 3D microelectronic devices comprising transistors, implemented from the stack-up according to the first embodiment, is described below with reference to [Fig. 3]. To simplify the description of this method, only a portion of the layers of the stack-up are shown in [Fig. 3].
[0119] In this process, the same steps as those of the process previously described in relation to [Fig. 2] are carried out, but in a different order. Thus, compared to the process previously described in relation to [Fig. 2], the steps of etching at least a portion of the remaining portions of the second layers 106 and depositing the second dielectric material 118 are carried out before the steps of etching a portion of the remaining portions of the first layers 104 and depositing the first dielectric material 116. In [Fig. 3], view b, the spaces formed by etching at least a portion of the remaining portions of the second layers 106 are designated by reference numeral 115. In this process, it is possible that the second dielectric material 118 corresponds to SiCO₃ or SiN.As in the previous process, after implementing the deposition of the first and second dielectric materials 116, 118, the etching of at least part of the remaining portions of the third layers 108 and the deposition of the materials forming the gates 120 of the transistors are implemented.
[0120] As an alternative to the stack 100 previously described according to the first embodiment, it is possible that each of the first and third layers 104, 108 is arranged between two second layers 106 and is in contact with these two second layers 106. The two processes described above can be implemented using a stack 100 according to this alternative embodiment, adapting in this case the etching agents used according to the materials to be etched.
[0121] In the processes described above, the first layers 104 are used to form the channels of the transistors of the device produced. Alternatively, the second layers 106 may be partially etched so that the remaining portions of the second layers 106 are used to form the channels of the transistors of the devices produced.
[0122] The stacking 100 according to the first embodiment as well as according to the above variant of the first embodiment is well suited for the realization of memory devices with 3D architecture 200 and for example of type 1T1R or 1T1C.
[0123] A 100 stack of single-crystal material layers suitable for the realization of 3D architecture microelectronic devices comprising CFET transistors, according to a second embodiment, is described below in relation to [Fig.4].
[0124] As in the first embodiment, the stack 100 according to the second embodiment is carried out on the substrate 102 and comprises first layers 104, second layers 106 and at least one third layer 108 (only one in the example of [Fig. 4]). The materials of these layers 104, 106 and 108 are similar to those previously described in connection with the first embodiment.
[0125] In this second embodiment, the first and second layers 104 and 106 of the stack 100 are distributed to form several sub-stacks, each separated from the others by a third layer 108. In the example of [Fig. 4], the stack 100 comprises: - a first sub-stacking 121 formed of an alternation of first and second layers 104, 106 such that each first layer 104 of the first sub-stacking 121 is arranged between two second layers 106 of the first sub-stacking 121; - a second substack 122 formed of an alternation of first and second layers 104, 106 such that each first layer 104 of the second substack 122 is arranged between two second layers 106 of the second substack 122.
[0126] The stack 100 shown in [Fig.4] also includes a third layer 108 arranged between the first and second sub-stacks 121, 122.
[0127] Following the example of [Fig.4], each of the first and second substacks 121, 122 comprises four first layers 104 and five second layers 106.
[0128] The individual characteristics (thickness, doping, etc.) of each of the layers 104, 106, 108 of the stack according to this second embodiment are, for example, identical to those previously described for the stack 100 according to the first embodiment.
[0129] A method for producing 3D architecture microelectronic devices 200 comprising transistors, implemented from the stack 100 according to the second embodiment, is described below in relation to figures 5 and 6.
[0130] The stack 100 as described above in relation to [Fig.4] is first made on the substrate 102. The different layers 104, 106 and 108 of the stack 100 can be made by epitaxy on the upper face of the substrate 102.
[0131] As in the processes described previously, trenches and / or cavities are then etched through at least part of the thickness of the stack 100 (through the entire thickness of the stack 100 in the embodiment described here), so that remaining portions of the various layers 104, 106, and 108 of the stack 100 form nanowires or nanosheets. In Figures 5 and 6, a Part of these engraved trenches are designated by reference 124.
[0132] A selective etching of at least a part of the remaining portions of the third layer 108, and preferably of all the remaining portions of the third layers 108, is then carried out, and then at least a first dielectric material 126, for example SiO2 or SiN, is deposited in first spaces formed between the sub-stacks 121, 122. This first dielectric material 126 provides electrical insulation between the semiconducting materials of the sub-stacks 121, 122. The structure obtained at this stage of the process is shown in [Fig. 5].
[0133] A selective etching of at least some of the remaining portions of the second layers 106 of the substacks 121, 122, and preferably of all the remaining portions of the second layers 106 of the substacks 121, 122, is subsequently carried out. At least one gate dielectric and at least one gate conductive material are then deposited in second spaces formed by the previous selective etching of the remaining portions of the second layers 106, forming a grid 128 above and below each of the remaining portions of the first layers 104 of the substacks 121, 122. The resulting structure is shown in [Fig. 6].
[0134] Other steps, not described here, such as the realization of the spacers, the source and drain regions, the electrical contacts, etc., are also implemented to complete the realization of the microelectronic devices with 3D architecture 200. These devices may include CFET type transistors such that one of the NMOS or PMOS type transistors has a channel formed by the remaining portions of the first layers 104 of the first sub-stack 121 and the other of the transistors, respectively of PMOS or NMOS type, has a channel formed by the remaining portions of the first layers 104 of the second sub-stack 122.
[0135] As an alternative to the configuration shown in [Fig.4], the stacking 100 may comprise:
[0136] - a first substack 121 formed by an alternation of first and second layers 104, 106 such that each second layer 106 of the first substack 121 is arranged between two first layers 104 of the first substack 121;
[0137] - a second substack 122 formed by an alternation of first and second layers 104, 106 such that each second layer 106 of the second substack 122 is arranged between two first layers 104 of the second substack 122.
[0138] In this case, when fabricating 3D microelectronic devices from such a stack, it is the remaining portions of the first layers 104 of the sub-stacks 121, 122 that are selectively etched with respect to the portions remaining portions of the second layers 106. The grids 128 are then made above and below each of the remaining portions of the second layers 106 of the sub-stacks 121, 122 which are intended to form the channels of the transistors.
[0139] A 100 stack of single-crystal material layers suitable for the realization of 3D architecture microelectronic devices comprising GAA-type transistors, according to a variant of the second embodiment, is described below in relation to [Fig.7].
[0140] As in the previous embodiments, the stack 100 according to this variant of the second embodiment is carried out on the substrate 102 and comprises first layers 104, second layers 106 and at least one third layer 108 (only one in the example in [Fig. 7]). The materials of these layers 104, 106 and 108 are similar to those previously described in connection with the first and second embodiments.
[0141] As in the second embodiment, the first and second layers 104 and 106 of the stack 100 are distributed to form several sub-stacks, each separated from the others by a third layer 108. In the example of [Fig. 7], the stack 100 comprises:
[0142] - a first substack 121 formed by an alternation of first and second layers 104, 106 such that each first layer 104 of the first substack 121 is arranged between two second layers 106 of the first substack 121;
[0143] - a second substack 122 formed by an alternation of first and second layers 104, 106 such that each second layer 106 of the second substack 122 is arranged between two first layers 104 of the second substack 122.
[0144] The stack 100 shown in [Fig.7] also includes a third layer 108 arranged between the first and second sub-stacks 121, 122.
[0145] On the example of [Fig.7], the first substack 121 has four first layers 104 and five second layers 106, the second substack 122 has five first layers 104 and four second layers 106.
[0146] A method for producing 3D architecture microelectronic devices comprising transistors, implemented from the 100 stack according to this variant of the second embodiment, is described below in relation to figures 8 and 9.
[0147] The stack 100 as described above in relation to [Fig.7] is first made on the substrate 102. The different layers 104, 106 and 108 of the stack 100 can be made by epitaxy on the upper face of the substrate 102.
[0148] As in the processes described above, trenches and / or cavities are then made through at least part of the thickness of the stack 100 (through the entire thickness of the stack 100 in the example described here), so that remaining portions of the various layers 104, 106, and 108 of the stack 100 form nanowires or nanosheets. In Figures 8 and 9, some of these etched trenches are designated by reference numeral 124.
[0149] A selective etching of at least a part of the remaining portions of the third layer 108, and preferably of all the remaining portions of the third layers 108, is then carried out, and then at least a first dielectric material 126, for example SiO2 or SiN, is deposited in first spaces formed between the sub-stacks 121, 122. This first dielectric material 126 is intended to provide electrical insulation between the sub-stacks 121, 122. The structure obtained at this stage of the process is shown in [Fig.8].
[0150] A selective etching of at least a part of the remaining portions of the second layers 106 of the first substack 121, and preferably all of the remaining portions of the second layers 106 of the first substack 121, is carried out subsequently.
[0151] A selective etching of at least some of the remaining portions of the first layers 104 of the second substack 122, and preferably all of the remaining portions of the first layers 104 of the second substack 122, is subsequently carried out. During these steps, the first substack 121 is protected so as not to damage the materials of the first substack 121 during this selective etching.
[0152] At least one grid dielectric and at least one grid conductive material are deposited in second and third spaces formed by selectively etching the remaining portions of the second layers 106 of the first substack 121 and by selectively etching the remaining portions of the first layers 104 of the second substack 122, forming a grid 128 above and below each of the remaining portions of the first layers 104 of the first substack 121 and the remaining portions of the second layers 106 of the second substack 122.
[0153] Other steps, not described here, such as the realization of spacers, source and drain regions, electrical contacts, etc., are also implemented to complete the realization of microelectronic devices with 3D architecture 200. These devices may include CFET type transistors such as NMOS transistors have a channel formed by the remaining portions of the first layers 104 of the first sub-stack 121 and PMOS transistors have a channel formed by the remaining portions of the second layers 106 of the second sub-stack 122.
[0154] Alternatively, it is also possible that the PMOS transistors have their channels formed by the remaining portions of the first layers 104 of the first sub-stack 121 and that the NMOS transistors have their channels formed by the remaining portions of the first layers 104 of the first sub-stack 121.
[0155] As an alternative to the process described above in relation to figures 7 to 9, it is possible to first carry out the engraving of the remaining portions of the first layers 104 of the second substack 122, then the engraving of the remaining portions of the second layers 106 of the first substack 121, and finally the production of the grids 128 in the two substacks 121, 122.
[0156] As an alternative to the 100 stacking previously described in relation to [Fig.7], it is possible to realize this 100 stacking such that:
[0157] - the first substack 121 is formed of an alternation of first and second layers 104, 106 such that each second layer 106 of the first substack 121 is arranged between two first layers 104 of the first substack 121;
[0158] - the second substack 122 is formed of an alternation of first and second layers 104, 106 such that each first layer 104 of the second substack 122 is arranged between two second layers 106 of the second substack 122.
[0159] In this case, in the various processes described above that can be applied to such a stack, the selective etching implemented in the first sub-stack 121 corresponds to a selective etching of the remaining portions of the first layers 104 of the first sub-stack 121 with respect to the remaining portions of the second layers 106 of the first sub-stack 121, and the selective etching implemented in the second sub-stack 122 corresponds to a selective etching of the remaining portions of the second layers 106 of the second sub-stack 122 with respect to the remaining portions of the first layers 104 of the second sub-stack 122.
[0160] When the stack 100 has several sub-stacks as described above, it is possible that this stack 100 also has several other third layers 108 of P-type doped silicon or P-type doped SiGe between which the sub-stacks 121, 122 are arranged.
[0161] When the material layers of the stack 100 are distributed across several sub-stacks, as in the examples described above, the total number of material layers in each of the sub-stacks 121, 122 intended to form transistor channels is advantageously between 3 and 10. Furthermore, the number of material layers in each of the sub-stacks may or may not be the same. For example, considering the embodiments described above in connection with Figures 4 and 7, the number of material layers the first substack 121 could be different from that of the second substack 122. Finally, the stack 100 may have more than two substacks of layers of single-crystal materials.
[0162] A 100 stack of single-crystal material layers suitable for the realization of 3D architecture microelectronic devices comprising GAA-type transistors, according to a third embodiment, is described below in relation to [Fig.10].
[0163] As in the previous embodiments, the stack 100 according to the third embodiment is carried out on the substrate 102 and comprises first layers 104, second layers 106 and at least one third layer 108 (only one in the example of [Fig. 10]). The materials of these layers 104, 106 and 108 are similar to those previously described in connection with the previous embodiments.
[0164] In this third embodiment, the first and second layers 104 and 106 of the stack 100 are arranged alternately one above the other. In the example shown in [Fig. 10], each first layer 104 is positioned between two second layers 106 and is in contact with these two second layers 106.
[0165] The stack 100 shown in [Fig. 10] also includes a third layer 108 arranged under the first and second layers 104, 106, between the substrate 102 and the set of first and second layers 104, 106.
[0166] A method for making microelectronic devices with a 3D architecture comprising transistors, implemented from the 100 stack according to the third embodiment, is described below in relation to figures 11 and 12.
[0167] The stack 100 as described above in relation to [Fig.10] is first made on the substrate 102. The different layers 104, 106 and 108 of the stack 100 can be made by epitaxy on the upper face of the substrate 102.
[0168] As in the processes described above, trenches and / or cavities are then made through the entire thickness of the stack 100, so that remaining portions of the various layers 104, 106, and 108 of the stack 100 form nanowires or nanosheets. In Figures 11 and 12, a portion of these etched trenches are designated by reference numeral 124.
[0169] Selective etching of at least some of the remaining portions of the third layer 108, and preferably of all the remaining portions of the third layer 108, is then carried out. At least one first dielectric material 126, for example SiO2 or SiN, is conformally deposited, for example by ALD or CVD deposition, and then selectively and isotropically etched so as to retain portions of this first dielectric material only under the portions remaining layers 104, 106. This first dielectric material 126 provides electrical insulation between the substrate 102 and the channel closest to the substrate 102. The structure obtained at this stage of the process is shown in [Fig. 11].
[0170] A selective etching of a portion of the remaining portions of the second layers 106 of the stack 100 is then carried out. At least one gate dielectric and at least one gate conductive material are then deposited in second spaces formed by the previous selective etching of the remaining portions of the second layers 106, forming a grid 128 above and below, or around, each of the remaining portions of the first layers 104 of the stack 100.
[0171] The structure obtained at the end of the process is shown in [Fig.12]. Other steps, not described here, such as the fabrication of the source and drain regions, electrical contacts, etc., are implemented to complete the fabrication of the 3D 200 architecture microelectronic devices which correspond to GAA MOS transistors.
[0172] As an alternative to the fourth embodiment described above, it is possible for each second layer 106 to be arranged between two first layers 104 and to be in contact with these two first layers 104. In this case, after depositing the first dielectric material 126, a selective etching of a portion of the remaining parts of the first layers 104 of the stack 100 is carried out. At least one grid dielectric and at least one grid conductive material are then deposited in the second spaces formed by the previous selective etching of the remaining parts of the first layers 104, forming a grid 128 above and below, or around, each of the remaining parts of the second layers 106 of the stack 100.
Claims
Demands
1. Stacking (100) of layers adapted for the realization of microelectronic devices with a 3D architecture comprising transistors, including several first layers (104) of unintentionally doped silicon, several second layers (106) of unintentionally doped SiGe, and at least one third layer (108) of P-type doped silicon or P-type doped SiGe, and such that the first, second and third layers (104, 106, 108) are stacked one on top of the other, in which each of the first and second layers (104, 106) is disposed between two third layers (108) and is in contact with these two third layers (108).
2. Stack (100) of layers according to claim 1, wherein the silicon or SiGe of the third layer (108) has a concentration of P-type dopants greater than or equal to 5.1019 at / cm3.
3. Stack (100) of layers according to any one of the preceding claims, wherein the intrinsic SiGe has a germanium concentration greater than or equal to 10% and less than 50%.
4. Stack (100) of layers according to any one of the preceding claims, wherein the number of first or second layers (104, 106) of the stack (100) is between 4 and 300.
5. A method for manufacturing 3D architecture microelectronic devices (200) comprising transistors, comprising carrying out the following steps: a) manufacturing a stack (100) according to claim 1 on a substrate (102); b) etching trenches (124) and / or cavities through at least a portion of the thickness of the stack (100), such that remaining portions of the first, second and third layers (104, 106, 108) form nanowires or nanosheets; c) selectively etching a portion of the remaining portions of the first layers (104) such that remaining portions (112) of the first layers (104) are configured to form channels of the transistors; d) deposition of at least a first dielectric material (116) in first spaces (114) formed by the selective etching of a part of the remaining portions (112) of the first layers (104), next to the channels of the transistors; e) selective etching of at least a part of the remaining portions of the second layers (106); f) deposition of at least a second dielectric material (118) in second spaces (115) formed by the selective etching of at least a part of the remaining portions of the second layers (106), between the remaining portions of the third layers (108); g) selective etching of the remaining portions of the third layers (108); h) deposition of at least one gate dielectric and at least one gate conductive material in third spaces formed by the selective etching of the remaining portions of the third layers (108), forming a gate (120) at least above and below each of the transistor channels.
6. Method for making 3D architecture microelectronic devices (200) comprising transistors, comprising the implementation of the following steps: a) realization of a stacking (100) according to claim 1 on a substrate (102); b) etching of trenches (124) and / or cavities through at least part of the thickness of the stack (100), such that remaining portions of the first, second and third layers (104, 106, 108) form nanowires or nanosheets; c) selective etching of a portion of the remaining portions of the second layers (106) such that the remaining portions of the second layers (106) are configured to form channels of the transistors; d) deposition of at least a first dielectric material (116) in first spaces (114) formed by the selective etching of a part of the remaining portions of the first layers (106), next to the channels of the transistors; e) selective etching of at least a part of the remaining portions of the first layers (104); f) deposition of at least a second dielectric material (118) in second spaces (115) formed by the selective etching of at least a part of the remaining portions of the first layers (104), between the remaining portions of the third layers (108); (g) selective etching of the remaining portions of the third layers (108); (h) deposition of at least one gate dielectric and at least one gate conductive material in third spaces formed by the selective etching of the remaining portions of the third layers (108), forming
7. a grid (120) at least above and below each of the transistor channels. Method according to any one of claims 5 or 6, wherein steps e) and f) are carried out between steps b) and c).